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bellard2c0262a2003-09-30 20:34:21 +00001/*
2 * ARM virtual CPU header
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard2c0262a2003-09-30 20:34:21 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
Chetan Pant50f57e02020-10-23 12:29:13 +00009 * version 2.1 of the License, or (at your option) any later version.
bellard2c0262a2003-09-30 20:34:21 +000010 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard2c0262a2003-09-30 20:34:21 +000018 */
bellard2c0262a2003-09-30 20:34:21 +000019
Markus Armbruster07f5a252016-06-29 11:05:55 +020020#ifndef ARM_CPU_H
21#define ARM_CPU_H
bellard3cf1e032004-01-24 15:19:09 +000022
Peter Maydell72b0cd32013-11-22 17:17:08 +000023#include "kvm-consts.h"
Marc-André Lureau69242e72022-03-23 19:57:39 +040024#include "qemu/cpu-float.h"
Peter Maydell2c4da502017-01-27 15:20:23 +000025#include "hw/registerfields.h"
Richard Henderson74433bf2019-03-22 11:51:19 -070026#include "cpu-qom.h"
27#include "exec/cpu-defs.h"
Andrew Jones68970d12020-10-01 08:17:18 +020028#include "qapi/qapi-types-common.h"
Philippe Mathieu-Daudée2d8cf92024-01-18 21:06:31 +010029#include "target/arm/multiprocessing.h"
Philippe Mathieu-Daudéf4f318b2024-01-18 21:06:40 +010030#include "target/arm/gtimer.h"
ths9042c0e2006-12-23 14:18:40 +000031
Alex Bennéeca759f92017-02-23 18:29:27 +000032/* ARM processors have a weak memory model */
33#define TCG_GUEST_DEFAULT_MO (0)
34
Dongjiu Genge24fd072020-05-12 11:06:08 +080035#ifdef TARGET_AARCH64
36#define KVM_HAVE_MCE_INJECTION 1
37#endif
38
bellardb8a9e8f2005-02-07 23:10:07 +000039#define EXCP_UDEF 1 /* undefined instruction */
40#define EXCP_SWI 2 /* software interrupt */
41#define EXCP_PREFETCH_ABORT 3
42#define EXCP_DATA_ABORT 4
bellardb5ff1b32005-11-26 10:38:39 +000043#define EXCP_IRQ 5
44#define EXCP_FIQ 6
pbrook06c949e2006-02-04 19:35:26 +000045#define EXCP_BKPT 7
pbrook9ee6e8b2007-11-11 00:04:49 +000046#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
pbrookfbb4a2e2008-05-29 00:20:44 +000047#define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
Edgar E. Iglesias35979d72014-09-29 18:48:50 +010048#define EXCP_HVC 11 /* HyperVisor Call */
Edgar E. Iglesias607d98b2014-09-29 18:48:50 +010049#define EXCP_HYP_TRAP 12
Edgar E. Iglesiase0d6e6a2014-09-29 18:48:50 +010050#define EXCP_SMC 13 /* Secure Monitor Call */
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +010051#define EXCP_VIRQ 14
52#define EXCP_VFIQ 15
Peter Maydell19a6e312016-10-24 16:26:56 +010053#define EXCP_SEMIHOST 16 /* semihosting call */
Peter Maydell75177482017-01-27 15:20:24 +000054#define EXCP_NOCP 17 /* v7M NOCP UsageFault */
Peter Maydelle13886e2017-02-28 12:08:19 +000055#define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
Peter Maydell86f026d2018-10-08 14:55:04 +010056#define EXCP_STKOF 19 /* v8M STKOF UsageFault */
Peter Maydelle33cf0f2019-04-29 17:36:02 +010057#define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */
Peter Maydell019076b2019-04-29 17:36:03 +010058#define EXCP_LSERR 21 /* v8M LSERR SecureFault */
59#define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
Peter Maydelle5346292021-07-30 16:16:36 +010060#define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */
Richard Henderson3c296322022-05-06 13:02:33 -050061#define EXCP_VSERR 24
Richard Henderson11b76fd2023-06-23 11:15:48 +010062#define EXCP_GPC 25 /* v9 Granule Protection Check Fault */
Peter Maydell2c4a7cc2017-04-20 17:32:28 +010063/* NB: add new EXCP_ defines to the array in arm_log_exception() too */
pbrook9ee6e8b2007-11-11 00:04:49 +000064
65#define ARMV7M_EXCP_RESET 1
66#define ARMV7M_EXCP_NMI 2
67#define ARMV7M_EXCP_HARD 3
68#define ARMV7M_EXCP_MEM 4
69#define ARMV7M_EXCP_BUS 5
70#define ARMV7M_EXCP_USAGE 6
Peter Maydell1e577cc2017-09-07 13:54:52 +010071#define ARMV7M_EXCP_SECURE 7
pbrook9ee6e8b2007-11-11 00:04:49 +000072#define ARMV7M_EXCP_SVC 11
73#define ARMV7M_EXCP_DEBUG 12
74#define ARMV7M_EXCP_PENDSV 14
75#define ARMV7M_EXCP_SYSTICK 15
bellard2c0262a2003-09-30 20:34:21 +000076
Richard Henderson403946c2011-05-04 13:34:29 -070077/* ARM-specific interrupt pending bits. */
78#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +010079#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
80#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
Richard Henderson3c296322022-05-06 13:02:33 -050081#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0
Richard Henderson403946c2011-05-04 13:34:29 -070082
Peter Maydelle4fe8302014-01-04 22:15:45 +000083/* The usual mapping for an AArch64 system register to its AArch32
84 * counterpart is for the 32 bit world to have access to the lower
85 * half only (with writes leaving the upper half untouched). It's
86 * therefore useful to be able to pass TCG the offset of the least
87 * significant half of a uint64_t struct member.
88 */
Marc-André Lureaue03b5682022-03-23 19:57:17 +040089#if HOST_BIG_ENDIAN
Alexey Kardashevskiy5cd8a112014-01-12 21:37:37 +000090#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
Peter Maydellb0fe2422014-02-26 17:20:03 +000091#define offsetofhigh32(S, M) offsetof(S, M)
Peter Maydelle4fe8302014-01-04 22:15:45 +000092#else
93#define offsetoflow32(S, M) offsetof(S, M)
Peter Maydellb0fe2422014-02-26 17:20:03 +000094#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
Peter Maydelle4fe8302014-01-04 22:15:45 +000095#endif
96
Edgar E. Iglesiasaaa1f952016-06-06 16:59:28 +010097/* ARM-specific extra insn start words:
98 * 1: Conditional execution bits
99 * 2: Partial exception syndrome for data aborts
100 */
101#define TARGET_INSN_START_EXTRA_WORDS 2
102
103/* The 2nd extra word holding syndrome info for data aborts does not use
Peter Maydell674e5342024-01-09 14:43:54 +0000104 * the upper 6 bits nor the lower 13 bits. We mask and shift it down to
Edgar E. Iglesiasaaa1f952016-06-06 16:59:28 +0100105 * help the sleb128 encoder do a better job.
106 * When restoring the CPU state, we shift it back up.
107 */
108#define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
Peter Maydell674e5342024-01-09 14:43:54 +0000109#define ARM_INSN_START_WORD2_SHIFT 13
j_mayer6ebbf392007-10-14 07:07:08 +0000110
bellardb7bcbe92005-02-22 19:27:29 +0000111/* We currently assume float and double are IEEE single and double
112 precision respectively.
113 Doing runtime conversions is tricky because VFP registers may contain
114 integer values (eg. as the result of a FTOSI instruction).
bellard8e960052005-04-07 19:42:46 +0000115 s<2n> maps to the least significant half of d<n>
116 s<2n+1> maps to the most significant half of d<n>
117 */
bellardb7bcbe92005-02-22 19:27:29 +0000118
Abdallah Bouassida200bf5b2018-05-18 17:48:07 +0100119/**
120 * DynamicGDBXMLInfo:
121 * @desc: Contains the XML descriptions.
Alex Bennée448d4d12020-03-16 17:21:42 +0000122 * @num: Number of the registers in this XML seen by GDB.
123 * @data: A union with data specific to the set of registers
124 * @cpregs_keys: Array that contains the corresponding Key of
125 * a given cpreg with the same order of the cpreg
126 * in the XML description.
Abdallah Bouassida200bf5b2018-05-18 17:48:07 +0100127 */
128typedef struct DynamicGDBXMLInfo {
129 char *desc;
Alex Bennée448d4d12020-03-16 17:21:42 +0000130 int num;
131 union {
132 struct {
133 uint32_t *keys;
134 } cpregs;
135 } data;
Abdallah Bouassida200bf5b2018-05-18 17:48:07 +0100136} DynamicGDBXMLInfo;
137
Peter Maydell55d284a2013-08-20 14:54:31 +0100138/* CPU state for each instance of a generic timer (in cp15 c14) */
139typedef struct ARMGenericTimer {
140 uint64_t cval; /* Timer CompareValue register */
Peter Maydella7adc4b2014-02-26 17:20:05 +0000141 uint64_t ctl; /* Timer Control register */
Peter Maydell55d284a2013-08-20 14:54:31 +0100142} ARMGenericTimer;
143
Rémi Denis-Courmonte9152ee2021-01-12 12:45:01 +0200144#define VTCR_NSW (1u << 29)
145#define VTCR_NSA (1u << 30)
146#define VSTCR_SW VTCR_NSW
147#define VSTCR_SA VTCR_NSA
148
Richard Hendersonc39c2b92018-02-09 10:40:31 +0000149/* Define a maximum sized vector register.
150 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
151 * For 64-bit, this is a 2048-bit SVE register.
152 *
153 * Note that the mapping between S, D, and Q views of the register bank
154 * differs between AArch64 and AArch32.
155 * In AArch32:
156 * Qn = regs[n].d[1]:regs[n].d[0]
157 * Dn = regs[n / 2].d[n & 1]
158 * Sn = regs[n / 4].d[n % 4 / 2],
159 * bits 31..0 for even n, and bits 63..32 for odd n
160 * (and regs[16] to regs[31] are inaccessible)
161 * In AArch64:
162 * Zn = regs[n].d[*]
163 * Qn = regs[n].d[1]:regs[n].d[0]
164 * Dn = regs[n].d[0]
165 * Sn = regs[n].d[0] bits 31..0
Alex Bennéed0e69ea2018-03-01 11:05:47 +0000166 * Hn = regs[n].d[0] bits 15..0
Richard Hendersonc39c2b92018-02-09 10:40:31 +0000167 *
168 * This corresponds to the architecturally defined mapping between
169 * the two execution states, and means we do not need to explicitly
170 * map these registers when changing states.
171 *
172 * Align the data for use with TCG host vector operations.
173 */
174
175#ifdef TARGET_AARCH64
176# define ARM_MAX_VQ 16
177#else
178# define ARM_MAX_VQ 1
179#endif
180
181typedef struct ARMVectorReg {
182 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
183} ARMVectorReg;
184
Richard Henderson3c7d3082018-01-22 19:53:46 -0800185#ifdef TARGET_AARCH64
Richard Henderson991ad912019-01-21 10:23:11 +0000186/* In AArch32 mode, predicate registers do not exist at all. */
Richard Henderson3c7d3082018-01-22 19:53:46 -0800187typedef struct ARMPredicateReg {
Andrew Jones46417782019-08-02 14:25:31 +0200188 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
Richard Henderson3c7d3082018-01-22 19:53:46 -0800189} ARMPredicateReg;
Richard Henderson991ad912019-01-21 10:23:11 +0000190
191/* In AArch32 mode, PAC keys do not exist at all. */
192typedef struct ARMPACKey {
193 uint64_t lo, hi;
194} ARMPACKey;
Richard Henderson3c7d3082018-01-22 19:53:46 -0800195#endif
196
Richard Henderson3902bfc2021-04-19 13:22:31 -0700197/* See the commentary above the TBFLAG field definitions. */
198typedef struct CPUARMTBFlags {
199 uint32_t flags;
Richard Hendersona3782062021-04-19 13:22:32 -0700200 target_ulong flags2;
Richard Henderson3902bfc2021-04-19 13:22:31 -0700201} CPUARMTBFlags;
Richard Hendersonc39c2b92018-02-09 10:40:31 +0000202
Richard Hendersonf3639a62022-10-10 20:18:57 -0700203typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
204
Philippe Mathieu-Daudé8f4e07c2023-02-06 23:35:01 +0100205typedef struct NVICState NVICState;
206
Philippe Mathieu-Daudé1ea4a062022-02-07 13:35:58 +0100207typedef struct CPUArchState {
bellardb5ff1b32005-11-26 10:38:39 +0000208 /* Regs for current mode. */
bellard2c0262a2003-09-30 20:34:21 +0000209 uint32_t regs[16];
Alexander Graf3926cc82013-09-03 20:12:09 +0100210
211 /* 32/64 switch only happens when taking and returning from
212 * exceptions so the overlap semantics are taken care of then
213 * instead of having a complicated union.
214 */
215 /* Regs for A64 mode. */
216 uint64_t xregs[32];
217 uint64_t pc;
Peter Maydelld3563122013-12-17 19:42:30 +0000218 /* PSTATE isn't an architectural register for ARMv8. However, it is
219 * convenient for us to assemble the underlying state into a 32 bit format
220 * identical to the architectural format used for the SPSR. (This is also
221 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
222 * 'pstate' register are.) Of the PSTATE bits:
223 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
224 * semantics as for AArch32, as described in the comments on each field)
225 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
Peter Maydell4cc35612014-02-26 17:20:06 +0000226 * DAIF (exception masks) are kept in env->daif
Richard Hendersonf6e52ea2019-02-05 16:52:36 +0000227 * BTYPE is kept in env->btype
Richard Hendersonc37e6ac2022-06-20 10:51:49 -0700228 * SM and ZA are kept in env->svcr
Peter Maydelld3563122013-12-17 19:42:30 +0000229 * all other bits are stored in their correct places in env->pstate
Alexander Graf3926cc82013-09-03 20:12:09 +0100230 */
231 uint32_t pstate;
Richard Henderson53221552022-04-17 10:43:32 -0700232 bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nRW */
Richard Henderson063bbd82022-04-17 10:43:35 -0700233 bool thumb; /* True if CPU is in thumb mode; cpsr[5] */
Alexander Graf3926cc82013-09-03 20:12:09 +0100234
Richard Hendersonfdd1b222019-10-23 11:00:34 -0400235 /* Cached TBFLAGS state. See below for which bits are included. */
Richard Henderson3902bfc2021-04-19 13:22:31 -0700236 CPUARMTBFlags hflags;
Richard Hendersonfdd1b222019-10-23 11:00:34 -0400237
Peter Maydellb90372a2012-08-06 17:42:18 +0100238 /* Frequently accessed CPSR bits are stored separately for efficiency.
pbrookd37aca62006-10-22 11:54:30 +0000239 This contains all the other bits. Use cpsr_{read,write} to access
bellardb5ff1b32005-11-26 10:38:39 +0000240 the whole CPSR. */
241 uint32_t uncached_cpsr;
242 uint32_t spsr;
243
244 /* Banked registers. */
Edgar E. Iglesias28c94572014-05-27 17:09:52 +0100245 uint64_t banked_spsr[8];
Fabian Aggeler0b7d4092014-10-24 12:19:14 +0100246 uint32_t banked_r13[8];
247 uint32_t banked_r14[8];
ths3b46e622007-09-17 08:09:54 +0000248
bellardb5ff1b32005-11-26 10:38:39 +0000249 /* These hold r8-r12. */
250 uint32_t usr_regs[5];
251 uint32_t fiq_regs[5];
ths3b46e622007-09-17 08:09:54 +0000252
bellard2c0262a2003-09-30 20:34:21 +0000253 /* cpsr flag cache for faster execution */
254 uint32_t CF; /* 0 or 1 */
255 uint32_t VF; /* V is the bit 31. All other bits are undefined */
pbrook6fbe23d2008-04-01 17:19:11 +0000256 uint32_t NF; /* N is bit 31. All other bits are undefined. */
257 uint32_t ZF; /* Z set if zero. */
bellard99c475a2005-01-31 20:45:13 +0000258 uint32_t QF; /* 0 or 1 */
pbrook9ee6e8b2007-11-11 00:04:49 +0000259 uint32_t GE; /* cpsr[19:16] */
pbrook9ee6e8b2007-11-11 00:04:49 +0000260 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
Richard Hendersonf6e52ea2019-02-05 16:52:36 +0000261 uint32_t btype; /* BTI branch type. spsr[11:10]. */
Daniel P. Berrangeb6af0972015-08-26 12:17:13 +0100262 uint64_t daif; /* exception masks, in the bits they are in PSTATE */
Richard Hendersonc37e6ac2022-06-20 10:51:49 -0700263 uint64_t svcr; /* PSTATE.{SM,ZA} in the bits they are in SVCR */
bellard2c0262a2003-09-30 20:34:21 +0000264
Edgar E. Iglesias1b174232014-05-27 17:09:52 +0100265 uint64_t elr_el[4]; /* AArch64 exception link regs */
Edgar E. Iglesias73fb3b72014-05-27 17:09:52 +0100266 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
Peter Maydella0618a12014-04-15 19:18:42 +0100267
bellardb5ff1b32005-11-26 10:38:39 +0000268 /* System control coprocessor (cp15) */
269 struct {
pbrook40f137e2006-02-20 00:33:36 +0000270 uint32_t c0_cpuid;
Fabian Aggelerb85a1fd2014-12-11 12:07:50 +0000271 union { /* Cache size selection */
272 struct {
273 uint64_t _unused_csselr0;
274 uint64_t csselr_ns;
275 uint64_t _unused_csselr1;
276 uint64_t csselr_s;
277 };
278 uint64_t csselr_el[4];
279 };
Fabian Aggeler137feaa2014-12-11 12:07:50 +0000280 union { /* System control register. */
281 struct {
282 uint64_t _unused_sctlr;
283 uint64_t sctlr_ns;
284 uint64_t hsctlr;
285 uint64_t sctlr_s;
286 };
287 uint64_t sctlr_el[4];
288 };
Tobias Röhmel761c4642022-12-06 11:25:02 +0100289 uint64_t vsctlr; /* Virtualization System control register. */
Sergey Fedorov7ebd5f22015-04-26 16:49:25 +0100290 uint64_t cpacr_el1; /* Architectural feature access control register */
Greg Bellowsc6f19162015-05-29 11:28:52 +0100291 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
balrog610c3c82007-06-24 12:09:48 +0000292 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
Greg Bellows144634a2014-12-11 12:07:50 +0000293 uint64_t sder; /* Secure debug enable register. */
Fabian Aggeler77022572014-12-11 12:07:49 +0000294 uint32_t nsacr; /* Non-secure access control register. */
Fabian Aggeler7dd8c9a2014-12-11 12:07:51 +0000295 union { /* MMU translation table base 0. */
296 struct {
297 uint64_t _unused_ttbr0_0;
298 uint64_t ttbr0_ns;
299 uint64_t _unused_ttbr0_1;
300 uint64_t ttbr0_s;
301 };
302 uint64_t ttbr0_el[4];
303 };
304 union { /* MMU translation table base 1. */
305 struct {
306 uint64_t _unused_ttbr1_0;
307 uint64_t ttbr1_ns;
308 uint64_t _unused_ttbr1_1;
309 uint64_t ttbr1_s;
310 };
311 uint64_t ttbr1_el[4];
312 };
Edgar E. Iglesiasb698e9c2015-09-14 14:39:50 +0100313 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */
Rémi Denis-Courmonte9152ee2021-01-12 12:45:01 +0200314 uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */
Fabian Aggeler11f136e2014-12-11 12:07:51 +0000315 /* MMU translation table base control. */
Peter Maydellcb4a0a32022-07-14 14:23:02 +0100316 uint64_t tcr_el[4];
Peter Maydell988cc192022-07-14 14:23:01 +0100317 uint64_t vtcr_el2; /* Virtualization Translation Control. */
318 uint64_t vstcr_el2; /* Secure Virtualization Translation Control. */
Veres Lajos67cc32e2015-09-08 22:45:14 +0100319 uint32_t c2_data; /* MPU data cacheable bits. */
320 uint32_t c2_insn; /* MPU instruction cacheable bits. */
Fabian Aggeler0c17d682014-12-11 12:07:51 +0000321 union { /* MMU domain access control register
322 * MPU write buffer control.
323 */
324 struct {
325 uint64_t dacr_ns;
326 uint64_t dacr_s;
327 };
328 struct {
329 uint64_t dacr32_el2;
330 };
331 };
Peter Maydell7e097972014-04-15 19:18:41 +0100332 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
333 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
Edgar E. Iglesiasf149e3e2014-09-29 18:48:48 +0100334 uint64_t hcr_el2; /* Hypervisor configuration register */
Richard Henderson5814d582022-05-16 22:48:44 -0700335 uint64_t hcrx_el2; /* Extended Hypervisor configuration register */
Edgar E. Iglesias64e0e2d2014-09-29 18:48:49 +0100336 uint64_t scr_el3; /* Secure configuration register. */
Fabian Aggeler88ca1c22014-12-11 12:07:51 +0000337 union { /* Fault status registers. */
338 struct {
339 uint64_t ifsr_ns;
340 uint64_t ifsr_s;
341 };
342 struct {
343 uint64_t ifsr32_el2;
344 };
345 };
Fabian Aggeler4a7e2d72014-12-11 12:07:51 +0000346 union {
347 struct {
348 uint64_t _unused_dfsr;
349 uint64_t dfsr_ns;
350 uint64_t hsr;
351 uint64_t dfsr_s;
352 };
353 uint64_t esr_el[4];
354 };
pbrookce819862007-05-08 02:30:40 +0000355 uint32_t c6_region[8]; /* MPU base/size registers. */
Fabian Aggelerb848ce22014-12-11 12:07:51 +0000356 union { /* Fault address registers. */
357 struct {
358 uint64_t _unused_far0;
Marc-André Lureaue03b5682022-03-23 19:57:17 +0400359#if HOST_BIG_ENDIAN
Fabian Aggelerb848ce22014-12-11 12:07:51 +0000360 uint32_t ifar_ns;
361 uint32_t dfar_ns;
362 uint32_t ifar_s;
363 uint32_t dfar_s;
364#else
365 uint32_t dfar_ns;
366 uint32_t ifar_ns;
367 uint32_t dfar_s;
368 uint32_t ifar_s;
369#endif
370 uint64_t _unused_far3;
371 };
372 uint64_t far_el[4];
373 };
Edgar E. Iglesias59e05532015-10-26 14:01:54 +0100374 uint64_t hpfar_el2;
Alistair Francis2a5a9ab2016-06-06 16:59:28 +0100375 uint64_t hstr_el2;
Fabian Aggeler01c097f2014-12-11 12:07:52 +0000376 union { /* Translation result. */
377 struct {
378 uint64_t _unused_par_0;
379 uint64_t par_ns;
380 uint64_t _unused_par_1;
381 uint64_t par_s;
382 };
383 uint64_t par_el[4];
384 };
Peter Crosthwaite6cb0b012015-06-19 14:17:44 +0100385
bellardb5ff1b32005-11-26 10:38:39 +0000386 uint32_t c9_insn; /* Cache lockdown registers. */
387 uint32_t c9_data;
Alistair Francis85214662014-08-29 15:00:29 +0100388 uint64_t c9_pmcr; /* performance monitor control register */
389 uint64_t c9_pmcnten; /* perf monitor counter enables */
Aaron Lindsaye4e91a22018-04-26 11:04:39 +0100390 uint64_t c9_pmovsr; /* perf monitor overflow status */
391 uint64_t c9_pmuserenr; /* perf monitor user enable */
Wei Huang6b040782017-02-10 17:40:28 +0000392 uint64_t c9_pmselr; /* perf monitor counter selection register */
Wei Huange6ec5452017-02-10 17:40:28 +0000393 uint64_t c9_pminten; /* perf monitor interrupt enables */
Greg Bellowsbe693c82014-12-11 12:07:52 +0000394 union { /* Memory attribute redirection */
395 struct {
Marc-André Lureaue03b5682022-03-23 19:57:17 +0400396#if HOST_BIG_ENDIAN
Greg Bellowsbe693c82014-12-11 12:07:52 +0000397 uint64_t _unused_mair_0;
398 uint32_t mair1_ns;
399 uint32_t mair0_ns;
400 uint64_t _unused_mair_1;
401 uint32_t mair1_s;
402 uint32_t mair0_s;
403#else
404 uint64_t _unused_mair_0;
405 uint32_t mair0_ns;
406 uint32_t mair1_ns;
407 uint64_t _unused_mair_1;
408 uint32_t mair0_s;
409 uint32_t mair1_s;
410#endif
411 };
412 uint64_t mair_el[4];
413 };
Greg Bellowsfb6c91b2014-12-11 12:07:52 +0000414 union { /* vector base address register */
415 struct {
416 uint64_t _unused_vbar;
417 uint64_t vbar_ns;
418 uint64_t hvbar;
419 uint64_t vbar_s;
420 };
421 uint64_t vbar_el[4];
422 };
Fabian Aggelere89e51a2014-12-11 12:07:50 +0000423 uint32_t mvbar; /* (monitor) vector base address register */
Edgar E. Iglesias4a7319b2022-03-16 17:46:41 +0100424 uint64_t rvbar; /* rvbar sampled from rvbar property at reset */
Fabian Aggeler54bf36e2014-12-11 12:07:52 +0000425 struct { /* FCSE PID. */
426 uint32_t fcseidr_ns;
427 uint32_t fcseidr_s;
428 };
429 union { /* Context ID. */
430 struct {
431 uint64_t _unused_contextidr_0;
432 uint64_t contextidr_ns;
433 uint64_t _unused_contextidr_1;
434 uint64_t contextidr_s;
435 };
436 uint64_t contextidr_el[4];
437 };
438 union { /* User RW Thread register. */
439 struct {
440 uint64_t tpidrurw_ns;
441 uint64_t tpidrprw_ns;
442 uint64_t htpidr;
443 uint64_t _tpidr_el3;
444 };
445 uint64_t tpidr_el[4];
446 };
Richard Henderson9e5ec742022-06-20 10:51:45 -0700447 uint64_t tpidr2_el0;
Fabian Aggeler54bf36e2014-12-11 12:07:52 +0000448 /* The secure banks of these registers don't map anywhere */
449 uint64_t tpidrurw_s;
450 uint64_t tpidrprw_s;
451 uint64_t tpidruro_s;
452
453 union { /* User RO Thread register. */
454 uint64_t tpidruro_ns;
455 uint64_t tpidrro_el[1];
456 };
Peter Maydella7adc4b2014-02-26 17:20:05 +0000457 uint64_t c14_cntfrq; /* Counter Frequency register */
458 uint64_t c14_cntkctl; /* Timer Control register */
Richard Hendersonbb461332023-01-15 07:16:33 -1000459 uint64_t cnthctl_el2; /* Counter/Timer Hyp Control register */
Edgar E. Iglesiasedac4d82015-08-13 11:26:17 +0100460 uint64_t cntvoff_el2; /* Counter Virtual Offset register */
Peter Maydell55d284a2013-08-20 14:54:31 +0100461 ARMGenericTimer c14_timer[NUM_GTIMERS];
balrogc1713132007-04-30 01:26:42 +0000462 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
balrogc3d26892007-07-29 17:57:26 +0000463 uint32_t c15_ticonfig; /* TI925T configuration byte. */
464 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
465 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
466 uint32_t c15_threadid; /* TI debugger thread-ID. */
Mark Langsdorf7da362d2012-01-05 15:49:06 +0000467 uint32_t c15_config_base_address; /* SCU base address. */
468 uint32_t c15_diagnostic; /* diagnostic register */
469 uint32_t c15_power_diagnostic;
470 uint32_t c15_power_control; /* power control */
Peter Maydell0b454512014-02-26 17:20:05 +0000471 uint64_t dbgbvr[16]; /* breakpoint value registers */
472 uint64_t dbgbcr[16]; /* breakpoint control registers */
473 uint64_t dbgwvr[16]; /* watchpoint value registers */
474 uint64_t dbgwcr[16]; /* watchpoint control registers */
Evgeny Iakovlev5fc83f12023-01-20 16:59:28 +0100475 uint64_t dbgclaim; /* DBGCLAIM bits */
Peter Maydell3a298202014-08-19 18:56:26 +0100476 uint64_t mdscr_el1;
Davorin Mista1424ca82015-10-16 11:14:53 +0100477 uint64_t oslsr_el1; /* OS Lock Status */
Peter Maydellf94a6df2022-07-07 11:38:36 +0100478 uint64_t osdlr_el1; /* OS DoubleLock status */
Sergey Fedorov14cc7b52015-10-16 11:14:54 +0100479 uint64_t mdcr_el2;
Peter Maydell5513c3a2016-02-11 11:17:30 +0000480 uint64_t mdcr_el3;
Aaron Lindsay5d05b9d2019-01-21 10:23:13 +0000481 /* Stores the architectural value of the counter *the last time it was
482 * updated* by pmccntr_op_start. Accesses should always be surrounded
483 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest
484 * architecturally-correct value is being read/set.
Alistair Francis7c2cb422014-03-10 14:56:28 +0000485 */
Alistair Francisc92c0682014-08-29 15:00:29 +0100486 uint64_t c15_ccnt;
Aaron Lindsay5d05b9d2019-01-21 10:23:13 +0000487 /* Stores the delta between the architectural value and the underlying
488 * cycle count during normal operation. It is used to update c15_ccnt
489 * to be the correct architectural value before accesses. During
490 * accesses, c15_ccnt_delta contains the underlying count being used
491 * for the access, after which it reverts to the delta value in
492 * pmccntr_op_finish.
493 */
494 uint64_t c15_ccnt_delta;
Aaron Lindsay5ecdd3e2019-01-21 10:23:14 +0000495 uint64_t c14_pmevcntr[31];
496 uint64_t c14_pmevcntr_delta[31];
497 uint64_t c14_pmevtyper[31];
Alistair Francis85214662014-08-29 15:00:29 +0100498 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
Edgar E. Iglesias731de9e2015-09-14 14:39:50 +0100499 uint64_t vpidr_el2; /* Virtualization Processor ID Register */
Edgar E. Iglesiasf0d574d2015-09-14 14:39:51 +0100500 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
Richard Henderson4b779ce2020-06-25 20:31:05 -0700501 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
502 uint64_t gcr_el1;
503 uint64_t rgsr_el1;
Richard Henderson58e93b42022-05-06 13:02:31 -0500504
505 /* Minimal RAS registers */
506 uint64_t disr_el1;
507 uint64_t vdisr_el2;
508 uint64_t vsesr_el2;
Peter Maydell15126d92023-01-30 18:24:44 +0000509
510 /*
511 * Fine-Grained Trap registers. We store these as arrays so the
512 * access checking code doesn't have to manually select
513 * HFGRTR_EL2 vs HFDFGRTR_EL2 etc when looking up the bit to test.
514 * FEAT_FGT2 will add more elements to these arrays.
515 */
516 uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */
517 uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */
518 uint64_t fgt_exec[1]; /* HFGITR */
Richard Hendersonef1febe2023-06-23 11:15:44 +0100519
520 /* RME registers */
521 uint64_t gpccr_el3;
522 uint64_t gptbr_el3;
523 uint64_t mfar_el3;
Peter Maydellb5ba6c92024-01-09 14:43:52 +0000524
525 /* NV2 register */
526 uint64_t vncr_el2;
bellardb5ff1b32005-11-26 10:38:39 +0000527 } cp15;
pbrook40f137e2006-02-20 00:33:36 +0000528
pbrook9ee6e8b2007-11-11 00:04:49 +0000529 struct {
Peter Maydellfb602cb2017-09-07 13:54:54 +0100530 /* M profile has up to 4 stack pointers:
531 * a Main Stack Pointer and a Process Stack Pointer for each
532 * of the Secure and Non-Secure states. (If the CPU doesn't support
533 * the security extension then it has only two SPs.)
534 * In QEMU we always store the currently active SP in regs[13],
535 * and the non-active SP for the current security state in
536 * v7m.other_sp. The stack pointers for the inactive security state
537 * are stored in other_ss_msp and other_ss_psp.
538 * switch_v7m_security_state() is responsible for rearranging them
539 * when we change security state.
540 */
pbrook9ee6e8b2007-11-11 00:04:49 +0000541 uint32_t other_sp;
Peter Maydellfb602cb2017-09-07 13:54:54 +0100542 uint32_t other_ss_msp;
543 uint32_t other_ss_psp;
Peter Maydell4a167242017-09-14 18:43:16 +0100544 uint32_t vecbase[M_REG_NUM_BANKS];
545 uint32_t basepri[M_REG_NUM_BANKS];
546 uint32_t control[M_REG_NUM_BANKS];
547 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
548 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
Peter Maydell2c4da502017-01-27 15:20:23 +0000549 uint32_t hfsr; /* HardFault Status */
550 uint32_t dfsr; /* Debug Fault Status Register */
Peter Maydellbed079d2017-10-06 16:46:48 +0100551 uint32_t sfsr; /* Secure Fault Status Register */
Peter Maydell4a167242017-09-14 18:43:16 +0100552 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
Peter Maydell2c4da502017-01-27 15:20:23 +0000553 uint32_t bfar; /* BusFault Address */
Peter Maydellbed079d2017-10-06 16:46:48 +0100554 uint32_t sfar; /* Secure Fault Address Register */
Peter Maydell4a167242017-09-14 18:43:16 +0100555 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
pbrook9ee6e8b2007-11-11 00:04:49 +0000556 int exception;
Peter Maydell4a167242017-09-14 18:43:16 +0100557 uint32_t primask[M_REG_NUM_BANKS];
558 uint32_t faultmask[M_REG_NUM_BANKS];
Peter Maydell3b2e9342017-09-12 19:13:52 +0100559 uint32_t aircr; /* only holds r/w state if security extn implemented */
Peter Maydell1e577cc2017-09-07 13:54:52 +0100560 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
Peter Maydell43bbce72018-02-15 18:29:37 +0000561 uint32_t csselr[M_REG_NUM_BANKS];
Peter Maydell24ac0fb2018-02-15 18:29:37 +0000562 uint32_t scr[M_REG_NUM_BANKS];
Peter Maydell57bb3152018-02-15 18:29:38 +0000563 uint32_t msplim[M_REG_NUM_BANKS];
564 uint32_t psplim[M_REG_NUM_BANKS];
Peter Maydelld33abe82019-04-29 17:35:58 +0100565 uint32_t fpcar[M_REG_NUM_BANKS];
566 uint32_t fpccr[M_REG_NUM_BANKS];
567 uint32_t fpdscr[M_REG_NUM_BANKS];
568 uint32_t cpacr[M_REG_NUM_BANKS];
569 uint32_t nsacr;
Peter Maydellb26b5622021-05-20 16:28:38 +0100570 uint32_t ltpsize;
Peter Maydell7c3d47d2021-05-20 16:28:37 +0100571 uint32_t vpr;
pbrook9ee6e8b2007-11-11 00:04:49 +0000572 } v7m;
573
Peter Maydellabf11722014-04-15 19:18:38 +0100574 /* Information associated with an exception about to be taken:
575 * code which raises an exception must set cs->exception_index and
576 * the relevant parts of this structure; the cpu_do_interrupt function
577 * will then set the guest-visible registers as part of the exception
578 * entry process.
579 */
580 struct {
581 uint32_t syndrome; /* AArch64 format syndrome register */
582 uint32_t fsr; /* AArch32 format fault status register info */
583 uint64_t vaddress; /* virtual addr associated with exception, if any */
Greg Bellows73710362015-05-29 11:28:50 +0100584 uint32_t target_el; /* EL the exception should be targeted for */
Peter Maydellabf11722014-04-15 19:18:38 +0100585 /* If we implement EL2 we will also need to store information
586 * about the intermediate physical address for stage 2 faults.
587 */
588 } exception;
589
Dongjiu Geng202ccb62018-10-24 07:50:16 +0100590 /* Information associated with an SError */
591 struct {
592 uint8_t pending;
593 uint8_t has_esr;
594 uint64_t esr;
595 } serror;
596
Beata Michalska1711bfa2020-07-03 16:59:42 +0100597 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
598
Peter Maydelled89f072018-11-13 10:47:59 +0000599 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
600 uint32_t irq_line_state;
601
pbrookfe1479c2008-12-19 13:18:36 +0000602 /* Thumb-2 EE state. */
603 uint32_t teecr;
604 uint32_t teehbr;
605
bellardb7bcbe92005-02-22 19:27:29 +0000606 /* VFP coprocessor state. */
607 struct {
Richard Hendersonc39c2b92018-02-09 10:40:31 +0000608 ARMVectorReg zregs[32];
bellardb7bcbe92005-02-22 19:27:29 +0000609
Richard Henderson3c7d3082018-01-22 19:53:46 -0800610#ifdef TARGET_AARCH64
611 /* Store FFR as pregs[16] to make it easier to treat as any other. */
Richard Henderson028e2a72018-05-18 17:48:08 +0100612#define FFR_PRED_NUM 16
Richard Henderson3c7d3082018-01-22 19:53:46 -0800613 ARMPredicateReg pregs[17];
Richard Henderson516e2462018-05-18 17:48:08 +0100614 /* Scratch space for aa64 sve predicate temporary. */
615 ARMPredicateReg preg_tmp;
Richard Henderson3c7d3082018-01-22 19:53:46 -0800616#endif
617
bellardb7bcbe92005-02-22 19:27:29 +0000618 /* We store these fpcsr fields separately for convenience. */
Richard Hendersona4d58462019-02-15 09:56:41 +0000619 uint32_t qc[4] QEMU_ALIGNED(16);
bellardb7bcbe92005-02-22 19:27:29 +0000620 int vec_len;
621 int vec_stride;
622
Richard Hendersona4d58462019-02-15 09:56:41 +0000623 uint32_t xregs[16];
624
Richard Henderson516e2462018-05-18 17:48:08 +0100625 /* Scratch space for aa32 neon expansion. */
pbrook9ee6e8b2007-11-11 00:04:49 +0000626 uint32_t scratch[8];
ths3b46e622007-09-17 08:09:54 +0000627
Alex Bennéed81ce0e2018-03-01 11:05:47 +0000628 /* There are a number of distinct float control structures:
629 *
630 * fp_status: is the "normal" fp status.
631 * fp_status_fp16: used for half-precision calculations
632 * standard_fp_status : the ARM "Standard FPSCR Value"
Peter Maydellaaae5632020-08-06 11:44:52 +0100633 * standard_fp_status_fp16 : used for half-precision
634 * calculations with the ARM "Standard FPSCR Value"
Alex Bennéed81ce0e2018-03-01 11:05:47 +0000635 *
636 * Half-precision operations are governed by a separate
637 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
638 * status structure to control this.
639 *
640 * The "Standard FPSCR", ie default-NaN, flush-to-zero,
641 * round-to-nearest and is used by any operations (generally
642 * Neon) which the architecture defines as controlled by the
643 * standard FPSCR value rather than the FPSCR.
Peter Maydell3a492f32011-01-14 20:39:18 +0100644 *
Peter Maydellaaae5632020-08-06 11:44:52 +0100645 * The "standard FPSCR but for fp16 ops" is needed because
646 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than
647 * using a fixed value for it.
648 *
Peter Maydell3a492f32011-01-14 20:39:18 +0100649 * To avoid having to transfer exception bits around, we simply
650 * say that the FPSCR cumulative exception flags are the logical
Peter Maydellaaae5632020-08-06 11:44:52 +0100651 * OR of the flags in the four fp statuses. This relies on the
Peter Maydell3a492f32011-01-14 20:39:18 +0100652 * only thing which needs to read the exception flags being
653 * an explicit FPSCR read.
654 */
bellard53cd6632005-03-13 18:50:23 +0000655 float_status fp_status;
Alex Bennéed81ce0e2018-03-01 11:05:47 +0000656 float_status fp_status_f16;
Peter Maydell3a492f32011-01-14 20:39:18 +0100657 float_status standard_fp_status;
Peter Maydellaaae5632020-08-06 11:44:52 +0100658 float_status standard_fp_status_f16;
Richard Henderson5be5e8e2018-01-22 19:53:48 -0800659
Richard Hendersonde561982022-06-20 10:51:50 -0700660 uint64_t zcr_el[4]; /* ZCR_EL[1-3] */
661 uint64_t smcr_el[4]; /* SMCR_EL[1-3] */
bellardb7bcbe92005-02-22 19:27:29 +0000662 } vfp;
Richard Henderson0f084292023-06-06 10:19:34 +0100663
Peter Maydell03d05e22014-01-04 22:15:47 +0000664 uint64_t exclusive_addr;
665 uint64_t exclusive_val;
Richard Henderson0f084292023-06-06 10:19:34 +0100666 /*
667 * Contains the 'val' for the second 64-bit register of LDXP, which comes
668 * from the higher address, not the high part of a complete 128-bit value.
669 * In some ways it might be more convenient to record the exclusive value
670 * as the low and high halves of a 128 bit data value, but the current
671 * semantics of these fields are baked into the migration format.
672 */
Peter Maydell03d05e22014-01-04 22:15:47 +0000673 uint64_t exclusive_high;
bellardb7bcbe92005-02-22 19:27:29 +0000674
balrog18c9b562007-04-30 02:02:17 +0000675 /* iwMMXt coprocessor state. */
676 struct {
677 uint64_t regs[16];
678 uint64_t val;
679
680 uint32_t cregs[16];
681 } iwmmxt;
682
Richard Henderson991ad912019-01-21 10:23:11 +0000683#ifdef TARGET_AARCH64
Richard Henderson108b3ba2019-03-14 17:28:32 -0700684 struct {
685 ARMPACKey apia;
686 ARMPACKey apib;
687 ARMPACKey apda;
688 ARMPACKey apdb;
689 ARMPACKey apga;
690 } keys;
Richard Henderson7cb1e612022-05-06 13:02:38 -0500691
692 uint64_t scxtnum_el[4];
Richard Hendersondc993a02022-06-20 10:51:53 -0700693
694 /*
695 * SME ZA storage -- 256 x 256 byte array, with bytes in host word order,
696 * as we do with vfp.zregs[]. This corresponds to the architectural ZA
697 * array, where ZA[N] is in the least-significant bytes of env->zarray[N].
698 * When SVL is less than the architectural maximum, the accessible
699 * storage is restricted, such that if the SVL is X bytes the guest can
700 * see only the bottom X elements of zarray[], and only the least
701 * significant X bytes of each element of the array. (In other words,
702 * the observable part is always square.)
703 *
704 * The ZA storage can also be considered as a set of square tiles of
705 * elements of different sizes. The mapping from tiles to the ZA array
706 * is architecturally defined, such that for tiles of elements of esz
707 * bytes, the Nth row (or "horizontal slice") of tile T is in
708 * ZA[T + N * esz]. Note that this means that each tile is not contiguous
709 * in the ZA storage, because its rows are striped through the ZA array.
710 *
711 * Because this is so large, keep this toward the end of the reset area,
712 * to keep the offsets into the rest of the structure smaller.
713 */
714 ARMVectorReg zarray[ARM_MAX_VQ * 16];
Richard Henderson991ad912019-01-21 10:23:11 +0000715#endif
716
Peter Maydell46747d12014-09-29 18:48:46 +0100717 struct CPUBreakpoint *cpu_breakpoint[16];
Peter Maydell9ee98ce2014-09-12 14:06:49 +0100718 struct CPUWatchpoint *cpu_watchpoint[16];
719
Richard Hendersonf3639a62022-10-10 20:18:57 -0700720 /* Optional fault info across tlb lookup. */
721 ARMMMUFaultInfo *tlb_fi;
722
Alex Bennée1f5c00c2016-11-14 14:19:17 +0000723 /* Fields up to this point are cleared by a CPU reset */
724 struct {} end_reset_fields;
725
Richard Hendersone8b5fae2019-03-23 11:35:53 -0700726 /* Fields after this point are preserved across CPU reset. */
Lars Munch9ba8c3f2010-05-08 22:42:43 +0200727
Peter Maydell581be092012-04-20 17:58:31 +0000728 /* Internal CPU feature flags. */
Peter Maydell918f5dc2012-07-12 10:59:06 +0000729 uint64_t features;
Peter Maydell581be092012-04-20 17:58:31 +0000730
Peter Crosthwaite6cb0b012015-06-19 14:17:44 +0100731 /* PMSAv7 MPU */
732 struct {
733 uint32_t *drbar;
734 uint32_t *drsr;
735 uint32_t *dracr;
Peter Maydell4a167242017-09-14 18:43:16 +0100736 uint32_t rnr[M_REG_NUM_BANKS];
Peter Crosthwaite6cb0b012015-06-19 14:17:44 +0100737 } pmsav7;
738
Peter Maydell0e1a46b2017-09-07 13:54:51 +0100739 /* PMSAv8 MPU */
740 struct {
741 /* The PMSAv8 implementation also shares some PMSAv7 config
742 * and state:
743 * pmsav7.rnr (region number register)
744 * pmsav7_dregion (number of configured regions)
745 */
Peter Maydell4a167242017-09-14 18:43:16 +0100746 uint32_t *rbar[M_REG_NUM_BANKS];
747 uint32_t *rlar[M_REG_NUM_BANKS];
Tobias Röhmel761c4642022-12-06 11:25:02 +0100748 uint32_t *hprbar;
749 uint32_t *hprlar;
Peter Maydell4a167242017-09-14 18:43:16 +0100750 uint32_t mair0[M_REG_NUM_BANKS];
751 uint32_t mair1[M_REG_NUM_BANKS];
Tobias Röhmel761c4642022-12-06 11:25:02 +0100752 uint32_t hprselr;
Peter Maydell0e1a46b2017-09-07 13:54:51 +0100753 } pmsav8;
754
Peter Maydell9901c572017-10-06 16:46:49 +0100755 /* v8M SAU */
756 struct {
757 uint32_t *rbar;
758 uint32_t *rlar;
759 uint32_t rnr;
760 uint32_t ctrl;
761 } sau;
762
Philippe Mathieu-Daudé1701d702023-02-06 23:34:58 +0100763#if !defined(CONFIG_USER_ONLY)
Philippe Mathieu-Daudé8f4e07c2023-02-06 23:35:01 +0100764 NVICState *nvic;
Philippe Mathieu-Daudé2a94a502023-02-06 23:34:59 +0100765 const struct arm_boot_info *boot_info;
Vijaya Kumar Kd3a3e522017-02-23 17:21:12 +0530766 /* Store GICv3CPUState to access from this struct */
767 void *gicv3state;
Philippe Mathieu-Daudé1701d702023-02-06 23:34:58 +0100768#else /* CONFIG_USER_ONLY */
Philippe Mathieu-Daudé26f08562023-02-06 23:34:57 +0100769 /* For usermode syscall translation. */
770 bool eabi;
771#endif /* CONFIG_USER_ONLY */
Richard Henderson0e0c0302021-02-12 10:48:51 -0800772
773#ifdef TARGET_TAGGED_ADDRESSES
774 /* Linux syscall tagged address support */
775 bool tagged_addr_enable;
776#endif
bellard2c0262a2003-09-30 20:34:21 +0000777} CPUARMState;
778
Thomas Huth5fda95042020-05-04 19:24:45 +0200779static inline void set_feature(CPUARMState *env, int feature)
780{
781 env->features |= 1ULL << feature;
782}
783
784static inline void unset_feature(CPUARMState *env, int feature)
785{
786 env->features &= ~(1ULL << feature);
787}
788
Paolo Bonzini74e75562016-03-15 13:49:25 +0100789/**
Aaron Lindsay08267482018-04-26 11:04:39 +0100790 * ARMELChangeHookFn:
Peter Maydellbd7d00f2016-06-17 15:23:46 +0100791 * type of a function which can be registered via arm_register_el_change_hook()
792 * to get callbacks when the CPU changes its exception level or mode.
793 */
Aaron Lindsay08267482018-04-26 11:04:39 +0100794typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
795typedef struct ARMELChangeHook ARMELChangeHook;
796struct ARMELChangeHook {
797 ARMELChangeHookFn *hook;
798 void *opaque;
799 QLIST_ENTRY(ARMELChangeHook) node;
800};
Alex Bennée062ba092017-02-23 18:29:23 +0000801
802/* These values map onto the return values for
803 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
804typedef enum ARMPSCIState {
Andrew Jonesd5affb02017-03-14 11:28:54 +0000805 PSCI_ON = 0,
806 PSCI_OFF = 1,
Alex Bennée062ba092017-02-23 18:29:23 +0000807 PSCI_ON_PENDING = 2
808} ARMPSCIState;
809
Richard Henderson962fcbf2018-10-24 07:50:16 +0100810typedef struct ARMISARegisters ARMISARegisters;
811
Richard Henderson7f9e25a2022-06-20 10:51:56 -0700812/*
813 * In map, each set bit is a supported vector length of (bit-number + 1) * 16
814 * bytes, i.e. each bit number + 1 is the vector length in quadwords.
815 *
816 * While processing properties during initialization, corresponding init bits
817 * are set for bits in sve_vq_map that have been set by properties.
818 *
819 * Bits set in supported represent valid vector lengths for the CPU type.
820 */
821typedef struct {
822 uint32_t map, init, supported;
823} ARMVQMap;
824
Peter Maydellbd7d00f2016-06-17 15:23:46 +0100825/**
Paolo Bonzini74e75562016-03-15 13:49:25 +0100826 * ARMCPU:
827 * @env: #CPUARMState
828 *
829 * An ARM CPU core.
830 */
Philippe Mathieu-Daudéb36e2392022-02-14 17:15:16 +0100831struct ArchCPU {
Paolo Bonzini74e75562016-03-15 13:49:25 +0100832 CPUState parent_obj;
Paolo Bonzini74e75562016-03-15 13:49:25 +0100833
834 CPUARMState env;
835
836 /* Coprocessor information */
837 GHashTable *cp_regs;
838 /* For marshalling (mostly coprocessor) register state between the
839 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
840 * we use these arrays.
841 */
842 /* List of register indexes managed via these arrays; (full KVM style
843 * 64 bit indexes, not CPRegInfo 32 bit indexes)
844 */
845 uint64_t *cpreg_indexes;
846 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
847 uint64_t *cpreg_values;
848 /* Length of the indexes, values, reset_values arrays */
849 int32_t cpreg_array_len;
850 /* These are used only for migration: incoming data arrives in
851 * these fields and is sanity checked in post_load before copying
852 * to the working data structures above.
853 */
854 uint64_t *cpreg_vmstate_indexes;
855 uint64_t *cpreg_vmstate_values;
856 int32_t cpreg_vmstate_array_len;
857
Alex Bennée448d4d12020-03-16 17:21:42 +0000858 DynamicGDBXMLInfo dyn_sysreg_xml;
Alex Bennéed12379c2020-03-16 17:21:45 +0000859 DynamicGDBXMLInfo dyn_svereg_xml;
Richard Henderson7d8b28b2023-02-27 11:33:29 -1000860 DynamicGDBXMLInfo dyn_m_systemreg_xml;
861 DynamicGDBXMLInfo dyn_m_secextreg_xml;
Abdallah Bouassida200bf5b2018-05-18 17:48:07 +0100862
Paolo Bonzini74e75562016-03-15 13:49:25 +0100863 /* Timers used by the generic (architected) timer */
864 QEMUTimer *gt_timer[NUM_GTIMERS];
Aaron Lindsay OS4e7beb02019-02-01 14:55:45 +0000865 /*
866 * Timer used by the PMU. Its state is restored after migration by
867 * pmu_op_finish() - it does not need other handling during migration
868 */
869 QEMUTimer *pmu_timer;
Paolo Bonzini74e75562016-03-15 13:49:25 +0100870 /* GPIO outputs for generic timer */
871 qemu_irq gt_timer_outputs[NUM_GTIMERS];
Peter Maydellaa1b3112017-01-20 11:15:09 +0000872 /* GPIO output for GICv3 maintenance interrupt signal */
873 qemu_irq gicv3_maintenance_interrupt;
Andrew Jones07f48732017-09-04 15:21:53 +0100874 /* GPIO output for the PMU interrupt */
875 qemu_irq pmu_interrupt;
Paolo Bonzini74e75562016-03-15 13:49:25 +0100876
877 /* MemoryRegion to use for secure physical accesses */
878 MemoryRegion *secure_memory;
879
Richard Henderson8bce44a2020-06-25 20:31:41 -0700880 /* MemoryRegion to use for allocation tag accesses */
881 MemoryRegion *tag_memory;
882 MemoryRegion *secure_tag_memory;
883
Peter Maydell181962f2018-03-02 10:45:36 +0000884 /* For v8M, pointer to the IDAU interface provided by board/SoC */
885 Object *idau;
886
Paolo Bonzini74e75562016-03-15 13:49:25 +0100887 /* 'compatible' string for this CPU for Linux device trees */
888 const char *dtb_compatible;
889
890 /* PSCI version for this CPU
891 * Bits[31:16] = Major Version
892 * Bits[15:0] = Minor Version
893 */
894 uint32_t psci_version;
895
Alex Bennée062ba092017-02-23 18:29:23 +0000896 /* Current power state, access guarded by BQL */
897 ARMPSCIState power_state;
898
Peter Maydellc25bd182017-01-20 11:15:10 +0000899 /* CPU has virtualization extension */
900 bool has_el2;
Paolo Bonzini74e75562016-03-15 13:49:25 +0100901 /* CPU has security extension */
902 bool has_el3;
Shannon Zhao5c0a3812016-06-14 15:59:12 +0100903 /* CPU has PMU (Performance Monitor Unit) */
904 bool has_pmu;
Peter Maydell97a28b02019-05-17 18:40:43 +0100905 /* CPU has VFP */
906 bool has_vfp;
Cédric Le Goater42bea952023-06-07 06:39:43 +0200907 /* CPU has 32 VFP registers */
908 bool has_vfp_d32;
Peter Maydell97a28b02019-05-17 18:40:43 +0100909 /* CPU has Neon */
910 bool has_neon;
Peter Maydellea90db02019-05-17 18:40:44 +0100911 /* CPU has M-profile DSP extension */
912 bool has_dsp;
Paolo Bonzini74e75562016-03-15 13:49:25 +0100913
914 /* CPU has memory protection unit */
915 bool has_mpu;
916 /* PMSAv7 MPU number of supported regions */
917 uint32_t pmsav7_dregion;
Tobias Röhmel761c4642022-12-06 11:25:02 +0100918 /* PMSAv8 MPU number of supported hyp regions */
919 uint32_t pmsav8r_hdregion;
Peter Maydell9901c572017-10-06 16:46:49 +0100920 /* v8M SAU number of supported regions */
921 uint32_t sau_sregion;
Paolo Bonzini74e75562016-03-15 13:49:25 +0100922
923 /* PSCI conduit used to invoke PSCI methods
924 * 0 - disabled, 1 - smc, 2 - hvc
925 */
926 uint32_t psci_conduit;
927
Peter Maydell38e2a772018-03-02 10:45:37 +0000928 /* For v8M, initial value of the Secure VTOR */
929 uint32_t init_svtor;
Peter Maydell7cda2142021-05-20 16:28:40 +0100930 /* For v8M, initial value of the Non-secure VTOR */
931 uint32_t init_nsvtor;
Peter Maydell38e2a772018-03-02 10:45:37 +0000932
Paolo Bonzini74e75562016-03-15 13:49:25 +0100933 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
934 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
935 */
936 uint32_t kvm_target;
937
Philippe Mathieu-Daudécf43b5b2023-04-04 11:12:38 +0200938#ifdef CONFIG_KVM
Paolo Bonzini74e75562016-03-15 13:49:25 +0100939 /* KVM init features for this CPU */
940 uint32_t kvm_init_features[7];
941
Andrew Jonese5ac4202020-01-30 16:02:06 +0000942 /* KVM CPU state */
943
944 /* KVM virtual time adjustment */
945 bool kvm_adjvtime;
946 bool kvm_vtime_dirty;
947 uint64_t kvm_vtime;
948
Andrew Jones68970d12020-10-01 08:17:18 +0200949 /* KVM steal time */
950 OnOffAuto kvm_steal_time;
Philippe Mathieu-Daudécf43b5b2023-04-04 11:12:38 +0200951#endif /* CONFIG_KVM */
Andrew Jones68970d12020-10-01 08:17:18 +0200952
Paolo Bonzini74e75562016-03-15 13:49:25 +0100953 /* Uniprocessor system with MP extensions */
954 bool mp_is_up;
955
Peter Maydellc4487d72018-03-09 17:09:44 +0000956 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init
957 * and the probe failed (so we need to report the error in realize)
958 */
959 bool host_cpu_probe_failed;
960
Alistair Francisf9a69712018-03-09 17:09:43 +0000961 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
962 * register.
963 */
964 int32_t core_count;
965
Paolo Bonzini74e75562016-03-15 13:49:25 +0100966 /* The instance init functions for implementation-specific subclasses
967 * set these fields to specify the implementation-dependent values of
968 * various constant registers and reset values of non-constant
969 * registers.
970 * Some of these might become QOM properties eventually.
971 * Field names match the official register names as defined in the
972 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
973 * is used for reset values of non-constant registers; no reset_
974 * prefix means a constant register.
Richard Henderson47576b92018-10-24 07:50:16 +0100975 * Some of these registers are split out into a substructure that
976 * is shared with the translators to control the ISA.
Peter Maydell1548a7b2020-02-14 17:51:07 +0000977 *
978 * Note that if you add an ID register to the ARMISARegisters struct
979 * you need to also update the 32-bit and 64-bit versions of the
980 * kvm_arm_get_host_cpu_features() function to correctly populate the
981 * field by reading the value from the KVM vCPU.
Paolo Bonzini74e75562016-03-15 13:49:25 +0100982 */
Richard Henderson47576b92018-10-24 07:50:16 +0100983 struct ARMISARegisters {
984 uint32_t id_isar0;
985 uint32_t id_isar1;
986 uint32_t id_isar2;
987 uint32_t id_isar3;
988 uint32_t id_isar4;
989 uint32_t id_isar5;
990 uint32_t id_isar6;
Peter Maydell10054012020-02-14 17:51:13 +0000991 uint32_t id_mmfr0;
992 uint32_t id_mmfr1;
993 uint32_t id_mmfr2;
994 uint32_t id_mmfr3;
995 uint32_t id_mmfr4;
Peter Maydell32957aa2022-08-19 12:00:49 +0100996 uint32_t id_mmfr5;
Peter Maydell8a130a72020-09-10 18:38:52 +0100997 uint32_t id_pfr0;
998 uint32_t id_pfr1;
Richard Henderson1d51bc92021-01-28 12:00:09 +0000999 uint32_t id_pfr2;
Richard Henderson47576b92018-10-24 07:50:16 +01001000 uint32_t mvfr0;
1001 uint32_t mvfr1;
1002 uint32_t mvfr2;
Peter Maydella6179532020-02-14 17:51:03 +00001003 uint32_t id_dfr0;
Peter Maydelld22c5642022-08-19 12:00:50 +01001004 uint32_t id_dfr1;
Peter Maydell4426d362020-02-14 17:51:06 +00001005 uint32_t dbgdidr;
Peter Maydell09754ca2022-06-30 20:41:15 +01001006 uint32_t dbgdevid;
1007 uint32_t dbgdevid1;
Richard Henderson47576b92018-10-24 07:50:16 +01001008 uint64_t id_aa64isar0;
1009 uint64_t id_aa64isar1;
Aaron Lindsaya969fe92023-08-29 16:23:25 -07001010 uint64_t id_aa64isar2;
Richard Henderson47576b92018-10-24 07:50:16 +01001011 uint64_t id_aa64pfr0;
1012 uint64_t id_aa64pfr1;
Peter Maydell3dc91dd2018-12-13 14:40:56 +00001013 uint64_t id_aa64mmfr0;
1014 uint64_t id_aa64mmfr1;
Richard Henderson64761e12020-02-08 12:58:13 +00001015 uint64_t id_aa64mmfr2;
Peter Maydell2a609df2020-02-14 17:51:04 +00001016 uint64_t id_aa64dfr0;
1017 uint64_t id_aa64dfr1;
Richard Henderson2dc10fa2021-05-24 18:02:27 -07001018 uint64_t id_aa64zfr0;
Richard Henderson414c54d2022-06-08 19:38:59 +01001019 uint64_t id_aa64smfr0;
Peter Maydell24526bb2022-05-13 13:28:52 +01001020 uint64_t reset_pmcr_el0;
Richard Henderson47576b92018-10-24 07:50:16 +01001021 } isar;
Philippe Mathieu-Daudée544f802020-04-28 19:26:34 +02001022 uint64_t midr;
Paolo Bonzini74e75562016-03-15 13:49:25 +01001023 uint32_t revidr;
1024 uint32_t reset_fpsid;
Leif Lindholma5fd3192021-01-08 18:51:51 +00001025 uint64_t ctr;
Paolo Bonzini74e75562016-03-15 13:49:25 +01001026 uint32_t reset_sctlr;
Aaron Lindsaycad86732019-01-21 10:23:14 +00001027 uint64_t pmceid0;
1028 uint64_t pmceid1;
Paolo Bonzini74e75562016-03-15 13:49:25 +01001029 uint32_t id_afr0;
Paolo Bonzini74e75562016-03-15 13:49:25 +01001030 uint64_t id_aa64afr0;
1031 uint64_t id_aa64afr1;
Leif Lindholmf6450bc2021-01-08 18:51:50 +00001032 uint64_t clidr;
Paolo Bonzini74e75562016-03-15 13:49:25 +01001033 uint64_t mp_affinity; /* MP ID without feature bits */
1034 /* The elements of this array are the CCSIDR values for each cache,
1035 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
1036 */
Peter Maydell957e6152020-02-24 18:26:26 +00001037 uint64_t ccsidr[16];
Paolo Bonzini74e75562016-03-15 13:49:25 +01001038 uint64_t reset_cbar;
1039 uint32_t reset_auxcr;
1040 bool reset_hivecs;
Richard Hendersonef1febe2023-06-23 11:15:44 +01001041 uint8_t reset_l0gptsz;
Richard Hendersoneb942842021-01-11 13:57:39 -10001042
1043 /*
1044 * Intermediate values used during property parsing.
Richard Henderson69b22652022-03-01 11:59:57 -10001045 * Once finalized, the values should be read from ID_AA64*.
Richard Hendersoneb942842021-01-11 13:57:39 -10001046 */
1047 bool prop_pauth;
1048 bool prop_pauth_impdef;
Richard Henderson399e5e72023-08-29 16:23:28 -07001049 bool prop_pauth_qarma3;
Richard Henderson69b22652022-03-01 11:59:57 -10001050 bool prop_lpa2;
Richard Hendersoneb942842021-01-11 13:57:39 -10001051
Paolo Bonzini74e75562016-03-15 13:49:25 +01001052 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
Richard Hendersonae4acc62023-08-31 09:45:14 +01001053 uint8_t dcz_blocksize;
Richard Henderson851ec6e2023-08-31 09:45:14 +01001054 /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
1055 uint8_t gm_blocksize;
Richard Hendersonae4acc62023-08-31 09:45:14 +01001056
Edgar E. Iglesias4a7319b2022-03-16 17:46:41 +01001057 uint64_t rvbar_prop; /* Property/input signals. */
Peter Maydellbd7d00f2016-06-17 15:23:46 +01001058
Peter Maydelle45868a2017-01-20 11:15:09 +00001059 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
1060 int gic_num_lrs; /* number of list registers */
1061 int gic_vpribits; /* number of virtual priority bits */
1062 int gic_vprebits; /* number of virtual preemption bits */
Peter Maydell39f29e52022-05-12 16:14:56 +01001063 int gic_pribits; /* number of physical priority bits */
Peter Maydelle45868a2017-01-20 11:15:09 +00001064
Julian Brown3a062d52017-02-07 18:29:59 +00001065 /* Whether the cfgend input is high (i.e. this CPU should reset into
1066 * big-endian mode). This setting isn't used directly: instead it modifies
1067 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
1068 * architecture version.
1069 */
1070 bool cfgend;
1071
Aaron Lindsayb5c53d12018-04-26 11:04:39 +01001072 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
Aaron Lindsay08267482018-04-26 11:04:39 +01001073 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
Igor Mammedov15f8b142017-05-30 18:24:00 +02001074
1075 int32_t node_id; /* NUMA node this CPU belongs to */
Alexander Graf5d721b72017-07-11 11:21:26 +01001076
1077 /* Used to synchronize KVM and QEMU in-kernel device levels */
1078 uint8_t device_irq_level;
Richard Hendersonadf92ea2018-08-16 14:05:28 +01001079
1080 /* Used to set the maximum vector length the cpu will support. */
1081 uint32_t sve_max_vq;
Andrew Jones0df91422019-10-31 15:27:29 +01001082
Richard Hendersonb3d52802021-07-23 10:33:44 -10001083#ifdef CONFIG_USER_ONLY
1084 /* Used to set the default vector length at process start. */
1085 uint32_t sve_default_vq;
Richard Hendersone74c0972022-06-20 10:52:01 -07001086 uint32_t sme_default_vq;
Richard Hendersonb3d52802021-07-23 10:33:44 -10001087#endif
1088
Richard Henderson7f9e25a2022-06-20 10:51:56 -07001089 ARMVQMap sve_vq;
Richard Hendersone74c0972022-06-20 10:52:01 -07001090 ARMVQMap sme_vq;
Andrew Jeffery7def8752019-12-20 14:02:59 +00001091
1092 /* Generic timer counter frequency, in Hz */
1093 uint64_t gt_cntfrq_hz;
Paolo Bonzini74e75562016-03-15 13:49:25 +01001094};
1095
Philippe Mathieu-Daudé93480282023-10-13 11:35:04 +02001096typedef struct ARMCPUInfo {
1097 const char *name;
1098 void (*initfn)(Object *obj);
1099 void (*class_init)(ObjectClass *oc, void *data);
1100} ARMCPUInfo;
1101
1102/**
1103 * ARMCPUClass:
1104 * @parent_realize: The parent class' realize handler.
1105 * @parent_phases: The parent class' reset phase handlers.
1106 *
1107 * An ARM CPU model.
1108 */
1109struct ARMCPUClass {
1110 CPUClass parent_class;
1111
1112 const ARMCPUInfo *info;
1113 DeviceRealize parent_realize;
1114 ResettablePhases parent_phases;
1115};
1116
1117struct AArch64CPUClass {
1118 ARMCPUClass parent_class;
1119};
1120
Philippe Mathieu-Daudéf6524dd2023-10-13 15:12:35 +02001121/* Callback functions for the generic timer's timers. */
1122void arm_gt_ptimer_cb(void *opaque);
1123void arm_gt_vtimer_cb(void *opaque);
1124void arm_gt_htimer_cb(void *opaque);
1125void arm_gt_stimer_cb(void *opaque);
1126void arm_gt_hvtimer_cb(void *opaque);
1127
Andrew Jeffery7def8752019-12-20 14:02:59 +00001128unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
Jean-Philippe Bruckerf6fc36d2023-08-22 17:31:13 +01001129void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
Andrew Jeffery7def8752019-12-20 14:02:59 +00001130
Marc-André Lureau51e5ef42018-11-27 12:55:59 +04001131void arm_cpu_post_init(Object *obj);
1132
Philippe Mathieu-Daudéf6524dd2023-10-13 15:12:35 +02001133#define ARM_AFF0_SHIFT 0
1134#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
1135#define ARM_AFF1_SHIFT 8
1136#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
1137#define ARM_AFF2_SHIFT 16
1138#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
1139#define ARM_AFF3_SHIFT 32
1140#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
1141#define ARM_DEFAULT_CPUS_PER_CLUSTER 8
1142
1143#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK)
1144#define ARM64_AFFINITY_MASK \
1145 (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK)
1146#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
1147
Richard Henderson750245e2024-01-18 21:06:29 +01001148uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz);
Igor Mammedov46de5912017-05-03 14:56:56 +02001149
Paolo Bonzini74e75562016-03-15 13:49:25 +01001150#ifndef CONFIG_USER_ONLY
Markus Armbruster8a9358c2019-08-12 07:23:44 +02001151extern const VMStateDescription vmstate_arm_cpu;
Paolo Bonzini74e75562016-03-15 13:49:25 +01001152
1153void arm_cpu_do_interrupt(CPUState *cpu);
1154void arm_v7m_cpu_do_interrupt(CPUState *cpu);
Paolo Bonzini74e75562016-03-15 13:49:25 +01001155
Paolo Bonzini74e75562016-03-15 13:49:25 +01001156hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1157 MemTxAttrs *attrs);
Philippe Mathieu-Daudé6d2d4542022-12-06 16:20:51 +01001158#endif /* !CONFIG_USER_ONLY */
Paolo Bonzini74e75562016-03-15 13:49:25 +01001159
Alex Bennéea010bdb2020-03-16 17:21:41 +00001160int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
Paolo Bonzini74e75562016-03-15 13:49:25 +01001161int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1162
Abdallah Bouassida200bf5b2018-05-18 17:48:07 +01001163/* Returns the dynamically generated XML for the gdb stub.
1164 * Returns a pointer to the XML contents for the specified XML file or NULL
1165 * if the XML name doesn't match the predefined one.
1166 */
1167const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
1168
Paolo Bonzini74e75562016-03-15 13:49:25 +01001169int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
Janosch Frank1af00062022-08-11 12:10:54 +00001170 int cpuid, DumpState *s);
Paolo Bonzini74e75562016-03-15 13:49:25 +01001171int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
Janosch Frank1af00062022-08-11 12:10:54 +00001172 int cpuid, DumpState *s);
Paolo Bonzini74e75562016-03-15 13:49:25 +01001173
Peter Maydell3a45f4f2023-09-26 16:56:19 +01001174/**
1175 * arm_emulate_firmware_reset: Emulate firmware CPU reset handling
1176 * @cpu: CPU (which must have been freshly reset)
1177 * @target_el: exception level to put the CPU into
1178 * @secure: whether to put the CPU in secure state
1179 *
1180 * When QEMU is directly running a guest kernel at a lower level than
1181 * EL3 it implicitly emulates some aspects of the guest firmware.
1182 * This includes that on reset we need to configure the parts of the
1183 * CPU corresponding to EL3 so that the real guest code can run at its
1184 * lower exception level. This function does that post-reset CPU setup,
1185 * for when we do direct boot of a guest kernel, and for when we
1186 * emulate PSCI and similar firmware interfaces starting a CPU at a
1187 * lower exception level.
1188 *
1189 * @target_el must be an EL implemented by the CPU between 1 and 3.
1190 * We do not support dropping into a Secure EL other than 3.
1191 *
1192 * It is the responsibility of the caller to call arm_rebuild_hflags().
1193 */
1194void arm_emulate_firmware_reset(CPUState *cpustate, int target_el);
1195
Paolo Bonzini74e75562016-03-15 13:49:25 +01001196#ifdef TARGET_AARCH64
Alex Bennéea010bdb2020-03-16 17:21:41 +00001197int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
Paolo Bonzini74e75562016-03-15 13:49:25 +01001198int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
Richard Henderson85fc7162018-03-09 17:09:43 +00001199void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
Richard Henderson9a05f7b2018-10-08 14:21:56 -07001200void aarch64_sve_change_el(CPUARMState *env, int old_el,
1201 int new_el, bool el0_a64);
Richard Henderson2a8af382023-01-12 11:24:32 +01001202void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask);
Andrew Jones538baab2020-01-23 15:22:40 +00001203
1204/*
1205 * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1206 * The byte at offset i from the start of the in-memory representation contains
1207 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
1208 * lowest offsets are stored in the lowest memory addresses, then that nearly
1209 * matches QEMU's representation, which is to use an array of host-endian
1210 * uint64_t's, where the lower offsets are at the lower indices. To complete
1211 * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1212 */
1213static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1214{
Marc-André Lureaue03b5682022-03-23 19:57:17 +04001215#if HOST_BIG_ENDIAN
Andrew Jones538baab2020-01-23 15:22:40 +00001216 int i;
1217
1218 for (i = 0; i < nr; ++i) {
1219 dst[i] = bswap64(src[i]);
1220 }
1221
1222 return dst;
1223#else
1224 return src;
1225#endif
1226}
1227
Richard Henderson0ab59532018-10-08 14:55:02 +01001228#else
1229static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
Richard Henderson9a05f7b2018-10-08 14:21:56 -07001230static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1231 int n, bool a)
1232{ }
Paolo Bonzini74e75562016-03-15 13:49:25 +01001233#endif
Andreas Färber778c3a02012-04-20 07:39:14 +00001234
Greg Bellowsce020492015-02-13 05:46:08 +00001235void aarch64_sync_32_to_64(CPUARMState *env);
1236void aarch64_sync_64_to_32(CPUARMState *env);
bellardb5ff1b32005-11-26 10:38:39 +00001237
Richard Hendersonced31552018-10-08 14:55:03 +01001238int fp_exception_el(CPUARMState *env, int cur_el);
1239int sve_exception_el(CPUARMState *env, int cur_el);
Richard Henderson6b2ca832022-06-20 10:51:46 -07001240int sme_exception_el(CPUARMState *env, int cur_el);
Richard Henderson5ef3cc52022-06-08 19:38:57 +01001241
1242/**
Richard Henderson6ca54aa2022-06-20 10:52:02 -07001243 * sve_vqm1_for_el_sm:
Richard Henderson5ef3cc52022-06-08 19:38:57 +01001244 * @env: CPUARMState
1245 * @el: exception level
Richard Henderson6ca54aa2022-06-20 10:52:02 -07001246 * @sm: streaming mode
Richard Henderson5ef3cc52022-06-08 19:38:57 +01001247 *
Richard Henderson6ca54aa2022-06-20 10:52:02 -07001248 * Compute the current vector length for @el & @sm, in units of
Richard Henderson5ef3cc52022-06-08 19:38:57 +01001249 * Quadwords Minus 1 -- the same scale used for ZCR_ELx.LEN.
Richard Henderson6ca54aa2022-06-20 10:52:02 -07001250 * If @sm, compute for SVL, otherwise NVL.
Richard Henderson5ef3cc52022-06-08 19:38:57 +01001251 */
Richard Henderson6ca54aa2022-06-20 10:52:02 -07001252uint32_t sve_vqm1_for_el_sm(CPUARMState *env, int el, bool sm);
1253
1254/* Likewise, but using @sm = PSTATE.SM. */
Richard Henderson5ef3cc52022-06-08 19:38:57 +01001255uint32_t sve_vqm1_for_el(CPUARMState *env, int el);
Richard Hendersonced31552018-10-08 14:55:03 +01001256
Alexander Graf3926cc82013-09-03 20:12:09 +01001257static inline bool is_a64(CPUARMState *env)
1258{
1259 return env->aarch64;
1260}
1261
Alistair Francisec7b4ce2014-08-29 15:00:29 +01001262/**
Aaron Lindsay5d05b9d2019-01-21 10:23:13 +00001263 * pmu_op_start/finish
1264 * @env: CPUARMState
1265 *
1266 * Convert all PMU counters between their delta form (the typical mode when
1267 * they are enabled) and the guest-visible values. These two calls must
1268 * surround any action which might affect the counters.
1269 */
1270void pmu_op_start(CPUARMState *env);
1271void pmu_op_finish(CPUARMState *env);
Alistair Francisec7b4ce2014-08-29 15:00:29 +01001272
Aaron Lindsay OS4e7beb02019-02-01 14:55:45 +00001273/*
1274 * Called when a PMU counter is due to overflow
1275 */
1276void arm_pmu_timer_cb(void *opaque);
1277
Aaron Lindsay033614c2019-01-21 10:23:14 +00001278/**
1279 * Functions to register as EL change hooks for PMU mode filtering
1280 */
1281void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1282void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1283
Aaron Lindsay57a4a112019-01-21 10:23:14 +00001284/*
Aaron Lindsay OSbf8d0962019-01-29 11:46:04 +00001285 * pmu_init
1286 * @cpu: ARMCPU
Aaron Lindsay57a4a112019-01-21 10:23:14 +00001287 *
Aaron Lindsay OSbf8d0962019-01-29 11:46:04 +00001288 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state
1289 * for the current configuration
Aaron Lindsay57a4a112019-01-21 10:23:14 +00001290 */
Aaron Lindsay OSbf8d0962019-01-29 11:46:04 +00001291void pmu_init(ARMCPU *cpu);
Aaron Lindsay57a4a112019-01-21 10:23:14 +00001292
Peter Maydell76e3e1b2014-02-20 10:35:51 +00001293/* SCTLR bit meanings. Several bits have been reused in newer
1294 * versions of the architecture; in that case we define constants
1295 * for both old and new bit meanings. Code which tests against those
1296 * bits should probably check or otherwise arrange that the CPU
1297 * is the architectural version it expects.
1298 */
1299#define SCTLR_M (1U << 0)
1300#define SCTLR_A (1U << 1)
1301#define SCTLR_C (1U << 2)
1302#define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
Richard Hendersonb2af69d2019-01-21 10:23:11 +00001303#define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1304#define SCTLR_SA (1U << 3) /* AArch64 only */
Peter Maydell76e3e1b2014-02-20 10:35:51 +00001305#define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
Richard Hendersonb2af69d2019-01-21 10:23:11 +00001306#define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
Peter Maydell76e3e1b2014-02-20 10:35:51 +00001307#define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
1308#define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
1309#define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1310#define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
Richard Henderson83f624d2023-06-06 10:19:38 +01001311#define SCTLR_nAA (1U << 6) /* when FEAT_LSE2 is implemented */
Peter Maydell76e3e1b2014-02-20 10:35:51 +00001312#define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
1313#define SCTLR_ITD (1U << 7) /* v8 onward */
1314#define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
1315#define SCTLR_SED (1U << 8) /* v8 onward */
1316#define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
1317#define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
1318#define SCTLR_F (1U << 10) /* up to v6 */
Richard Hendersoncb570bd2019-03-01 12:04:54 -08001319#define SCTLR_SW (1U << 10) /* v7 */
1320#define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
Richard Hendersonb2af69d2019-01-21 10:23:11 +00001321#define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */
1322#define SCTLR_EOS (1U << 11) /* v8.5-ExS */
Peter Maydell76e3e1b2014-02-20 10:35:51 +00001323#define SCTLR_I (1U << 12)
Richard Hendersonb2af69d2019-01-21 10:23:11 +00001324#define SCTLR_V (1U << 13) /* AArch32 only */
1325#define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */
Peter Maydell76e3e1b2014-02-20 10:35:51 +00001326#define SCTLR_RR (1U << 14) /* up to v7 */
1327#define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
1328#define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
1329#define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
1330#define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
1331#define SCTLR_nTWI (1U << 16) /* v8 onward */
Richard Hendersonb2af69d2019-01-21 10:23:11 +00001332#define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */
Peter Crosthwaitef6bda882015-06-19 14:17:45 +01001333#define SCTLR_BR (1U << 17) /* PMSA only */
Peter Maydell76e3e1b2014-02-20 10:35:51 +00001334#define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
1335#define SCTLR_nTWE (1U << 18) /* v8 onward */
1336#define SCTLR_WXN (1U << 19)
1337#define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
Richard Hendersonb2af69d2019-01-21 10:23:11 +00001338#define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
Richard Henderson7cb1e612022-05-06 13:02:38 -05001339#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */
Richard Hendersonb2af69d2019-01-21 10:23:11 +00001340#define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
1341#define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
1342#define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
1343#define SCTLR_EIS (1U << 22) /* v8.5-ExS */
Peter Maydell76e3e1b2014-02-20 10:35:51 +00001344#define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
Richard Hendersonb2af69d2019-01-21 10:23:11 +00001345#define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
Peter Maydell76e3e1b2014-02-20 10:35:51 +00001346#define SCTLR_VE (1U << 24) /* up to v7 */
1347#define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
1348#define SCTLR_EE (1U << 25)
1349#define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
1350#define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
Richard Hendersonb2af69d2019-01-21 10:23:11 +00001351#define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1352#define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */
1353#define SCTLR_TRE (1U << 28) /* AArch32 only */
1354#define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1355#define SCTLR_AFE (1U << 29) /* AArch32 only */
1356#define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1357#define SCTLR_TE (1U << 30) /* AArch32 only */
1358#define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
1359#define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
Rebecca Cranf2f68a72021-02-16 15:45:41 -07001360#define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */
Peter Maydelldbc678f2023-09-12 15:04:24 +01001361#define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */
Richard Hendersonb2af69d2019-01-21 10:23:11 +00001362#define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
1363#define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
1364#define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
1365#define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */
1366#define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
1367#define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
1368#define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
Rebecca Cranf2f68a72021-02-16 15:45:41 -07001369#define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */
Richard Hendersonad1e6012022-04-17 10:43:30 -07001370#define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */
1371#define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */
1372#define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */
1373#define SCTLR_TMT (1ULL << 51) /* FEAT_TME */
1374#define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */
1375#define SCTLR_TME (1ULL << 53) /* FEAT_TME */
1376#define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */
1377#define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */
1378#define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */
1379#define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */
1380#define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */
1381#define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */
1382#define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */
1383#define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */
Peter Maydell76e3e1b2014-02-20 10:35:51 +00001384
Richard Hendersonfab8ad32022-05-16 22:48:45 -07001385/* Bit definitions for CPACR (AArch32 only) */
1386FIELD(CPACR, CP10, 20, 2)
1387FIELD(CPACR, CP11, 22, 2)
1388FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */
1389FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */
1390FIELD(CPACR, ASEDIS, 31, 1)
1391
1392/* Bit definitions for CPACR_EL1 (AArch64 only) */
1393FIELD(CPACR_EL1, ZEN, 16, 2)
1394FIELD(CPACR_EL1, FPEN, 20, 2)
1395FIELD(CPACR_EL1, SMEN, 24, 2)
1396FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */
1397
1398/* Bit definitions for HCPTR (AArch32 only) */
1399FIELD(HCPTR, TCP10, 10, 1)
1400FIELD(HCPTR, TCP11, 11, 1)
1401FIELD(HCPTR, TASE, 15, 1)
1402FIELD(HCPTR, TTA, 20, 1)
1403FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */
1404FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */
1405
1406/* Bit definitions for CPTR_EL2 (AArch64 only) */
1407FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */
1408FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */
1409FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */
1410FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */
1411FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */
1412FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */
1413FIELD(CPTR_EL2, TTA, 28, 1)
1414FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */
1415FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */
1416
1417/* Bit definitions for CPTR_EL3 (AArch64 only) */
1418FIELD(CPTR_EL3, EZ, 8, 1)
1419FIELD(CPTR_EL3, TFP, 10, 1)
1420FIELD(CPTR_EL3, ESM, 12, 1)
1421FIELD(CPTR_EL3, TTA, 20, 1)
1422FIELD(CPTR_EL3, TAM, 30, 1)
1423FIELD(CPTR_EL3, TCPAC, 31, 1)
Greg Bellowsc6f19162015-05-29 11:28:52 +01001424
Peter Maydellf190bd12022-09-23 13:34:12 +01001425#define MDCR_MTPME (1U << 28)
1426#define MDCR_TDCC (1U << 27)
Peter Maydell47b385d2022-08-22 14:23:57 +01001427#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
Peter Maydell0b42f4f2022-08-22 14:23:56 +01001428#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
1429#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
Peter Maydell187f6782016-02-18 14:16:15 +00001430#define MDCR_EPMAD (1U << 21)
1431#define MDCR_EDAD (1U << 20)
Peter Maydellf190bd12022-09-23 13:34:12 +01001432#define MDCR_TTRF (1U << 19)
1433#define MDCR_STE (1U << 18) /* MDCR_EL3 */
Aaron Lindsay033614c2019-01-21 10:23:14 +00001434#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
1435#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
Peter Maydell187f6782016-02-18 14:16:15 +00001436#define MDCR_SDD (1U << 16)
Peter Maydella8d64e72016-02-19 14:39:43 +00001437#define MDCR_SPD (3U << 14)
Peter Maydell187f6782016-02-18 14:16:15 +00001438#define MDCR_TDRA (1U << 11)
1439#define MDCR_TDOSA (1U << 10)
1440#define MDCR_TDA (1U << 9)
1441#define MDCR_TDE (1U << 8)
1442#define MDCR_HPME (1U << 7)
1443#define MDCR_TPM (1U << 6)
1444#define MDCR_TPMCR (1U << 5)
Aaron Lindsay033614c2019-01-21 10:23:14 +00001445#define MDCR_HPMN (0x1fU)
Peter Maydell187f6782016-02-18 14:16:15 +00001446
Peter Maydella8d64e72016-02-19 14:39:43 +00001447/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
Peter Maydellf190bd12022-09-23 13:34:12 +01001448#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
1449 MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
1450 MDCR_STE | MDCR_SPME | MDCR_SPD)
Peter Maydella8d64e72016-02-19 14:39:43 +00001451
Peter Maydell78dbbbe2013-09-10 19:09:32 +01001452#define CPSR_M (0x1fU)
1453#define CPSR_T (1U << 5)
1454#define CPSR_F (1U << 6)
1455#define CPSR_I (1U << 7)
1456#define CPSR_A (1U << 8)
1457#define CPSR_E (1U << 9)
1458#define CPSR_IT_2_7 (0xfc00U)
1459#define CPSR_GE (0xfU << 16)
Peter Maydell4051e122014-08-19 18:56:26 +01001460#define CPSR_IL (1U << 20)
Rebecca Crandc8b1852021-02-07 23:56:57 -07001461#define CPSR_DIT (1U << 21)
Richard Henderson220f5082020-02-08 12:58:07 +00001462#define CPSR_PAN (1U << 22)
Rebecca Cranf2f68a72021-02-16 15:45:41 -07001463#define CPSR_SSBS (1U << 23)
Peter Maydell78dbbbe2013-09-10 19:09:32 +01001464#define CPSR_J (1U << 24)
1465#define CPSR_IT_0_1 (3U << 25)
1466#define CPSR_Q (1U << 27)
1467#define CPSR_V (1U << 28)
1468#define CPSR_C (1U << 29)
1469#define CPSR_Z (1U << 30)
1470#define CPSR_N (1U << 31)
pbrook9ee6e8b2007-11-11 00:04:49 +00001471#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
Peter Maydell4cc35612014-02-26 17:20:06 +00001472#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
bellardb5ff1b32005-11-26 10:38:39 +00001473
pbrook9ee6e8b2007-11-11 00:04:49 +00001474#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
Peter Maydell4cc35612014-02-26 17:20:06 +00001475#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1476 | CPSR_NZCV)
pbrook9ee6e8b2007-11-11 00:04:49 +00001477/* Bits writable in user mode. */
Peter Maydell268b1b32020-05-18 15:28:01 +01001478#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
pbrook9ee6e8b2007-11-11 00:04:49 +00001479/* Execution state bits. MRS read as zero, MSR writes ignored. */
Peter Maydell4051e122014-08-19 18:56:26 +01001480#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
pbrook9ee6e8b2007-11-11 00:04:49 +00001481
Peter Maydell987ab452017-09-04 15:21:52 +01001482/* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1483#define XPSR_EXCP 0x1ffU
1484#define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1485#define XPSR_IT_2_7 CPSR_IT_2_7
1486#define XPSR_GE CPSR_GE
1487#define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1488#define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1489#define XPSR_IT_0_1 CPSR_IT_0_1
1490#define XPSR_Q CPSR_Q
1491#define XPSR_V CPSR_V
1492#define XPSR_C CPSR_C
1493#define XPSR_Z CPSR_Z
1494#define XPSR_N CPSR_N
1495#define XPSR_NZCV CPSR_NZCV
1496#define XPSR_IT CPSR_IT
1497
Fabian Aggelere389be12014-06-19 18:06:24 +01001498#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
1499#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
1500#define TTBCR_PD0 (1U << 4)
1501#define TTBCR_PD1 (1U << 5)
1502#define TTBCR_EPD0 (1U << 7)
1503#define TTBCR_IRGN0 (3U << 8)
1504#define TTBCR_ORGN0 (3U << 10)
1505#define TTBCR_SH0 (3U << 12)
1506#define TTBCR_T1SZ (3U << 16)
1507#define TTBCR_A1 (1U << 22)
1508#define TTBCR_EPD1 (1U << 23)
1509#define TTBCR_IRGN1 (3U << 24)
1510#define TTBCR_ORGN1 (3U << 26)
1511#define TTBCR_SH1 (1U << 28)
1512#define TTBCR_EAE (1U << 31)
1513
Peter Maydellf04383e2022-07-14 14:23:03 +01001514FIELD(VTCR, T0SZ, 0, 6)
1515FIELD(VTCR, SL0, 6, 2)
1516FIELD(VTCR, IRGN0, 8, 2)
1517FIELD(VTCR, ORGN0, 10, 2)
1518FIELD(VTCR, SH0, 12, 2)
1519FIELD(VTCR, TG0, 14, 2)
1520FIELD(VTCR, PS, 16, 3)
1521FIELD(VTCR, VS, 19, 1)
1522FIELD(VTCR, HA, 21, 1)
1523FIELD(VTCR, HD, 22, 1)
1524FIELD(VTCR, HWU59, 25, 1)
1525FIELD(VTCR, HWU60, 26, 1)
1526FIELD(VTCR, HWU61, 27, 1)
1527FIELD(VTCR, HWU62, 28, 1)
1528FIELD(VTCR, NSW, 29, 1)
1529FIELD(VTCR, NSA, 30, 1)
1530FIELD(VTCR, DS, 32, 1)
1531FIELD(VTCR, SL2, 33, 1)
1532
Peter Maydelld3563122013-12-17 19:42:30 +00001533/* Bit definitions for ARMv8 SPSR (PSTATE) format.
1534 * Only these are valid when in AArch64 mode; in
1535 * AArch32 mode SPSRs are basically CPSR-format.
1536 */
Peter Maydellf502cfc2014-04-15 19:18:43 +01001537#define PSTATE_SP (1U)
Peter Maydelld3563122013-12-17 19:42:30 +00001538#define PSTATE_M (0xFU)
1539#define PSTATE_nRW (1U << 4)
1540#define PSTATE_F (1U << 6)
1541#define PSTATE_I (1U << 7)
1542#define PSTATE_A (1U << 8)
1543#define PSTATE_D (1U << 9)
Richard Hendersonf6e52ea2019-02-05 16:52:36 +00001544#define PSTATE_BTYPE (3U << 10)
Rebecca Cranf2f68a72021-02-16 15:45:41 -07001545#define PSTATE_SSBS (1U << 12)
Peter Maydelld3563122013-12-17 19:42:30 +00001546#define PSTATE_IL (1U << 20)
1547#define PSTATE_SS (1U << 21)
Richard Henderson220f5082020-02-08 12:58:07 +00001548#define PSTATE_PAN (1U << 22)
Richard Henderson9eeb7a12020-02-08 12:58:14 +00001549#define PSTATE_UAO (1U << 23)
Rebecca Crandc8b1852021-02-07 23:56:57 -07001550#define PSTATE_DIT (1U << 24)
Richard Henderson4b779ce2020-06-25 20:31:05 -07001551#define PSTATE_TCO (1U << 25)
Peter Maydelld3563122013-12-17 19:42:30 +00001552#define PSTATE_V (1U << 28)
1553#define PSTATE_C (1U << 29)
1554#define PSTATE_Z (1U << 30)
1555#define PSTATE_N (1U << 31)
1556#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
Peter Maydell4cc35612014-02-26 17:20:06 +00001557#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
Richard Hendersonf6e52ea2019-02-05 16:52:36 +00001558#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
Peter Maydelld3563122013-12-17 19:42:30 +00001559/* Mode values for AArch64 */
1560#define PSTATE_MODE_EL3h 13
1561#define PSTATE_MODE_EL3t 12
1562#define PSTATE_MODE_EL2h 9
1563#define PSTATE_MODE_EL2t 8
1564#define PSTATE_MODE_EL1h 5
1565#define PSTATE_MODE_EL1t 4
1566#define PSTATE_MODE_EL0t 0
1567
Richard Hendersonc37e6ac2022-06-20 10:51:49 -07001568/* PSTATE bits that are accessed via SVCR and not stored in SPSR_ELx. */
1569FIELD(SVCR, SM, 0, 1)
1570FIELD(SVCR, ZA, 1, 1)
1571
Richard Hendersonde561982022-06-20 10:51:50 -07001572/* Fields for SMCR_ELx. */
1573FIELD(SMCR, LEN, 0, 4)
1574FIELD(SMCR, FA64, 31, 1)
1575
Peter Maydellde2db7e2017-10-06 16:46:47 +01001576/* Write a new value to v7m.exception, thus transitioning into or out
1577 * of Handler mode; this may result in a change of active stack pointer.
1578 */
1579void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1580
Edgar E. Iglesias9e729b52014-09-29 18:48:49 +01001581/* Map EL and handler into a PSTATE_MODE. */
1582static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1583{
1584 return (el << 2) | handler;
1585}
1586
Peter Maydelld3563122013-12-17 19:42:30 +00001587/* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1588 * interprocessing, so we don't attempt to sync with the cpsr state used by
1589 * the 32 bit decoder.
1590 */
1591static inline uint32_t pstate_read(CPUARMState *env)
1592{
1593 int ZF;
1594
1595 ZF = (env->ZF == 0);
1596 return (env->NF & 0x80000000) | (ZF << 30)
1597 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
Richard Hendersonf6e52ea2019-02-05 16:52:36 +00001598 | env->pstate | env->daif | (env->btype << 10);
Peter Maydelld3563122013-12-17 19:42:30 +00001599}
1600
1601static inline void pstate_write(CPUARMState *env, uint32_t val)
1602{
1603 env->ZF = (~val) & PSTATE_Z;
1604 env->NF = val;
1605 env->CF = (val >> 29) & 1;
1606 env->VF = (val << 3) & 0x80000000;
Peter Maydell4cc35612014-02-26 17:20:06 +00001607 env->daif = val & PSTATE_DAIF;
Richard Hendersonf6e52ea2019-02-05 16:52:36 +00001608 env->btype = (val >> 10) & 3;
Peter Maydelld3563122013-12-17 19:42:30 +00001609 env->pstate = val & ~CACHED_PSTATE_BITS;
1610}
1611
bellardb5ff1b32005-11-26 10:38:39 +00001612/* Return the current CPSR value. */
balrog2f4a40e2007-11-13 01:50:15 +00001613uint32_t cpsr_read(CPUARMState *env);
Peter Maydell50866ba2016-02-23 15:36:43 +00001614
1615typedef enum CPSRWriteType {
1616 CPSRWriteByInstr = 0, /* from guest MSR or CPS */
1617 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
Peter Maydelle7848072021-08-17 21:18:43 +01001618 CPSRWriteRaw = 2,
1619 /* trust values, no reg bank switch, no hflags rebuild */
Peter Maydell50866ba2016-02-23 15:36:43 +00001620 CPSRWriteByGDBStub = 3, /* from the GDB stub */
1621} CPSRWriteType;
1622
Peter Maydelle7848072021-08-17 21:18:43 +01001623/*
1624 * Set the CPSR. Note that some bits of mask must be all-set or all-clear.
1625 * This will do an arm_rebuild_hflags() if any of the bits in @mask
1626 * correspond to TB flags bits cached in the hflags, unless @write_type
1627 * is CPSRWriteRaw.
1628 */
Peter Maydell50866ba2016-02-23 15:36:43 +00001629void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1630 CPSRWriteType write_type);
pbrook9ee6e8b2007-11-11 00:04:49 +00001631
1632/* Return the current xPSR value. */
1633static inline uint32_t xpsr_read(CPUARMState *env)
1634{
1635 int ZF;
pbrook6fbe23d2008-04-01 17:19:11 +00001636 ZF = (env->ZF == 0);
1637 return (env->NF & 0x80000000) | (ZF << 30)
pbrook9ee6e8b2007-11-11 00:04:49 +00001638 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1639 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1640 | ((env->condexec_bits & 0xfc) << 8)
Peter Maydellf1e25982019-05-07 12:55:04 +01001641 | (env->GE << 16)
pbrook9ee6e8b2007-11-11 00:04:49 +00001642 | env->v7m.exception;
bellardb5ff1b32005-11-26 10:38:39 +00001643}
1644
pbrook9ee6e8b2007-11-11 00:04:49 +00001645/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
1646static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1647{
Peter Maydell987ab452017-09-04 15:21:52 +01001648 if (mask & XPSR_NZCV) {
1649 env->ZF = (~val) & XPSR_Z;
pbrook6fbe23d2008-04-01 17:19:11 +00001650 env->NF = val;
pbrook9ee6e8b2007-11-11 00:04:49 +00001651 env->CF = (val >> 29) & 1;
1652 env->VF = (val << 3) & 0x80000000;
1653 }
Peter Maydell987ab452017-09-04 15:21:52 +01001654 if (mask & XPSR_Q) {
1655 env->QF = ((val & XPSR_Q) != 0);
1656 }
Peter Maydellf1e25982019-05-07 12:55:04 +01001657 if (mask & XPSR_GE) {
1658 env->GE = (val & XPSR_GE) >> 16;
1659 }
Richard Henderson04c9c812019-11-19 13:20:28 +00001660#ifndef CONFIG_USER_ONLY
Peter Maydell987ab452017-09-04 15:21:52 +01001661 if (mask & XPSR_T) {
1662 env->thumb = ((val & XPSR_T) != 0);
1663 }
1664 if (mask & XPSR_IT_0_1) {
pbrook9ee6e8b2007-11-11 00:04:49 +00001665 env->condexec_bits &= ~3;
1666 env->condexec_bits |= (val >> 25) & 3;
1667 }
Peter Maydell987ab452017-09-04 15:21:52 +01001668 if (mask & XPSR_IT_2_7) {
pbrook9ee6e8b2007-11-11 00:04:49 +00001669 env->condexec_bits &= 3;
1670 env->condexec_bits |= (val >> 8) & 0xfc;
1671 }
Peter Maydell987ab452017-09-04 15:21:52 +01001672 if (mask & XPSR_EXCP) {
Peter Maydellde2db7e2017-10-06 16:46:47 +01001673 /* Note that this only happens on exception exit */
1674 write_v7m_exception(env, val & XPSR_EXCP);
pbrook9ee6e8b2007-11-11 00:04:49 +00001675 }
Richard Henderson04c9c812019-11-19 13:20:28 +00001676#endif
pbrook9ee6e8b2007-11-11 00:04:49 +00001677}
1678
Edgar E. Iglesiasf149e3e2014-09-29 18:48:48 +01001679#define HCR_VM (1ULL << 0)
1680#define HCR_SWIO (1ULL << 1)
1681#define HCR_PTW (1ULL << 2)
1682#define HCR_FMO (1ULL << 3)
1683#define HCR_IMO (1ULL << 4)
1684#define HCR_AMO (1ULL << 5)
1685#define HCR_VF (1ULL << 6)
1686#define HCR_VI (1ULL << 7)
1687#define HCR_VSE (1ULL << 8)
1688#define HCR_FB (1ULL << 9)
1689#define HCR_BSU_MASK (3ULL << 10)
1690#define HCR_DC (1ULL << 12)
1691#define HCR_TWI (1ULL << 13)
1692#define HCR_TWE (1ULL << 14)
1693#define HCR_TID0 (1ULL << 15)
1694#define HCR_TID1 (1ULL << 16)
1695#define HCR_TID2 (1ULL << 17)
1696#define HCR_TID3 (1ULL << 18)
1697#define HCR_TSC (1ULL << 19)
1698#define HCR_TIDCP (1ULL << 20)
1699#define HCR_TACR (1ULL << 21)
1700#define HCR_TSW (1ULL << 22)
Richard Henderson099bf532018-12-13 13:48:04 +00001701#define HCR_TPCP (1ULL << 23)
Edgar E. Iglesiasf149e3e2014-09-29 18:48:48 +01001702#define HCR_TPU (1ULL << 24)
1703#define HCR_TTLB (1ULL << 25)
1704#define HCR_TVM (1ULL << 26)
1705#define HCR_TGE (1ULL << 27)
1706#define HCR_TDZ (1ULL << 28)
1707#define HCR_HCD (1ULL << 29)
1708#define HCR_TRVM (1ULL << 30)
1709#define HCR_RW (1ULL << 31)
1710#define HCR_CD (1ULL << 32)
1711#define HCR_ID (1ULL << 33)
Peter Maydellac656b12018-08-14 17:17:21 +01001712#define HCR_E2H (1ULL << 34)
Richard Henderson099bf532018-12-13 13:48:04 +00001713#define HCR_TLOR (1ULL << 35)
1714#define HCR_TERR (1ULL << 36)
1715#define HCR_TEA (1ULL << 37)
1716#define HCR_MIOCNCE (1ULL << 38)
Richard Hendersonaa3cc422023-06-23 11:15:43 +01001717#define HCR_TME (1ULL << 39)
Richard Henderson099bf532018-12-13 13:48:04 +00001718#define HCR_APK (1ULL << 40)
1719#define HCR_API (1ULL << 41)
1720#define HCR_NV (1ULL << 42)
1721#define HCR_NV1 (1ULL << 43)
1722#define HCR_AT (1ULL << 44)
1723#define HCR_NV2 (1ULL << 45)
1724#define HCR_FWB (1ULL << 46)
1725#define HCR_FIEN (1ULL << 47)
Richard Hendersonaa3cc422023-06-23 11:15:43 +01001726#define HCR_GPF (1ULL << 48)
Richard Henderson099bf532018-12-13 13:48:04 +00001727#define HCR_TID4 (1ULL << 49)
1728#define HCR_TICAB (1ULL << 50)
Richard Hendersone0a38bb2020-03-05 16:09:16 +00001729#define HCR_AMVOFFEN (1ULL << 51)
Richard Henderson099bf532018-12-13 13:48:04 +00001730#define HCR_TOCU (1ULL << 52)
Richard Hendersone0a38bb2020-03-05 16:09:16 +00001731#define HCR_ENSCXT (1ULL << 53)
Richard Henderson099bf532018-12-13 13:48:04 +00001732#define HCR_TTLBIS (1ULL << 54)
1733#define HCR_TTLBOS (1ULL << 55)
1734#define HCR_ATA (1ULL << 56)
1735#define HCR_DCT (1ULL << 57)
Richard Hendersone0a38bb2020-03-05 16:09:16 +00001736#define HCR_TID5 (1ULL << 58)
1737#define HCR_TWEDEN (1ULL << 59)
1738#define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
Richard Henderson099bf532018-12-13 13:48:04 +00001739
Richard Henderson5814d582022-05-16 22:48:44 -07001740#define HCRX_ENAS0 (1ULL << 0)
1741#define HCRX_ENALS (1ULL << 1)
1742#define HCRX_ENASR (1ULL << 2)
1743#define HCRX_FNXS (1ULL << 3)
1744#define HCRX_FGTNXS (1ULL << 4)
1745#define HCRX_SMPME (1ULL << 5)
1746#define HCRX_TALLINT (1ULL << 6)
1747#define HCRX_VINMI (1ULL << 7)
1748#define HCRX_VFNMI (1ULL << 8)
1749#define HCRX_CMOW (1ULL << 9)
1750#define HCRX_MCE2 (1ULL << 10)
1751#define HCRX_MSCEN (1ULL << 11)
1752
Rémi Denis-Courmont98612482021-01-12 12:45:07 +02001753#define HPFAR_NS (1ULL << 63)
1754
Jerome Forissier06f2adc2022-10-04 09:23:54 +02001755#define SCR_NS (1ULL << 0)
1756#define SCR_IRQ (1ULL << 1)
1757#define SCR_FIQ (1ULL << 2)
1758#define SCR_EA (1ULL << 3)
1759#define SCR_FW (1ULL << 4)
1760#define SCR_AW (1ULL << 5)
1761#define SCR_NET (1ULL << 6)
1762#define SCR_SMD (1ULL << 7)
1763#define SCR_HCE (1ULL << 8)
1764#define SCR_SIF (1ULL << 9)
1765#define SCR_RW (1ULL << 10)
1766#define SCR_ST (1ULL << 11)
1767#define SCR_TWI (1ULL << 12)
1768#define SCR_TWE (1ULL << 13)
1769#define SCR_TLOR (1ULL << 14)
1770#define SCR_TERR (1ULL << 15)
1771#define SCR_APK (1ULL << 16)
1772#define SCR_API (1ULL << 17)
1773#define SCR_EEL2 (1ULL << 18)
1774#define SCR_EASE (1ULL << 19)
1775#define SCR_NMEA (1ULL << 20)
1776#define SCR_FIEN (1ULL << 21)
1777#define SCR_ENSCXT (1ULL << 25)
1778#define SCR_ATA (1ULL << 26)
1779#define SCR_FGTEN (1ULL << 27)
1780#define SCR_ECVEN (1ULL << 28)
1781#define SCR_TWEDEN (1ULL << 29)
Richard Hendersonf527d662022-04-17 10:43:29 -07001782#define SCR_TWEDEL MAKE_64BIT_MASK(30, 4)
1783#define SCR_TME (1ULL << 34)
1784#define SCR_AMVOFFEN (1ULL << 35)
1785#define SCR_ENAS0 (1ULL << 36)
1786#define SCR_ADEN (1ULL << 37)
1787#define SCR_HXEN (1ULL << 38)
1788#define SCR_TRNDR (1ULL << 40)
1789#define SCR_ENTP2 (1ULL << 41)
1790#define SCR_GPF (1ULL << 48)
Richard Hendersonaa3cc422023-06-23 11:15:43 +01001791#define SCR_NSE (1ULL << 62)
Edgar E. Iglesias64e0e2d2014-09-29 18:48:49 +01001792
Peter Maydellcc7613b2021-08-16 19:03:04 +01001793#define HSTR_TTEE (1 << 16)
Peter Maydell8e228c92021-08-16 19:03:05 +01001794#define HSTR_TJDBX (1 << 17)
Peter Maydellcc7613b2021-08-16 19:03:04 +01001795
Jean-Philippe Bruckerf6fc36d2023-08-22 17:31:13 +01001796#define CNTHCTL_CNTVMASK (1 << 18)
1797#define CNTHCTL_CNTPMASK (1 << 19)
1798
Peter Maydell01653292010-11-24 15:20:04 +00001799/* Return the current FPSCR value. */
1800uint32_t vfp_get_fpscr(CPUARMState *env);
1801void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1802
Alex Bennéed81ce0e2018-03-01 11:05:47 +00001803/* FPCR, Floating Point Control Register
1804 * FPSR, Floating Poiht Status Register
1805 *
1806 * For A64 the FPSCR is split into two logically distinct registers,
Peter Maydellf903fa22013-12-17 19:42:31 +00001807 * FPCR and FPSR. However since they still use non-overlapping bits
1808 * we store the underlying state in fpscr and just mask on read/write.
1809 */
1810#define FPSR_MASK 0xf800009f
Richard Henderson0b621592018-08-16 14:05:29 +01001811#define FPCR_MASK 0x07ff9f00
Alex Bennéed81ce0e2018-03-01 11:05:47 +00001812
Peter Maydella15945d2019-02-05 16:52:42 +00001813#define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */
1814#define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */
1815#define FPCR_OFE (1 << 10) /* Overflow exception trap enable */
1816#define FPCR_UFE (1 << 11) /* Underflow exception trap enable */
1817#define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
1818#define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
Alex Bennéed81ce0e2018-03-01 11:05:47 +00001819#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
Peter Maydell99c78342020-11-19 21:56:04 +00001820#define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */
Alex Bennéed81ce0e2018-03-01 11:05:47 +00001821#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1822#define FPCR_DN (1 << 25) /* Default NaN enable bit */
Peter Maydell99c78342020-11-19 21:56:04 +00001823#define FPCR_AHP (1 << 26) /* Alternative half-precision */
Richard Hendersona4d58462019-02-15 09:56:41 +00001824#define FPCR_QC (1 << 27) /* Cumulative saturation bit */
Peter Maydell9542c302020-11-19 21:55:59 +00001825#define FPCR_V (1 << 28) /* FP overflow flag */
1826#define FPCR_C (1 << 29) /* FP carry flag */
1827#define FPCR_Z (1 << 30) /* FP zero flag */
1828#define FPCR_N (1 << 31) /* FP negative flag */
1829
Peter Maydell99c78342020-11-19 21:56:04 +00001830#define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
1831#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
Peter Maydellb26b5622021-05-20 16:28:38 +01001832#define FPCR_LTPSIZE_LENGTH 3
Peter Maydell99c78342020-11-19 21:56:04 +00001833
Peter Maydell9542c302020-11-19 21:55:59 +00001834#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
1835#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
Alex Bennéed81ce0e2018-03-01 11:05:47 +00001836
Peter Maydellf903fa22013-12-17 19:42:31 +00001837static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1838{
1839 return vfp_get_fpscr(env) & FPSR_MASK;
1840}
1841
1842static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1843{
1844 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1845 vfp_set_fpscr(env, new_fpscr);
1846}
1847
1848static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1849{
1850 return vfp_get_fpscr(env) & FPCR_MASK;
1851}
1852
1853static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1854{
1855 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1856 vfp_set_fpscr(env, new_fpscr);
1857}
1858
bellardb5ff1b32005-11-26 10:38:39 +00001859enum arm_cpu_mode {
1860 ARM_CPU_MODE_USR = 0x10,
1861 ARM_CPU_MODE_FIQ = 0x11,
1862 ARM_CPU_MODE_IRQ = 0x12,
1863 ARM_CPU_MODE_SVC = 0x13,
Edgar E. Iglesias28c94572014-05-27 17:09:52 +01001864 ARM_CPU_MODE_MON = 0x16,
bellardb5ff1b32005-11-26 10:38:39 +00001865 ARM_CPU_MODE_ABT = 0x17,
Edgar E. Iglesias28c94572014-05-27 17:09:52 +01001866 ARM_CPU_MODE_HYP = 0x1a,
bellardb5ff1b32005-11-26 10:38:39 +00001867 ARM_CPU_MODE_UND = 0x1b,
1868 ARM_CPU_MODE_SYS = 0x1f
1869};
1870
pbrook40f137e2006-02-20 00:33:36 +00001871/* VFP system registers. */
1872#define ARM_VFP_FPSID 0
1873#define ARM_VFP_FPSCR 1
Peter Maydella50c0f52014-04-15 19:18:44 +01001874#define ARM_VFP_MVFR2 5
pbrook9ee6e8b2007-11-11 00:04:49 +00001875#define ARM_VFP_MVFR1 6
1876#define ARM_VFP_MVFR0 7
pbrook40f137e2006-02-20 00:33:36 +00001877#define ARM_VFP_FPEXC 8
1878#define ARM_VFP_FPINST 9
1879#define ARM_VFP_FPINST2 10
Peter Maydell9542c302020-11-19 21:55:59 +00001880/* These ones are M-profile only */
1881#define ARM_VFP_FPSCR_NZCVQC 2
1882#define ARM_VFP_VPR 12
1883#define ARM_VFP_P0 13
1884#define ARM_VFP_FPCXT_NS 14
1885#define ARM_VFP_FPCXT_S 15
pbrook40f137e2006-02-20 00:33:36 +00001886
Peter Maydell32a290b2020-11-19 21:55:56 +00001887/* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
1888#define QEMU_VFP_FPSCR_NZCV 0xffff
1889
balrog18c9b562007-04-30 02:02:17 +00001890/* iwMMXt coprocessor control registers. */
Peter Maydell6e0fafe2018-08-24 13:17:48 +01001891#define ARM_IWMMXT_wCID 0
1892#define ARM_IWMMXT_wCon 1
1893#define ARM_IWMMXT_wCSSF 2
1894#define ARM_IWMMXT_wCASF 3
1895#define ARM_IWMMXT_wCGR0 8
1896#define ARM_IWMMXT_wCGR1 9
1897#define ARM_IWMMXT_wCGR2 10
1898#define ARM_IWMMXT_wCGR3 11
balrog18c9b562007-04-30 02:02:17 +00001899
Peter Maydell2c4da502017-01-27 15:20:23 +00001900/* V7M CCR bits */
1901FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1902FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1903FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1904FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1905FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1906FIELD(V7M_CCR, STKALIGN, 9, 1)
Peter Maydell4730fb82018-10-08 14:55:04 +01001907FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
Peter Maydell2c4da502017-01-27 15:20:23 +00001908FIELD(V7M_CCR, DC, 16, 1)
1909FIELD(V7M_CCR, IC, 17, 1)
Peter Maydell4730fb82018-10-08 14:55:04 +01001910FIELD(V7M_CCR, BP, 18, 1)
Peter Maydell0e83f902020-11-19 21:56:11 +00001911FIELD(V7M_CCR, LOB, 19, 1)
1912FIELD(V7M_CCR, TRD, 20, 1)
Peter Maydell2c4da502017-01-27 15:20:23 +00001913
Peter Maydell24ac0fb2018-02-15 18:29:37 +00001914/* V7M SCR bits */
1915FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1916FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1917FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1918FIELD(V7M_SCR, SEVONPEND, 4, 1)
1919
Peter Maydell3b2e9342017-09-12 19:13:52 +01001920/* V7M AIRCR bits */
1921FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1922FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1923FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1924FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1925FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1926FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1927FIELD(V7M_AIRCR, PRIS, 14, 1)
1928FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1929FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1930
Peter Maydell2c4da502017-01-27 15:20:23 +00001931/* V7M CFSR bits for MMFSR */
1932FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1933FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1934FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1935FIELD(V7M_CFSR, MSTKERR, 4, 1)
1936FIELD(V7M_CFSR, MLSPERR, 5, 1)
1937FIELD(V7M_CFSR, MMARVALID, 7, 1)
1938
1939/* V7M CFSR bits for BFSR */
1940FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1941FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1942FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1943FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1944FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1945FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1946FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1947
1948/* V7M CFSR bits for UFSR */
1949FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1950FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1951FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1952FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
Peter Maydell86f026d2018-10-08 14:55:04 +01001953FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
Peter Maydell2c4da502017-01-27 15:20:23 +00001954FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1955FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1956
Peter Maydell334e8da2017-09-07 13:54:54 +01001957/* V7M CFSR bit masks covering all of the subregister bits */
1958FIELD(V7M_CFSR, MMFSR, 0, 8)
1959FIELD(V7M_CFSR, BFSR, 8, 8)
1960FIELD(V7M_CFSR, UFSR, 16, 16)
1961
Peter Maydell2c4da502017-01-27 15:20:23 +00001962/* V7M HFSR bits */
1963FIELD(V7M_HFSR, VECTTBL, 1, 1)
1964FIELD(V7M_HFSR, FORCED, 30, 1)
1965FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1966
1967/* V7M DFSR bits */
1968FIELD(V7M_DFSR, HALTED, 0, 1)
1969FIELD(V7M_DFSR, BKPT, 1, 1)
1970FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1971FIELD(V7M_DFSR, VCATCH, 3, 1)
1972FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1973
Peter Maydellbed079d2017-10-06 16:46:48 +01001974/* V7M SFSR bits */
1975FIELD(V7M_SFSR, INVEP, 0, 1)
1976FIELD(V7M_SFSR, INVIS, 1, 1)
1977FIELD(V7M_SFSR, INVER, 2, 1)
1978FIELD(V7M_SFSR, AUVIOL, 3, 1)
1979FIELD(V7M_SFSR, INVTRAN, 4, 1)
1980FIELD(V7M_SFSR, LSPERR, 5, 1)
1981FIELD(V7M_SFSR, SFARVALID, 6, 1)
1982FIELD(V7M_SFSR, LSERR, 7, 1)
1983
Michael Davidsaver29c483a2017-06-02 11:51:48 +01001984/* v7M MPU_CTRL bits */
1985FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1986FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1987FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1988
Peter Maydell43bbce72018-02-15 18:29:37 +00001989/* v7M CLIDR bits */
1990FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1991FIELD(V7M_CLIDR, LOUIS, 21, 3)
1992FIELD(V7M_CLIDR, LOC, 24, 3)
1993FIELD(V7M_CLIDR, LOUU, 27, 3)
1994FIELD(V7M_CLIDR, ICB, 30, 2)
1995
1996FIELD(V7M_CSSELR, IND, 0, 1)
1997FIELD(V7M_CSSELR, LEVEL, 1, 3)
1998/* We use the combination of InD and Level to index into cpu->ccsidr[];
1999 * define a mask for this and check that it doesn't permit running off
2000 * the end of the array.
2001 */
2002FIELD(V7M_CSSELR, INDEX, 0, 4)
2003
Peter Maydelld33abe82019-04-29 17:35:58 +01002004/* v7M FPCCR bits */
2005FIELD(V7M_FPCCR, LSPACT, 0, 1)
2006FIELD(V7M_FPCCR, USER, 1, 1)
2007FIELD(V7M_FPCCR, S, 2, 1)
2008FIELD(V7M_FPCCR, THREAD, 3, 1)
2009FIELD(V7M_FPCCR, HFRDY, 4, 1)
2010FIELD(V7M_FPCCR, MMRDY, 5, 1)
2011FIELD(V7M_FPCCR, BFRDY, 6, 1)
2012FIELD(V7M_FPCCR, SFRDY, 7, 1)
2013FIELD(V7M_FPCCR, MONRDY, 8, 1)
2014FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
2015FIELD(V7M_FPCCR, UFRDY, 10, 1)
2016FIELD(V7M_FPCCR, RES0, 11, 15)
2017FIELD(V7M_FPCCR, TS, 26, 1)
2018FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
2019FIELD(V7M_FPCCR, CLRONRET, 28, 1)
2020FIELD(V7M_FPCCR, LSPENS, 29, 1)
2021FIELD(V7M_FPCCR, LSPEN, 30, 1)
2022FIELD(V7M_FPCCR, ASPEN, 31, 1)
2023/* These bits are banked. Others are non-banked and live in the M_REG_S bank */
2024#define R_V7M_FPCCR_BANKED_MASK \
2025 (R_V7M_FPCCR_LSPACT_MASK | \
2026 R_V7M_FPCCR_USER_MASK | \
2027 R_V7M_FPCCR_THREAD_MASK | \
2028 R_V7M_FPCCR_MMRDY_MASK | \
2029 R_V7M_FPCCR_SPLIMVIOL_MASK | \
2030 R_V7M_FPCCR_UFRDY_MASK | \
2031 R_V7M_FPCCR_ASPEN_MASK)
2032
Peter Maydell7c3d47d2021-05-20 16:28:37 +01002033/* v7M VPR bits */
2034FIELD(V7M_VPR, P0, 0, 16)
2035FIELD(V7M_VPR, MASK01, 16, 4)
2036FIELD(V7M_VPR, MASK23, 20, 4)
2037
Richard Hendersona62e62a2018-10-08 14:21:57 -07002038/*
2039 * System register ID fields.
2040 */
Leif Lindholm2a145262021-01-08 18:51:52 +00002041FIELD(CLIDR_EL1, CTYPE1, 0, 3)
2042FIELD(CLIDR_EL1, CTYPE2, 3, 3)
2043FIELD(CLIDR_EL1, CTYPE3, 6, 3)
2044FIELD(CLIDR_EL1, CTYPE4, 9, 3)
2045FIELD(CLIDR_EL1, CTYPE5, 12, 3)
2046FIELD(CLIDR_EL1, CTYPE6, 15, 3)
2047FIELD(CLIDR_EL1, CTYPE7, 18, 3)
2048FIELD(CLIDR_EL1, LOUIS, 21, 3)
2049FIELD(CLIDR_EL1, LOC, 24, 3)
2050FIELD(CLIDR_EL1, LOUU, 27, 3)
2051FIELD(CLIDR_EL1, ICB, 30, 3)
2052
2053/* When FEAT_CCIDX is implemented */
2054FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
2055FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
2056FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
2057
2058/* When FEAT_CCIDX is not implemented */
2059FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
2060FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
2061FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
2062
2063FIELD(CTR_EL0, IMINLINE, 0, 4)
2064FIELD(CTR_EL0, L1IP, 14, 2)
2065FIELD(CTR_EL0, DMINLINE, 16, 4)
2066FIELD(CTR_EL0, ERG, 20, 4)
2067FIELD(CTR_EL0, CWG, 24, 4)
2068FIELD(CTR_EL0, IDC, 28, 1)
2069FIELD(CTR_EL0, DIC, 29, 1)
2070FIELD(CTR_EL0, TMINLINE, 32, 6)
2071
Alex Bennée2bd5f412019-08-15 09:46:41 +01002072FIELD(MIDR_EL1, REVISION, 0, 4)
2073FIELD(MIDR_EL1, PARTNUM, 4, 12)
2074FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
2075FIELD(MIDR_EL1, VARIANT, 20, 4)
2076FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
2077
Richard Hendersona62e62a2018-10-08 14:21:57 -07002078FIELD(ID_ISAR0, SWAP, 0, 4)
2079FIELD(ID_ISAR0, BITCOUNT, 4, 4)
2080FIELD(ID_ISAR0, BITFIELD, 8, 4)
2081FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
2082FIELD(ID_ISAR0, COPROC, 16, 4)
2083FIELD(ID_ISAR0, DEBUG, 20, 4)
2084FIELD(ID_ISAR0, DIVIDE, 24, 4)
2085
2086FIELD(ID_ISAR1, ENDIAN, 0, 4)
2087FIELD(ID_ISAR1, EXCEPT, 4, 4)
2088FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
2089FIELD(ID_ISAR1, EXTEND, 12, 4)
2090FIELD(ID_ISAR1, IFTHEN, 16, 4)
2091FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
2092FIELD(ID_ISAR1, INTERWORK, 24, 4)
2093FIELD(ID_ISAR1, JAZELLE, 28, 4)
2094
2095FIELD(ID_ISAR2, LOADSTORE, 0, 4)
2096FIELD(ID_ISAR2, MEMHINT, 4, 4)
2097FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
2098FIELD(ID_ISAR2, MULT, 12, 4)
2099FIELD(ID_ISAR2, MULTS, 16, 4)
2100FIELD(ID_ISAR2, MULTU, 20, 4)
2101FIELD(ID_ISAR2, PSR_AR, 24, 4)
2102FIELD(ID_ISAR2, REVERSAL, 28, 4)
2103
2104FIELD(ID_ISAR3, SATURATE, 0, 4)
2105FIELD(ID_ISAR3, SIMD, 4, 4)
2106FIELD(ID_ISAR3, SVC, 8, 4)
2107FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
2108FIELD(ID_ISAR3, TABBRANCH, 16, 4)
2109FIELD(ID_ISAR3, T32COPY, 20, 4)
2110FIELD(ID_ISAR3, TRUENOP, 24, 4)
2111FIELD(ID_ISAR3, T32EE, 28, 4)
2112
2113FIELD(ID_ISAR4, UNPRIV, 0, 4)
2114FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
2115FIELD(ID_ISAR4, WRITEBACK, 8, 4)
2116FIELD(ID_ISAR4, SMC, 12, 4)
2117FIELD(ID_ISAR4, BARRIER, 16, 4)
2118FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
2119FIELD(ID_ISAR4, PSR_M, 24, 4)
2120FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
2121
2122FIELD(ID_ISAR5, SEVL, 0, 4)
2123FIELD(ID_ISAR5, AES, 4, 4)
2124FIELD(ID_ISAR5, SHA1, 8, 4)
2125FIELD(ID_ISAR5, SHA2, 12, 4)
2126FIELD(ID_ISAR5, CRC32, 16, 4)
2127FIELD(ID_ISAR5, RDM, 24, 4)
2128FIELD(ID_ISAR5, VCMA, 28, 4)
2129
2130FIELD(ID_ISAR6, JSCVT, 0, 4)
2131FIELD(ID_ISAR6, DP, 4, 4)
2132FIELD(ID_ISAR6, FHM, 8, 4)
2133FIELD(ID_ISAR6, SB, 12, 4)
2134FIELD(ID_ISAR6, SPECRES, 16, 4)
Leif Lindholmbd78b6b2021-01-08 18:51:54 +00002135FIELD(ID_ISAR6, BF16, 20, 4)
2136FIELD(ID_ISAR6, I8MM, 24, 4)
Richard Hendersona62e62a2018-10-08 14:21:57 -07002137
Peter Maydell0ae03262020-09-10 18:38:51 +01002138FIELD(ID_MMFR0, VMSA, 0, 4)
2139FIELD(ID_MMFR0, PMSA, 4, 4)
2140FIELD(ID_MMFR0, OUTERSHR, 8, 4)
2141FIELD(ID_MMFR0, SHARELVL, 12, 4)
2142FIELD(ID_MMFR0, TCM, 16, 4)
2143FIELD(ID_MMFR0, AUXREG, 20, 4)
2144FIELD(ID_MMFR0, FCSE, 24, 4)
2145FIELD(ID_MMFR0, INNERSHR, 28, 4)
2146
Leif Lindholmbd78b6b2021-01-08 18:51:54 +00002147FIELD(ID_MMFR1, L1HVDVA, 0, 4)
2148FIELD(ID_MMFR1, L1UNIVA, 4, 4)
2149FIELD(ID_MMFR1, L1HVDSW, 8, 4)
2150FIELD(ID_MMFR1, L1UNISW, 12, 4)
2151FIELD(ID_MMFR1, L1HVD, 16, 4)
2152FIELD(ID_MMFR1, L1UNI, 20, 4)
2153FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
2154FIELD(ID_MMFR1, BPRED, 28, 4)
2155
2156FIELD(ID_MMFR2, L1HVDFG, 0, 4)
2157FIELD(ID_MMFR2, L1HVDBG, 4, 4)
2158FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
2159FIELD(ID_MMFR2, HVDTLB, 12, 4)
2160FIELD(ID_MMFR2, UNITLB, 16, 4)
2161FIELD(ID_MMFR2, MEMBARR, 20, 4)
2162FIELD(ID_MMFR2, WFISTALL, 24, 4)
2163FIELD(ID_MMFR2, HWACCFLG, 28, 4)
2164
Richard Henderson3d6ad6b2020-02-08 12:57:59 +00002165FIELD(ID_MMFR3, CMAINTVA, 0, 4)
2166FIELD(ID_MMFR3, CMAINTSW, 4, 4)
2167FIELD(ID_MMFR3, BPMAINT, 8, 4)
2168FIELD(ID_MMFR3, MAINTBCST, 12, 4)
2169FIELD(ID_MMFR3, PAN, 16, 4)
2170FIELD(ID_MMFR3, COHWALK, 20, 4)
2171FIELD(ID_MMFR3, CMEMSZ, 24, 4)
2172FIELD(ID_MMFR3, SUPERSEC, 28, 4)
2173
Richard Hendersonab638a32018-12-13 13:48:07 +00002174FIELD(ID_MMFR4, SPECSEI, 0, 4)
2175FIELD(ID_MMFR4, AC2, 4, 4)
2176FIELD(ID_MMFR4, XNX, 8, 4)
2177FIELD(ID_MMFR4, CNP, 12, 4)
2178FIELD(ID_MMFR4, HPDS, 16, 4)
2179FIELD(ID_MMFR4, LSM, 20, 4)
2180FIELD(ID_MMFR4, CCIDX, 24, 4)
2181FIELD(ID_MMFR4, EVT, 28, 4)
2182
Leif Lindholmbd78b6b2021-01-08 18:51:54 +00002183FIELD(ID_MMFR5, ETS, 0, 4)
Richard Hendersonc42fb262022-04-17 10:43:28 -07002184FIELD(ID_MMFR5, NTLBPA, 4, 4)
Leif Lindholmbd78b6b2021-01-08 18:51:54 +00002185
Peter Maydell46f49762020-11-19 21:56:14 +00002186FIELD(ID_PFR0, STATE0, 0, 4)
2187FIELD(ID_PFR0, STATE1, 4, 4)
2188FIELD(ID_PFR0, STATE2, 8, 4)
2189FIELD(ID_PFR0, STATE3, 12, 4)
2190FIELD(ID_PFR0, CSV2, 16, 4)
2191FIELD(ID_PFR0, AMU, 20, 4)
2192FIELD(ID_PFR0, DIT, 24, 4)
2193FIELD(ID_PFR0, RAS, 28, 4)
2194
Peter Maydelldfc523a2020-09-10 18:38:55 +01002195FIELD(ID_PFR1, PROGMOD, 0, 4)
2196FIELD(ID_PFR1, SECURITY, 4, 4)
2197FIELD(ID_PFR1, MPROGMOD, 8, 4)
2198FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
2199FIELD(ID_PFR1, GENTIMER, 16, 4)
2200FIELD(ID_PFR1, SEC_FRAC, 20, 4)
2201FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
2202FIELD(ID_PFR1, GIC, 28, 4)
2203
Leif Lindholmbd78b6b2021-01-08 18:51:54 +00002204FIELD(ID_PFR2, CSV3, 0, 4)
2205FIELD(ID_PFR2, SSBS, 4, 4)
2206FIELD(ID_PFR2, RAS_FRAC, 8, 4)
2207
Richard Hendersona62e62a2018-10-08 14:21:57 -07002208FIELD(ID_AA64ISAR0, AES, 4, 4)
2209FIELD(ID_AA64ISAR0, SHA1, 8, 4)
2210FIELD(ID_AA64ISAR0, SHA2, 12, 4)
2211FIELD(ID_AA64ISAR0, CRC32, 16, 4)
2212FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
Peter Maydell4d9eb292023-09-15 15:37:00 +01002213FIELD(ID_AA64ISAR0, TME, 24, 4)
Richard Hendersona62e62a2018-10-08 14:21:57 -07002214FIELD(ID_AA64ISAR0, RDM, 28, 4)
2215FIELD(ID_AA64ISAR0, SHA3, 32, 4)
2216FIELD(ID_AA64ISAR0, SM3, 36, 4)
2217FIELD(ID_AA64ISAR0, SM4, 40, 4)
2218FIELD(ID_AA64ISAR0, DP, 44, 4)
2219FIELD(ID_AA64ISAR0, FHM, 48, 4)
2220FIELD(ID_AA64ISAR0, TS, 52, 4)
2221FIELD(ID_AA64ISAR0, TLB, 56, 4)
2222FIELD(ID_AA64ISAR0, RNDR, 60, 4)
2223
2224FIELD(ID_AA64ISAR1, DPB, 0, 4)
2225FIELD(ID_AA64ISAR1, APA, 4, 4)
2226FIELD(ID_AA64ISAR1, API, 8, 4)
2227FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
2228FIELD(ID_AA64ISAR1, FCMA, 16, 4)
2229FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
2230FIELD(ID_AA64ISAR1, GPA, 24, 4)
2231FIELD(ID_AA64ISAR1, GPI, 28, 4)
2232FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
2233FIELD(ID_AA64ISAR1, SB, 36, 4)
2234FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
Leif Lindholm00a92832021-01-08 18:51:53 +00002235FIELD(ID_AA64ISAR1, BF16, 44, 4)
2236FIELD(ID_AA64ISAR1, DGH, 48, 4)
2237FIELD(ID_AA64ISAR1, I8MM, 52, 4)
Richard Hendersonc42fb262022-04-17 10:43:28 -07002238FIELD(ID_AA64ISAR1, XS, 56, 4)
2239FIELD(ID_AA64ISAR1, LS64, 60, 4)
2240
2241FIELD(ID_AA64ISAR2, WFXT, 0, 4)
2242FIELD(ID_AA64ISAR2, RPRES, 4, 4)
2243FIELD(ID_AA64ISAR2, GPA3, 8, 4)
2244FIELD(ID_AA64ISAR2, APA3, 12, 4)
2245FIELD(ID_AA64ISAR2, MOPS, 16, 4)
2246FIELD(ID_AA64ISAR2, BC, 20, 4)
2247FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4)
Peter Maydell4d9eb292023-09-15 15:37:00 +01002248FIELD(ID_AA64ISAR2, CLRBHB, 28, 4)
2249FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4)
2250FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4)
2251FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4)
2252FIELD(ID_AA64ISAR2, RPRFM, 48, 4)
2253FIELD(ID_AA64ISAR2, CSSC, 52, 4)
2254FIELD(ID_AA64ISAR2, ATS1A, 60, 4)
Richard Hendersona62e62a2018-10-08 14:21:57 -07002255
Richard Hendersoncd208a12018-10-24 07:50:17 +01002256FIELD(ID_AA64PFR0, EL0, 0, 4)
2257FIELD(ID_AA64PFR0, EL1, 4, 4)
2258FIELD(ID_AA64PFR0, EL2, 8, 4)
2259FIELD(ID_AA64PFR0, EL3, 12, 4)
2260FIELD(ID_AA64PFR0, FP, 16, 4)
2261FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
2262FIELD(ID_AA64PFR0, GIC, 24, 4)
2263FIELD(ID_AA64PFR0, RAS, 28, 4)
2264FIELD(ID_AA64PFR0, SVE, 32, 4)
Leif Lindholm00a92832021-01-08 18:51:53 +00002265FIELD(ID_AA64PFR0, SEL2, 36, 4)
2266FIELD(ID_AA64PFR0, MPAM, 40, 4)
2267FIELD(ID_AA64PFR0, AMU, 44, 4)
2268FIELD(ID_AA64PFR0, DIT, 48, 4)
Richard Hendersonb9f335c2023-06-23 11:15:43 +01002269FIELD(ID_AA64PFR0, RME, 52, 4)
Leif Lindholm00a92832021-01-08 18:51:53 +00002270FIELD(ID_AA64PFR0, CSV2, 56, 4)
2271FIELD(ID_AA64PFR0, CSV3, 60, 4)
Richard Hendersoncd208a12018-10-24 07:50:17 +01002272
Richard Hendersonbe53b6f2019-02-05 16:52:36 +00002273FIELD(ID_AA64PFR1, BT, 0, 4)
Leif Lindholm9a286bc2021-01-08 18:51:49 +00002274FIELD(ID_AA64PFR1, SSBS, 4, 4)
Richard Hendersonbe53b6f2019-02-05 16:52:36 +00002275FIELD(ID_AA64PFR1, MTE, 8, 4)
2276FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
Leif Lindholm00a92832021-01-08 18:51:53 +00002277FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
Richard Hendersonc42fb262022-04-17 10:43:28 -07002278FIELD(ID_AA64PFR1, SME, 24, 4)
2279FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4)
2280FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4)
2281FIELD(ID_AA64PFR1, NMI, 36, 4)
Peter Maydell4d9eb292023-09-15 15:37:00 +01002282FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4)
2283FIELD(ID_AA64PFR1, GCS, 44, 4)
2284FIELD(ID_AA64PFR1, THE, 48, 4)
2285FIELD(ID_AA64PFR1, MTEX, 52, 4)
2286FIELD(ID_AA64PFR1, DF2, 56, 4)
2287FIELD(ID_AA64PFR1, PFAR, 60, 4)
Richard Hendersonbe53b6f2019-02-05 16:52:36 +00002288
Peter Maydell3dc91dd2018-12-13 14:40:56 +00002289FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
2290FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
2291FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
2292FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
2293FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
2294FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
2295FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
2296FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
2297FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
2298FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
2299FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
2300FIELD(ID_AA64MMFR0, EXS, 44, 4)
Leif Lindholm00a92832021-01-08 18:51:53 +00002301FIELD(ID_AA64MMFR0, FGT, 56, 4)
2302FIELD(ID_AA64MMFR0, ECV, 60, 4)
Peter Maydell3dc91dd2018-12-13 14:40:56 +00002303
2304FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
2305FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
2306FIELD(ID_AA64MMFR1, VH, 8, 4)
2307FIELD(ID_AA64MMFR1, HPDS, 12, 4)
2308FIELD(ID_AA64MMFR1, LO, 16, 4)
2309FIELD(ID_AA64MMFR1, PAN, 20, 4)
2310FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
2311FIELD(ID_AA64MMFR1, XNX, 28, 4)
Leif Lindholm00a92832021-01-08 18:51:53 +00002312FIELD(ID_AA64MMFR1, TWED, 32, 4)
2313FIELD(ID_AA64MMFR1, ETS, 36, 4)
Richard Hendersonc42fb262022-04-17 10:43:28 -07002314FIELD(ID_AA64MMFR1, HCX, 40, 4)
2315FIELD(ID_AA64MMFR1, AFP, 44, 4)
2316FIELD(ID_AA64MMFR1, NTLBPA, 48, 4)
2317FIELD(ID_AA64MMFR1, TIDCP1, 52, 4)
2318FIELD(ID_AA64MMFR1, CMOW, 56, 4)
Peter Maydell4d9eb292023-09-15 15:37:00 +01002319FIELD(ID_AA64MMFR1, ECBHB, 60, 4)
Peter Maydell3dc91dd2018-12-13 14:40:56 +00002320
Richard Henderson64761e12020-02-08 12:58:13 +00002321FIELD(ID_AA64MMFR2, CNP, 0, 4)
2322FIELD(ID_AA64MMFR2, UAO, 4, 4)
2323FIELD(ID_AA64MMFR2, LSM, 8, 4)
2324FIELD(ID_AA64MMFR2, IESB, 12, 4)
2325FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
2326FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
2327FIELD(ID_AA64MMFR2, NV, 24, 4)
2328FIELD(ID_AA64MMFR2, ST, 28, 4)
2329FIELD(ID_AA64MMFR2, AT, 32, 4)
2330FIELD(ID_AA64MMFR2, IDS, 36, 4)
2331FIELD(ID_AA64MMFR2, FWB, 40, 4)
2332FIELD(ID_AA64MMFR2, TTL, 48, 4)
2333FIELD(ID_AA64MMFR2, BBM, 52, 4)
2334FIELD(ID_AA64MMFR2, EVT, 56, 4)
2335FIELD(ID_AA64MMFR2, E0PD, 60, 4)
2336
Peter Maydellceb27442020-02-14 17:51:01 +00002337FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
2338FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
2339FIELD(ID_AA64DFR0, PMUVER, 8, 4)
2340FIELD(ID_AA64DFR0, BRPS, 12, 4)
Peter Maydell4d9eb292023-09-15 15:37:00 +01002341FIELD(ID_AA64DFR0, PMSS, 16, 4)
Peter Maydellceb27442020-02-14 17:51:01 +00002342FIELD(ID_AA64DFR0, WRPS, 20, 4)
Peter Maydell4d9eb292023-09-15 15:37:00 +01002343FIELD(ID_AA64DFR0, SEBEP, 24, 4)
Peter Maydellceb27442020-02-14 17:51:01 +00002344FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
2345FIELD(ID_AA64DFR0, PMSVER, 32, 4)
2346FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
2347FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
Richard Hendersonc42fb262022-04-17 10:43:28 -07002348FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4)
Leif Lindholm00a92832021-01-08 18:51:53 +00002349FIELD(ID_AA64DFR0, MTPMU, 48, 4)
Richard Hendersonc42fb262022-04-17 10:43:28 -07002350FIELD(ID_AA64DFR0, BRBE, 52, 4)
Peter Maydell4d9eb292023-09-15 15:37:00 +01002351FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4)
Richard Hendersonc42fb262022-04-17 10:43:28 -07002352FIELD(ID_AA64DFR0, HPMN0, 60, 4)
Peter Maydellceb27442020-02-14 17:51:01 +00002353
Richard Henderson2dc10fa2021-05-24 18:02:27 -07002354FIELD(ID_AA64ZFR0, SVEVER, 0, 4)
2355FIELD(ID_AA64ZFR0, AES, 4, 4)
2356FIELD(ID_AA64ZFR0, BITPERM, 16, 4)
2357FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4)
Peter Maydell4d9eb292023-09-15 15:37:00 +01002358FIELD(ID_AA64ZFR0, B16B16, 24, 4)
Richard Henderson2dc10fa2021-05-24 18:02:27 -07002359FIELD(ID_AA64ZFR0, SHA3, 32, 4)
2360FIELD(ID_AA64ZFR0, SM4, 40, 4)
2361FIELD(ID_AA64ZFR0, I8MM, 44, 4)
2362FIELD(ID_AA64ZFR0, F32MM, 52, 4)
2363FIELD(ID_AA64ZFR0, F64MM, 56, 4)
2364
Richard Henderson414c54d2022-06-08 19:38:59 +01002365FIELD(ID_AA64SMFR0, F32F32, 32, 1)
Peter Maydell4d9eb292023-09-15 15:37:00 +01002366FIELD(ID_AA64SMFR0, BI32I32, 33, 1)
Richard Henderson414c54d2022-06-08 19:38:59 +01002367FIELD(ID_AA64SMFR0, B16F32, 34, 1)
2368FIELD(ID_AA64SMFR0, F16F32, 35, 1)
2369FIELD(ID_AA64SMFR0, I8I32, 36, 4)
Peter Maydell4d9eb292023-09-15 15:37:00 +01002370FIELD(ID_AA64SMFR0, F16F16, 42, 1)
2371FIELD(ID_AA64SMFR0, B16B16, 43, 1)
2372FIELD(ID_AA64SMFR0, I16I32, 44, 4)
Richard Henderson414c54d2022-06-08 19:38:59 +01002373FIELD(ID_AA64SMFR0, F64F64, 48, 1)
2374FIELD(ID_AA64SMFR0, I16I64, 52, 4)
2375FIELD(ID_AA64SMFR0, SMEVER, 56, 4)
2376FIELD(ID_AA64SMFR0, FA64, 63, 1)
2377
Aaron Lindsaybeceb992019-01-21 10:23:14 +00002378FIELD(ID_DFR0, COPDBG, 0, 4)
2379FIELD(ID_DFR0, COPSDBG, 4, 4)
2380FIELD(ID_DFR0, MMAPDBG, 8, 4)
2381FIELD(ID_DFR0, COPTRC, 12, 4)
2382FIELD(ID_DFR0, MMAPTRC, 16, 4)
2383FIELD(ID_DFR0, MPROFDBG, 20, 4)
2384FIELD(ID_DFR0, PERFMON, 24, 4)
2385FIELD(ID_DFR0, TRACEFILT, 28, 4)
2386
Leif Lindholmbd78b6b2021-01-08 18:51:54 +00002387FIELD(ID_DFR1, MTPMU, 0, 4)
Richard Hendersonc42fb262022-04-17 10:43:28 -07002388FIELD(ID_DFR1, HPMN0, 4, 4)
Leif Lindholmbd78b6b2021-01-08 18:51:54 +00002389
Peter Maydell88ce6c62020-02-14 17:51:05 +00002390FIELD(DBGDIDR, SE_IMP, 12, 1)
2391FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
2392FIELD(DBGDIDR, VERSION, 16, 4)
2393FIELD(DBGDIDR, CTX_CMPS, 20, 4)
2394FIELD(DBGDIDR, BRPS, 24, 4)
2395FIELD(DBGDIDR, WRPS, 28, 4)
2396
Peter Maydellf94a6df2022-07-07 11:38:36 +01002397FIELD(DBGDEVID, PCSAMPLE, 0, 4)
2398FIELD(DBGDEVID, WPADDRMASK, 4, 4)
2399FIELD(DBGDEVID, BPADDRMASK, 8, 4)
2400FIELD(DBGDEVID, VECTORCATCH, 12, 4)
2401FIELD(DBGDEVID, VIRTEXTNS, 16, 4)
2402FIELD(DBGDEVID, DOUBLELOCK, 20, 4)
2403FIELD(DBGDEVID, AUXREGS, 24, 4)
2404FIELD(DBGDEVID, CIDMASK, 28, 4)
2405
Peter Maydell602f6e42019-02-28 10:55:16 +00002406FIELD(MVFR0, SIMDREG, 0, 4)
2407FIELD(MVFR0, FPSP, 4, 4)
2408FIELD(MVFR0, FPDP, 8, 4)
2409FIELD(MVFR0, FPTRAP, 12, 4)
2410FIELD(MVFR0, FPDIVIDE, 16, 4)
2411FIELD(MVFR0, FPSQRT, 20, 4)
2412FIELD(MVFR0, FPSHVEC, 24, 4)
2413FIELD(MVFR0, FPROUND, 28, 4)
2414
2415FIELD(MVFR1, FPFTZ, 0, 4)
2416FIELD(MVFR1, FPDNAN, 4, 4)
Peter Maydelldfc523a2020-09-10 18:38:55 +01002417FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
2418FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
2419FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
2420FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
2421FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
2422FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
Peter Maydell602f6e42019-02-28 10:55:16 +00002423FIELD(MVFR1, FPHP, 24, 4)
2424FIELD(MVFR1, SIMDFMAC, 28, 4)
2425
2426FIELD(MVFR2, SIMDMISC, 0, 4)
2427FIELD(MVFR2, FPMISC, 4, 4)
2428
Richard Hendersonef1febe2023-06-23 11:15:44 +01002429FIELD(GPCCR, PPS, 0, 3)
2430FIELD(GPCCR, IRGN, 8, 2)
2431FIELD(GPCCR, ORGN, 10, 2)
2432FIELD(GPCCR, SH, 12, 2)
2433FIELD(GPCCR, PGS, 14, 2)
2434FIELD(GPCCR, GPC, 16, 1)
2435FIELD(GPCCR, GPCP, 17, 1)
2436FIELD(GPCCR, L0GPTSZ, 20, 4)
2437
2438FIELD(MFAR, FPA, 12, 40)
2439FIELD(MFAR, NSE, 62, 1)
2440FIELD(MFAR, NS, 63, 1)
2441
Peter Maydell43bbce72018-02-15 18:29:37 +00002442QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
2443
Benoit Canetce854d72011-11-09 07:32:59 +00002444/* If adding a feature bit which corresponds to a Linux ELF
2445 * HWCAP bit, remember to update the feature-bit-to-hwcap
2446 * mapping in linux-user/elfload.c:get_elf_hwcap().
2447 */
pbrook40f137e2006-02-20 00:33:36 +00002448enum arm_features {
balrogc1713132007-04-30 01:26:42 +00002449 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
2450 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
pbrookce819862007-05-08 02:30:40 +00002451 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
pbrook9ee6e8b2007-11-11 00:04:49 +00002452 ARM_FEATURE_V6,
2453 ARM_FEATURE_V6K,
2454 ARM_FEATURE_V7,
2455 ARM_FEATURE_THUMB2,
Peter Maydell452a0952017-06-02 11:51:47 +01002456 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
pbrook9ee6e8b2007-11-11 00:04:49 +00002457 ARM_FEATURE_NEON,
pbrook9ee6e8b2007-11-11 00:04:49 +00002458 ARM_FEATURE_M, /* Microcontroller profile. */
pbrookfe1479c2008-12-19 13:18:36 +00002459 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
Peter Maydelle1bbf442011-02-03 19:43:22 +00002460 ARM_FEATURE_THUMB2EE,
Dmitry Eremin-Solenikovbe5e7a72011-04-04 17:38:44 +04002461 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
Aaron Lindsay5110e682018-06-29 15:11:17 +01002462 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
Dmitry Eremin-Solenikovbe5e7a72011-04-04 17:38:44 +04002463 ARM_FEATURE_V4T,
2464 ARM_FEATURE_V5,
Dmitry Eremin-Solenikov5bc95aa2011-04-19 18:56:45 +04002465 ARM_FEATURE_STRONGARM,
Peter Maydell906879a2011-07-20 10:32:55 +00002466 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
Peter Maydell0383ac02012-01-25 12:42:29 +00002467 ARM_FEATURE_GENERIC_TIMER,
Andrew Towers06ed5d62012-03-29 02:41:08 +00002468 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
Peter Maydell1047b9d2012-06-20 11:57:15 +00002469 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
Peter Maydellc4804212012-06-20 11:57:17 +00002470 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
2471 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
2472 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
Peter Maydell81bdde92012-06-20 11:57:20 +00002473 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
Peter Maydellde9b05b2012-07-12 10:59:05 +00002474 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
Mans Rullgard81e69fb2013-07-15 14:35:25 +01002475 ARM_FEATURE_V8,
Alexander Graf3926cc82013-09-03 20:12:09 +01002476 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
Peter Crosthwaited8ba7802013-12-17 19:42:28 +00002477 ARM_FEATURE_CBAR, /* has cp15 CBAR */
Peter Maydellf318cec2014-04-15 19:18:49 +01002478 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
Edgar E. Iglesiascca7c2f2014-05-27 17:09:52 +01002479 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
Edgar E. Iglesias1fe81412014-05-27 17:09:53 +01002480 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
Aurelio C. Remonda62b44f02015-06-15 18:06:09 +01002481 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
Wei Huang929e7542016-10-28 14:12:31 +01002482 ARM_FEATURE_PMU, /* has PMU support */
Cédric Le Goater91db4642016-12-27 14:59:30 +00002483 ARM_FEATURE_VBAR, /* has cp15 VBAR */
Peter Maydell1e577cc2017-09-07 13:54:52 +01002484 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
Julia Suvorovacc2ae7c2018-06-22 13:28:41 +01002485 ARM_FEATURE_M_MAIN, /* M profile Main Extension */
Peter Maydell5d2555a2020-10-19 16:12:53 +01002486 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
pbrook40f137e2006-02-20 00:33:36 +00002487};
2488
2489static inline int arm_feature(CPUARMState *env, int feature)
2490{
Peter Maydell918f5dc2012-07-12 10:59:06 +00002491 return (env->features & (1ULL << feature)) != 0;
pbrook40f137e2006-02-20 00:33:36 +00002492}
2493
Andrew Jones0df91422019-10-31 15:27:29 +01002494void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
2495
Richard Hendersonfcc74042023-02-27 12:58:31 -10002496/*
Richard Henderson5d28ac02023-06-23 11:15:44 +01002497 * ARM v9 security states.
2498 * The ordering of the enumeration corresponds to the low 2 bits
2499 * of the GPI value, and (except for Root) the concat of NSE:NS.
2500 */
2501
2502typedef enum ARMSecuritySpace {
2503 ARMSS_Secure = 0,
2504 ARMSS_NonSecure = 1,
2505 ARMSS_Root = 2,
2506 ARMSS_Realm = 3,
2507} ARMSecuritySpace;
2508
2509/* Return true if @space is secure, in the pre-v9 sense. */
2510static inline bool arm_space_is_secure(ARMSecuritySpace space)
2511{
2512 return space == ARMSS_Secure || space == ARMSS_Root;
2513}
2514
2515/* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */
2516static inline ARMSecuritySpace arm_secure_to_space(bool secure)
2517{
2518 return secure ? ARMSS_Secure : ARMSS_NonSecure;
2519}
2520
2521#if !defined(CONFIG_USER_ONLY)
2522/**
2523 * arm_security_space_below_el3:
2524 * @env: cpu context
2525 *
2526 * Return the security space of exception levels below EL3, following
2527 * an exception return to those levels. Unlike arm_security_space,
2528 * this doesn't care about the current EL.
2529 */
2530ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env);
2531
2532/**
2533 * arm_is_secure_below_el3:
2534 * @env: cpu context
2535 *
Richard Hendersonfcc74042023-02-27 12:58:31 -10002536 * Return true if exception levels below EL3 are in secure state,
Richard Henderson5d28ac02023-06-23 11:15:44 +01002537 * or would be following an exception return to those levels.
Fabian Aggeler19e0fef2014-10-24 12:19:14 +01002538 */
2539static inline bool arm_is_secure_below_el3(CPUARMState *env)
2540{
Richard Henderson5d28ac02023-06-23 11:15:44 +01002541 ARMSecuritySpace ss = arm_security_space_below_el3(env);
2542 return ss == ARMSS_Secure;
Fabian Aggeler19e0fef2014-10-24 12:19:14 +01002543}
2544
Peter Maydell71205872016-06-17 15:23:45 +01002545/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
2546static inline bool arm_is_el3_or_mon(CPUARMState *env)
Fabian Aggeler19e0fef2014-10-24 12:19:14 +01002547{
Richard Hendersonfcc74042023-02-27 12:58:31 -10002548 assert(!arm_feature(env, ARM_FEATURE_M));
Fabian Aggeler19e0fef2014-10-24 12:19:14 +01002549 if (arm_feature(env, ARM_FEATURE_EL3)) {
2550 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2551 /* CPU currently in AArch64 state and EL3 */
2552 return true;
2553 } else if (!is_a64(env) &&
2554 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2555 /* CPU currently in AArch32 state and monitor mode */
2556 return true;
2557 }
2558 }
Peter Maydell71205872016-06-17 15:23:45 +01002559 return false;
2560}
2561
Richard Henderson5d28ac02023-06-23 11:15:44 +01002562/**
2563 * arm_security_space:
2564 * @env: cpu context
2565 *
2566 * Return the current security space of the cpu.
2567 */
2568ARMSecuritySpace arm_security_space(CPUARMState *env);
2569
2570/**
2571 * arm_is_secure:
2572 * @env: cpu context
2573 *
2574 * Return true if the processor is in secure state.
2575 */
Peter Maydell71205872016-06-17 15:23:45 +01002576static inline bool arm_is_secure(CPUARMState *env)
2577{
Richard Henderson5d28ac02023-06-23 11:15:44 +01002578 return arm_space_is_secure(arm_security_space(env));
Fabian Aggeler19e0fef2014-10-24 12:19:14 +01002579}
2580
Rémi Denis-Courmontf3ee5162021-01-12 12:44:54 +02002581/*
2582 * Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
Peter Maydell44770202023-08-22 17:31:07 +01002583 * This corresponds to the pseudocode EL2Enabled().
Rémi Denis-Courmontf3ee5162021-01-12 12:44:54 +02002584 */
Peter Maydell44770202023-08-22 17:31:07 +01002585static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
2586 ARMSecuritySpace space)
Richard Hendersonb74c0442022-10-01 09:22:49 -07002587{
Peter Maydell44770202023-08-22 17:31:07 +01002588 assert(space != ARMSS_Root);
Richard Hendersonb74c0442022-10-01 09:22:49 -07002589 return arm_feature(env, ARM_FEATURE_EL2)
Peter Maydell44770202023-08-22 17:31:07 +01002590 && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2));
Richard Hendersonb74c0442022-10-01 09:22:49 -07002591}
2592
Rémi Denis-Courmontf3ee5162021-01-12 12:44:54 +02002593static inline bool arm_is_el2_enabled(CPUARMState *env)
2594{
Peter Maydell44770202023-08-22 17:31:07 +01002595 return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env));
Rémi Denis-Courmontf3ee5162021-01-12 12:44:54 +02002596}
2597
Fabian Aggeler19e0fef2014-10-24 12:19:14 +01002598#else
Richard Henderson5d28ac02023-06-23 11:15:44 +01002599static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env)
2600{
2601 return ARMSS_NonSecure;
2602}
2603
Fabian Aggeler19e0fef2014-10-24 12:19:14 +01002604static inline bool arm_is_secure_below_el3(CPUARMState *env)
2605{
2606 return false;
2607}
2608
Richard Henderson5d28ac02023-06-23 11:15:44 +01002609static inline ARMSecuritySpace arm_security_space(CPUARMState *env)
2610{
2611 return ARMSS_NonSecure;
2612}
2613
Fabian Aggeler19e0fef2014-10-24 12:19:14 +01002614static inline bool arm_is_secure(CPUARMState *env)
2615{
2616 return false;
2617}
Rémi Denis-Courmontf3ee5162021-01-12 12:44:54 +02002618
Peter Maydell44770202023-08-22 17:31:07 +01002619static inline bool arm_is_el2_enabled_secstate(CPUARMState *env,
2620 ARMSecuritySpace space)
Richard Hendersonb74c0442022-10-01 09:22:49 -07002621{
2622 return false;
2623}
2624
Rémi Denis-Courmontf3ee5162021-01-12 12:44:54 +02002625static inline bool arm_is_el2_enabled(CPUARMState *env)
2626{
2627 return false;
2628}
Fabian Aggeler19e0fef2014-10-24 12:19:14 +01002629#endif
2630
Richard Hendersonf7778442018-12-13 13:48:07 +00002631/**
2632 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
2633 * E.g. when in secure state, fields in HCR_EL2 are suppressed,
2634 * "for all purposes other than a direct read or write access of HCR_EL2."
2635 * Not included here is HCR_RW.
2636 */
Peter Maydell2d12bb92023-08-22 17:31:07 +01002637uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space);
Richard Hendersonf7778442018-12-13 13:48:07 +00002638uint64_t arm_hcr_el2_eff(CPUARMState *env);
Richard Henderson5814d582022-05-16 22:48:44 -07002639uint64_t arm_hcrx_el2_eff(CPUARMState *env);
Richard Hendersonf7778442018-12-13 13:48:07 +00002640
Peter Maydell1f79ee32014-02-26 17:20:07 +00002641/* Return true if the specified exception level is running in AArch64 state. */
2642static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2643{
Peter Maydell446c81a2016-01-21 14:15:08 +00002644 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
2645 * and if we're not in EL0 then the state of EL0 isn't well defined.)
Peter Maydell1f79ee32014-02-26 17:20:07 +00002646 */
Peter Maydell446c81a2016-01-21 14:15:08 +00002647 assert(el >= 1 && el <= 3);
2648 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
Fabian Aggeler592125f2014-10-24 12:19:14 +01002649
Peter Maydell446c81a2016-01-21 14:15:08 +00002650 /* The highest exception level is always at the maximum supported
2651 * register width, and then lower levels have a register width controlled
2652 * by bits in the SCR or HCR registers.
Peter Maydell1f79ee32014-02-26 17:20:07 +00002653 */
Peter Maydell446c81a2016-01-21 14:15:08 +00002654 if (el == 3) {
2655 return aa64;
2656 }
2657
Rémi Denis-Courmont926c1b92021-01-12 12:45:09 +02002658 if (arm_feature(env, ARM_FEATURE_EL3) &&
2659 ((env->cp15.scr_el3 & SCR_NS) || !(env->cp15.scr_el3 & SCR_EEL2))) {
Peter Maydell446c81a2016-01-21 14:15:08 +00002660 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2661 }
2662
2663 if (el == 2) {
2664 return aa64;
2665 }
2666
Rémi Denis-Courmonte6ef0162021-01-12 12:44:55 +02002667 if (arm_is_el2_enabled(env)) {
Peter Maydell446c81a2016-01-21 14:15:08 +00002668 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2669 }
2670
2671 return aa64;
Peter Maydell1f79ee32014-02-26 17:20:07 +00002672}
2673
Michael Tokarev673d8212023-07-14 14:14:49 +03002674/* Function for determining whether guest cp register reads and writes should
Sergey Fedorov3f342b92014-12-11 12:07:48 +00002675 * access the secure or non-secure bank of a cp register. When EL3 is
2676 * operating in AArch32 state, the NS-bit determines whether the secure
2677 * instance of a cp register should be used. When EL3 is AArch64 (or if
2678 * it doesn't exist at all) then there is no register banking, and all
2679 * accesses are to the non-secure version.
2680 */
2681static inline bool access_secure_reg(CPUARMState *env)
2682{
2683 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2684 !arm_el_is_aa64(env, 3) &&
2685 !(env->cp15.scr_el3 & SCR_NS));
2686
2687 return ret;
2688}
2689
Fabian Aggelerea30a4b2014-12-11 12:07:48 +00002690/* Macros for accessing a specified CP register bank */
2691#define A32_BANKED_REG_GET(_env, _regname, _secure) \
2692 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2693
2694#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
2695 do { \
2696 if (_secure) { \
2697 (_env)->cp15._regname##_s = (_val); \
2698 } else { \
2699 (_env)->cp15._regname##_ns = (_val); \
2700 } \
2701 } while (0)
2702
2703/* Macros for automatically accessing a specific CP register bank depending on
2704 * the current secure state of the system. These macros are not intended for
2705 * supporting instruction translation reads/writes as these are dependent
2706 * solely on the SCR.NS bit and not the mode.
2707 */
2708#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
2709 A32_BANKED_REG_GET((_env), _regname, \
Sergey Sorokin2cde0312015-10-16 11:14:52 +01002710 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
Fabian Aggelerea30a4b2014-12-11 12:07:48 +00002711
2712#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
2713 A32_BANKED_REG_SET((_env), _regname, \
Sergey Sorokin2cde0312015-10-16 11:14:52 +01002714 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
Fabian Aggelerea30a4b2014-12-11 12:07:48 +00002715 (_val))
2716
Greg Bellows012a9062015-05-29 11:28:51 +01002717uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2718 uint32_t cur_el, bool secure);
pbrook40f137e2006-02-20 00:33:36 +00002719
Peter Maydell75502672016-02-18 14:16:15 +00002720/* Return the highest implemented Exception Level */
2721static inline int arm_highest_el(CPUARMState *env)
2722{
2723 if (arm_feature(env, ARM_FEATURE_EL3)) {
2724 return 3;
2725 }
2726 if (arm_feature(env, ARM_FEATURE_EL2)) {
2727 return 2;
2728 }
2729 return 1;
2730}
2731
Peter Maydell15b3f552017-09-04 15:21:53 +01002732/* Return true if a v7M CPU is in Handler mode */
2733static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2734{
2735 return env->v7m.exception != 0;
2736}
2737
Greg Bellowsdcbff192014-10-24 12:19:14 +01002738/* Return the current Exception Level (as per ARMv8; note that this differs
2739 * from the ARMv7 Privilege Level).
2740 */
2741static inline int arm_current_el(CPUARMState *env)
Peter Maydell4b6a83f2012-06-20 11:57:06 +00002742{
Peter Maydell6d54ed32015-02-05 13:37:23 +00002743 if (arm_feature(env, ARM_FEATURE_M)) {
Peter Maydell8bfc26e2017-09-07 13:54:53 +01002744 return arm_v7m_is_handler_mode(env) ||
2745 !(env->v7m.control[env->v7m.secure] & 1);
Peter Maydell6d54ed32015-02-05 13:37:23 +00002746 }
2747
Fabian Aggeler592125f2014-10-24 12:19:14 +01002748 if (is_a64(env)) {
Peter Maydellf5a0a5a2014-01-04 22:15:44 +00002749 return extract32(env->pstate, 2, 2);
2750 }
2751
Fabian Aggeler592125f2014-10-24 12:19:14 +01002752 switch (env->uncached_cpsr & 0x1f) {
2753 case ARM_CPU_MODE_USR:
Peter Maydell4b6a83f2012-06-20 11:57:06 +00002754 return 0;
Fabian Aggeler592125f2014-10-24 12:19:14 +01002755 case ARM_CPU_MODE_HYP:
2756 return 2;
2757 case ARM_CPU_MODE_MON:
2758 return 3;
2759 default:
2760 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2761 /* If EL3 is 32-bit then all secure privileged modes run in
2762 * EL3
2763 */
2764 return 3;
2765 }
2766
2767 return 1;
Peter Maydell4b6a83f2012-06-20 11:57:06 +00002768 }
Peter Maydell4b6a83f2012-06-20 11:57:06 +00002769}
2770
Peter Maydell721fae12013-06-25 18:16:07 +01002771/**
2772 * write_list_to_cpustate
2773 * @cpu: ARMCPU
2774 *
2775 * For each register listed in the ARMCPU cpreg_indexes list, write
2776 * its value from the cpreg_values list into the ARMCPUState structure.
2777 * This updates TCG's working data structures from KVM data or
2778 * from incoming migration state.
2779 *
2780 * Returns: true if all register values were updated correctly,
2781 * false if some register was unknown or could not be written.
2782 * Note that we do not stop early on failure -- we will attempt
2783 * writing all registers in the list.
2784 */
2785bool write_list_to_cpustate(ARMCPU *cpu);
2786
2787/**
2788 * write_cpustate_to_list:
2789 * @cpu: ARMCPU
Peter Maydellb698e4e2019-05-07 12:55:02 +01002790 * @kvm_sync: true if this is for syncing back to KVM
Peter Maydell721fae12013-06-25 18:16:07 +01002791 *
2792 * For each register listed in the ARMCPU cpreg_indexes list, write
2793 * its value from the ARMCPUState structure into the cpreg_values list.
2794 * This is used to copy info from TCG's working data structures into
2795 * KVM or for outbound migration.
2796 *
Peter Maydellb698e4e2019-05-07 12:55:02 +01002797 * @kvm_sync is true if we are doing this in order to sync the
2798 * register state back to KVM. In this case we will only update
2799 * values in the list if the previous list->cpustate sync actually
2800 * successfully wrote the CPU state. Otherwise we will keep the value
2801 * that is in the list.
2802 *
Peter Maydell721fae12013-06-25 18:16:07 +01002803 * Returns: true if all register values were read correctly,
2804 * false if some register was unknown or could not be read.
2805 * Note that we do not stop early on failure -- we will attempt
2806 * reading all registers in the list.
2807 */
Peter Maydellb698e4e2019-05-07 12:55:02 +01002808bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
Peter Maydell721fae12013-06-25 18:16:07 +01002809
pbrook9ee6e8b2007-11-11 00:04:49 +00002810#define ARM_CPUID_TI915T 0x54029152
2811#define ARM_CPUID_TI925T 0x54029252
pbrook40f137e2006-02-20 00:33:36 +00002812
Igor Mammedov0dacec82018-02-07 11:40:25 +01002813#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
Igor Mammedovba1ba5c2017-09-13 18:04:57 +02002814
Peter Maydell585df852021-09-20 10:21:08 +01002815#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU
2816
Peter Maydellc1e37812015-02-05 13:37:23 +00002817/* ARM has the following "translation regimes" (as the ARM ARM calls them):
2818 *
2819 * If EL3 is 64-bit:
2820 * + NonSecure EL1 & 0 stage 1
2821 * + NonSecure EL1 & 0 stage 2
2822 * + NonSecure EL2
Richard Hendersonb9f60332020-02-07 14:04:24 +00002823 * + NonSecure EL2 & 0 (ARMv8.1-VHE)
2824 * + Secure EL1 & 0
Peter Maydellc1e37812015-02-05 13:37:23 +00002825 * + Secure EL3
2826 * If EL3 is 32-bit:
2827 * + NonSecure PL1 & 0 stage 1
2828 * + NonSecure PL1 & 0 stage 2
2829 * + NonSecure PL2
Richard Hendersonb9f60332020-02-07 14:04:24 +00002830 * + Secure PL0
2831 * + Secure PL1
Peter Maydellc1e37812015-02-05 13:37:23 +00002832 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2833 *
2834 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
Richard Hendersonb9f60332020-02-07 14:04:24 +00002835 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
2836 * because they may differ in access permissions even if the VA->PA map is
2837 * the same
Peter Maydellc1e37812015-02-05 13:37:23 +00002838 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2839 * translation, which means that we have one mmu_idx that deals with two
2840 * concatenated translation regimes [this sort of combined s1+2 TLB is
2841 * architecturally permitted]
2842 * 3. we don't need to allocate an mmu_idx to translations that we won't be
2843 * handling via the TLB. The only way to do a stage 1 translation without
2844 * the immediate stage 2 translation is via the ATS or AT system insns,
2845 * which can be slow-pathed and always do a page table walk.
Peter Maydellbf053402020-03-30 22:03:57 +01002846 * The only use of stage 2 translations is either as part of an s1+2
2847 * lookup or when loading the descriptors during a stage 1 page table walk,
2848 * and in both those cases we don't use the TLB.
Peter Maydellc1e37812015-02-05 13:37:23 +00002849 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2850 * translation regimes, because they map reasonably well to each other
2851 * and they can't both be active at the same time.
Richard Hendersonb9f60332020-02-07 14:04:24 +00002852 * 5. we want to be able to use the TLB for accesses done as part of a
2853 * stage1 page table walk, rather than having to walk the stage2 page
2854 * table over and over.
Richard Henderson452ef8c2020-02-08 12:57:58 +00002855 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
2856 * Never (PAN) bit within PSTATE.
Richard Hendersond902ae72022-10-01 09:22:46 -07002857 * 7. we fold together the secure and non-secure regimes for A-profile,
2858 * because there are no banked system registers for aarch64, so the
2859 * process of switching between secure and non-secure is
2860 * already heavyweight.
Peter Maydellc1e37812015-02-05 13:37:23 +00002861 *
Richard Hendersonb9f60332020-02-07 14:04:24 +00002862 * This gives us the following list of cases:
2863 *
Richard Hendersond902ae72022-10-01 09:22:46 -07002864 * EL0 EL1&0 stage 1+2 (aka NS PL0)
2865 * EL1 EL1&0 stage 1+2 (aka NS PL1)
2866 * EL1 EL1&0 stage 1+2 +PAN
2867 * EL0 EL2&0
2868 * EL2 EL2&0
2869 * EL2 EL2&0 +PAN
2870 * EL2 (aka NS PL2)
2871 * EL3 (aka S PL1)
Richard Hendersona1ce3082022-10-10 20:18:51 -07002872 * Physical (NS & S)
Richard Henderson575a94a2022-10-10 20:18:52 -07002873 * Stage2 (NS & S)
Peter Maydellc1e37812015-02-05 13:37:23 +00002874 *
Richard Henderson575a94a2022-10-10 20:18:52 -07002875 * for a total of 12 different mmu_idx.
Peter Maydellc1e37812015-02-05 13:37:23 +00002876 *
Peter Maydell3bef7012017-06-02 11:51:49 +01002877 * R profile CPUs have an MPU, but can use the same set of MMU indexes
Richard Hendersond902ae72022-10-01 09:22:46 -07002878 * as A profile. They only need to distinguish EL0 and EL1 (and
2879 * EL2 if we ever model a Cortex-R52).
Peter Maydell3bef7012017-06-02 11:51:49 +01002880 *
2881 * M profile CPUs are rather different as they do not have a true MMU.
2882 * They have the following different MMU indexes:
2883 * User
2884 * Privileged
Peter Maydell62593712017-12-13 17:59:23 +00002885 * User, execution priority negative (ie the MPU HFNMIENA bit may apply)
2886 * Privileged, execution priority negative (ditto)
Peter Maydell66787c72017-09-07 13:54:52 +01002887 * If the CPU supports the v8M Security Extension then there are also:
2888 * Secure User
2889 * Secure Privileged
Peter Maydell62593712017-12-13 17:59:23 +00002890 * Secure User, execution priority negative
2891 * Secure Privileged, execution priority negative
Peter Maydell3bef7012017-06-02 11:51:49 +01002892 *
Peter Maydell8bd5c822017-06-02 11:51:47 +01002893 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
2894 * are not quite the same -- different CPU types (most notably M profile
2895 * vs A/R profile) would like to use MMU indexes with different semantics,
2896 * but since we don't ever need to use all of those in a single CPU we
Peter Maydellbf053402020-03-30 22:03:57 +01002897 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
2898 * modes + total number of M profile MMU modes". The lower bits of
Peter Maydell8bd5c822017-06-02 11:51:47 +01002899 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
2900 * the same for any particular CPU.
2901 * Variables of type ARMMUIdx are always full values, and the core
2902 * index values are in variables of type 'int'.
2903 *
Peter Maydellc1e37812015-02-05 13:37:23 +00002904 * Our enumeration includes at the end some entries which are not "true"
2905 * mmu_idx values in that they don't have corresponding TLBs and are only
2906 * valid for doing slow path page table walks.
2907 *
2908 * The constant names here are patterned after the general style of the names
2909 * of the AT/ATS operations.
2910 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
Peter Maydell62593712017-12-13 17:59:23 +00002911 * For M profile we arrange them to have a bit for priv, a bit for negpri
2912 * and a bit for secure.
Peter Maydellc1e37812015-02-05 13:37:23 +00002913 */
Richard Hendersonb9f60332020-02-07 14:04:24 +00002914#define ARM_MMU_IDX_A 0x10 /* A profile */
2915#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
2916#define ARM_MMU_IDX_M 0x40 /* M profile */
Peter Maydell8bd5c822017-06-02 11:51:47 +01002917
Richard Hendersonb9f60332020-02-07 14:04:24 +00002918/* Meanings of the bits for M profile mmu idx values */
2919#define ARM_MMU_IDX_M_PRIV 0x1
Peter Maydell62593712017-12-13 17:59:23 +00002920#define ARM_MMU_IDX_M_NEGPRI 0x2
Richard Hendersonb9f60332020-02-07 14:04:24 +00002921#define ARM_MMU_IDX_M_S 0x4 /* Secure */
Peter Maydell62593712017-12-13 17:59:23 +00002922
Richard Hendersonb9f60332020-02-07 14:04:24 +00002923#define ARM_MMU_IDX_TYPE_MASK \
2924 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
2925#define ARM_MMU_IDX_COREIDX_MASK 0xf
Peter Maydell8bd5c822017-06-02 11:51:47 +01002926
Peter Maydellc1e37812015-02-05 13:37:23 +00002927typedef enum ARMMMUIdx {
Richard Hendersonb9f60332020-02-07 14:04:24 +00002928 /*
2929 * A-profile.
2930 */
Richard Hendersond902ae72022-10-01 09:22:46 -07002931 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
2932 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A,
2933 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A,
2934 ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A,
2935 ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A,
2936 ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A,
2937 ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A,
2938 ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A,
Richard Hendersonb9f60332020-02-07 14:04:24 +00002939
Richard Hendersonb9f60332020-02-07 14:04:24 +00002940 /*
Richard Henderson575a94a2022-10-10 20:18:52 -07002941 * Used for second stage of an S12 page table walk, or for descriptor
2942 * loads during first stage of an S1 page table walk. Note that both
2943 * are in use simultaneously for SecureEL2: the security state for
2944 * the S2 ptw is selected by the NS bit from the S1 ptw.
2945 */
Richard Hendersond38fa962023-06-23 11:15:45 +01002946 ARMMMUIdx_Stage2_S = 8 | ARM_MMU_IDX_A,
2947 ARMMMUIdx_Stage2 = 9 | ARM_MMU_IDX_A,
2948
2949 /* TLBs with 1-1 mapping to the physical address spaces. */
Richard Hendersonbb5cc2c2023-06-23 11:15:45 +01002950 ARMMMUIdx_Phys_S = 10 | ARM_MMU_IDX_A,
2951 ARMMMUIdx_Phys_NS = 11 | ARM_MMU_IDX_A,
2952 ARMMMUIdx_Phys_Root = 12 | ARM_MMU_IDX_A,
2953 ARMMMUIdx_Phys_Realm = 13 | ARM_MMU_IDX_A,
Richard Henderson575a94a2022-10-10 20:18:52 -07002954
2955 /*
Richard Hendersonb9f60332020-02-07 14:04:24 +00002956 * These are not allocated TLBs and are used only for AT system
2957 * instructions or for the first stage of an S12 page table walk.
2958 */
2959 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
2960 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
Richard Henderson452ef8c2020-02-08 12:57:58 +00002961 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
Richard Hendersonb9f60332020-02-07 14:04:24 +00002962
2963 /*
2964 * M-profile.
2965 */
Richard Henderson25568312020-02-07 14:04:24 +00002966 ARMMMUIdx_MUser = ARM_MMU_IDX_M,
2967 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
2968 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
2969 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
2970 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
2971 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
2972 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
2973 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
Peter Maydellc1e37812015-02-05 13:37:23 +00002974} ARMMMUIdx;
2975
Richard Henderson5f09a6d2020-02-07 14:04:23 +00002976/*
2977 * Bit macros for the core-mmu-index values for each index,
Peter Maydell8bd5c822017-06-02 11:51:47 +01002978 * for use when calling tlb_flush_by_mmuidx() and friends.
2979 */
Richard Henderson5f09a6d2020-02-07 14:04:23 +00002980#define TO_CORE_BIT(NAME) \
2981 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
2982
Peter Maydell8bd5c822017-06-02 11:51:47 +01002983typedef enum ARMMMUIdxBit {
Richard Henderson5f09a6d2020-02-07 14:04:23 +00002984 TO_CORE_BIT(E10_0),
Richard Hendersonb9f60332020-02-07 14:04:24 +00002985 TO_CORE_BIT(E20_0),
Richard Henderson5f09a6d2020-02-07 14:04:23 +00002986 TO_CORE_BIT(E10_1),
Richard Henderson452ef8c2020-02-08 12:57:58 +00002987 TO_CORE_BIT(E10_1_PAN),
Richard Henderson5f09a6d2020-02-07 14:04:23 +00002988 TO_CORE_BIT(E2),
Richard Hendersonb9f60332020-02-07 14:04:24 +00002989 TO_CORE_BIT(E20_2),
Richard Henderson452ef8c2020-02-08 12:57:58 +00002990 TO_CORE_BIT(E20_2_PAN),
Richard Hendersond902ae72022-10-01 09:22:46 -07002991 TO_CORE_BIT(E3),
Richard Henderson575a94a2022-10-10 20:18:52 -07002992 TO_CORE_BIT(Stage2),
2993 TO_CORE_BIT(Stage2_S),
Richard Henderson5f09a6d2020-02-07 14:04:23 +00002994
2995 TO_CORE_BIT(MUser),
2996 TO_CORE_BIT(MPriv),
2997 TO_CORE_BIT(MUserNegPri),
2998 TO_CORE_BIT(MPrivNegPri),
2999 TO_CORE_BIT(MSUser),
3000 TO_CORE_BIT(MSPriv),
3001 TO_CORE_BIT(MSUserNegPri),
3002 TO_CORE_BIT(MSPrivNegPri),
Peter Maydell8bd5c822017-06-02 11:51:47 +01003003} ARMMMUIdxBit;
3004
Richard Henderson5f09a6d2020-02-07 14:04:23 +00003005#undef TO_CORE_BIT
3006
Edgar E. Iglesiasf79fbf32014-05-27 17:09:51 +01003007#define MMU_USER_IDX 0
Peter Maydellc1e37812015-02-05 13:37:23 +00003008
Peter Maydell9e273ef2016-01-21 14:15:06 +00003009/* Indexes used when registering address spaces with cpu_address_space_init */
3010typedef enum ARMASIdx {
3011 ARMASIdx_NS = 0,
3012 ARMASIdx_S = 1,
Richard Henderson8bce44a2020-06-25 20:31:41 -07003013 ARMASIdx_TagNS = 2,
3014 ARMASIdx_TagS = 3,
Peter Maydell9e273ef2016-01-21 14:15:06 +00003015} ARMASIdx;
3016
Richard Hendersonbb5cc2c2023-06-23 11:15:45 +01003017static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space)
3018{
3019 /* Assert the relative order of the physical mmu indexes. */
3020 QEMU_BUILD_BUG_ON(ARMSS_Secure != 0);
3021 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS != ARMMMUIdx_Phys_S + ARMSS_NonSecure);
3022 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root != ARMMMUIdx_Phys_S + ARMSS_Root);
3023 QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm != ARMMMUIdx_Phys_S + ARMSS_Realm);
3024
3025 return ARMMMUIdx_Phys_S + space;
3026}
3027
3028static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx)
3029{
3030 assert(idx >= ARMMMUIdx_Phys_S && idx <= ARMMMUIdx_Phys_Realm);
3031 return idx - ARMMMUIdx_Phys_S;
3032}
3033
Peter Maydell43bbce72018-02-15 18:29:37 +00003034static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
3035{
3036 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
3037 * CSSELR is RAZ/WI.
3038 */
3039 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
3040}
3041
Paolo Bonzinif9fd40e2016-03-04 11:30:19 +00003042static inline bool arm_sctlr_b(CPUARMState *env)
3043{
3044 return
3045 /* We need not implement SCTLR.ITD in user-mode emulation, so
3046 * let linux-user ignore the fact that it conflicts with SCTLR_B.
3047 * This lets people run BE32 binaries with "-cpu any".
3048 */
3049#ifndef CONFIG_USER_ONLY
3050 !arm_feature(env, ARM_FEATURE_V7) &&
3051#endif
3052 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3053}
3054
Richard Hendersonaaec1432020-02-07 14:04:24 +00003055uint64_t arm_sctlr(CPUARMState *env, int el);
Richard Henderson64e40752019-03-01 12:04:52 -08003056
Richard Henderson8061a642019-10-23 11:00:37 -04003057static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
3058 bool sctlr_b)
3059{
3060#ifdef CONFIG_USER_ONLY
3061 /*
3062 * In system mode, BE32 is modelled in line with the
3063 * architecture (as word-invariant big-endianness), where loads
3064 * and stores are done little endian but from addresses which
3065 * are adjusted by XORing with the appropriate constant. So the
3066 * endianness to use for the raw data access is not affected by
3067 * SCTLR.B.
3068 * In user mode, however, we model BE32 as byte-invariant
3069 * big-endianness (because user-only code cannot tell the
3070 * difference), and so we need to use a data access endianness
3071 * that depends on SCTLR.B.
3072 */
3073 if (sctlr_b) {
3074 return true;
3075 }
3076#endif
3077 /* In 32bit endianness is determined by looking at CPSR's E bit */
3078 return env->uncached_cpsr & CPSR_E;
3079}
3080
3081static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3082{
3083 return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3084}
Richard Henderson64e40752019-03-01 12:04:52 -08003085
Peter Crosthwaiteed50ff72016-03-04 11:30:19 +00003086/* Return true if the processor is in big-endian mode. */
3087static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3088{
Peter Crosthwaiteed50ff72016-03-04 11:30:19 +00003089 if (!is_a64(env)) {
Richard Henderson8061a642019-10-23 11:00:37 -04003090 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
Richard Henderson64e40752019-03-01 12:04:52 -08003091 } else {
3092 int cur_el = arm_current_el(env);
3093 uint64_t sctlr = arm_sctlr(env, cur_el);
Richard Henderson8061a642019-10-23 11:00:37 -04003094 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
Peter Crosthwaiteed50ff72016-03-04 11:30:19 +00003095 }
Peter Crosthwaiteed50ff72016-03-04 11:30:19 +00003096}
3097
Paolo Bonzini022c62c2012-12-17 18:19:49 +01003098#include "exec/cpu-all.h"
aliguori622ed362008-11-18 19:36:03 +00003099
Richard Hendersonfdd1b222019-10-23 11:00:34 -04003100/*
Richard Hendersona3782062021-04-19 13:22:32 -07003101 * We have more than 32-bits worth of state per TB, so we split the data
3102 * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
3103 * We collect these two parts in CPUARMTBFlags where they are named
3104 * flags and flags2 respectively.
Richard Hendersonfdd1b222019-10-23 11:00:34 -04003105 *
Richard Hendersona3782062021-04-19 13:22:32 -07003106 * The flags that are shared between all execution modes, TBFLAG_ANY,
3107 * are stored in flags. The flags that are specific to a given mode
3108 * are stores in flags2. Since cs_base is sized on the configured
3109 * address size, flags2 always has 64-bits for A64, and a minimum of
3110 * 32-bits for A32 and M32.
3111 *
3112 * The bits for 32-bit A-profile and M-profile partially overlap:
3113 *
Richard Henderson5896f392021-04-19 13:22:34 -07003114 * 31 23 11 10 0
3115 * +-------------+----------+----------------+
3116 * | | | TBFLAG_A32 |
3117 * | TBFLAG_AM32 | +-----+----------+
3118 * | | |TBFLAG_M32|
3119 * +-------------+----------------+----------+
Peter Maydell26702212021-09-13 10:54:31 +01003120 * 31 23 6 5 0
Richard Henderson79cabf12020-02-07 14:04:23 +00003121 *
Richard Hendersonfdd1b222019-10-23 11:00:34 -04003122 * Unless otherwise noted, these bits are cached in env->hflags.
Alexander Graf3926cc82013-09-03 20:12:09 +01003123 */
Richard Hendersoneee81d42021-04-19 13:22:35 -07003124FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
3125FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
3126FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */
3127FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
3128FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
Greg Bellows9dbbc742015-05-29 11:28:53 +01003129/* Target EL if we take a floating-point-disabled exception */
Richard Hendersoneee81d42021-04-19 13:22:35 -07003130FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
Richard Henderson4479ec32021-04-19 13:22:36 -07003131/* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
Richard Henderson8480e932022-06-10 14:32:33 +01003132FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1)
3133FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1)
Peter Maydell361c33f2023-01-30 18:24:45 +00003134FIELD(TBFLAG_ANY, FGT_ACTIVE, 12, 1)
Peter Maydell34a8a072023-01-30 18:24:57 +00003135FIELD(TBFLAG_ANY, FGT_SVC, 13, 1)
Alexander Graf3926cc82013-09-03 20:12:09 +01003136
Richard Henderson79cabf12020-02-07 14:04:23 +00003137/*
3138 * Bit usage when in AArch32 state, both A- and M-profile.
3139 */
Richard Henderson5896f392021-04-19 13:22:34 -07003140FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */
3141FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */
Richard Henderson79cabf12020-02-07 14:04:23 +00003142
3143/*
3144 * Bit usage when in AArch32 state, for A-profile only.
3145 */
Richard Henderson5896f392021-04-19 13:22:34 -07003146FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */
3147FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */
Peter Maydell7fbb5352019-04-29 17:36:01 +01003148/*
Peter Maydellea7ac692019-04-29 17:36:01 +01003149 * We store the bottom two bits of the CPAR as TB flags and handle
3150 * checks on the other bits at runtime. This shares the same bits as
3151 * VECSTRIDE, which is OK as no XScale CPU has VFP.
Richard Hendersonfdd1b222019-10-23 11:00:34 -04003152 * Not cached, because VECLEN+VECSTRIDE are not cached.
Peter Maydellea7ac692019-04-29 17:36:01 +01003153 */
Richard Henderson5896f392021-04-19 13:22:34 -07003154FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2)
3155FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */
3156FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */
3157FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
Peter Maydellea7ac692019-04-29 17:36:01 +01003158/*
Peter Maydell7fbb5352019-04-29 17:36:01 +01003159 * Indicates whether cp register reads and writes by guest code should access
3160 * the secure or nonsecure bank of banked registers; note that this is not
3161 * the same thing as the current security state of the processor!
3162 */
Richard Henderson5896f392021-04-19 13:22:34 -07003163FIELD(TBFLAG_A32, NS, 10, 1)
Richard Henderson75fe8352022-07-08 20:44:58 +05303164/*
3165 * Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not.
3166 * This requires an SME trap from AArch32 mode when using NEON.
3167 */
3168FIELD(TBFLAG_A32, SME_TRAP_NONSTREAMING, 11, 1)
Marc Zyngier5bb0a202019-12-01 12:20:17 +00003169
Richard Henderson79cabf12020-02-07 14:04:23 +00003170/*
3171 * Bit usage when in AArch32 state, for M-profile only.
3172 */
3173/* Handler (ie not Thread) mode */
Richard Henderson5896f392021-04-19 13:22:34 -07003174FIELD(TBFLAG_M32, HANDLER, 0, 1)
Richard Henderson79cabf12020-02-07 14:04:23 +00003175/* Whether we should generate stack-limit checks */
Richard Henderson5896f392021-04-19 13:22:34 -07003176FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
Richard Henderson79cabf12020-02-07 14:04:23 +00003177/* Set if FPCCR.LSPACT is set */
Richard Henderson5896f392021-04-19 13:22:34 -07003178FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */
Richard Henderson79cabf12020-02-07 14:04:23 +00003179/* Set if we must create a new FP context */
Richard Henderson5896f392021-04-19 13:22:34 -07003180FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */
Richard Henderson79cabf12020-02-07 14:04:23 +00003181/* Set if FPCCR.S does not match current security state */
Richard Henderson5896f392021-04-19 13:22:34 -07003182FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */
Peter Maydell26702212021-09-13 10:54:31 +01003183/* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */
3184FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */
Richard Hendersona393dee2022-10-01 09:22:43 -07003185/* Set if in secure mode */
3186FIELD(TBFLAG_M32, SECURE, 6, 1)
Alexander Graf3926cc82013-09-03 20:12:09 +01003187
Richard Henderson79cabf12020-02-07 14:04:23 +00003188/*
3189 * Bit usage when in AArch64 state
3190 */
Richard Henderson476a4692019-01-21 10:23:12 +00003191FIELD(TBFLAG_A64, TBII, 0, 2)
Richard Hendersonaad821a2019-01-07 15:23:45 +00003192FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
Richard Hendersonf45ce4c2022-06-08 19:38:54 +01003193/* The current vector length, either NVL or SVL. */
3194FIELD(TBFLAG_A64, VL, 4, 4)
Richard Henderson0816ef12019-01-21 10:23:11 +00003195FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
Richard Henderson08f14342019-02-05 16:52:36 +00003196FIELD(TBFLAG_A64, BT, 9, 1)
Richard Hendersonfdd1b222019-10-23 11:00:34 -04003197FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */
Richard Henderson4a9ee992019-02-05 16:52:39 +00003198FIELD(TBFLAG_A64, TBID, 12, 2)
Richard Hendersoncc28fc32020-02-07 14:04:26 +00003199FIELD(TBFLAG_A64, UNPRIV, 14, 1)
Richard Henderson81ae05f2020-06-25 20:31:06 -07003200FIELD(TBFLAG_A64, ATA, 15, 1)
3201FIELD(TBFLAG_A64, TCMA, 16, 2)
3202FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3203FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
Richard Henderson6b2ca832022-06-20 10:51:46 -07003204FIELD(TBFLAG_A64, SMEEXC_EL, 20, 2)
Richard Hendersona3637e82022-06-20 10:51:52 -07003205FIELD(TBFLAG_A64, PSTATE_SM, 22, 1)
3206FIELD(TBFLAG_A64, PSTATE_ZA, 23, 1)
Richard Henderson5d7953a2022-06-20 10:52:03 -07003207FIELD(TBFLAG_A64, SVL, 24, 4)
Richard Henderson75fe8352022-07-08 20:44:58 +05303208/* Indicates that SME Streaming mode is active, and SMCR_ELx.FA64 is not. */
3209FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1)
Peter Maydelle37e98b2024-01-09 14:43:45 +00003210FIELD(TBFLAG_A64, TRAP_ERET, 29, 1)
Richard Henderson83f624d2023-06-06 10:19:38 +01003211FIELD(TBFLAG_A64, NAA, 30, 1)
Peter Maydell179e9a32023-09-12 15:04:30 +01003212FIELD(TBFLAG_A64, ATA0, 31, 1)
Peter Maydell67d10fc2024-01-09 14:43:48 +00003213FIELD(TBFLAG_A64, NV, 32, 1)
Peter Maydellc35da112024-01-09 14:43:53 +00003214FIELD(TBFLAG_A64, NV1, 33, 1)
3215FIELD(TBFLAG_A64, NV2, 34, 1)
Peter Maydelldaf9b4a2024-01-09 14:43:53 +00003216/* Set if FEAT_NV2 RAM accesses use the EL2&0 translation regime */
3217FIELD(TBFLAG_A64, NV2_MEM_E20, 35, 1)
3218/* Set if FEAT_NV2 RAM accesses are big-endian */
3219FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1)
Peter Maydella1705762011-01-14 20:39:18 +01003220
Richard Hendersona729a462021-04-19 13:22:30 -07003221/*
Peter Maydell29a15a62024-01-09 14:43:46 +00003222 * Helpers for using the above. Note that only the A64 accessors use
3223 * FIELD_DP64() and FIELD_EX64(), because in the other cases the flags
3224 * word either is or might be 32 bits only.
Richard Hendersona729a462021-04-19 13:22:30 -07003225 */
3226#define DP_TBFLAG_ANY(DST, WHICH, VAL) \
Richard Henderson3902bfc2021-04-19 13:22:31 -07003227 (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
Richard Hendersona729a462021-04-19 13:22:30 -07003228#define DP_TBFLAG_A64(DST, WHICH, VAL) \
Peter Maydell29a15a62024-01-09 14:43:46 +00003229 (DST.flags2 = FIELD_DP64(DST.flags2, TBFLAG_A64, WHICH, VAL))
Richard Hendersona729a462021-04-19 13:22:30 -07003230#define DP_TBFLAG_A32(DST, WHICH, VAL) \
Richard Hendersona3782062021-04-19 13:22:32 -07003231 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
Richard Hendersona729a462021-04-19 13:22:30 -07003232#define DP_TBFLAG_M32(DST, WHICH, VAL) \
Richard Hendersona3782062021-04-19 13:22:32 -07003233 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
Richard Hendersona729a462021-04-19 13:22:30 -07003234#define DP_TBFLAG_AM32(DST, WHICH, VAL) \
Richard Hendersona3782062021-04-19 13:22:32 -07003235 (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
Richard Hendersona729a462021-04-19 13:22:30 -07003236
Richard Henderson3902bfc2021-04-19 13:22:31 -07003237#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
Peter Maydell29a15a62024-01-09 14:43:46 +00003238#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX64(IN.flags2, TBFLAG_A64, WHICH)
Richard Hendersona3782062021-04-19 13:22:32 -07003239#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
3240#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
3241#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
Richard Hendersona729a462021-04-19 13:22:30 -07003242
Richard Hendersonfb901c92020-03-05 16:09:20 +00003243/**
Richard Henderson8b599e52022-06-08 19:38:55 +01003244 * sve_vq
3245 * @env: the cpu context
3246 *
3247 * Return the VL cached within env->hflags, in units of quadwords.
3248 */
3249static inline int sve_vq(CPUARMState *env)
3250{
3251 return EX_TBFLAG_A64(env->hflags, VL) + 1;
3252}
3253
Richard Henderson5d7953a2022-06-20 10:52:03 -07003254/**
3255 * sme_vq
3256 * @env: the cpu context
3257 *
3258 * Return the SVL cached within env->hflags, in units of quadwords.
3259 */
3260static inline int sme_vq(CPUARMState *env)
3261{
3262 return EX_TBFLAG_A64(env->hflags, SVL) + 1;
3263}
3264
Paolo Bonzinif9fd40e2016-03-04 11:30:19 +00003265static inline bool bswap_code(bool sctlr_b)
3266{
3267#ifdef CONFIG_USER_ONLY
Marc-André Lureauee3eb3a2022-03-23 19:57:18 +04003268 /* BE8 (SCTLR.B = 0, TARGET_BIG_ENDIAN = 1) is mixed endian.
3269 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_BIG_ENDIAN=0
Paolo Bonzinif9fd40e2016-03-04 11:30:19 +00003270 * would also end up as a mixed-endian mode with BE code, LE data.
3271 */
Thomas Huthded625e2023-09-07 13:35:00 +02003272 return TARGET_BIG_ENDIAN ^ sctlr_b;
Paolo Bonzinif9fd40e2016-03-04 11:30:19 +00003273#else
Paolo Bonzinie334bd32016-03-04 11:30:21 +00003274 /* All code access in ARM is little endian, and there are no loaders
3275 * doing swaps that need to be reversed
Paolo Bonzinif9fd40e2016-03-04 11:30:19 +00003276 */
3277 return 0;
3278#endif
3279}
3280
Paolo Bonzinic3ae85f2016-03-04 11:30:19 +00003281#ifdef CONFIG_USER_ONLY
3282static inline bool arm_cpu_bswap_data(CPUARMState *env)
3283{
Thomas Huthded625e2023-09-07 13:35:00 +02003284 return TARGET_BIG_ENDIAN ^ arm_cpu_data_is_big_endian(env);
Paolo Bonzinic3ae85f2016-03-04 11:30:19 +00003285}
3286#endif
3287
Anton Johanssonbb5de522023-06-21 15:56:24 +02003288void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc,
3289 uint64_t *cs_base, uint32_t *flags);
aliguori6b917542008-11-18 19:46:41 +00003290
Rob Herring98128602014-10-24 12:19:13 +01003291enum {
3292 QEMU_PSCI_CONDUIT_DISABLED = 0,
3293 QEMU_PSCI_CONDUIT_SMC = 1,
3294 QEMU_PSCI_CONDUIT_HVC = 2,
3295};
3296
Peter Maydell017518c2016-01-21 14:15:06 +00003297#ifndef CONFIG_USER_ONLY
3298/* Return the address space index to use for a memory access */
3299static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3300{
3301 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3302}
Peter Maydell5ce4ff62016-01-21 14:15:07 +00003303
3304/* Return the AddressSpace to use for a memory access
3305 * (which depends on whether the access is S or NS, and whether
3306 * the board gave us a separate AddressSpace for S accesses).
3307 */
3308static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3309{
3310 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3311}
Peter Maydell017518c2016-01-21 14:15:06 +00003312#endif
3313
Peter Maydellbd7d00f2016-06-17 15:23:46 +01003314/**
Aaron Lindsayb5c53d12018-04-26 11:04:39 +01003315 * arm_register_pre_el_change_hook:
3316 * Register a hook function which will be called immediately before this
Peter Maydellbd7d00f2016-06-17 15:23:46 +01003317 * CPU changes exception level or mode. The hook function will be
3318 * passed a pointer to the ARMCPU and the opaque data pointer passed
3319 * to this function when the hook was registered.
Aaron Lindsayb5c53d12018-04-26 11:04:39 +01003320 *
3321 * Note that if a pre-change hook is called, any registered post-change hooks
3322 * are guaranteed to subsequently be called.
Peter Maydellbd7d00f2016-06-17 15:23:46 +01003323 */
Aaron Lindsayb5c53d12018-04-26 11:04:39 +01003324void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
Peter Maydellbd7d00f2016-06-17 15:23:46 +01003325 void *opaque);
Aaron Lindsayb5c53d12018-04-26 11:04:39 +01003326/**
3327 * arm_register_el_change_hook:
3328 * Register a hook function which will be called immediately after this
3329 * CPU changes exception level or mode. The hook function will be
3330 * passed a pointer to the ARMCPU and the opaque data pointer passed
3331 * to this function when the hook was registered.
3332 *
3333 * Note that any registered hooks registered here are guaranteed to be called
3334 * if pre-change hooks have been.
3335 */
3336void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3337 *opaque);
Peter Maydellbd7d00f2016-06-17 15:23:46 +01003338
3339/**
Richard Henderson3d74e2e2019-10-23 11:00:45 -04003340 * arm_rebuild_hflags:
3341 * Rebuild the cached TBFLAGS for arbitrary changed processor state.
3342 */
3343void arm_rebuild_hflags(CPUARMState *env);
3344
3345/**
Richard Henderson9a2b5252018-01-25 11:45:29 +00003346 * aa32_vfp_dreg:
3347 * Return a pointer to the Dn register within env in 32-bit mode.
3348 */
3349static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3350{
Richard Hendersonc39c2b92018-02-09 10:40:31 +00003351 return &env->vfp.zregs[regno >> 1].d[regno & 1];
Richard Henderson9a2b5252018-01-25 11:45:29 +00003352}
3353
3354/**
3355 * aa32_vfp_qreg:
3356 * Return a pointer to the Qn register within env in 32-bit mode.
3357 */
3358static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3359{
Richard Hendersonc39c2b92018-02-09 10:40:31 +00003360 return &env->vfp.zregs[regno].d[0];
Richard Henderson9a2b5252018-01-25 11:45:29 +00003361}
3362
3363/**
3364 * aa64_vfp_qreg:
3365 * Return a pointer to the Qn register within env in 64-bit mode.
3366 */
3367static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3368{
Richard Hendersonc39c2b92018-02-09 10:40:31 +00003369 return &env->vfp.zregs[regno].d[0];
Richard Henderson9a2b5252018-01-25 11:45:29 +00003370}
3371
Richard Henderson028e2a72018-05-18 17:48:08 +01003372/* Shared between translate-sve.c and sve_helper.c. */
Peter Maydellfca75f62022-07-18 11:01:44 +01003373extern const uint64_t pred_esz_masks[5];
Richard Henderson028e2a72018-05-18 17:48:08 +01003374
Richard Henderson962fcbf2018-10-24 07:50:16 +01003375/*
Richard Hendersonbe5d6f42020-10-21 10:37:39 -07003376 * AArch64 usage of the PAGE_TARGET_* bits for linux-user.
Richard Henderson7f2cf762022-07-11 08:44:20 +05303377 * Note that with the Linux kernel, PROT_MTE may not be cleared by mprotect
3378 * mprotect but PROT_BTI may be cleared. C.f. the kernel's VM_ARCH_CLEAR.
Richard Hendersonbe5d6f42020-10-21 10:37:39 -07003379 */
Richard Henderson7f2cf762022-07-11 08:44:20 +05303380#define PAGE_BTI PAGE_TARGET_1
3381#define PAGE_MTE PAGE_TARGET_2
3382#define PAGE_TARGET_STICKY PAGE_MTE
Richard Hendersonbe5d6f42020-10-21 10:37:39 -07003383
Richard Henderson50d4c8c2022-09-17 14:25:12 +02003384/* We associate one allocation tag per 16 bytes, the minimum. */
3385#define LOG2_TAG_GRANULE 4
3386#define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
3387
3388#ifdef CONFIG_USER_ONLY
3389#define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1))
3390#endif
3391
Richard Henderson0e0c0302021-02-12 10:48:51 -08003392#ifdef TARGET_TAGGED_ADDRESSES
3393/**
3394 * cpu_untagged_addr:
3395 * @cs: CPU context
3396 * @x: tagged address
3397 *
3398 * Remove any address tag from @x. This is explicitly related to the
3399 * linux syscall TIF_TAGGED_ADDR setting, not TBI in general.
3400 *
3401 * There should be a better place to put this, but we need this in
3402 * include/exec/cpu_ldst.h, and not some place linux-user specific.
3403 */
3404static inline target_ulong cpu_untagged_addr(CPUState *cs, target_ulong x)
3405{
3406 ARMCPU *cpu = ARM_CPU(cs);
3407 if (cpu->env.tagged_addr_enable) {
3408 /*
3409 * TBI is enabled for userspace but not kernelspace addresses.
3410 * Only clear the tag if bit 55 is clear.
3411 */
3412 x &= sextract64(x, 0, 56);
3413 }
3414 return x;
3415}
3416#endif
3417
bellard2c0262a2003-09-30 20:34:21 +00003418#endif