commit b848ce2b9cbd38da3f2530fd93dba76dba0621c0
author Fabian Aggeler <aggelerf@ethz.ch> Thu Dec 11 12:07:51 2014 +0000
committer Peter Maydell <peter.maydell@linaro.org> Thu Dec 11 12:07:51 2014 +0000
tree 555f341e54ffbd2e006ca27c2d8d6d4251e159b2
parent 4a7e2d7315bd2ce28e49ccd0bde73eabdfd7437b

target-arm: make IFAR/DFAR banked

When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
IFAR and DFAR have a secure and a non-secure instance.

Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-22-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

target-arm/cpu.h

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 29870bd..52d5719 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -261,7 +261,24 @@
             uint64_t esr_el[4];
         };
         uint32_t c6_region[8]; /* MPU base/size registers.  */
-        uint64_t far_el[4]; /* Fault address registers.  */
+        union { /* Fault address registers. */
+            struct {
+                uint64_t _unused_far0;
+#ifdef HOST_WORDS_BIGENDIAN
+                uint32_t ifar_ns;
+                uint32_t dfar_ns;
+                uint32_t ifar_s;
+                uint32_t dfar_s;
+#else
+                uint32_t dfar_ns;
+                uint32_t ifar_ns;
+                uint32_t dfar_s;
+                uint32_t ifar_s;
+#endif
+                uint64_t _unused_far3;
+            };
+            uint64_t far_el[4];
+        };
         uint64_t par_el1;  /* Translation result. */
         uint32_t c9_insn; /* Cache lockdown registers.  */
         uint32_t c9_data;