target-arm: A64: Add SP entries for EL2 and 3
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1400980132-25949-10-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 62d85ff..ba1d495 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -163,7 +163,7 @@
uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
uint64_t elr_el[2]; /* AArch64 exception link regs */
- uint64_t sp_el[2]; /* AArch64 banked stack pointers */
+ uint64_t sp_el[4]; /* AArch64 banked stack pointers */
/* System control coprocessor (cp15) */
struct {
