target/arm: Implement HSTR.TJDBX
In v7A, the HSTR register has a TJDBX bit which traps NS EL0/EL1
access to the JOSCR and JMCR trivial Jazelle registers, and also BXJ.
Implement these traps. In v8A this HSTR bit doesn't exist, so don't
trap for v8A CPUs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210816180305.20137-3-peter.maydell@linaro.org
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0cd3206..0976033 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1542,6 +1542,7 @@
#define SCR_ATA (1U << 26)
#define HSTR_TTEE (1 << 16)
+#define HSTR_TJDBX (1 << 17)
/* Return the current FPSCR value. */
uint32_t vfp_get_fpscr(CPUARMState *env);
