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bellard2c0262a2003-09-30 20:34:21 +00001/*
2 * ARM virtual CPU header
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard2c0262a2003-09-30 20:34:21 +00004 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard2c0262a2003-09-30 20:34:21 +000018 */
19#ifndef CPU_ARM_H
20#define CPU_ARM_H
21
Alexander Graf3926cc82013-09-03 20:12:09 +010022#include "config.h"
bellard3cf1e032004-01-24 15:19:09 +000023
Peter Maydell72b0cd32013-11-22 17:17:08 +000024#include "kvm-consts.h"
25
Alexander Graf3926cc82013-09-03 20:12:09 +010026#if defined(TARGET_AARCH64)
27 /* AArch64 definitions */
28# define TARGET_LONG_BITS 64
Alexander Graf3926cc82013-09-03 20:12:09 +010029#else
30# define TARGET_LONG_BITS 32
Alexander Graf3926cc82013-09-03 20:12:09 +010031#endif
ths9042c0e2006-12-23 14:18:40 +000032
Pranavkumar Sawargaonkar84f2bed2015-02-05 13:37:25 +000033#define TARGET_IS_BIENDIAN 1
34
Andreas Färber9349b4f2012-03-14 01:38:32 +010035#define CPUArchState struct CPUARMState
pbrookc2764712009-03-07 15:24:59 +000036
Stefan Weil9a78eea2010-10-22 23:03:33 +020037#include "qemu-common.h"
Paolo Bonzini022c62c2012-12-17 18:19:49 +010038#include "exec/cpu-defs.h"
bellard2c0262a2003-09-30 20:34:21 +000039
Paolo Bonzini6b4c3052012-10-24 13:12:00 +020040#include "fpu/softfloat.h"
bellard53cd6632005-03-13 18:50:23 +000041
bellardb8a9e8f2005-02-07 23:10:07 +000042#define EXCP_UDEF 1 /* undefined instruction */
43#define EXCP_SWI 2 /* software interrupt */
44#define EXCP_PREFETCH_ABORT 3
45#define EXCP_DATA_ABORT 4
bellardb5ff1b32005-11-26 10:38:39 +000046#define EXCP_IRQ 5
47#define EXCP_FIQ 6
pbrook06c949e2006-02-04 19:35:26 +000048#define EXCP_BKPT 7
pbrook9ee6e8b2007-11-11 00:04:49 +000049#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
pbrookfbb4a2e2008-05-29 00:20:44 +000050#define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
Paul Brook426f5ab2009-11-22 21:35:13 +000051#define EXCP_STREX 10
Edgar E. Iglesias35979d72014-09-29 18:48:50 +010052#define EXCP_HVC 11 /* HyperVisor Call */
Edgar E. Iglesias607d98b2014-09-29 18:48:50 +010053#define EXCP_HYP_TRAP 12
Edgar E. Iglesiase0d6e6a2014-09-29 18:48:50 +010054#define EXCP_SMC 13 /* Secure Monitor Call */
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +010055#define EXCP_VIRQ 14
56#define EXCP_VFIQ 15
Peter Maydell8012c842015-09-07 10:39:28 +010057#define EXCP_SEMIHOST 16 /* semihosting call (A64 only) */
pbrook9ee6e8b2007-11-11 00:04:49 +000058
59#define ARMV7M_EXCP_RESET 1
60#define ARMV7M_EXCP_NMI 2
61#define ARMV7M_EXCP_HARD 3
62#define ARMV7M_EXCP_MEM 4
63#define ARMV7M_EXCP_BUS 5
64#define ARMV7M_EXCP_USAGE 6
65#define ARMV7M_EXCP_SVC 11
66#define ARMV7M_EXCP_DEBUG 12
67#define ARMV7M_EXCP_PENDSV 14
68#define ARMV7M_EXCP_SYSTICK 15
bellard2c0262a2003-09-30 20:34:21 +000069
Richard Henderson403946c2011-05-04 13:34:29 -070070/* ARM-specific interrupt pending bits. */
71#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +010072#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
73#define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
Richard Henderson403946c2011-05-04 13:34:29 -070074
Peter Maydelle4fe8302014-01-04 22:15:45 +000075/* The usual mapping for an AArch64 system register to its AArch32
76 * counterpart is for the 32 bit world to have access to the lower
77 * half only (with writes leaving the upper half untouched). It's
78 * therefore useful to be able to pass TCG the offset of the least
79 * significant half of a uint64_t struct member.
80 */
81#ifdef HOST_WORDS_BIGENDIAN
Alexey Kardashevskiy5cd8a112014-01-12 21:37:37 +000082#define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
Peter Maydellb0fe2422014-02-26 17:20:03 +000083#define offsetofhigh32(S, M) offsetof(S, M)
Peter Maydelle4fe8302014-01-04 22:15:45 +000084#else
85#define offsetoflow32(S, M) offsetof(S, M)
Peter Maydellb0fe2422014-02-26 17:20:03 +000086#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
Peter Maydelle4fe8302014-01-04 22:15:45 +000087#endif
88
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +010089/* Meanings of the ARMCPU object's four inbound GPIO lines */
Peter Maydell7c1840b2013-08-20 14:54:28 +010090#define ARM_CPU_IRQ 0
91#define ARM_CPU_FIQ 1
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +010092#define ARM_CPU_VIRQ 2
93#define ARM_CPU_VFIQ 3
Richard Henderson403946c2011-05-04 13:34:29 -070094
balrogf93eb9f2008-04-14 20:27:51 +000095struct arm_boot_info;
96
Peter Maydellc1e37812015-02-05 13:37:23 +000097#define NB_MMU_MODES 7
Richard Henderson52e971d2015-08-30 09:22:06 -070098#define TARGET_INSN_START_EXTRA_WORDS 1
j_mayer6ebbf392007-10-14 07:07:08 +000099
bellardb7bcbe92005-02-22 19:27:29 +0000100/* We currently assume float and double are IEEE single and double
101 precision respectively.
102 Doing runtime conversions is tricky because VFP registers may contain
103 integer values (eg. as the result of a FTOSI instruction).
bellard8e960052005-04-07 19:42:46 +0000104 s<2n> maps to the least significant half of d<n>
105 s<2n+1> maps to the most significant half of d<n>
106 */
bellardb7bcbe92005-02-22 19:27:29 +0000107
Peter Maydell55d284a2013-08-20 14:54:31 +0100108/* CPU state for each instance of a generic timer (in cp15 c14) */
109typedef struct ARMGenericTimer {
110 uint64_t cval; /* Timer CompareValue register */
Peter Maydella7adc4b2014-02-26 17:20:05 +0000111 uint64_t ctl; /* Timer Control register */
Peter Maydell55d284a2013-08-20 14:54:31 +0100112} ARMGenericTimer;
113
114#define GTIMER_PHYS 0
115#define GTIMER_VIRT 1
Edgar E. Iglesiasb0e66d92015-08-13 11:26:18 +0100116#define GTIMER_HYP 2
Peter Maydellb4d39782015-08-13 11:26:22 +0100117#define GTIMER_SEC 3
118#define NUM_GTIMERS 4
Peter Maydell55d284a2013-08-20 14:54:31 +0100119
Fabian Aggeler11f136e2014-12-11 12:07:51 +0000120typedef struct {
121 uint64_t raw_tcr;
122 uint32_t mask;
123 uint32_t base_mask;
124} TCR;
125
bellard2c0262a2003-09-30 20:34:21 +0000126typedef struct CPUARMState {
bellardb5ff1b32005-11-26 10:38:39 +0000127 /* Regs for current mode. */
bellard2c0262a2003-09-30 20:34:21 +0000128 uint32_t regs[16];
Alexander Graf3926cc82013-09-03 20:12:09 +0100129
130 /* 32/64 switch only happens when taking and returning from
131 * exceptions so the overlap semantics are taken care of then
132 * instead of having a complicated union.
133 */
134 /* Regs for A64 mode. */
135 uint64_t xregs[32];
136 uint64_t pc;
Peter Maydelld3563122013-12-17 19:42:30 +0000137 /* PSTATE isn't an architectural register for ARMv8. However, it is
138 * convenient for us to assemble the underlying state into a 32 bit format
139 * identical to the architectural format used for the SPSR. (This is also
140 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
141 * 'pstate' register are.) Of the PSTATE bits:
142 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
143 * semantics as for AArch32, as described in the comments on each field)
144 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
Peter Maydell4cc35612014-02-26 17:20:06 +0000145 * DAIF (exception masks) are kept in env->daif
Peter Maydelld3563122013-12-17 19:42:30 +0000146 * all other bits are stored in their correct places in env->pstate
Alexander Graf3926cc82013-09-03 20:12:09 +0100147 */
148 uint32_t pstate;
149 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
150
Peter Maydellb90372a2012-08-06 17:42:18 +0100151 /* Frequently accessed CPSR bits are stored separately for efficiency.
pbrookd37aca62006-10-22 11:54:30 +0000152 This contains all the other bits. Use cpsr_{read,write} to access
bellardb5ff1b32005-11-26 10:38:39 +0000153 the whole CPSR. */
154 uint32_t uncached_cpsr;
155 uint32_t spsr;
156
157 /* Banked registers. */
Edgar E. Iglesias28c94572014-05-27 17:09:52 +0100158 uint64_t banked_spsr[8];
Fabian Aggeler0b7d4092014-10-24 12:19:14 +0100159 uint32_t banked_r13[8];
160 uint32_t banked_r14[8];
ths3b46e622007-09-17 08:09:54 +0000161
bellardb5ff1b32005-11-26 10:38:39 +0000162 /* These hold r8-r12. */
163 uint32_t usr_regs[5];
164 uint32_t fiq_regs[5];
ths3b46e622007-09-17 08:09:54 +0000165
bellard2c0262a2003-09-30 20:34:21 +0000166 /* cpsr flag cache for faster execution */
167 uint32_t CF; /* 0 or 1 */
168 uint32_t VF; /* V is the bit 31. All other bits are undefined */
pbrook6fbe23d2008-04-01 17:19:11 +0000169 uint32_t NF; /* N is bit 31. All other bits are undefined. */
170 uint32_t ZF; /* Z set if zero. */
bellard99c475a2005-01-31 20:45:13 +0000171 uint32_t QF; /* 0 or 1 */
pbrook9ee6e8b2007-11-11 00:04:49 +0000172 uint32_t GE; /* cpsr[19:16] */
pbrookb26eefb2008-03-31 03:44:26 +0000173 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
pbrook9ee6e8b2007-11-11 00:04:49 +0000174 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
Daniel P. Berrangeb6af0972015-08-26 12:17:13 +0100175 uint64_t daif; /* exception masks, in the bits they are in PSTATE */
bellard2c0262a2003-09-30 20:34:21 +0000176
Edgar E. Iglesias1b174232014-05-27 17:09:52 +0100177 uint64_t elr_el[4]; /* AArch64 exception link regs */
Edgar E. Iglesias73fb3b72014-05-27 17:09:52 +0100178 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
Peter Maydella0618a12014-04-15 19:18:42 +0100179
bellardb5ff1b32005-11-26 10:38:39 +0000180 /* System control coprocessor (cp15) */
181 struct {
pbrook40f137e2006-02-20 00:33:36 +0000182 uint32_t c0_cpuid;
Fabian Aggelerb85a1fd2014-12-11 12:07:50 +0000183 union { /* Cache size selection */
184 struct {
185 uint64_t _unused_csselr0;
186 uint64_t csselr_ns;
187 uint64_t _unused_csselr1;
188 uint64_t csselr_s;
189 };
190 uint64_t csselr_el[4];
191 };
Fabian Aggeler137feaa2014-12-11 12:07:50 +0000192 union { /* System control register. */
193 struct {
194 uint64_t _unused_sctlr;
195 uint64_t sctlr_ns;
196 uint64_t hsctlr;
197 uint64_t sctlr_s;
198 };
199 uint64_t sctlr_el[4];
200 };
Sergey Fedorov7ebd5f22015-04-26 16:49:25 +0100201 uint64_t cpacr_el1; /* Architectural feature access control register */
Greg Bellowsc6f19162015-05-29 11:28:52 +0100202 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
balrog610c3c82007-06-24 12:09:48 +0000203 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
Greg Bellows144634a2014-12-11 12:07:50 +0000204 uint64_t sder; /* Secure debug enable register. */
Fabian Aggeler77022572014-12-11 12:07:49 +0000205 uint32_t nsacr; /* Non-secure access control register. */
Fabian Aggeler7dd8c9a2014-12-11 12:07:51 +0000206 union { /* MMU translation table base 0. */
207 struct {
208 uint64_t _unused_ttbr0_0;
209 uint64_t ttbr0_ns;
210 uint64_t _unused_ttbr0_1;
211 uint64_t ttbr0_s;
212 };
213 uint64_t ttbr0_el[4];
214 };
215 union { /* MMU translation table base 1. */
216 struct {
217 uint64_t _unused_ttbr1_0;
218 uint64_t ttbr1_ns;
219 uint64_t _unused_ttbr1_1;
220 uint64_t ttbr1_s;
221 };
222 uint64_t ttbr1_el[4];
223 };
Edgar E. Iglesiasb698e9c2015-09-14 14:39:50 +0100224 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */
Fabian Aggeler11f136e2014-12-11 12:07:51 +0000225 /* MMU translation table base control. */
226 TCR tcr_el[4];
Edgar E. Iglesias68e9c2f2015-09-14 14:39:50 +0100227 TCR vtcr_el2; /* Virtualization Translation Control. */
Veres Lajos67cc32e2015-09-08 22:45:14 +0100228 uint32_t c2_data; /* MPU data cacheable bits. */
229 uint32_t c2_insn; /* MPU instruction cacheable bits. */
Fabian Aggeler0c17d682014-12-11 12:07:51 +0000230 union { /* MMU domain access control register
231 * MPU write buffer control.
232 */
233 struct {
234 uint64_t dacr_ns;
235 uint64_t dacr_s;
236 };
237 struct {
238 uint64_t dacr32_el2;
239 };
240 };
Peter Maydell7e097972014-04-15 19:18:41 +0100241 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
242 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
Edgar E. Iglesiasf149e3e2014-09-29 18:48:48 +0100243 uint64_t hcr_el2; /* Hypervisor configuration register */
Edgar E. Iglesias64e0e2d2014-09-29 18:48:49 +0100244 uint64_t scr_el3; /* Secure configuration register. */
Fabian Aggeler88ca1c22014-12-11 12:07:51 +0000245 union { /* Fault status registers. */
246 struct {
247 uint64_t ifsr_ns;
248 uint64_t ifsr_s;
249 };
250 struct {
251 uint64_t ifsr32_el2;
252 };
253 };
Fabian Aggeler4a7e2d72014-12-11 12:07:51 +0000254 union {
255 struct {
256 uint64_t _unused_dfsr;
257 uint64_t dfsr_ns;
258 uint64_t hsr;
259 uint64_t dfsr_s;
260 };
261 uint64_t esr_el[4];
262 };
pbrookce819862007-05-08 02:30:40 +0000263 uint32_t c6_region[8]; /* MPU base/size registers. */
Fabian Aggelerb848ce22014-12-11 12:07:51 +0000264 union { /* Fault address registers. */
265 struct {
266 uint64_t _unused_far0;
267#ifdef HOST_WORDS_BIGENDIAN
268 uint32_t ifar_ns;
269 uint32_t dfar_ns;
270 uint32_t ifar_s;
271 uint32_t dfar_s;
272#else
273 uint32_t dfar_ns;
274 uint32_t ifar_ns;
275 uint32_t dfar_s;
276 uint32_t ifar_s;
277#endif
278 uint64_t _unused_far3;
279 };
280 uint64_t far_el[4];
281 };
Edgar E. Iglesias59e05532015-10-26 14:01:54 +0100282 uint64_t hpfar_el2;
Fabian Aggeler01c097f2014-12-11 12:07:52 +0000283 union { /* Translation result. */
284 struct {
285 uint64_t _unused_par_0;
286 uint64_t par_ns;
287 uint64_t _unused_par_1;
288 uint64_t par_s;
289 };
290 uint64_t par_el[4];
291 };
Peter Crosthwaite6cb0b012015-06-19 14:17:44 +0100292
293 uint32_t c6_rgnr;
294
bellardb5ff1b32005-11-26 10:38:39 +0000295 uint32_t c9_insn; /* Cache lockdown registers. */
296 uint32_t c9_data;
Alistair Francis85214662014-08-29 15:00:29 +0100297 uint64_t c9_pmcr; /* performance monitor control register */
298 uint64_t c9_pmcnten; /* perf monitor counter enables */
Peter Maydell74594c92011-03-22 12:16:16 +0000299 uint32_t c9_pmovsr; /* perf monitor overflow status */
300 uint32_t c9_pmxevtyper; /* perf monitor event type */
301 uint32_t c9_pmuserenr; /* perf monitor user enable */
302 uint32_t c9_pminten; /* perf monitor interrupt enables */
Greg Bellowsbe693c82014-12-11 12:07:52 +0000303 union { /* Memory attribute redirection */
304 struct {
305#ifdef HOST_WORDS_BIGENDIAN
306 uint64_t _unused_mair_0;
307 uint32_t mair1_ns;
308 uint32_t mair0_ns;
309 uint64_t _unused_mair_1;
310 uint32_t mair1_s;
311 uint32_t mair0_s;
312#else
313 uint64_t _unused_mair_0;
314 uint32_t mair0_ns;
315 uint32_t mair1_ns;
316 uint64_t _unused_mair_1;
317 uint32_t mair0_s;
318 uint32_t mair1_s;
319#endif
320 };
321 uint64_t mair_el[4];
322 };
Greg Bellowsfb6c91b2014-12-11 12:07:52 +0000323 union { /* vector base address register */
324 struct {
325 uint64_t _unused_vbar;
326 uint64_t vbar_ns;
327 uint64_t hvbar;
328 uint64_t vbar_s;
329 };
330 uint64_t vbar_el[4];
331 };
Fabian Aggelere89e51a2014-12-11 12:07:50 +0000332 uint32_t mvbar; /* (monitor) vector base address register */
Fabian Aggeler54bf36e2014-12-11 12:07:52 +0000333 struct { /* FCSE PID. */
334 uint32_t fcseidr_ns;
335 uint32_t fcseidr_s;
336 };
337 union { /* Context ID. */
338 struct {
339 uint64_t _unused_contextidr_0;
340 uint64_t contextidr_ns;
341 uint64_t _unused_contextidr_1;
342 uint64_t contextidr_s;
343 };
344 uint64_t contextidr_el[4];
345 };
346 union { /* User RW Thread register. */
347 struct {
348 uint64_t tpidrurw_ns;
349 uint64_t tpidrprw_ns;
350 uint64_t htpidr;
351 uint64_t _tpidr_el3;
352 };
353 uint64_t tpidr_el[4];
354 };
355 /* The secure banks of these registers don't map anywhere */
356 uint64_t tpidrurw_s;
357 uint64_t tpidrprw_s;
358 uint64_t tpidruro_s;
359
360 union { /* User RO Thread register. */
361 uint64_t tpidruro_ns;
362 uint64_t tpidrro_el[1];
363 };
Peter Maydella7adc4b2014-02-26 17:20:05 +0000364 uint64_t c14_cntfrq; /* Counter Frequency register */
365 uint64_t c14_cntkctl; /* Timer Control register */
Edgar E. Iglesias0b6440a2015-08-13 11:26:18 +0100366 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
Edgar E. Iglesiasedac4d82015-08-13 11:26:17 +0100367 uint64_t cntvoff_el2; /* Counter Virtual Offset register */
Peter Maydell55d284a2013-08-20 14:54:31 +0100368 ARMGenericTimer c14_timer[NUM_GTIMERS];
balrogc1713132007-04-30 01:26:42 +0000369 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
balrogc3d26892007-07-29 17:57:26 +0000370 uint32_t c15_ticonfig; /* TI925T configuration byte. */
371 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
372 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
373 uint32_t c15_threadid; /* TI debugger thread-ID. */
Mark Langsdorf7da362d2012-01-05 15:49:06 +0000374 uint32_t c15_config_base_address; /* SCU base address. */
375 uint32_t c15_diagnostic; /* diagnostic register */
376 uint32_t c15_power_diagnostic;
377 uint32_t c15_power_control; /* power control */
Peter Maydell0b454512014-02-26 17:20:05 +0000378 uint64_t dbgbvr[16]; /* breakpoint value registers */
379 uint64_t dbgbcr[16]; /* breakpoint control registers */
380 uint64_t dbgwvr[16]; /* watchpoint value registers */
381 uint64_t dbgwcr[16]; /* watchpoint control registers */
Peter Maydell3a298202014-08-19 18:56:26 +0100382 uint64_t mdscr_el1;
Davorin Mista1424ca82015-10-16 11:14:53 +0100383 uint64_t oslsr_el1; /* OS Lock Status */
Sergey Fedorov14cc7b52015-10-16 11:14:54 +0100384 uint64_t mdcr_el2;
Alistair Francis7c2cb422014-03-10 14:56:28 +0000385 /* If the counter is enabled, this stores the last time the counter
386 * was reset. Otherwise it stores the counter value
387 */
Alistair Francisc92c0682014-08-29 15:00:29 +0100388 uint64_t c15_ccnt;
Alistair Francis85214662014-08-29 15:00:29 +0100389 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
Edgar E. Iglesias731de9e2015-09-14 14:39:50 +0100390 uint64_t vpidr_el2; /* Virtualization Processor ID Register */
Edgar E. Iglesiasf0d574d2015-09-14 14:39:51 +0100391 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
bellardb5ff1b32005-11-26 10:38:39 +0000392 } cp15;
pbrook40f137e2006-02-20 00:33:36 +0000393
pbrook9ee6e8b2007-11-11 00:04:49 +0000394 struct {
395 uint32_t other_sp;
396 uint32_t vecbase;
397 uint32_t basepri;
398 uint32_t control;
399 int current_sp;
400 int exception;
pbrook9ee6e8b2007-11-11 00:04:49 +0000401 } v7m;
402
Peter Maydellabf11722014-04-15 19:18:38 +0100403 /* Information associated with an exception about to be taken:
404 * code which raises an exception must set cs->exception_index and
405 * the relevant parts of this structure; the cpu_do_interrupt function
406 * will then set the guest-visible registers as part of the exception
407 * entry process.
408 */
409 struct {
410 uint32_t syndrome; /* AArch64 format syndrome register */
411 uint32_t fsr; /* AArch32 format fault status register info */
412 uint64_t vaddress; /* virtual addr associated with exception, if any */
Greg Bellows73710362015-05-29 11:28:50 +0100413 uint32_t target_el; /* EL the exception should be targeted for */
Peter Maydellabf11722014-04-15 19:18:38 +0100414 /* If we implement EL2 we will also need to store information
415 * about the intermediate physical address for stage 2 faults.
416 */
417 } exception;
418
pbrookfe1479c2008-12-19 13:18:36 +0000419 /* Thumb-2 EE state. */
420 uint32_t teecr;
421 uint32_t teehbr;
422
bellardb7bcbe92005-02-22 19:27:29 +0000423 /* VFP coprocessor state. */
424 struct {
Alexander Graf3926cc82013-09-03 20:12:09 +0100425 /* VFP/Neon register state. Note that the mapping between S, D and Q
426 * views of the register bank differs between AArch64 and AArch32:
427 * In AArch32:
428 * Qn = regs[2n+1]:regs[2n]
429 * Dn = regs[n]
430 * Sn = regs[n/2] bits 31..0 for even n, and bits 63..32 for odd n
431 * (and regs[32] to regs[63] are inaccessible)
432 * In AArch64:
433 * Qn = regs[2n+1]:regs[2n]
434 * Dn = regs[2n]
435 * Sn = regs[2n] bits 31..0
436 * This corresponds to the architecturally defined mapping between
437 * the two execution states, and means we do not need to explicitly
438 * map these registers when changing states.
439 */
440 float64 regs[64];
bellardb7bcbe92005-02-22 19:27:29 +0000441
pbrook40f137e2006-02-20 00:33:36 +0000442 uint32_t xregs[16];
bellardb7bcbe92005-02-22 19:27:29 +0000443 /* We store these fpcsr fields separately for convenience. */
444 int vec_len;
445 int vec_stride;
446
pbrook9ee6e8b2007-11-11 00:04:49 +0000447 /* scratch space when Tn are not sufficient. */
448 uint32_t scratch[8];
ths3b46e622007-09-17 08:09:54 +0000449
Peter Maydell3a492f32011-01-14 20:39:18 +0100450 /* fp_status is the "normal" fp status. standard_fp_status retains
451 * values corresponding to the ARM "Standard FPSCR Value", ie
452 * default-NaN, flush-to-zero, round-to-nearest and is used by
453 * any operations (generally Neon) which the architecture defines
454 * as controlled by the standard FPSCR value rather than the FPSCR.
455 *
456 * To avoid having to transfer exception bits around, we simply
457 * say that the FPSCR cumulative exception flags are the logical
458 * OR of the flags in the two fp statuses. This relies on the
459 * only thing which needs to read the exception flags being
460 * an explicit FPSCR read.
461 */
bellard53cd6632005-03-13 18:50:23 +0000462 float_status fp_status;
Peter Maydell3a492f32011-01-14 20:39:18 +0100463 float_status standard_fp_status;
bellardb7bcbe92005-02-22 19:27:29 +0000464 } vfp;
Peter Maydell03d05e22014-01-04 22:15:47 +0000465 uint64_t exclusive_addr;
466 uint64_t exclusive_val;
467 uint64_t exclusive_high;
pbrook9ee6e8b2007-11-11 00:04:49 +0000468#if defined(CONFIG_USER_ONLY)
Peter Maydell03d05e22014-01-04 22:15:47 +0000469 uint64_t exclusive_test;
Paul Brook426f5ab2009-11-22 21:35:13 +0000470 uint32_t exclusive_info;
pbrook9ee6e8b2007-11-11 00:04:49 +0000471#endif
bellardb7bcbe92005-02-22 19:27:29 +0000472
balrog18c9b562007-04-30 02:02:17 +0000473 /* iwMMXt coprocessor state. */
474 struct {
475 uint64_t regs[16];
476 uint64_t val;
477
478 uint32_t cregs[16];
479 } iwmmxt;
480
Paul Brookd8fd2952012-03-30 18:02:50 +0100481 /* For mixed endian mode. */
482 bool bswap_code;
483
pbrookce4defa2006-02-09 16:49:55 +0000484#if defined(CONFIG_USER_ONLY)
485 /* For usermode syscall translation. */
486 int eabi;
487#endif
488
Peter Maydell46747d12014-09-29 18:48:46 +0100489 struct CPUBreakpoint *cpu_breakpoint[16];
Peter Maydell9ee98ce2014-09-12 14:06:49 +0100490 struct CPUWatchpoint *cpu_watchpoint[16];
491
bellarda316d332005-11-20 10:32:34 +0000492 CPU_COMMON
493
balrog9d551992007-04-30 02:24:42 +0000494 /* These fields after the common ones so they are preserved on reset. */
Lars Munch9ba8c3f2010-05-08 22:42:43 +0200495
Peter Maydell581be092012-04-20 17:58:31 +0000496 /* Internal CPU feature flags. */
Peter Maydell918f5dc2012-07-12 10:59:06 +0000497 uint64_t features;
Peter Maydell581be092012-04-20 17:58:31 +0000498
Peter Crosthwaite6cb0b012015-06-19 14:17:44 +0100499 /* PMSAv7 MPU */
500 struct {
501 uint32_t *drbar;
502 uint32_t *drsr;
503 uint32_t *dracr;
504 } pmsav7;
505
Paul Brook983fe822010-04-05 19:34:51 +0100506 void *nvic;
Stefan Weil462a8bc2011-06-23 17:53:48 +0200507 const struct arm_boot_info *boot_info;
bellard2c0262a2003-09-30 20:34:21 +0000508} CPUARMState;
509
Andreas Färber778c3a02012-04-20 07:39:14 +0000510#include "cpu-qom.h"
511
512ARMCPU *cpu_arm_init(const char *cpu_model);
Peter Crosthwaiteea3e9842015-06-18 10:24:55 -0700513int cpu_arm_exec(CPUState *cpu);
Peter Maydellfaacc042015-09-07 10:39:28 +0100514target_ulong do_arm_semihosting(CPUARMState *env);
Greg Bellowsce020492015-02-13 05:46:08 +0000515void aarch64_sync_32_to_64(CPUARMState *env);
516void aarch64_sync_64_to_32(CPUARMState *env);
bellardb5ff1b32005-11-26 10:38:39 +0000517
Alexander Graf3926cc82013-09-03 20:12:09 +0100518static inline bool is_a64(CPUARMState *env)
519{
520 return env->aarch64;
521}
522
bellard2c0262a2003-09-30 20:34:21 +0000523/* you can call this signal handler from your SIGBUS and SIGSEGV
524 signal handlers to inform the virtual CPU of exceptions. non zero
525 is returned if the signal was handled by the virtual CPU. */
ths5fafdf22007-09-16 21:08:06 +0000526int cpu_arm_signal_handler(int host_signum, void *pinfo,
bellard2c0262a2003-09-30 20:34:21 +0000527 void *puc);
528
Alistair Francisec7b4ce2014-08-29 15:00:29 +0100529/**
530 * pmccntr_sync
531 * @env: CPUARMState
532 *
533 * Synchronises the counter in the PMCCNTR. This must always be called twice,
534 * once before any action that might affect the timer and again afterwards.
535 * The function is used to swap the state of the register if required.
536 * This only happens when not in user mode (!CONFIG_USER_ONLY)
537 */
538void pmccntr_sync(CPUARMState *env);
539
Peter Maydell76e3e1b2014-02-20 10:35:51 +0000540/* SCTLR bit meanings. Several bits have been reused in newer
541 * versions of the architecture; in that case we define constants
542 * for both old and new bit meanings. Code which tests against those
543 * bits should probably check or otherwise arrange that the CPU
544 * is the architectural version it expects.
545 */
546#define SCTLR_M (1U << 0)
547#define SCTLR_A (1U << 1)
548#define SCTLR_C (1U << 2)
549#define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
550#define SCTLR_SA (1U << 3)
551#define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
552#define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
553#define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
554#define SCTLR_CP15BEN (1U << 5) /* v7 onward */
555#define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
556#define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
557#define SCTLR_ITD (1U << 7) /* v8 onward */
558#define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
559#define SCTLR_SED (1U << 8) /* v8 onward */
560#define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
561#define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
562#define SCTLR_F (1U << 10) /* up to v6 */
563#define SCTLR_SW (1U << 10) /* v7 onward */
564#define SCTLR_Z (1U << 11)
565#define SCTLR_I (1U << 12)
566#define SCTLR_V (1U << 13)
567#define SCTLR_RR (1U << 14) /* up to v7 */
568#define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
569#define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
570#define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
571#define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
572#define SCTLR_nTWI (1U << 16) /* v8 onward */
573#define SCTLR_HA (1U << 17)
Peter Crosthwaitef6bda882015-06-19 14:17:45 +0100574#define SCTLR_BR (1U << 17) /* PMSA only */
Peter Maydell76e3e1b2014-02-20 10:35:51 +0000575#define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
576#define SCTLR_nTWE (1U << 18) /* v8 onward */
577#define SCTLR_WXN (1U << 19)
578#define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
579#define SCTLR_UWXN (1U << 20) /* v7 onward */
580#define SCTLR_FI (1U << 21)
581#define SCTLR_U (1U << 22)
582#define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
583#define SCTLR_VE (1U << 24) /* up to v7 */
584#define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
585#define SCTLR_EE (1U << 25)
586#define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
587#define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
588#define SCTLR_NMFI (1U << 27)
589#define SCTLR_TRE (1U << 28)
590#define SCTLR_AFE (1U << 29)
591#define SCTLR_TE (1U << 30)
592
Greg Bellowsc6f19162015-05-29 11:28:52 +0100593#define CPTR_TCPAC (1U << 31)
594#define CPTR_TTA (1U << 20)
595#define CPTR_TFP (1U << 10)
596
Peter Maydell78dbbbe2013-09-10 19:09:32 +0100597#define CPSR_M (0x1fU)
598#define CPSR_T (1U << 5)
599#define CPSR_F (1U << 6)
600#define CPSR_I (1U << 7)
601#define CPSR_A (1U << 8)
602#define CPSR_E (1U << 9)
603#define CPSR_IT_2_7 (0xfc00U)
604#define CPSR_GE (0xfU << 16)
Peter Maydell4051e122014-08-19 18:56:26 +0100605#define CPSR_IL (1U << 20)
606/* Note that the RESERVED bits include bit 21, which is PSTATE_SS in
607 * an AArch64 SPSR but RES0 in AArch32 SPSR and CPSR. In QEMU we use
608 * env->uncached_cpsr bit 21 to store PSTATE.SS when executing in AArch32,
609 * where it is live state but not accessible to the AArch32 code.
610 */
611#define CPSR_RESERVED (0x7U << 21)
Peter Maydell78dbbbe2013-09-10 19:09:32 +0100612#define CPSR_J (1U << 24)
613#define CPSR_IT_0_1 (3U << 25)
614#define CPSR_Q (1U << 27)
615#define CPSR_V (1U << 28)
616#define CPSR_C (1U << 29)
617#define CPSR_Z (1U << 30)
618#define CPSR_N (1U << 31)
pbrook9ee6e8b2007-11-11 00:04:49 +0000619#define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
Peter Maydell4cc35612014-02-26 17:20:06 +0000620#define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
bellardb5ff1b32005-11-26 10:38:39 +0000621
pbrook9ee6e8b2007-11-11 00:04:49 +0000622#define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
Peter Maydell4cc35612014-02-26 17:20:06 +0000623#define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
624 | CPSR_NZCV)
pbrook9ee6e8b2007-11-11 00:04:49 +0000625/* Bits writable in user mode. */
626#define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
627/* Execution state bits. MRS read as zero, MSR writes ignored. */
Peter Maydell4051e122014-08-19 18:56:26 +0100628#define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
629/* Mask of bits which may be set by exception return copying them from SPSR */
630#define CPSR_ERET_MASK (~CPSR_RESERVED)
pbrook9ee6e8b2007-11-11 00:04:49 +0000631
Fabian Aggelere389be12014-06-19 18:06:24 +0100632#define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
633#define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
634#define TTBCR_PD0 (1U << 4)
635#define TTBCR_PD1 (1U << 5)
636#define TTBCR_EPD0 (1U << 7)
637#define TTBCR_IRGN0 (3U << 8)
638#define TTBCR_ORGN0 (3U << 10)
639#define TTBCR_SH0 (3U << 12)
640#define TTBCR_T1SZ (3U << 16)
641#define TTBCR_A1 (1U << 22)
642#define TTBCR_EPD1 (1U << 23)
643#define TTBCR_IRGN1 (3U << 24)
644#define TTBCR_ORGN1 (3U << 26)
645#define TTBCR_SH1 (1U << 28)
646#define TTBCR_EAE (1U << 31)
647
Peter Maydelld3563122013-12-17 19:42:30 +0000648/* Bit definitions for ARMv8 SPSR (PSTATE) format.
649 * Only these are valid when in AArch64 mode; in
650 * AArch32 mode SPSRs are basically CPSR-format.
651 */
Peter Maydellf502cfc2014-04-15 19:18:43 +0100652#define PSTATE_SP (1U)
Peter Maydelld3563122013-12-17 19:42:30 +0000653#define PSTATE_M (0xFU)
654#define PSTATE_nRW (1U << 4)
655#define PSTATE_F (1U << 6)
656#define PSTATE_I (1U << 7)
657#define PSTATE_A (1U << 8)
658#define PSTATE_D (1U << 9)
659#define PSTATE_IL (1U << 20)
660#define PSTATE_SS (1U << 21)
661#define PSTATE_V (1U << 28)
662#define PSTATE_C (1U << 29)
663#define PSTATE_Z (1U << 30)
664#define PSTATE_N (1U << 31)
665#define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
Peter Maydell4cc35612014-02-26 17:20:06 +0000666#define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
667#define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF)
Peter Maydelld3563122013-12-17 19:42:30 +0000668/* Mode values for AArch64 */
669#define PSTATE_MODE_EL3h 13
670#define PSTATE_MODE_EL3t 12
671#define PSTATE_MODE_EL2h 9
672#define PSTATE_MODE_EL2t 8
673#define PSTATE_MODE_EL1h 5
674#define PSTATE_MODE_EL1t 4
675#define PSTATE_MODE_EL0t 0
676
Edgar E. Iglesias9e729b52014-09-29 18:48:49 +0100677/* Map EL and handler into a PSTATE_MODE. */
678static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
679{
680 return (el << 2) | handler;
681}
682
Peter Maydelld3563122013-12-17 19:42:30 +0000683/* Return the current PSTATE value. For the moment we don't support 32<->64 bit
684 * interprocessing, so we don't attempt to sync with the cpsr state used by
685 * the 32 bit decoder.
686 */
687static inline uint32_t pstate_read(CPUARMState *env)
688{
689 int ZF;
690
691 ZF = (env->ZF == 0);
692 return (env->NF & 0x80000000) | (ZF << 30)
693 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
Peter Maydell4cc35612014-02-26 17:20:06 +0000694 | env->pstate | env->daif;
Peter Maydelld3563122013-12-17 19:42:30 +0000695}
696
697static inline void pstate_write(CPUARMState *env, uint32_t val)
698{
699 env->ZF = (~val) & PSTATE_Z;
700 env->NF = val;
701 env->CF = (val >> 29) & 1;
702 env->VF = (val << 3) & 0x80000000;
Peter Maydell4cc35612014-02-26 17:20:06 +0000703 env->daif = val & PSTATE_DAIF;
Peter Maydelld3563122013-12-17 19:42:30 +0000704 env->pstate = val & ~CACHED_PSTATE_BITS;
705}
706
bellardb5ff1b32005-11-26 10:38:39 +0000707/* Return the current CPSR value. */
balrog2f4a40e2007-11-13 01:50:15 +0000708uint32_t cpsr_read(CPUARMState *env);
709/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */
710void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
pbrook9ee6e8b2007-11-11 00:04:49 +0000711
712/* Return the current xPSR value. */
713static inline uint32_t xpsr_read(CPUARMState *env)
714{
715 int ZF;
pbrook6fbe23d2008-04-01 17:19:11 +0000716 ZF = (env->ZF == 0);
717 return (env->NF & 0x80000000) | (ZF << 30)
pbrook9ee6e8b2007-11-11 00:04:49 +0000718 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
719 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
720 | ((env->condexec_bits & 0xfc) << 8)
721 | env->v7m.exception;
bellardb5ff1b32005-11-26 10:38:39 +0000722}
723
pbrook9ee6e8b2007-11-11 00:04:49 +0000724/* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
725static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
726{
pbrook9ee6e8b2007-11-11 00:04:49 +0000727 if (mask & CPSR_NZCV) {
pbrook6fbe23d2008-04-01 17:19:11 +0000728 env->ZF = (~val) & CPSR_Z;
729 env->NF = val;
pbrook9ee6e8b2007-11-11 00:04:49 +0000730 env->CF = (val >> 29) & 1;
731 env->VF = (val << 3) & 0x80000000;
732 }
733 if (mask & CPSR_Q)
734 env->QF = ((val & CPSR_Q) != 0);
735 if (mask & (1 << 24))
736 env->thumb = ((val & (1 << 24)) != 0);
737 if (mask & CPSR_IT_0_1) {
738 env->condexec_bits &= ~3;
739 env->condexec_bits |= (val >> 25) & 3;
740 }
741 if (mask & CPSR_IT_2_7) {
742 env->condexec_bits &= 3;
743 env->condexec_bits |= (val >> 8) & 0xfc;
744 }
745 if (mask & 0x1ff) {
746 env->v7m.exception = val & 0x1ff;
747 }
748}
749
Edgar E. Iglesiasf149e3e2014-09-29 18:48:48 +0100750#define HCR_VM (1ULL << 0)
751#define HCR_SWIO (1ULL << 1)
752#define HCR_PTW (1ULL << 2)
753#define HCR_FMO (1ULL << 3)
754#define HCR_IMO (1ULL << 4)
755#define HCR_AMO (1ULL << 5)
756#define HCR_VF (1ULL << 6)
757#define HCR_VI (1ULL << 7)
758#define HCR_VSE (1ULL << 8)
759#define HCR_FB (1ULL << 9)
760#define HCR_BSU_MASK (3ULL << 10)
761#define HCR_DC (1ULL << 12)
762#define HCR_TWI (1ULL << 13)
763#define HCR_TWE (1ULL << 14)
764#define HCR_TID0 (1ULL << 15)
765#define HCR_TID1 (1ULL << 16)
766#define HCR_TID2 (1ULL << 17)
767#define HCR_TID3 (1ULL << 18)
768#define HCR_TSC (1ULL << 19)
769#define HCR_TIDCP (1ULL << 20)
770#define HCR_TACR (1ULL << 21)
771#define HCR_TSW (1ULL << 22)
772#define HCR_TPC (1ULL << 23)
773#define HCR_TPU (1ULL << 24)
774#define HCR_TTLB (1ULL << 25)
775#define HCR_TVM (1ULL << 26)
776#define HCR_TGE (1ULL << 27)
777#define HCR_TDZ (1ULL << 28)
778#define HCR_HCD (1ULL << 29)
779#define HCR_TRVM (1ULL << 30)
780#define HCR_RW (1ULL << 31)
781#define HCR_CD (1ULL << 32)
782#define HCR_ID (1ULL << 33)
783#define HCR_MASK ((1ULL << 34) - 1)
784
Edgar E. Iglesias64e0e2d2014-09-29 18:48:49 +0100785#define SCR_NS (1U << 0)
786#define SCR_IRQ (1U << 1)
787#define SCR_FIQ (1U << 2)
788#define SCR_EA (1U << 3)
789#define SCR_FW (1U << 4)
790#define SCR_AW (1U << 5)
791#define SCR_NET (1U << 6)
792#define SCR_SMD (1U << 7)
793#define SCR_HCE (1U << 8)
794#define SCR_SIF (1U << 9)
795#define SCR_RW (1U << 10)
796#define SCR_ST (1U << 11)
797#define SCR_TWI (1U << 12)
798#define SCR_TWE (1U << 13)
799#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
800#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
801
Peter Maydell01653292010-11-24 15:20:04 +0000802/* Return the current FPSCR value. */
803uint32_t vfp_get_fpscr(CPUARMState *env);
804void vfp_set_fpscr(CPUARMState *env, uint32_t val);
805
Peter Maydellf903fa22013-12-17 19:42:31 +0000806/* For A64 the FPSCR is split into two logically distinct registers,
807 * FPCR and FPSR. However since they still use non-overlapping bits
808 * we store the underlying state in fpscr and just mask on read/write.
809 */
810#define FPSR_MASK 0xf800009f
811#define FPCR_MASK 0x07f79f00
812static inline uint32_t vfp_get_fpsr(CPUARMState *env)
813{
814 return vfp_get_fpscr(env) & FPSR_MASK;
815}
816
817static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
818{
819 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
820 vfp_set_fpscr(env, new_fpscr);
821}
822
823static inline uint32_t vfp_get_fpcr(CPUARMState *env)
824{
825 return vfp_get_fpscr(env) & FPCR_MASK;
826}
827
828static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
829{
830 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
831 vfp_set_fpscr(env, new_fpscr);
832}
833
bellardb5ff1b32005-11-26 10:38:39 +0000834enum arm_cpu_mode {
835 ARM_CPU_MODE_USR = 0x10,
836 ARM_CPU_MODE_FIQ = 0x11,
837 ARM_CPU_MODE_IRQ = 0x12,
838 ARM_CPU_MODE_SVC = 0x13,
Edgar E. Iglesias28c94572014-05-27 17:09:52 +0100839 ARM_CPU_MODE_MON = 0x16,
bellardb5ff1b32005-11-26 10:38:39 +0000840 ARM_CPU_MODE_ABT = 0x17,
Edgar E. Iglesias28c94572014-05-27 17:09:52 +0100841 ARM_CPU_MODE_HYP = 0x1a,
bellardb5ff1b32005-11-26 10:38:39 +0000842 ARM_CPU_MODE_UND = 0x1b,
843 ARM_CPU_MODE_SYS = 0x1f
844};
845
pbrook40f137e2006-02-20 00:33:36 +0000846/* VFP system registers. */
847#define ARM_VFP_FPSID 0
848#define ARM_VFP_FPSCR 1
Peter Maydella50c0f52014-04-15 19:18:44 +0100849#define ARM_VFP_MVFR2 5
pbrook9ee6e8b2007-11-11 00:04:49 +0000850#define ARM_VFP_MVFR1 6
851#define ARM_VFP_MVFR0 7
pbrook40f137e2006-02-20 00:33:36 +0000852#define ARM_VFP_FPEXC 8
853#define ARM_VFP_FPINST 9
854#define ARM_VFP_FPINST2 10
855
balrog18c9b562007-04-30 02:02:17 +0000856/* iwMMXt coprocessor control registers. */
857#define ARM_IWMMXT_wCID 0
858#define ARM_IWMMXT_wCon 1
859#define ARM_IWMMXT_wCSSF 2
860#define ARM_IWMMXT_wCASF 3
861#define ARM_IWMMXT_wCGR0 8
862#define ARM_IWMMXT_wCGR1 9
863#define ARM_IWMMXT_wCGR2 10
864#define ARM_IWMMXT_wCGR3 11
865
Benoit Canetce854d72011-11-09 07:32:59 +0000866/* If adding a feature bit which corresponds to a Linux ELF
867 * HWCAP bit, remember to update the feature-bit-to-hwcap
868 * mapping in linux-user/elfload.c:get_elf_hwcap().
869 */
pbrook40f137e2006-02-20 00:33:36 +0000870enum arm_features {
871 ARM_FEATURE_VFP,
balrogc1713132007-04-30 01:26:42 +0000872 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
873 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
pbrookce819862007-05-08 02:30:40 +0000874 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
pbrook9ee6e8b2007-11-11 00:04:49 +0000875 ARM_FEATURE_V6,
876 ARM_FEATURE_V6K,
877 ARM_FEATURE_V7,
878 ARM_FEATURE_THUMB2,
balrogc3d26892007-07-29 17:57:26 +0000879 ARM_FEATURE_MPU, /* Only has Memory Protection Unit, not full MMU. */
pbrook9ee6e8b2007-11-11 00:04:49 +0000880 ARM_FEATURE_VFP3,
Paul Brook60011492009-11-19 16:45:20 +0000881 ARM_FEATURE_VFP_FP16,
pbrook9ee6e8b2007-11-11 00:04:49 +0000882 ARM_FEATURE_NEON,
Peter Maydell47789992011-10-19 16:14:06 +0000883 ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
pbrook9ee6e8b2007-11-11 00:04:49 +0000884 ARM_FEATURE_M, /* Microcontroller profile. */
pbrookfe1479c2008-12-19 13:18:36 +0000885 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
Peter Maydelle1bbf442011-02-03 19:43:22 +0000886 ARM_FEATURE_THUMB2EE,
Dmitry Eremin-Solenikovbe5e7a72011-04-04 17:38:44 +0400887 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
888 ARM_FEATURE_V4T,
889 ARM_FEATURE_V5,
Dmitry Eremin-Solenikov5bc95aa2011-04-19 18:56:45 +0400890 ARM_FEATURE_STRONGARM,
Peter Maydell906879a2011-07-20 10:32:55 +0000891 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
Peter Maydellb8b8ea02011-10-19 16:14:06 +0000892 ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
Peter Maydellda97f522011-10-19 16:14:07 +0000893 ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
Peter Maydell0383ac02012-01-25 12:42:29 +0000894 ARM_FEATURE_GENERIC_TIMER,
Andrew Towers06ed5d62012-03-29 02:41:08 +0000895 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
Peter Maydell1047b9d2012-06-20 11:57:15 +0000896 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
Peter Maydellc4804212012-06-20 11:57:17 +0000897 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
898 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
899 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
Peter Maydell81bdde92012-06-20 11:57:20 +0000900 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
Peter Maydellde9b05b2012-07-12 10:59:05 +0000901 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
902 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
Mans Rullgard81e69fb2013-07-15 14:35:25 +0100903 ARM_FEATURE_V8,
Alexander Graf3926cc82013-09-03 20:12:09 +0100904 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
Ard Biesheuvel9d935502013-12-17 19:42:25 +0000905 ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions */
Peter Crosthwaited8ba7802013-12-17 19:42:28 +0000906 ARM_FEATURE_CBAR, /* has cp15 CBAR */
Will Newtoneb0ecd52014-02-26 17:20:07 +0000907 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */
Peter Maydellf318cec2014-04-15 19:18:49 +0100908 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
Edgar E. Iglesiascca7c2f2014-05-27 17:09:52 +0100909 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
Edgar E. Iglesias1fe81412014-05-27 17:09:53 +0100910 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
Ard Biesheuvelf1ecb912014-06-09 15:43:23 +0100911 ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensions */
912 ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Extensions */
Peter Maydell4e624ed2014-06-09 15:43:23 +0100913 ARM_FEATURE_V8_PMULL, /* implements PMULL part of v8 Crypto Extensions */
Aurelio C. Remonda62b44f02015-06-15 18:06:09 +0100914 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
pbrook40f137e2006-02-20 00:33:36 +0000915};
916
917static inline int arm_feature(CPUARMState *env, int feature)
918{
Peter Maydell918f5dc2012-07-12 10:59:06 +0000919 return (env->features & (1ULL << feature)) != 0;
pbrook40f137e2006-02-20 00:33:36 +0000920}
921
Fabian Aggeler19e0fef2014-10-24 12:19:14 +0100922#if !defined(CONFIG_USER_ONLY)
923/* Return true if exception levels below EL3 are in secure state,
924 * or would be following an exception return to that level.
925 * Unlike arm_is_secure() (which is always a question about the
926 * _current_ state of the CPU) this doesn't care about the current
927 * EL or mode.
928 */
929static inline bool arm_is_secure_below_el3(CPUARMState *env)
930{
931 if (arm_feature(env, ARM_FEATURE_EL3)) {
932 return !(env->cp15.scr_el3 & SCR_NS);
933 } else {
934 /* If EL2 is not supported then the secure state is implementation
935 * defined, in which case QEMU defaults to non-secure.
936 */
937 return false;
938 }
939}
940
941/* Return true if the processor is in secure state */
942static inline bool arm_is_secure(CPUARMState *env)
943{
944 if (arm_feature(env, ARM_FEATURE_EL3)) {
945 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
946 /* CPU currently in AArch64 state and EL3 */
947 return true;
948 } else if (!is_a64(env) &&
949 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
950 /* CPU currently in AArch32 state and monitor mode */
951 return true;
952 }
953 }
954 return arm_is_secure_below_el3(env);
955}
956
957#else
958static inline bool arm_is_secure_below_el3(CPUARMState *env)
959{
960 return false;
961}
962
963static inline bool arm_is_secure(CPUARMState *env)
964{
965 return false;
966}
967#endif
968
Peter Maydell1f79ee32014-02-26 17:20:07 +0000969/* Return true if the specified exception level is running in AArch64 state. */
970static inline bool arm_el_is_aa64(CPUARMState *env, int el)
971{
Fabian Aggeler592125f2014-10-24 12:19:14 +0100972 /* We don't currently support EL2, and this isn't valid for EL0
Peter Maydell1f79ee32014-02-26 17:20:07 +0000973 * (if we're in EL0, is_a64() is what you want, and if we're not in EL0
974 * then the state of EL0 isn't well defined.)
975 */
Fabian Aggeler592125f2014-10-24 12:19:14 +0100976 assert(el == 1 || el == 3);
977
Peter Maydell1f79ee32014-02-26 17:20:07 +0000978 /* AArch64-capable CPUs always run with EL1 in AArch64 mode. This
979 * is a QEMU-imposed simplification which we may wish to change later.
980 * If we in future support EL2 and/or EL3, then the state of lower
981 * exception levels is controlled by the HCR.RW and SCR.RW bits.
982 */
983 return arm_feature(env, ARM_FEATURE_AARCH64);
984}
985
Sergey Fedorov3f342b92014-12-11 12:07:48 +0000986/* Function for determing whether guest cp register reads and writes should
987 * access the secure or non-secure bank of a cp register. When EL3 is
988 * operating in AArch32 state, the NS-bit determines whether the secure
989 * instance of a cp register should be used. When EL3 is AArch64 (or if
990 * it doesn't exist at all) then there is no register banking, and all
991 * accesses are to the non-secure version.
992 */
993static inline bool access_secure_reg(CPUARMState *env)
994{
995 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
996 !arm_el_is_aa64(env, 3) &&
997 !(env->cp15.scr_el3 & SCR_NS));
998
999 return ret;
1000}
1001
Fabian Aggelerea30a4b2014-12-11 12:07:48 +00001002/* Macros for accessing a specified CP register bank */
1003#define A32_BANKED_REG_GET(_env, _regname, _secure) \
1004 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
1005
1006#define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
1007 do { \
1008 if (_secure) { \
1009 (_env)->cp15._regname##_s = (_val); \
1010 } else { \
1011 (_env)->cp15._regname##_ns = (_val); \
1012 } \
1013 } while (0)
1014
1015/* Macros for automatically accessing a specific CP register bank depending on
1016 * the current secure state of the system. These macros are not intended for
1017 * supporting instruction translation reads/writes as these are dependent
1018 * solely on the SCR.NS bit and not the mode.
1019 */
1020#define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
1021 A32_BANKED_REG_GET((_env), _regname, \
Sergey Sorokin2cde0312015-10-16 11:14:52 +01001022 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
Fabian Aggelerea30a4b2014-12-11 12:07:48 +00001023
1024#define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
1025 A32_BANKED_REG_SET((_env), _regname, \
Sergey Sorokin2cde0312015-10-16 11:14:52 +01001026 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
Fabian Aggelerea30a4b2014-12-11 12:07:48 +00001027 (_val))
1028
Stefan Weil9a78eea2010-10-22 23:03:33 +02001029void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
Greg Bellows012a9062015-05-29 11:28:51 +01001030uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
1031 uint32_t cur_el, bool secure);
pbrook40f137e2006-02-20 00:33:36 +00001032
pbrook9ee6e8b2007-11-11 00:04:49 +00001033/* Interface between CPU and Interrupt controller. */
1034void armv7m_nvic_set_pending(void *opaque, int irq);
1035int armv7m_nvic_acknowledge_irq(void *opaque);
1036void armv7m_nvic_complete_irq(void *opaque, int irq);
1037
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001038/* Interface for defining coprocessor registers.
1039 * Registers are defined in tables of arm_cp_reginfo structs
1040 * which are passed to define_arm_cp_regs().
1041 */
1042
1043/* When looking up a coprocessor register we look for it
1044 * via an integer which encodes all of:
1045 * coprocessor number
1046 * Crn, Crm, opc1, opc2 fields
1047 * 32 or 64 bit register (ie is it accessed via MRC/MCR
1048 * or via MRRC/MCRR?)
Peter Maydell51a79b02014-12-11 12:07:49 +00001049 * non-secure/secure bank (AArch32 only)
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001050 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
1051 * (In this case crn and opc2 should be zero.)
Peter Maydellf5a0a5a2014-01-04 22:15:44 +00001052 * For AArch64, there is no 32/64 bit size distinction;
1053 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
1054 * and 4 bit CRn and CRm. The encoding patterns are chosen
1055 * to be easy to convert to and from the KVM encodings, and also
1056 * so that the hashtable can contain both AArch32 and AArch64
1057 * registers (to allow for interprocessing where we might run
1058 * 32 bit code on a 64 bit core).
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001059 */
Peter Maydellf5a0a5a2014-01-04 22:15:44 +00001060/* This bit is private to our hashtable cpreg; in KVM register
1061 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
1062 * in the upper bits of the 64 bit ID.
1063 */
1064#define CP_REG_AA64_SHIFT 28
1065#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
1066
Peter Maydell51a79b02014-12-11 12:07:49 +00001067/* To enable banking of coprocessor registers depending on ns-bit we
1068 * add a bit to distinguish between secure and non-secure cpregs in the
1069 * hashtable.
1070 */
1071#define CP_REG_NS_SHIFT 29
1072#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
1073
1074#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
1075 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
1076 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001077
Peter Maydellf5a0a5a2014-01-04 22:15:44 +00001078#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
1079 (CP_REG_AA64_MASK | \
1080 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
1081 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
1082 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
1083 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
1084 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
1085 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
1086
Peter Maydell721fae12013-06-25 18:16:07 +01001087/* Convert a full 64 bit KVM register ID to the truncated 32 bit
1088 * version used as a key for the coprocessor register hashtable
1089 */
1090static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
1091{
1092 uint32_t cpregid = kvmid;
Peter Maydellf5a0a5a2014-01-04 22:15:44 +00001093 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
1094 cpregid |= CP_REG_AA64_MASK;
Peter Maydell51a79b02014-12-11 12:07:49 +00001095 } else {
1096 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
1097 cpregid |= (1 << 15);
1098 }
1099
1100 /* KVM is always non-secure so add the NS flag on AArch32 register
1101 * entries.
1102 */
1103 cpregid |= 1 << CP_REG_NS_SHIFT;
Peter Maydell721fae12013-06-25 18:16:07 +01001104 }
1105 return cpregid;
1106}
1107
1108/* Convert a truncated 32 bit hashtable key into the full
1109 * 64 bit KVM register ID.
1110 */
1111static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
1112{
Peter Maydellf5a0a5a2014-01-04 22:15:44 +00001113 uint64_t kvmid;
1114
1115 if (cpregid & CP_REG_AA64_MASK) {
1116 kvmid = cpregid & ~CP_REG_AA64_MASK;
1117 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
Peter Maydell721fae12013-06-25 18:16:07 +01001118 } else {
Peter Maydellf5a0a5a2014-01-04 22:15:44 +00001119 kvmid = cpregid & ~(1 << 15);
1120 if (cpregid & (1 << 15)) {
1121 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
1122 } else {
1123 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
1124 }
Peter Maydell721fae12013-06-25 18:16:07 +01001125 }
1126 return kvmid;
1127}
1128
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001129/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
1130 * special-behaviour cp reg and bits [15..8] indicate what behaviour
1131 * it has. Otherwise it is a simple cp reg, where CONST indicates that
1132 * TCG can assume the value to be constant (ie load at translate time)
1133 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
1134 * indicates that the TB should not be ended after a write to this register
1135 * (the default is that the TB ends after cp writes). OVERRIDE permits
1136 * a register definition to override a previous definition for the
1137 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
1138 * old must have the OVERRIDE bit set.
Peter Maydell7a0e58f2015-02-05 13:37:22 +00001139 * ALIAS indicates that this register is an alias view of some underlying
1140 * state which is also visible via another register, and that the other
Sergey Fedorovb061a822015-06-19 14:17:44 +01001141 * register is handling migration and reset; registers marked ALIAS will not be
1142 * migrated but may have their state set by syncing of register state from KVM.
Peter Maydell7a0e58f2015-02-05 13:37:22 +00001143 * NO_RAW indicates that this register has no underlying state and does not
1144 * support raw access for state saving/loading; it will not be used for either
1145 * migration or KVM state synchronization. (Typically this is for "registers"
1146 * which are actually used as instructions for cache maintenance and so on.)
Peter Maydell24527312013-08-20 14:54:31 +01001147 * IO indicates that this register does I/O and therefore its accesses
1148 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
1149 * registers which implement clocks or timers require this.
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001150 */
1151#define ARM_CP_SPECIAL 1
1152#define ARM_CP_CONST 2
1153#define ARM_CP_64BIT 4
1154#define ARM_CP_SUPPRESS_TB_END 8
1155#define ARM_CP_OVERRIDE 16
Peter Maydell7a0e58f2015-02-05 13:37:22 +00001156#define ARM_CP_ALIAS 32
Peter Maydell24527312013-08-20 14:54:31 +01001157#define ARM_CP_IO 64
Peter Maydell7a0e58f2015-02-05 13:37:22 +00001158#define ARM_CP_NO_RAW 128
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001159#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
1160#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
Peter Maydellb0d2b7d2014-01-04 22:15:45 +00001161#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
Peter Maydell0eef9d92014-02-26 17:20:02 +00001162#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
Peter Maydellaca3f402014-04-15 19:18:41 +01001163#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
1164#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001165/* Used only as a terminator for ARMCPRegInfo lists */
1166#define ARM_CP_SENTINEL 0xffff
1167/* Mask of only the flag bits in a type field */
Peter Maydell7a0e58f2015-02-05 13:37:22 +00001168#define ARM_CP_FLAG_MASK 0xff
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001169
Peter Maydellf5a0a5a2014-01-04 22:15:44 +00001170/* Valid values for ARMCPRegInfo state field, indicating which of
1171 * the AArch32 and AArch64 execution states this register is visible in.
1172 * If the reginfo doesn't explicitly specify then it is AArch32 only.
1173 * If the reginfo is declared to be visible in both states then a second
1174 * reginfo is synthesised for the AArch32 view of the AArch64 register,
1175 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
1176 * Note that we rely on the values of these enums as we iterate through
1177 * the various states in some places.
1178 */
1179enum {
1180 ARM_CP_STATE_AA32 = 0,
1181 ARM_CP_STATE_AA64 = 1,
1182 ARM_CP_STATE_BOTH = 2,
1183};
1184
Fabian Aggelerc3e30262014-12-11 12:07:49 +00001185/* ARM CP register secure state flags. These flags identify security state
1186 * attributes for a given CP register entry.
1187 * The existence of both or neither secure and non-secure flags indicates that
1188 * the register has both a secure and non-secure hash entry. A single one of
1189 * these flags causes the register to only be hashed for the specified
1190 * security state.
1191 * Although definitions may have any combination of the S/NS bits, each
1192 * registered entry will only have one to identify whether the entry is secure
1193 * or non-secure.
1194 */
1195enum {
1196 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
1197 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
1198};
1199
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001200/* Return true if cptype is a valid type field. This is used to try to
1201 * catch errors where the sentinel has been accidentally left off the end
1202 * of a list of registers.
1203 */
1204static inline bool cptype_valid(int cptype)
1205{
1206 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
1207 || ((cptype & ARM_CP_SPECIAL) &&
Peter Maydell34affee2013-06-25 18:16:06 +01001208 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001209}
1210
1211/* Access rights:
1212 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
1213 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
1214 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
1215 * (ie any of the privileged modes in Secure state, or Monitor mode).
1216 * If a register is accessible in one privilege level it's always accessible
1217 * in higher privilege levels too. Since "Secure PL1" also follows this rule
1218 * (ie anything visible in PL2 is visible in S-PL1, some things are only
1219 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
1220 * terminology a little and call this PL3.
Peter Maydellf5a0a5a2014-01-04 22:15:44 +00001221 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
1222 * with the ELx exception levels.
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001223 *
1224 * If access permissions for a register are more complex than can be
1225 * described with these bits, then use a laxer set of restrictions, and
1226 * do the more restrictive/complex check inside a helper function.
1227 */
1228#define PL3_R 0x80
1229#define PL3_W 0x40
1230#define PL2_R (0x20 | PL3_R)
1231#define PL2_W (0x10 | PL3_W)
1232#define PL1_R (0x08 | PL2_R)
1233#define PL1_W (0x04 | PL2_W)
1234#define PL0_R (0x02 | PL1_R)
1235#define PL0_W (0x01 | PL1_W)
1236
1237#define PL3_RW (PL3_R | PL3_W)
1238#define PL2_RW (PL2_R | PL2_W)
1239#define PL1_RW (PL1_R | PL1_W)
1240#define PL0_RW (PL0_R | PL0_W)
1241
Greg Bellowsdcbff192014-10-24 12:19:14 +01001242/* Return the current Exception Level (as per ARMv8; note that this differs
1243 * from the ARMv7 Privilege Level).
1244 */
1245static inline int arm_current_el(CPUARMState *env)
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001246{
Peter Maydell6d54ed32015-02-05 13:37:23 +00001247 if (arm_feature(env, ARM_FEATURE_M)) {
1248 return !((env->v7m.exception == 0) && (env->v7m.control & 1));
1249 }
1250
Fabian Aggeler592125f2014-10-24 12:19:14 +01001251 if (is_a64(env)) {
Peter Maydellf5a0a5a2014-01-04 22:15:44 +00001252 return extract32(env->pstate, 2, 2);
1253 }
1254
Fabian Aggeler592125f2014-10-24 12:19:14 +01001255 switch (env->uncached_cpsr & 0x1f) {
1256 case ARM_CPU_MODE_USR:
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001257 return 0;
Fabian Aggeler592125f2014-10-24 12:19:14 +01001258 case ARM_CPU_MODE_HYP:
1259 return 2;
1260 case ARM_CPU_MODE_MON:
1261 return 3;
1262 default:
1263 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
1264 /* If EL3 is 32-bit then all secure privileged modes run in
1265 * EL3
1266 */
1267 return 3;
1268 }
1269
1270 return 1;
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001271 }
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001272}
1273
1274typedef struct ARMCPRegInfo ARMCPRegInfo;
1275
Peter Maydellf59df3f2014-02-20 10:35:52 +00001276typedef enum CPAccessResult {
1277 /* Access is permitted */
1278 CP_ACCESS_OK = 0,
1279 /* Access fails due to a configurable trap or enable which would
1280 * result in a categorized exception syndrome giving information about
1281 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
Peter Maydell38836a22015-05-29 11:28:52 +01001282 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
1283 * PL1 if in EL0, otherwise to the current EL).
Peter Maydellf59df3f2014-02-20 10:35:52 +00001284 */
1285 CP_ACCESS_TRAP = 1,
1286 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
1287 * Note that this is not a catch-all case -- the set of cases which may
1288 * result in this failure is specifically defined by the architecture.
1289 */
1290 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
Peter Maydell38836a22015-05-29 11:28:52 +01001291 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
1292 CP_ACCESS_TRAP_EL2 = 3,
1293 CP_ACCESS_TRAP_EL3 = 4,
Peter Maydelle7615722015-08-25 15:45:08 +01001294 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
1295 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
1296 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
Peter Maydellf59df3f2014-02-20 10:35:52 +00001297} CPAccessResult;
1298
Peter Maydellc4241c72014-02-20 10:35:54 +00001299/* Access functions for coprocessor registers. These cannot fail and
1300 * may not raise exceptions.
1301 */
1302typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1303typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
1304 uint64_t value);
Peter Maydellf59df3f2014-02-20 10:35:52 +00001305/* Access permission check functions for coprocessor registers. */
1306typedef CPAccessResult CPAccessFn(CPUARMState *env, const ARMCPRegInfo *opaque);
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001307/* Hook function for register reset */
1308typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
1309
1310#define CP_ANY 0xff
1311
1312/* Definition of an ARM coprocessor register */
1313struct ARMCPRegInfo {
1314 /* Name of register (useful mainly for debugging, need not be unique) */
1315 const char *name;
1316 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
1317 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
1318 * 'wildcard' field -- any value of that field in the MRC/MCR insn
1319 * will be decoded to this register. The register read and write
1320 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
1321 * used by the program, so it is possible to register a wildcard and
1322 * then behave differently on read/write if necessary.
1323 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
1324 * must both be zero.
Peter Maydellf5a0a5a2014-01-04 22:15:44 +00001325 * For AArch64-visible registers, opc0 is also used.
1326 * Since there are no "coprocessors" in AArch64, cp is purely used as a
1327 * way to distinguish (for KVM's benefit) guest-visible system registers
1328 * from demuxed ones provided to preserve the "no side effects on
1329 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
1330 * visible (to match KVM's encoding); cp==0 will be converted to
1331 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001332 */
1333 uint8_t cp;
1334 uint8_t crn;
1335 uint8_t crm;
Peter Maydellf5a0a5a2014-01-04 22:15:44 +00001336 uint8_t opc0;
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001337 uint8_t opc1;
1338 uint8_t opc2;
Peter Maydellf5a0a5a2014-01-04 22:15:44 +00001339 /* Execution state in which this register is visible: ARM_CP_STATE_* */
1340 int state;
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001341 /* Register type: ARM_CP_* bits/values */
1342 int type;
1343 /* Access rights: PL*_[RW] */
1344 int access;
Fabian Aggelerc3e30262014-12-11 12:07:49 +00001345 /* Security state: ARM_CP_SECSTATE_* bits/values */
1346 int secure;
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001347 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
1348 * this register was defined: can be used to hand data through to the
1349 * register read/write functions, since they are passed the ARMCPRegInfo*.
1350 */
1351 void *opaque;
1352 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
1353 * fieldoffset is non-zero, the reset value of the register.
1354 */
1355 uint64_t resetvalue;
Fabian Aggelerc3e30262014-12-11 12:07:49 +00001356 /* Offset of the field in CPUARMState for this register.
1357 *
1358 * This is not needed if either:
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001359 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
1360 * 2. both readfn and writefn are specified
1361 */
1362 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
Fabian Aggelerc3e30262014-12-11 12:07:49 +00001363
1364 /* Offsets of the secure and non-secure fields in CPUARMState for the
1365 * register if it is banked. These fields are only used during the static
1366 * registration of a register. During hashing the bank associated
1367 * with a given security state is copied to fieldoffset which is used from
1368 * there on out.
1369 *
1370 * It is expected that register definitions use either fieldoffset or
1371 * bank_fieldoffsets in the definition but not both. It is also expected
1372 * that both bank offsets are set when defining a banked register. This
1373 * use indicates that a register is banked.
1374 */
1375 ptrdiff_t bank_fieldoffsets[2];
1376
Peter Maydellf59df3f2014-02-20 10:35:52 +00001377 /* Function for making any access checks for this register in addition to
1378 * those specified by the 'access' permissions bits. If NULL, no extra
1379 * checks required. The access check is performed at runtime, not at
1380 * translate time.
1381 */
1382 CPAccessFn *accessfn;
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001383 /* Function for handling reads of this register. If NULL, then reads
1384 * will be done by loading from the offset into CPUARMState specified
1385 * by fieldoffset.
1386 */
1387 CPReadFn *readfn;
1388 /* Function for handling writes of this register. If NULL, then writes
1389 * will be done by writing to the offset into CPUARMState specified
1390 * by fieldoffset.
1391 */
1392 CPWriteFn *writefn;
Peter Maydell7023ec72013-06-25 18:16:06 +01001393 /* Function for doing a "raw" read; used when we need to copy
1394 * coprocessor state to the kernel for KVM or out for
1395 * migration. This only needs to be provided if there is also a
Peter Maydellc4241c72014-02-20 10:35:54 +00001396 * readfn and it has side effects (for instance clear-on-read bits).
Peter Maydell7023ec72013-06-25 18:16:06 +01001397 */
1398 CPReadFn *raw_readfn;
1399 /* Function for doing a "raw" write; used when we need to copy KVM
1400 * kernel coprocessor state into userspace, or for inbound
1401 * migration. This only needs to be provided if there is also a
Peter Maydellc4241c72014-02-20 10:35:54 +00001402 * writefn and it masks out "unwritable" bits or has write-one-to-clear
1403 * or similar behaviour.
Peter Maydell7023ec72013-06-25 18:16:06 +01001404 */
1405 CPWriteFn *raw_writefn;
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001406 /* Function for resetting the register. If NULL, then reset will be done
1407 * by writing resetvalue to the field specified in fieldoffset. If
1408 * fieldoffset is 0 then no reset will be done.
1409 */
1410 CPResetFn *resetfn;
1411};
1412
1413/* Macros which are lvalues for the field in CPUARMState for the
1414 * ARMCPRegInfo *ri.
1415 */
1416#define CPREG_FIELD32(env, ri) \
1417 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
1418#define CPREG_FIELD64(env, ri) \
1419 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
1420
1421#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
1422
1423void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1424 const ARMCPRegInfo *regs, void *opaque);
1425void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1426 const ARMCPRegInfo *regs, void *opaque);
1427static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
1428{
1429 define_arm_cp_regs_with_opaque(cpu, regs, 0);
1430}
1431static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
1432{
1433 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
1434}
Peter Maydell60322b32014-01-04 22:15:44 +00001435const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001436
1437/* CPWriteFn that can be used to implement writes-ignored behaviour */
Peter Maydellc4241c72014-02-20 10:35:54 +00001438void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1439 uint64_t value);
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001440/* CPReadFn that can be used for read-as-zero behaviour */
Peter Maydellc4241c72014-02-20 10:35:54 +00001441uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001442
Peter Maydellf5a0a5a2014-01-04 22:15:44 +00001443/* CPResetFn that does nothing, for use if no reset is required even
1444 * if fieldoffset is non zero.
1445 */
1446void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
1447
Peter Maydell67ed7712014-02-26 17:20:01 +00001448/* Return true if this reginfo struct's field in the cpu state struct
1449 * is 64 bits wide.
1450 */
1451static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
1452{
1453 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
1454}
1455
Greg Bellowsdcbff192014-10-24 12:19:14 +01001456static inline bool cp_access_ok(int current_el,
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001457 const ARMCPRegInfo *ri, int isread)
1458{
Greg Bellowsdcbff192014-10-24 12:19:14 +01001459 return (ri->access >> ((current_el * 2) + isread)) & 1;
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001460}
1461
Peter Maydell49a66192015-08-13 11:26:21 +01001462/* Raw read of a coprocessor register (as needed for migration, etc) */
1463uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
1464
Peter Maydell721fae12013-06-25 18:16:07 +01001465/**
1466 * write_list_to_cpustate
1467 * @cpu: ARMCPU
1468 *
1469 * For each register listed in the ARMCPU cpreg_indexes list, write
1470 * its value from the cpreg_values list into the ARMCPUState structure.
1471 * This updates TCG's working data structures from KVM data or
1472 * from incoming migration state.
1473 *
1474 * Returns: true if all register values were updated correctly,
1475 * false if some register was unknown or could not be written.
1476 * Note that we do not stop early on failure -- we will attempt
1477 * writing all registers in the list.
1478 */
1479bool write_list_to_cpustate(ARMCPU *cpu);
1480
1481/**
1482 * write_cpustate_to_list:
1483 * @cpu: ARMCPU
1484 *
1485 * For each register listed in the ARMCPU cpreg_indexes list, write
1486 * its value from the ARMCPUState structure into the cpreg_values list.
1487 * This is used to copy info from TCG's working data structures into
1488 * KVM or for outbound migration.
1489 *
1490 * Returns: true if all register values were read correctly,
1491 * false if some register was unknown or could not be read.
1492 * Note that we do not stop early on failure -- we will attempt
1493 * reading all registers in the list.
1494 */
1495bool write_cpustate_to_list(ARMCPU *cpu);
1496
Daniel P. Berrangeb6af0972015-08-26 12:17:13 +01001497/* Does the core conform to the "MicroController" profile. e.g. Cortex-M3.
pbrook9ee6e8b2007-11-11 00:04:49 +00001498 Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
1499 conventional cores (ie. Application or Realtime profile). */
1500
1501#define IS_M(env) arm_feature(env, ARM_FEATURE_M)
pbrook9ee6e8b2007-11-11 00:04:49 +00001502
pbrook9ee6e8b2007-11-11 00:04:49 +00001503#define ARM_CPUID_TI915T 0x54029152
1504#define ARM_CPUID_TI925T 0x54029252
pbrook40f137e2006-02-20 00:33:36 +00001505
bellardb5ff1b32005-11-26 10:38:39 +00001506#if defined(CONFIG_USER_ONLY)
bellard2c0262a2003-09-30 20:34:21 +00001507#define TARGET_PAGE_BITS 12
bellardb5ff1b32005-11-26 10:38:39 +00001508#else
1509/* The ARM MMU allows 1k pages. */
1510/* ??? Linux doesn't actually use these, and they're deprecated in recent
balrog82d17972007-07-24 01:07:44 +00001511 architecture revisions. Maybe a configure option to disable them. */
bellardb5ff1b32005-11-26 10:38:39 +00001512#define TARGET_PAGE_BITS 10
1513#endif
ths9467d442007-06-03 21:02:38 +00001514
Alexander Graf3926cc82013-09-03 20:12:09 +01001515#if defined(TARGET_AARCH64)
1516# define TARGET_PHYS_ADDR_SPACE_BITS 48
1517# define TARGET_VIRT_ADDR_SPACE_BITS 64
1518#else
1519# define TARGET_PHYS_ADDR_SPACE_BITS 40
1520# define TARGET_VIRT_ADDR_SPACE_BITS 32
1521#endif
Richard Henderson52705892010-03-10 14:33:23 -08001522
Greg Bellows012a9062015-05-29 11:28:51 +01001523static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
1524 unsigned int target_el)
Edgar E. Iglesias043b7f82014-09-29 18:48:49 +01001525{
1526 CPUARMState *env = cs->env_ptr;
Greg Bellowsdcbff192014-10-24 12:19:14 +01001527 unsigned int cur_el = arm_current_el(env);
Greg Bellows57e3a0c2014-12-11 12:07:48 +00001528 bool secure = arm_is_secure(env);
Greg Bellows57e3a0c2014-12-11 12:07:48 +00001529 bool pstate_unmasked;
1530 int8_t unmasked = 0;
Edgar E. Iglesiasdfafd092014-09-29 18:48:49 +01001531
Greg Bellows57e3a0c2014-12-11 12:07:48 +00001532 /* Don't take exceptions if they target a lower EL.
1533 * This check should catch any exceptions that would not be taken but left
1534 * pending.
1535 */
Edgar E. Iglesiasdfafd092014-09-29 18:48:49 +01001536 if (cur_el > target_el) {
1537 return false;
1538 }
Edgar E. Iglesias043b7f82014-09-29 18:48:49 +01001539
1540 switch (excp_idx) {
1541 case EXCP_FIQ:
Greg Bellows57e3a0c2014-12-11 12:07:48 +00001542 pstate_unmasked = !(env->daif & PSTATE_F);
1543 break;
1544
Edgar E. Iglesias043b7f82014-09-29 18:48:49 +01001545 case EXCP_IRQ:
Greg Bellows57e3a0c2014-12-11 12:07:48 +00001546 pstate_unmasked = !(env->daif & PSTATE_I);
1547 break;
1548
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +01001549 case EXCP_VFIQ:
Peter Maydell9fae24f2014-10-30 15:48:52 +00001550 if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) {
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +01001551 /* VFIQs are only taken when hypervized and non-secure. */
1552 return false;
1553 }
1554 return !(env->daif & PSTATE_F);
1555 case EXCP_VIRQ:
Peter Maydell9fae24f2014-10-30 15:48:52 +00001556 if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) {
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +01001557 /* VIRQs are only taken when hypervized and non-secure. */
1558 return false;
1559 }
Peter Maydellb5c633c2014-10-30 15:48:51 +00001560 return !(env->daif & PSTATE_I);
Edgar E. Iglesias043b7f82014-09-29 18:48:49 +01001561 default:
1562 g_assert_not_reached();
1563 }
Greg Bellows57e3a0c2014-12-11 12:07:48 +00001564
1565 /* Use the target EL, current execution state and SCR/HCR settings to
1566 * determine whether the corresponding CPSR bit is used to mask the
1567 * interrupt.
1568 */
1569 if ((target_el > cur_el) && (target_el != 1)) {
Peter Maydell7cd6de32015-10-27 12:00:50 +00001570 /* Exceptions targeting a higher EL may not be maskable */
1571 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
1572 /* 64-bit masking rules are simple: exceptions to EL3
1573 * can't be masked, and exceptions to EL2 can only be
1574 * masked from Secure state. The HCR and SCR settings
1575 * don't affect the masking logic, only the interrupt routing.
1576 */
1577 if (target_el == 3 || !secure) {
1578 unmasked = 1;
1579 }
1580 } else {
1581 /* The old 32-bit-only environment has a more complicated
1582 * masking setup. HCR and SCR bits not only affect interrupt
1583 * routing but also change the behaviour of masking.
1584 */
1585 bool hcr, scr;
1586
1587 switch (excp_idx) {
1588 case EXCP_FIQ:
1589 /* If FIQs are routed to EL3 or EL2 then there are cases where
1590 * we override the CPSR.F in determining if the exception is
1591 * masked or not. If neither of these are set then we fall back
1592 * to the CPSR.F setting otherwise we further assess the state
1593 * below.
1594 */
1595 hcr = (env->cp15.hcr_el2 & HCR_FMO);
1596 scr = (env->cp15.scr_el3 & SCR_FIQ);
1597
1598 /* When EL3 is 32-bit, the SCR.FW bit controls whether the
1599 * CPSR.F bit masks FIQ interrupts when taken in non-secure
1600 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
1601 * when non-secure but only when FIQs are only routed to EL3.
1602 */
1603 scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
1604 break;
1605 case EXCP_IRQ:
1606 /* When EL3 execution state is 32-bit, if HCR.IMO is set then
1607 * we may override the CPSR.I masking when in non-secure state.
1608 * The SCR.IRQ setting has already been taken into consideration
1609 * when setting the target EL, so it does not have a further
1610 * affect here.
1611 */
1612 hcr = (env->cp15.hcr_el2 & HCR_IMO);
1613 scr = false;
1614 break;
1615 default:
1616 g_assert_not_reached();
1617 }
1618
1619 if ((scr || hcr) && !secure) {
1620 unmasked = 1;
1621 }
Greg Bellows57e3a0c2014-12-11 12:07:48 +00001622 }
1623 }
1624
1625 /* The PSTATE bits only mask the interrupt if we have not overriden the
1626 * ability above.
1627 */
1628 return unmasked || pstate_unmasked;
Edgar E. Iglesias043b7f82014-09-29 18:48:49 +01001629}
1630
Eduardo Habkost2994fd92015-02-26 17:37:49 -03001631#define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model))
Peter Maydellad37ad52012-05-10 12:56:09 +00001632
ths9467d442007-06-03 21:02:38 +00001633#define cpu_exec cpu_arm_exec
ths9467d442007-06-03 21:02:38 +00001634#define cpu_signal_handler cpu_arm_signal_handler
j_mayerc732abe2007-10-12 06:47:46 +00001635#define cpu_list arm_cpu_list
ths9467d442007-06-03 21:02:38 +00001636
Peter Maydellc1e37812015-02-05 13:37:23 +00001637/* ARM has the following "translation regimes" (as the ARM ARM calls them):
1638 *
1639 * If EL3 is 64-bit:
1640 * + NonSecure EL1 & 0 stage 1
1641 * + NonSecure EL1 & 0 stage 2
1642 * + NonSecure EL2
1643 * + Secure EL1 & EL0
1644 * + Secure EL3
1645 * If EL3 is 32-bit:
1646 * + NonSecure PL1 & 0 stage 1
1647 * + NonSecure PL1 & 0 stage 2
1648 * + NonSecure PL2
1649 * + Secure PL0 & PL1
1650 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
1651 *
1652 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
1653 * 1. we need to split the "EL1 & 0" regimes into two mmu_idxes, because they
1654 * may differ in access permissions even if the VA->PA map is the same
1655 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
1656 * translation, which means that we have one mmu_idx that deals with two
1657 * concatenated translation regimes [this sort of combined s1+2 TLB is
1658 * architecturally permitted]
1659 * 3. we don't need to allocate an mmu_idx to translations that we won't be
1660 * handling via the TLB. The only way to do a stage 1 translation without
1661 * the immediate stage 2 translation is via the ATS or AT system insns,
1662 * which can be slow-pathed and always do a page table walk.
1663 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
1664 * translation regimes, because they map reasonably well to each other
1665 * and they can't both be active at the same time.
1666 * This gives us the following list of mmu_idx values:
1667 *
1668 * NS EL0 (aka NS PL0) stage 1+2
1669 * NS EL1 (aka NS PL1) stage 1+2
1670 * NS EL2 (aka NS PL2)
1671 * S EL3 (aka S PL1)
1672 * S EL0 (aka S PL0)
1673 * S EL1 (not used if EL3 is 32 bit)
1674 * NS EL0+1 stage 2
1675 *
1676 * (The last of these is an mmu_idx because we want to be able to use the TLB
1677 * for the accesses done as part of a stage 1 page table walk, rather than
1678 * having to walk the stage 2 page table over and over.)
1679 *
1680 * Our enumeration includes at the end some entries which are not "true"
1681 * mmu_idx values in that they don't have corresponding TLBs and are only
1682 * valid for doing slow path page table walks.
1683 *
1684 * The constant names here are patterned after the general style of the names
1685 * of the AT/ATS operations.
1686 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
1687 */
1688typedef enum ARMMMUIdx {
1689 ARMMMUIdx_S12NSE0 = 0,
1690 ARMMMUIdx_S12NSE1 = 1,
1691 ARMMMUIdx_S1E2 = 2,
1692 ARMMMUIdx_S1E3 = 3,
1693 ARMMMUIdx_S1SE0 = 4,
1694 ARMMMUIdx_S1SE1 = 5,
1695 ARMMMUIdx_S2NS = 6,
1696 /* Indexes below here don't have TLBs and are used only for AT system
1697 * instructions or for the first stage of an S12 page table walk.
1698 */
1699 ARMMMUIdx_S1NSE0 = 7,
1700 ARMMMUIdx_S1NSE1 = 8,
1701} ARMMMUIdx;
1702
Edgar E. Iglesiasf79fbf32014-05-27 17:09:51 +01001703#define MMU_USER_IDX 0
Peter Maydellc1e37812015-02-05 13:37:23 +00001704
1705/* Return the exception level we're running at if this is our mmu_idx */
1706static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
j_mayer6ebbf392007-10-14 07:07:08 +00001707{
Peter Maydellc1e37812015-02-05 13:37:23 +00001708 assert(mmu_idx < ARMMMUIdx_S2NS);
1709 return mmu_idx & 3;
1710}
1711
1712/* Determine the current mmu_idx to use for normal loads/stores */
Benjamin Herrenschmidt97ed5cc2015-08-17 17:34:10 +10001713static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
Peter Maydellc1e37812015-02-05 13:37:23 +00001714{
1715 int el = arm_current_el(env);
1716
1717 if (el < 2 && arm_is_secure_below_el3(env)) {
1718 return ARMMMUIdx_S1SE0 + el;
1719 }
1720 return el;
j_mayer6ebbf392007-10-14 07:07:08 +00001721}
1722
Peter Maydell3a298202014-08-19 18:56:26 +01001723/* Return the Exception Level targeted by debug exceptions;
1724 * currently always EL1 since we don't implement EL2 or EL3.
1725 */
1726static inline int arm_debug_target_el(CPUARMState *env)
1727{
Sergey Fedorov81669b82015-09-14 13:53:48 +03001728 bool secure = arm_is_secure(env);
1729 bool route_to_el2 = false;
1730
1731 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
1732 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
1733 env->cp15.mdcr_el2 & (1 << 8);
1734 }
1735
1736 if (route_to_el2) {
1737 return 2;
1738 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
1739 !arm_el_is_aa64(env, 3) && secure) {
1740 return 3;
1741 } else {
1742 return 1;
1743 }
Peter Maydell3a298202014-08-19 18:56:26 +01001744}
1745
1746static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
1747{
Greg Bellowsdcbff192014-10-24 12:19:14 +01001748 if (arm_current_el(env) == arm_debug_target_el(env)) {
Peter Maydell3a298202014-08-19 18:56:26 +01001749 if ((extract32(env->cp15.mdscr_el1, 13, 1) == 0)
1750 || (env->daif & PSTATE_D)) {
1751 return false;
1752 }
1753 }
1754 return true;
1755}
1756
1757static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
1758{
Greg Bellowsdcbff192014-10-24 12:19:14 +01001759 if (arm_current_el(env) == 0 && arm_el_is_aa64(env, 1)) {
Peter Maydell3a298202014-08-19 18:56:26 +01001760 return aa64_generate_debug_exceptions(env);
1761 }
Greg Bellowsdcbff192014-10-24 12:19:14 +01001762 return arm_current_el(env) != 2;
Peter Maydell3a298202014-08-19 18:56:26 +01001763}
1764
1765/* Return true if debugging exceptions are currently enabled.
1766 * This corresponds to what in ARM ARM pseudocode would be
1767 * if UsingAArch32() then
1768 * return AArch32.GenerateDebugExceptions()
1769 * else
1770 * return AArch64.GenerateDebugExceptions()
1771 * We choose to push the if() down into this function for clarity,
1772 * since the pseudocode has it at all callsites except for the one in
1773 * CheckSoftwareStep(), where it is elided because both branches would
1774 * always return the same value.
1775 *
1776 * Parts of the pseudocode relating to EL2 and EL3 are omitted because we
1777 * don't yet implement those exception levels or their associated trap bits.
1778 */
1779static inline bool arm_generate_debug_exceptions(CPUARMState *env)
1780{
1781 if (env->aarch64) {
1782 return aa64_generate_debug_exceptions(env);
1783 } else {
1784 return aa32_generate_debug_exceptions(env);
1785 }
1786}
1787
1788/* Is single-stepping active? (Note that the "is EL_D AArch64?" check
1789 * implicitly means this always returns false in pre-v8 CPUs.)
1790 */
1791static inline bool arm_singlestep_active(CPUARMState *env)
1792{
1793 return extract32(env->cp15.mdscr_el1, 0, 1)
1794 && arm_el_is_aa64(env, arm_debug_target_el(env))
1795 && arm_generate_debug_exceptions(env);
1796}
1797
Paolo Bonzini022c62c2012-12-17 18:19:49 +01001798#include "exec/cpu-all.h"
aliguori622ed362008-11-18 19:36:03 +00001799
Alexander Graf3926cc82013-09-03 20:12:09 +01001800/* Bit usage in the TB flags field: bit 31 indicates whether we are
1801 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
Peter Maydellc1e37812015-02-05 13:37:23 +00001802 * We put flags which are shared between 32 and 64 bit mode at the top
1803 * of the word, and flags which apply to only one mode at the bottom.
Alexander Graf3926cc82013-09-03 20:12:09 +01001804 */
1805#define ARM_TBFLAG_AARCH64_STATE_SHIFT 31
1806#define ARM_TBFLAG_AARCH64_STATE_MASK (1U << ARM_TBFLAG_AARCH64_STATE_SHIFT)
Peter Maydellc1e37812015-02-05 13:37:23 +00001807#define ARM_TBFLAG_MMUIDX_SHIFT 28
1808#define ARM_TBFLAG_MMUIDX_MASK (0x7 << ARM_TBFLAG_MMUIDX_SHIFT)
Peter Maydell3cf6a0f2015-05-29 11:28:52 +01001809#define ARM_TBFLAG_SS_ACTIVE_SHIFT 27
1810#define ARM_TBFLAG_SS_ACTIVE_MASK (1 << ARM_TBFLAG_SS_ACTIVE_SHIFT)
1811#define ARM_TBFLAG_PSTATE_SS_SHIFT 26
1812#define ARM_TBFLAG_PSTATE_SS_MASK (1 << ARM_TBFLAG_PSTATE_SS_SHIFT)
Greg Bellows9dbbc742015-05-29 11:28:53 +01001813/* Target EL if we take a floating-point-disabled exception */
1814#define ARM_TBFLAG_FPEXC_EL_SHIFT 24
1815#define ARM_TBFLAG_FPEXC_EL_MASK (0x3 << ARM_TBFLAG_FPEXC_EL_SHIFT)
Alexander Graf3926cc82013-09-03 20:12:09 +01001816
1817/* Bit usage when in AArch32 state: */
Peter Maydella1705762011-01-14 20:39:18 +01001818#define ARM_TBFLAG_THUMB_SHIFT 0
1819#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT)
1820#define ARM_TBFLAG_VECLEN_SHIFT 1
1821#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
1822#define ARM_TBFLAG_VECSTRIDE_SHIFT 4
1823#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
Peter Maydella1705762011-01-14 20:39:18 +01001824#define ARM_TBFLAG_VFPEN_SHIFT 7
1825#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT)
1826#define ARM_TBFLAG_CONDEXEC_SHIFT 8
1827#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
Paul Brookd8fd2952012-03-30 18:02:50 +01001828#define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
1829#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
Peter Maydellc0f4af12014-09-29 18:48:48 +01001830/* We store the bottom two bits of the CPAR as TB flags and handle
1831 * checks on the other bits at runtime
1832 */
Peter Maydell647f7672015-05-29 11:28:53 +01001833#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
Peter Maydellc0f4af12014-09-29 18:48:48 +01001834#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
Sergey Fedorov3f342b92014-12-11 12:07:48 +00001835/* Indicates whether cp register reads and writes by guest code should access
1836 * the secure or nonsecure bank of banked registers; note that this is not
1837 * the same thing as the current security state of the processor!
1838 */
Peter Maydell647f7672015-05-29 11:28:53 +01001839#define ARM_TBFLAG_NS_SHIFT 19
Sergey Fedorov3f342b92014-12-11 12:07:48 +00001840#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
Alexander Graf3926cc82013-09-03 20:12:09 +01001841
Greg Bellows9dbbc742015-05-29 11:28:53 +01001842/* Bit usage when in AArch64 state: currently we have no A64 specific bits */
Peter Maydella1705762011-01-14 20:39:18 +01001843
1844/* some convenience accessor macros */
Alexander Graf3926cc82013-09-03 20:12:09 +01001845#define ARM_TBFLAG_AARCH64_STATE(F) \
1846 (((F) & ARM_TBFLAG_AARCH64_STATE_MASK) >> ARM_TBFLAG_AARCH64_STATE_SHIFT)
Peter Maydellc1e37812015-02-05 13:37:23 +00001847#define ARM_TBFLAG_MMUIDX(F) \
1848 (((F) & ARM_TBFLAG_MMUIDX_MASK) >> ARM_TBFLAG_MMUIDX_SHIFT)
Peter Maydell3cf6a0f2015-05-29 11:28:52 +01001849#define ARM_TBFLAG_SS_ACTIVE(F) \
1850 (((F) & ARM_TBFLAG_SS_ACTIVE_MASK) >> ARM_TBFLAG_SS_ACTIVE_SHIFT)
1851#define ARM_TBFLAG_PSTATE_SS(F) \
1852 (((F) & ARM_TBFLAG_PSTATE_SS_MASK) >> ARM_TBFLAG_PSTATE_SS_SHIFT)
Greg Bellows9dbbc742015-05-29 11:28:53 +01001853#define ARM_TBFLAG_FPEXC_EL(F) \
1854 (((F) & ARM_TBFLAG_FPEXC_EL_MASK) >> ARM_TBFLAG_FPEXC_EL_SHIFT)
Peter Maydella1705762011-01-14 20:39:18 +01001855#define ARM_TBFLAG_THUMB(F) \
1856 (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
1857#define ARM_TBFLAG_VECLEN(F) \
1858 (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
1859#define ARM_TBFLAG_VECSTRIDE(F) \
1860 (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
Peter Maydella1705762011-01-14 20:39:18 +01001861#define ARM_TBFLAG_VFPEN(F) \
1862 (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
1863#define ARM_TBFLAG_CONDEXEC(F) \
1864 (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
Paul Brookd8fd2952012-03-30 18:02:50 +01001865#define ARM_TBFLAG_BSWAP_CODE(F) \
1866 (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
Peter Maydellc0f4af12014-09-29 18:48:48 +01001867#define ARM_TBFLAG_XSCALE_CPAR(F) \
1868 (((F) & ARM_TBFLAG_XSCALE_CPAR_MASK) >> ARM_TBFLAG_XSCALE_CPAR_SHIFT)
Sergey Fedorov3f342b92014-12-11 12:07:48 +00001869#define ARM_TBFLAG_NS(F) \
1870 (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
Peter Maydella1705762011-01-14 20:39:18 +01001871
Greg Bellows9dbbc742015-05-29 11:28:53 +01001872/* Return the exception level to which FP-disabled exceptions should
1873 * be taken, or 0 if FP is enabled.
1874 */
1875static inline int fp_exception_el(CPUARMState *env)
1876{
1877 int fpen;
1878 int cur_el = arm_current_el(env);
1879
1880 /* CPACR and the CPTR registers don't exist before v6, so FP is
1881 * always accessible
1882 */
1883 if (!arm_feature(env, ARM_FEATURE_V6)) {
1884 return 0;
1885 }
1886
1887 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
1888 * 0, 2 : trap EL0 and EL1/PL1 accesses
1889 * 1 : trap only EL0 accesses
1890 * 3 : trap no accesses
1891 */
1892 fpen = extract32(env->cp15.cpacr_el1, 20, 2);
1893 switch (fpen) {
1894 case 0:
1895 case 2:
1896 if (cur_el == 0 || cur_el == 1) {
1897 /* Trap to PL1, which might be EL1 or EL3 */
1898 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
1899 return 3;
1900 }
1901 return 1;
1902 }
1903 if (cur_el == 3 && !is_a64(env)) {
1904 /* Secure PL1 running at EL3 */
1905 return 3;
1906 }
1907 break;
1908 case 1:
1909 if (cur_el == 0) {
1910 return 1;
1911 }
1912 break;
1913 case 3:
1914 break;
1915 }
1916
1917 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
1918 * check because zero bits in the registers mean "don't trap".
1919 */
1920
1921 /* CPTR_EL2 : present in v7VE or v8 */
1922 if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
1923 && !arm_is_secure_below_el3(env)) {
1924 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
1925 return 2;
1926 }
1927
1928 /* CPTR_EL3 : present in v8 */
1929 if (extract32(env->cp15.cptr_el[3], 10, 1)) {
1930 /* Trap all FP ops to EL3 */
1931 return 3;
1932 }
1933
1934 return 0;
1935}
1936
Andreas Färber0ecb72a2012-03-14 01:38:21 +01001937static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
aliguori6b917542008-11-18 19:46:41 +00001938 target_ulong *cs_base, int *flags)
1939{
Alexander Graf3926cc82013-09-03 20:12:09 +01001940 if (is_a64(env)) {
1941 *pc = env->pc;
Peter Maydellc1e37812015-02-05 13:37:23 +00001942 *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
Peter Maydell05ed9a92011-01-14 20:39:19 +01001943 } else {
Alexander Graf3926cc82013-09-03 20:12:09 +01001944 *pc = env->regs[15];
1945 *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
1946 | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
1947 | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
1948 | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
1949 | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
Sergey Fedorov3f342b92014-12-11 12:07:48 +00001950 if (!(access_secure_reg(env))) {
1951 *flags |= ARM_TBFLAG_NS_MASK;
1952 }
Peter Maydell2c7ffc42014-04-15 19:18:40 +01001953 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)
1954 || arm_el_is_aa64(env, 1)) {
Alexander Graf3926cc82013-09-03 20:12:09 +01001955 *flags |= ARM_TBFLAG_VFPEN_MASK;
1956 }
Peter Maydellc0f4af12014-09-29 18:48:48 +01001957 *flags |= (extract32(env->cp15.c15_cpar, 0, 2)
1958 << ARM_TBFLAG_XSCALE_CPAR_SHIFT);
Peter Maydell05ed9a92011-01-14 20:39:19 +01001959 }
Alexander Graf3926cc82013-09-03 20:12:09 +01001960
Benjamin Herrenschmidt97ed5cc2015-08-17 17:34:10 +10001961 *flags |= (cpu_mmu_index(env, false) << ARM_TBFLAG_MMUIDX_SHIFT);
Peter Maydell3cf6a0f2015-05-29 11:28:52 +01001962 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
1963 * states defined in the ARM ARM for software singlestep:
1964 * SS_ACTIVE PSTATE.SS State
1965 * 0 x Inactive (the TB flag for SS is always 0)
1966 * 1 0 Active-pending
1967 * 1 1 Active-not-pending
1968 */
1969 if (arm_singlestep_active(env)) {
1970 *flags |= ARM_TBFLAG_SS_ACTIVE_MASK;
1971 if (is_a64(env)) {
1972 if (env->pstate & PSTATE_SS) {
1973 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
1974 }
1975 } else {
1976 if (env->uncached_cpsr & PSTATE_SS) {
1977 *flags |= ARM_TBFLAG_PSTATE_SS_MASK;
1978 }
1979 }
1980 }
Greg Bellows9dbbc742015-05-29 11:28:53 +01001981 *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
Peter Maydellc1e37812015-02-05 13:37:23 +00001982
Alexander Graf3926cc82013-09-03 20:12:09 +01001983 *cs_base = 0;
aliguori6b917542008-11-18 19:46:41 +00001984}
1985
Paolo Bonzini022c62c2012-12-17 18:19:49 +01001986#include "exec/exec-all.h"
Blue Swirlf081c762011-05-21 07:10:23 +00001987
Rob Herring98128602014-10-24 12:19:13 +01001988enum {
1989 QEMU_PSCI_CONDUIT_DISABLED = 0,
1990 QEMU_PSCI_CONDUIT_SMC = 1,
1991 QEMU_PSCI_CONDUIT_HVC = 2,
1992};
1993
bellard2c0262a2003-09-30 20:34:21 +00001994#endif