bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 1 | /* |
| 2 | * ARM translation |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003 Fabrice Bellard |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5 | * Copyright (c) 2005-2007 CodeSourcery |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 6 | * Copyright (c) 2007 OpenedHand, Ltd. |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 7 | * |
| 8 | * This library is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU Lesser General Public |
| 10 | * License as published by the Free Software Foundation; either |
| 11 | * version 2 of the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This library is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 16 | * Lesser General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU Lesser General Public |
| 19 | * License along with this library; if not, write to the Free Software |
aurel32 | fad6cb1 | 2009-01-04 22:05:52 +0000 | [diff] [blame] | 20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 21 | */ |
| 22 | #include <stdarg.h> |
| 23 | #include <stdlib.h> |
| 24 | #include <stdio.h> |
| 25 | #include <string.h> |
| 26 | #include <inttypes.h> |
| 27 | |
| 28 | #include "cpu.h" |
| 29 | #include "exec-all.h" |
| 30 | #include "disas.h" |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 31 | #include "tcg-op.h" |
blueswir1 | 79383c9 | 2008-08-30 09:51:20 +0000 | [diff] [blame] | 32 | #include "qemu-log.h" |
pbrook | 1497c96 | 2008-03-31 03:45:50 +0000 | [diff] [blame] | 33 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 34 | #include "helpers.h" |
pbrook | 1497c96 | 2008-03-31 03:45:50 +0000 | [diff] [blame] | 35 | #define GEN_HELPER 1 |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 36 | #include "helpers.h" |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 37 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 38 | #define ENABLE_ARCH_5J 0 |
| 39 | #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6) |
| 40 | #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K) |
| 41 | #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2) |
| 42 | #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7) |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 43 | |
pbrook | 8675340 | 2008-10-22 20:35:54 +0000 | [diff] [blame] | 44 | #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0) |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 45 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 46 | /* internal defines */ |
| 47 | typedef struct DisasContext { |
bellard | 0fa85d4 | 2005-01-03 23:43:32 +0000 | [diff] [blame] | 48 | target_ulong pc; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 49 | int is_jmp; |
bellard | e50e6a2 | 2005-04-26 20:36:11 +0000 | [diff] [blame] | 50 | /* Nonzero if this instruction has been conditionally skipped. */ |
| 51 | int condjmp; |
| 52 | /* The label that will be jumped to when the instruction is skipped. */ |
| 53 | int condlabel; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 54 | /* Thumb-2 condtional execution bits. */ |
| 55 | int condexec_mask; |
| 56 | int condexec_cond; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 57 | struct TranslationBlock *tb; |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 58 | int singlestep_enabled; |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 59 | int thumb; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 60 | #if !defined(CONFIG_USER_ONLY) |
| 61 | int user; |
| 62 | #endif |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 63 | } DisasContext; |
| 64 | |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 65 | #if defined(CONFIG_USER_ONLY) |
| 66 | #define IS_USER(s) 1 |
| 67 | #else |
| 68 | #define IS_USER(s) (s->user) |
| 69 | #endif |
| 70 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 71 | /* These instructions trap after executing, so defer them until after the |
| 72 | conditional executions state has been updated. */ |
| 73 | #define DISAS_WFI 4 |
| 74 | #define DISAS_SWI 5 |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 75 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 76 | static TCGv_ptr cpu_env; |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 77 | /* We reuse the same 64-bit temporaries for efficiency. */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 78 | static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 79 | |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 80 | /* FIXME: These should be removed. */ |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 81 | static TCGv cpu_T[2]; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 82 | static TCGv cpu_F0s, cpu_F1s; |
| 83 | static TCGv_i64 cpu_F0d, cpu_F1d; |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 84 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 85 | #define ICOUNT_TEMP cpu_T[0] |
| 86 | #include "gen-icount.h" |
| 87 | |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 88 | /* initialize TCG globals. */ |
| 89 | void arm_translate_init(void) |
| 90 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 91 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 92 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 93 | cpu_T[0] = tcg_global_reg_new_i32(TCG_AREG1, "T0"); |
| 94 | cpu_T[1] = tcg_global_reg_new_i32(TCG_AREG2, "T1"); |
| 95 | |
| 96 | #define GEN_HELPER 2 |
| 97 | #include "helpers.h" |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | /* The code generator doesn't like lots of temporaries, so maintain our own |
| 101 | cache for reuse within a function. */ |
| 102 | #define MAX_TEMPS 8 |
| 103 | static int num_temps; |
| 104 | static TCGv temps[MAX_TEMPS]; |
| 105 | |
| 106 | /* Allocate a temporary variable. */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 107 | static TCGv_i32 new_tmp(void) |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 108 | { |
| 109 | TCGv tmp; |
| 110 | if (num_temps == MAX_TEMPS) |
| 111 | abort(); |
| 112 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 113 | if (GET_TCGV_I32(temps[num_temps])) |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 114 | return temps[num_temps++]; |
| 115 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 116 | tmp = tcg_temp_new_i32(); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 117 | temps[num_temps++] = tmp; |
| 118 | return tmp; |
| 119 | } |
| 120 | |
| 121 | /* Release a temporary variable. */ |
| 122 | static void dead_tmp(TCGv tmp) |
| 123 | { |
| 124 | int i; |
| 125 | num_temps--; |
| 126 | i = num_temps; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 127 | if (TCGV_EQUAL(temps[i], tmp)) |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 128 | return; |
| 129 | |
| 130 | /* Shuffle this temp to the last slot. */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 131 | while (!TCGV_EQUAL(temps[i], tmp)) |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 132 | i--; |
| 133 | while (i < num_temps) { |
| 134 | temps[i] = temps[i + 1]; |
| 135 | i++; |
| 136 | } |
| 137 | temps[i] = tmp; |
| 138 | } |
| 139 | |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 140 | static inline TCGv load_cpu_offset(int offset) |
| 141 | { |
| 142 | TCGv tmp = new_tmp(); |
| 143 | tcg_gen_ld_i32(tmp, cpu_env, offset); |
| 144 | return tmp; |
| 145 | } |
| 146 | |
| 147 | #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name)) |
| 148 | |
| 149 | static inline void store_cpu_offset(TCGv var, int offset) |
| 150 | { |
| 151 | tcg_gen_st_i32(var, cpu_env, offset); |
| 152 | dead_tmp(var); |
| 153 | } |
| 154 | |
| 155 | #define store_cpu_field(var, name) \ |
| 156 | store_cpu_offset(var, offsetof(CPUState, name)) |
| 157 | |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 158 | /* Set a variable to the value of a CPU register. */ |
| 159 | static void load_reg_var(DisasContext *s, TCGv var, int reg) |
| 160 | { |
| 161 | if (reg == 15) { |
| 162 | uint32_t addr; |
| 163 | /* normaly, since we updated PC, we need only to add one insn */ |
| 164 | if (s->thumb) |
| 165 | addr = (long)s->pc + 2; |
| 166 | else |
| 167 | addr = (long)s->pc + 4; |
| 168 | tcg_gen_movi_i32(var, addr); |
| 169 | } else { |
| 170 | tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, regs[reg])); |
| 171 | } |
| 172 | } |
| 173 | |
| 174 | /* Create a new temporary and set it to the value of a CPU register. */ |
| 175 | static inline TCGv load_reg(DisasContext *s, int reg) |
| 176 | { |
| 177 | TCGv tmp = new_tmp(); |
| 178 | load_reg_var(s, tmp, reg); |
| 179 | return tmp; |
| 180 | } |
| 181 | |
| 182 | /* Set a CPU register. The source must be a temporary and will be |
| 183 | marked as dead. */ |
| 184 | static void store_reg(DisasContext *s, int reg, TCGv var) |
| 185 | { |
| 186 | if (reg == 15) { |
| 187 | tcg_gen_andi_i32(var, var, ~1); |
| 188 | s->is_jmp = DISAS_JUMP; |
| 189 | } |
| 190 | tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, regs[reg])); |
| 191 | dead_tmp(var); |
| 192 | } |
| 193 | |
| 194 | |
| 195 | /* Basic operations. */ |
| 196 | #define gen_op_movl_T0_T1() tcg_gen_mov_i32(cpu_T[0], cpu_T[1]) |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 197 | #define gen_op_movl_T0_im(im) tcg_gen_movi_i32(cpu_T[0], im) |
| 198 | #define gen_op_movl_T1_im(im) tcg_gen_movi_i32(cpu_T[1], im) |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 199 | |
| 200 | #define gen_op_addl_T1_im(im) tcg_gen_addi_i32(cpu_T[1], cpu_T[1], im) |
| 201 | #define gen_op_addl_T0_T1() tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_T[1]) |
| 202 | #define gen_op_subl_T0_T1() tcg_gen_sub_i32(cpu_T[0], cpu_T[0], cpu_T[1]) |
| 203 | #define gen_op_rsbl_T0_T1() tcg_gen_sub_i32(cpu_T[0], cpu_T[1], cpu_T[0]) |
| 204 | |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 205 | #define gen_op_addl_T0_T1_cc() gen_helper_add_cc(cpu_T[0], cpu_T[0], cpu_T[1]) |
| 206 | #define gen_op_adcl_T0_T1_cc() gen_helper_adc_cc(cpu_T[0], cpu_T[0], cpu_T[1]) |
| 207 | #define gen_op_subl_T0_T1_cc() gen_helper_sub_cc(cpu_T[0], cpu_T[0], cpu_T[1]) |
| 208 | #define gen_op_sbcl_T0_T1_cc() gen_helper_sbc_cc(cpu_T[0], cpu_T[0], cpu_T[1]) |
| 209 | #define gen_op_rsbl_T0_T1_cc() gen_helper_sub_cc(cpu_T[0], cpu_T[1], cpu_T[0]) |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 210 | |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 211 | #define gen_op_andl_T0_T1() tcg_gen_and_i32(cpu_T[0], cpu_T[0], cpu_T[1]) |
| 212 | #define gen_op_xorl_T0_T1() tcg_gen_xor_i32(cpu_T[0], cpu_T[0], cpu_T[1]) |
| 213 | #define gen_op_orl_T0_T1() tcg_gen_or_i32(cpu_T[0], cpu_T[0], cpu_T[1]) |
| 214 | #define gen_op_notl_T0() tcg_gen_not_i32(cpu_T[0], cpu_T[0]) |
| 215 | #define gen_op_notl_T1() tcg_gen_not_i32(cpu_T[1], cpu_T[1]) |
| 216 | #define gen_op_logic_T0_cc() gen_logic_CC(cpu_T[0]); |
| 217 | #define gen_op_logic_T1_cc() gen_logic_CC(cpu_T[1]); |
| 218 | |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 219 | #define gen_op_shll_T1_im(im) tcg_gen_shli_i32(cpu_T[1], cpu_T[1], im) |
| 220 | #define gen_op_shrl_T1_im(im) tcg_gen_shri_i32(cpu_T[1], cpu_T[1], im) |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 221 | |
| 222 | /* Value extensions. */ |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 223 | #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var) |
| 224 | #define gen_uxth(var) tcg_gen_ext16u_i32(var, var) |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 225 | #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var) |
| 226 | #define gen_sxth(var) tcg_gen_ext16s_i32(var, var) |
| 227 | |
pbrook | 1497c96 | 2008-03-31 03:45:50 +0000 | [diff] [blame] | 228 | #define gen_sxtb16(var) gen_helper_sxtb16(var, var) |
| 229 | #define gen_uxtb16(var) gen_helper_uxtb16(var, var) |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 230 | |
| 231 | #define gen_op_mul_T0_T1() tcg_gen_mul_i32(cpu_T[0], cpu_T[0], cpu_T[1]) |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 232 | |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 233 | #define gen_set_cpsr(var, mask) gen_helper_cpsr_write(var, tcg_const_i32(mask)) |
| 234 | /* Set NZCV flags from the high 4 bits of var. */ |
| 235 | #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV) |
| 236 | |
| 237 | static void gen_exception(int excp) |
| 238 | { |
| 239 | TCGv tmp = new_tmp(); |
| 240 | tcg_gen_movi_i32(tmp, excp); |
| 241 | gen_helper_exception(tmp); |
| 242 | dead_tmp(tmp); |
| 243 | } |
| 244 | |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 245 | static void gen_smul_dual(TCGv a, TCGv b) |
| 246 | { |
| 247 | TCGv tmp1 = new_tmp(); |
| 248 | TCGv tmp2 = new_tmp(); |
balrog | 22478e7 | 2008-07-19 10:12:22 +0000 | [diff] [blame] | 249 | tcg_gen_ext16s_i32(tmp1, a); |
| 250 | tcg_gen_ext16s_i32(tmp2, b); |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 251 | tcg_gen_mul_i32(tmp1, tmp1, tmp2); |
| 252 | dead_tmp(tmp2); |
| 253 | tcg_gen_sari_i32(a, a, 16); |
| 254 | tcg_gen_sari_i32(b, b, 16); |
| 255 | tcg_gen_mul_i32(b, b, a); |
| 256 | tcg_gen_mov_i32(a, tmp1); |
| 257 | dead_tmp(tmp1); |
| 258 | } |
| 259 | |
| 260 | /* Byteswap each halfword. */ |
| 261 | static void gen_rev16(TCGv var) |
| 262 | { |
| 263 | TCGv tmp = new_tmp(); |
| 264 | tcg_gen_shri_i32(tmp, var, 8); |
| 265 | tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff); |
| 266 | tcg_gen_shli_i32(var, var, 8); |
| 267 | tcg_gen_andi_i32(var, var, 0xff00ff00); |
| 268 | tcg_gen_or_i32(var, var, tmp); |
| 269 | dead_tmp(tmp); |
| 270 | } |
| 271 | |
| 272 | /* Byteswap low halfword and sign extend. */ |
| 273 | static void gen_revsh(TCGv var) |
| 274 | { |
| 275 | TCGv tmp = new_tmp(); |
| 276 | tcg_gen_shri_i32(tmp, var, 8); |
| 277 | tcg_gen_andi_i32(tmp, tmp, 0x00ff); |
| 278 | tcg_gen_shli_i32(var, var, 8); |
| 279 | tcg_gen_ext8s_i32(var, var); |
| 280 | tcg_gen_or_i32(var, var, tmp); |
| 281 | dead_tmp(tmp); |
| 282 | } |
| 283 | |
| 284 | /* Unsigned bitfield extract. */ |
| 285 | static void gen_ubfx(TCGv var, int shift, uint32_t mask) |
| 286 | { |
| 287 | if (shift) |
| 288 | tcg_gen_shri_i32(var, var, shift); |
| 289 | tcg_gen_andi_i32(var, var, mask); |
| 290 | } |
| 291 | |
| 292 | /* Signed bitfield extract. */ |
| 293 | static void gen_sbfx(TCGv var, int shift, int width) |
| 294 | { |
| 295 | uint32_t signbit; |
| 296 | |
| 297 | if (shift) |
| 298 | tcg_gen_sari_i32(var, var, shift); |
| 299 | if (shift + width < 32) { |
| 300 | signbit = 1u << (width - 1); |
| 301 | tcg_gen_andi_i32(var, var, (1u << width) - 1); |
| 302 | tcg_gen_xori_i32(var, var, signbit); |
| 303 | tcg_gen_subi_i32(var, var, signbit); |
| 304 | } |
| 305 | } |
| 306 | |
| 307 | /* Bitfield insertion. Insert val into base. Clobbers base and val. */ |
| 308 | static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask) |
| 309 | { |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 310 | tcg_gen_andi_i32(val, val, mask); |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 311 | tcg_gen_shli_i32(val, val, shift); |
| 312 | tcg_gen_andi_i32(base, base, ~(mask << shift)); |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 313 | tcg_gen_or_i32(dest, base, val); |
| 314 | } |
| 315 | |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 316 | /* Round the top 32 bits of a 64-bit value. */ |
| 317 | static void gen_roundqd(TCGv a, TCGv b) |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 318 | { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 319 | tcg_gen_shri_i32(a, a, 31); |
| 320 | tcg_gen_add_i32(a, a, b); |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 321 | } |
| 322 | |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 323 | /* FIXME: Most targets have native widening multiplication. |
| 324 | It would be good to use that instead of a full wide multiply. */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 325 | /* 32x32->64 multiply. Marks inputs as dead. */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 326 | static TCGv_i64 gen_mulu_i64_i32(TCGv a, TCGv b) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 327 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 328 | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
| 329 | TCGv_i64 tmp2 = tcg_temp_new_i64(); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 330 | |
| 331 | tcg_gen_extu_i32_i64(tmp1, a); |
| 332 | dead_tmp(a); |
| 333 | tcg_gen_extu_i32_i64(tmp2, b); |
| 334 | dead_tmp(b); |
| 335 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
| 336 | return tmp1; |
| 337 | } |
| 338 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 339 | static TCGv_i64 gen_muls_i64_i32(TCGv a, TCGv b) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 340 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 341 | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
| 342 | TCGv_i64 tmp2 = tcg_temp_new_i64(); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 343 | |
| 344 | tcg_gen_ext_i32_i64(tmp1, a); |
| 345 | dead_tmp(a); |
| 346 | tcg_gen_ext_i32_i64(tmp2, b); |
| 347 | dead_tmp(b); |
| 348 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
| 349 | return tmp1; |
| 350 | } |
| 351 | |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 352 | /* Unsigned 32x32->64 multiply. */ |
| 353 | static void gen_op_mull_T0_T1(void) |
| 354 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 355 | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
| 356 | TCGv_i64 tmp2 = tcg_temp_new_i64(); |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 357 | |
| 358 | tcg_gen_extu_i32_i64(tmp1, cpu_T[0]); |
| 359 | tcg_gen_extu_i32_i64(tmp2, cpu_T[1]); |
| 360 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
| 361 | tcg_gen_trunc_i64_i32(cpu_T[0], tmp1); |
| 362 | tcg_gen_shri_i64(tmp1, tmp1, 32); |
| 363 | tcg_gen_trunc_i64_i32(cpu_T[1], tmp1); |
| 364 | } |
| 365 | |
| 366 | /* Signed 32x32->64 multiply. */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 367 | static void gen_imull(TCGv a, TCGv b) |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 368 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 369 | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
| 370 | TCGv_i64 tmp2 = tcg_temp_new_i64(); |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 371 | |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 372 | tcg_gen_ext_i32_i64(tmp1, a); |
| 373 | tcg_gen_ext_i32_i64(tmp2, b); |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 374 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 375 | tcg_gen_trunc_i64_i32(a, tmp1); |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 376 | tcg_gen_shri_i64(tmp1, tmp1, 32); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 377 | tcg_gen_trunc_i64_i32(b, tmp1); |
| 378 | } |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 379 | |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 380 | /* Swap low and high halfwords. */ |
| 381 | static void gen_swap_half(TCGv var) |
| 382 | { |
| 383 | TCGv tmp = new_tmp(); |
| 384 | tcg_gen_shri_i32(tmp, var, 16); |
| 385 | tcg_gen_shli_i32(var, var, 16); |
| 386 | tcg_gen_or_i32(var, var, tmp); |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 387 | dead_tmp(tmp); |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 388 | } |
| 389 | |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 390 | /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead. |
| 391 | tmp = (t0 ^ t1) & 0x8000; |
| 392 | t0 &= ~0x8000; |
| 393 | t1 &= ~0x8000; |
| 394 | t0 = (t0 + t1) ^ tmp; |
| 395 | */ |
| 396 | |
| 397 | static void gen_add16(TCGv t0, TCGv t1) |
| 398 | { |
| 399 | TCGv tmp = new_tmp(); |
| 400 | tcg_gen_xor_i32(tmp, t0, t1); |
| 401 | tcg_gen_andi_i32(tmp, tmp, 0x8000); |
| 402 | tcg_gen_andi_i32(t0, t0, ~0x8000); |
| 403 | tcg_gen_andi_i32(t1, t1, ~0x8000); |
| 404 | tcg_gen_add_i32(t0, t0, t1); |
| 405 | tcg_gen_xor_i32(t0, t0, tmp); |
| 406 | dead_tmp(tmp); |
| 407 | dead_tmp(t1); |
| 408 | } |
| 409 | |
pbrook | 9a119ff | 2008-03-31 03:45:35 +0000 | [diff] [blame] | 410 | #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF)) |
| 411 | |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 412 | /* Set CF to the top bit of var. */ |
| 413 | static void gen_set_CF_bit31(TCGv var) |
| 414 | { |
| 415 | TCGv tmp = new_tmp(); |
| 416 | tcg_gen_shri_i32(tmp, var, 31); |
balrog | 4cc633c | 2008-12-07 13:32:09 +0000 | [diff] [blame] | 417 | gen_set_CF(tmp); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 418 | dead_tmp(tmp); |
| 419 | } |
| 420 | |
| 421 | /* Set N and Z flags from var. */ |
| 422 | static inline void gen_logic_CC(TCGv var) |
| 423 | { |
pbrook | 6fbe23d | 2008-04-01 17:19:11 +0000 | [diff] [blame] | 424 | tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF)); |
| 425 | tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF)); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 426 | } |
| 427 | |
| 428 | /* T0 += T1 + CF. */ |
| 429 | static void gen_adc_T0_T1(void) |
| 430 | { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 431 | TCGv tmp; |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 432 | gen_op_addl_T0_T1(); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 433 | tmp = load_cpu_field(CF); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 434 | tcg_gen_add_i32(cpu_T[0], cpu_T[0], tmp); |
| 435 | dead_tmp(tmp); |
| 436 | } |
| 437 | |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 438 | /* dest = T0 + T1 + CF. */ |
| 439 | static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1) |
| 440 | { |
| 441 | TCGv tmp; |
| 442 | tcg_gen_add_i32(dest, t0, t1); |
| 443 | tmp = load_cpu_field(CF); |
| 444 | tcg_gen_add_i32(dest, dest, tmp); |
| 445 | dead_tmp(tmp); |
| 446 | } |
| 447 | |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 448 | /* dest = T0 - T1 + CF - 1. */ |
| 449 | static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1) |
| 450 | { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 451 | TCGv tmp; |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 452 | tcg_gen_sub_i32(dest, t0, t1); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 453 | tmp = load_cpu_field(CF); |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 454 | tcg_gen_add_i32(dest, dest, tmp); |
| 455 | tcg_gen_subi_i32(dest, dest, 1); |
| 456 | dead_tmp(tmp); |
| 457 | } |
| 458 | |
| 459 | #define gen_sbc_T0_T1() gen_sub_carry(cpu_T[0], cpu_T[0], cpu_T[1]) |
| 460 | #define gen_rsc_T0_T1() gen_sub_carry(cpu_T[0], cpu_T[1], cpu_T[0]) |
| 461 | |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 462 | /* T0 &= ~T1. Clobbers T1. */ |
| 463 | /* FIXME: Implement bic natively. */ |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 464 | static inline void tcg_gen_bic_i32(TCGv dest, TCGv t0, TCGv t1) |
| 465 | { |
| 466 | TCGv tmp = new_tmp(); |
| 467 | tcg_gen_not_i32(tmp, t1); |
| 468 | tcg_gen_and_i32(dest, t0, tmp); |
| 469 | dead_tmp(tmp); |
| 470 | } |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 471 | static inline void gen_op_bicl_T0_T1(void) |
| 472 | { |
| 473 | gen_op_notl_T1(); |
| 474 | gen_op_andl_T0_T1(); |
| 475 | } |
| 476 | |
| 477 | /* FIXME: Implement this natively. */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 478 | #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1) |
| 479 | |
| 480 | /* FIXME: Implement this natively. */ |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 481 | static void tcg_gen_rori_i32(TCGv t0, TCGv t1, int i) |
| 482 | { |
| 483 | TCGv tmp; |
| 484 | |
| 485 | if (i == 0) |
| 486 | return; |
| 487 | |
| 488 | tmp = new_tmp(); |
| 489 | tcg_gen_shri_i32(tmp, t1, i); |
| 490 | tcg_gen_shli_i32(t1, t1, 32 - i); |
| 491 | tcg_gen_or_i32(t0, t1, tmp); |
| 492 | dead_tmp(tmp); |
| 493 | } |
| 494 | |
pbrook | 9a119ff | 2008-03-31 03:45:35 +0000 | [diff] [blame] | 495 | static void shifter_out_im(TCGv var, int shift) |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 496 | { |
pbrook | 9a119ff | 2008-03-31 03:45:35 +0000 | [diff] [blame] | 497 | TCGv tmp = new_tmp(); |
| 498 | if (shift == 0) { |
| 499 | tcg_gen_andi_i32(tmp, var, 1); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 500 | } else { |
pbrook | 9a119ff | 2008-03-31 03:45:35 +0000 | [diff] [blame] | 501 | tcg_gen_shri_i32(tmp, var, shift); |
balrog | 4cc633c | 2008-12-07 13:32:09 +0000 | [diff] [blame] | 502 | if (shift != 31) |
pbrook | 9a119ff | 2008-03-31 03:45:35 +0000 | [diff] [blame] | 503 | tcg_gen_andi_i32(tmp, tmp, 1); |
| 504 | } |
| 505 | gen_set_CF(tmp); |
| 506 | dead_tmp(tmp); |
| 507 | } |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 508 | |
pbrook | 9a119ff | 2008-03-31 03:45:35 +0000 | [diff] [blame] | 509 | /* Shift by immediate. Includes special handling for shift == 0. */ |
| 510 | static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags) |
| 511 | { |
| 512 | switch (shiftop) { |
| 513 | case 0: /* LSL */ |
| 514 | if (shift != 0) { |
| 515 | if (flags) |
| 516 | shifter_out_im(var, 32 - shift); |
| 517 | tcg_gen_shli_i32(var, var, shift); |
| 518 | } |
| 519 | break; |
| 520 | case 1: /* LSR */ |
| 521 | if (shift == 0) { |
| 522 | if (flags) { |
| 523 | tcg_gen_shri_i32(var, var, 31); |
| 524 | gen_set_CF(var); |
| 525 | } |
| 526 | tcg_gen_movi_i32(var, 0); |
| 527 | } else { |
| 528 | if (flags) |
| 529 | shifter_out_im(var, shift - 1); |
| 530 | tcg_gen_shri_i32(var, var, shift); |
| 531 | } |
| 532 | break; |
| 533 | case 2: /* ASR */ |
| 534 | if (shift == 0) |
| 535 | shift = 32; |
| 536 | if (flags) |
| 537 | shifter_out_im(var, shift - 1); |
| 538 | if (shift == 32) |
| 539 | shift = 31; |
| 540 | tcg_gen_sari_i32(var, var, shift); |
| 541 | break; |
| 542 | case 3: /* ROR/RRX */ |
| 543 | if (shift != 0) { |
| 544 | if (flags) |
| 545 | shifter_out_im(var, shift - 1); |
| 546 | tcg_gen_rori_i32(var, var, shift); break; |
| 547 | } else { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 548 | TCGv tmp = load_cpu_field(CF); |
pbrook | 9a119ff | 2008-03-31 03:45:35 +0000 | [diff] [blame] | 549 | if (flags) |
| 550 | shifter_out_im(var, 0); |
| 551 | tcg_gen_shri_i32(var, var, 1); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 552 | tcg_gen_shli_i32(tmp, tmp, 31); |
| 553 | tcg_gen_or_i32(var, var, tmp); |
| 554 | dead_tmp(tmp); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 555 | } |
| 556 | } |
| 557 | }; |
| 558 | |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 559 | static inline void gen_arm_shift_reg(TCGv var, int shiftop, |
| 560 | TCGv shift, int flags) |
| 561 | { |
| 562 | if (flags) { |
| 563 | switch (shiftop) { |
| 564 | case 0: gen_helper_shl_cc(var, var, shift); break; |
| 565 | case 1: gen_helper_shr_cc(var, var, shift); break; |
| 566 | case 2: gen_helper_sar_cc(var, var, shift); break; |
| 567 | case 3: gen_helper_ror_cc(var, var, shift); break; |
| 568 | } |
| 569 | } else { |
| 570 | switch (shiftop) { |
| 571 | case 0: gen_helper_shl(var, var, shift); break; |
| 572 | case 1: gen_helper_shr(var, var, shift); break; |
| 573 | case 2: gen_helper_sar(var, var, shift); break; |
| 574 | case 3: gen_helper_ror(var, var, shift); break; |
| 575 | } |
| 576 | } |
| 577 | dead_tmp(shift); |
| 578 | } |
| 579 | |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 580 | #define PAS_OP(pfx) \ |
| 581 | switch (op2) { \ |
| 582 | case 0: gen_pas_helper(glue(pfx,add16)); break; \ |
| 583 | case 1: gen_pas_helper(glue(pfx,addsubx)); break; \ |
| 584 | case 2: gen_pas_helper(glue(pfx,subaddx)); break; \ |
| 585 | case 3: gen_pas_helper(glue(pfx,sub16)); break; \ |
| 586 | case 4: gen_pas_helper(glue(pfx,add8)); break; \ |
| 587 | case 7: gen_pas_helper(glue(pfx,sub8)); break; \ |
| 588 | } |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 589 | static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 590 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 591 | TCGv_ptr tmp; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 592 | |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 593 | switch (op1) { |
| 594 | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) |
| 595 | case 1: |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 596 | tmp = tcg_temp_new_ptr(); |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 597 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
| 598 | PAS_OP(s) |
| 599 | break; |
| 600 | case 5: |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 601 | tmp = tcg_temp_new_ptr(); |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 602 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
| 603 | PAS_OP(u) |
| 604 | break; |
| 605 | #undef gen_pas_helper |
| 606 | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) |
| 607 | case 2: |
| 608 | PAS_OP(q); |
| 609 | break; |
| 610 | case 3: |
| 611 | PAS_OP(sh); |
| 612 | break; |
| 613 | case 6: |
| 614 | PAS_OP(uq); |
| 615 | break; |
| 616 | case 7: |
| 617 | PAS_OP(uh); |
| 618 | break; |
| 619 | #undef gen_pas_helper |
| 620 | } |
| 621 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 622 | #undef PAS_OP |
| 623 | |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 624 | /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */ |
| 625 | #define PAS_OP(pfx) \ |
| 626 | switch (op2) { \ |
| 627 | case 0: gen_pas_helper(glue(pfx,add8)); break; \ |
| 628 | case 1: gen_pas_helper(glue(pfx,add16)); break; \ |
| 629 | case 2: gen_pas_helper(glue(pfx,addsubx)); break; \ |
| 630 | case 4: gen_pas_helper(glue(pfx,sub8)); break; \ |
| 631 | case 5: gen_pas_helper(glue(pfx,sub16)); break; \ |
| 632 | case 6: gen_pas_helper(glue(pfx,subaddx)); break; \ |
| 633 | } |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 634 | static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 635 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 636 | TCGv_ptr tmp; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 637 | |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 638 | switch (op1) { |
| 639 | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) |
| 640 | case 0: |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 641 | tmp = tcg_temp_new_ptr(); |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 642 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
| 643 | PAS_OP(s) |
| 644 | break; |
| 645 | case 4: |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 646 | tmp = tcg_temp_new_ptr(); |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 647 | tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE)); |
| 648 | PAS_OP(u) |
| 649 | break; |
| 650 | #undef gen_pas_helper |
| 651 | #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) |
| 652 | case 1: |
| 653 | PAS_OP(q); |
| 654 | break; |
| 655 | case 2: |
| 656 | PAS_OP(sh); |
| 657 | break; |
| 658 | case 5: |
| 659 | PAS_OP(uq); |
| 660 | break; |
| 661 | case 6: |
| 662 | PAS_OP(uh); |
| 663 | break; |
| 664 | #undef gen_pas_helper |
| 665 | } |
| 666 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 667 | #undef PAS_OP |
| 668 | |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 669 | static void gen_test_cc(int cc, int label) |
| 670 | { |
| 671 | TCGv tmp; |
| 672 | TCGv tmp2; |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 673 | int inv; |
| 674 | |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 675 | switch (cc) { |
| 676 | case 0: /* eq: Z */ |
pbrook | 6fbe23d | 2008-04-01 17:19:11 +0000 | [diff] [blame] | 677 | tmp = load_cpu_field(ZF); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 678 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 679 | break; |
| 680 | case 1: /* ne: !Z */ |
pbrook | 6fbe23d | 2008-04-01 17:19:11 +0000 | [diff] [blame] | 681 | tmp = load_cpu_field(ZF); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 682 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 683 | break; |
| 684 | case 2: /* cs: C */ |
| 685 | tmp = load_cpu_field(CF); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 686 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 687 | break; |
| 688 | case 3: /* cc: !C */ |
| 689 | tmp = load_cpu_field(CF); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 690 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 691 | break; |
| 692 | case 4: /* mi: N */ |
pbrook | 6fbe23d | 2008-04-01 17:19:11 +0000 | [diff] [blame] | 693 | tmp = load_cpu_field(NF); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 694 | tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 695 | break; |
| 696 | case 5: /* pl: !N */ |
pbrook | 6fbe23d | 2008-04-01 17:19:11 +0000 | [diff] [blame] | 697 | tmp = load_cpu_field(NF); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 698 | tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 699 | break; |
| 700 | case 6: /* vs: V */ |
| 701 | tmp = load_cpu_field(VF); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 702 | tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 703 | break; |
| 704 | case 7: /* vc: !V */ |
| 705 | tmp = load_cpu_field(VF); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 706 | tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 707 | break; |
| 708 | case 8: /* hi: C && !Z */ |
| 709 | inv = gen_new_label(); |
| 710 | tmp = load_cpu_field(CF); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 711 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 712 | dead_tmp(tmp); |
pbrook | 6fbe23d | 2008-04-01 17:19:11 +0000 | [diff] [blame] | 713 | tmp = load_cpu_field(ZF); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 714 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 715 | gen_set_label(inv); |
| 716 | break; |
| 717 | case 9: /* ls: !C || Z */ |
| 718 | tmp = load_cpu_field(CF); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 719 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 720 | dead_tmp(tmp); |
pbrook | 6fbe23d | 2008-04-01 17:19:11 +0000 | [diff] [blame] | 721 | tmp = load_cpu_field(ZF); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 722 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 723 | break; |
| 724 | case 10: /* ge: N == V -> N ^ V == 0 */ |
| 725 | tmp = load_cpu_field(VF); |
pbrook | 6fbe23d | 2008-04-01 17:19:11 +0000 | [diff] [blame] | 726 | tmp2 = load_cpu_field(NF); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 727 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
| 728 | dead_tmp(tmp2); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 729 | tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 730 | break; |
| 731 | case 11: /* lt: N != V -> N ^ V != 0 */ |
| 732 | tmp = load_cpu_field(VF); |
pbrook | 6fbe23d | 2008-04-01 17:19:11 +0000 | [diff] [blame] | 733 | tmp2 = load_cpu_field(NF); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 734 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
| 735 | dead_tmp(tmp2); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 736 | tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 737 | break; |
| 738 | case 12: /* gt: !Z && N == V */ |
| 739 | inv = gen_new_label(); |
pbrook | 6fbe23d | 2008-04-01 17:19:11 +0000 | [diff] [blame] | 740 | tmp = load_cpu_field(ZF); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 741 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, inv); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 742 | dead_tmp(tmp); |
| 743 | tmp = load_cpu_field(VF); |
pbrook | 6fbe23d | 2008-04-01 17:19:11 +0000 | [diff] [blame] | 744 | tmp2 = load_cpu_field(NF); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 745 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
| 746 | dead_tmp(tmp2); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 747 | tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 748 | gen_set_label(inv); |
| 749 | break; |
| 750 | case 13: /* le: Z || N != V */ |
pbrook | 6fbe23d | 2008-04-01 17:19:11 +0000 | [diff] [blame] | 751 | tmp = load_cpu_field(ZF); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 752 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 753 | dead_tmp(tmp); |
| 754 | tmp = load_cpu_field(VF); |
pbrook | 6fbe23d | 2008-04-01 17:19:11 +0000 | [diff] [blame] | 755 | tmp2 = load_cpu_field(NF); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 756 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
| 757 | dead_tmp(tmp2); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 758 | tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, label); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 759 | break; |
| 760 | default: |
| 761 | fprintf(stderr, "Bad condition code 0x%x\n", cc); |
| 762 | abort(); |
| 763 | } |
| 764 | dead_tmp(tmp); |
| 765 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 766 | |
blueswir1 | b1d8e52 | 2008-10-26 13:43:07 +0000 | [diff] [blame] | 767 | static const uint8_t table_logic_cc[16] = { |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 768 | 1, /* and */ |
| 769 | 1, /* xor */ |
| 770 | 0, /* sub */ |
| 771 | 0, /* rsb */ |
| 772 | 0, /* add */ |
| 773 | 0, /* adc */ |
| 774 | 0, /* sbc */ |
| 775 | 0, /* rsc */ |
| 776 | 1, /* andl */ |
| 777 | 1, /* xorl */ |
| 778 | 0, /* cmp */ |
| 779 | 0, /* cmn */ |
| 780 | 1, /* orr */ |
| 781 | 1, /* mov */ |
| 782 | 1, /* bic */ |
| 783 | 1, /* mvn */ |
| 784 | }; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 785 | |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 786 | /* Set PC and Thumb state from an immediate address. */ |
| 787 | static inline void gen_bx_im(DisasContext *s, uint32_t addr) |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 788 | { |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 789 | TCGv tmp; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 790 | |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 791 | s->is_jmp = DISAS_UPDATE; |
| 792 | tmp = new_tmp(); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 793 | if (s->thumb != (addr & 1)) { |
| 794 | tcg_gen_movi_i32(tmp, addr & 1); |
| 795 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb)); |
| 796 | } |
| 797 | tcg_gen_movi_i32(tmp, addr & ~1); |
| 798 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, regs[15])); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 799 | dead_tmp(tmp); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 800 | } |
| 801 | |
| 802 | /* Set PC and Thumb state from var. var is marked as dead. */ |
| 803 | static inline void gen_bx(DisasContext *s, TCGv var) |
| 804 | { |
| 805 | TCGv tmp; |
| 806 | |
| 807 | s->is_jmp = DISAS_UPDATE; |
| 808 | tmp = new_tmp(); |
| 809 | tcg_gen_andi_i32(tmp, var, 1); |
| 810 | store_cpu_field(tmp, thumb); |
| 811 | tcg_gen_andi_i32(var, var, ~1); |
| 812 | store_cpu_field(var, regs[15]); |
| 813 | } |
| 814 | |
| 815 | /* TODO: This should be removed. Use gen_bx instead. */ |
| 816 | static inline void gen_bx_T0(DisasContext *s) |
| 817 | { |
| 818 | TCGv tmp = new_tmp(); |
| 819 | tcg_gen_mov_i32(tmp, cpu_T[0]); |
| 820 | gen_bx(s, tmp); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 821 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 822 | |
Juha Riihimäki | 21aeb34 | 2009-05-06 09:16:12 +0300 | [diff] [blame] | 823 | /* Variant of store_reg which uses branch&exchange logic when storing |
| 824 | to r15 in ARM architecture v7 and above. The source must be a temporary |
| 825 | and will be marked as dead. */ |
| 826 | static inline void store_reg_bx(CPUState *env, DisasContext *s, |
| 827 | int reg, TCGv var) |
| 828 | { |
| 829 | if (reg == 15 && ENABLE_ARCH_7) { |
| 830 | gen_bx(s, var); |
| 831 | } else { |
| 832 | store_reg(s, reg, var); |
| 833 | } |
| 834 | } |
| 835 | |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 836 | static inline TCGv gen_ld8s(TCGv addr, int index) |
| 837 | { |
| 838 | TCGv tmp = new_tmp(); |
| 839 | tcg_gen_qemu_ld8s(tmp, addr, index); |
| 840 | return tmp; |
| 841 | } |
| 842 | static inline TCGv gen_ld8u(TCGv addr, int index) |
| 843 | { |
| 844 | TCGv tmp = new_tmp(); |
| 845 | tcg_gen_qemu_ld8u(tmp, addr, index); |
| 846 | return tmp; |
| 847 | } |
| 848 | static inline TCGv gen_ld16s(TCGv addr, int index) |
| 849 | { |
| 850 | TCGv tmp = new_tmp(); |
| 851 | tcg_gen_qemu_ld16s(tmp, addr, index); |
| 852 | return tmp; |
| 853 | } |
| 854 | static inline TCGv gen_ld16u(TCGv addr, int index) |
| 855 | { |
| 856 | TCGv tmp = new_tmp(); |
| 857 | tcg_gen_qemu_ld16u(tmp, addr, index); |
| 858 | return tmp; |
| 859 | } |
| 860 | static inline TCGv gen_ld32(TCGv addr, int index) |
| 861 | { |
| 862 | TCGv tmp = new_tmp(); |
| 863 | tcg_gen_qemu_ld32u(tmp, addr, index); |
| 864 | return tmp; |
| 865 | } |
| 866 | static inline void gen_st8(TCGv val, TCGv addr, int index) |
| 867 | { |
| 868 | tcg_gen_qemu_st8(val, addr, index); |
| 869 | dead_tmp(val); |
| 870 | } |
| 871 | static inline void gen_st16(TCGv val, TCGv addr, int index) |
| 872 | { |
| 873 | tcg_gen_qemu_st16(val, addr, index); |
| 874 | dead_tmp(val); |
| 875 | } |
| 876 | static inline void gen_st32(TCGv val, TCGv addr, int index) |
| 877 | { |
| 878 | tcg_gen_qemu_st32(val, addr, index); |
| 879 | dead_tmp(val); |
| 880 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 881 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 882 | static inline void gen_movl_T0_reg(DisasContext *s, int reg) |
| 883 | { |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 884 | load_reg_var(s, cpu_T[0], reg); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 885 | } |
| 886 | |
| 887 | static inline void gen_movl_T1_reg(DisasContext *s, int reg) |
| 888 | { |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 889 | load_reg_var(s, cpu_T[1], reg); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 890 | } |
| 891 | |
| 892 | static inline void gen_movl_T2_reg(DisasContext *s, int reg) |
| 893 | { |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 894 | load_reg_var(s, cpu_T[2], reg); |
| 895 | } |
| 896 | |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 897 | static inline void gen_set_pc_im(uint32_t val) |
| 898 | { |
| 899 | TCGv tmp = new_tmp(); |
| 900 | tcg_gen_movi_i32(tmp, val); |
| 901 | store_cpu_field(tmp, regs[15]); |
| 902 | } |
| 903 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 904 | static inline void gen_movl_reg_TN(DisasContext *s, int reg, int t) |
| 905 | { |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 906 | TCGv tmp; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 907 | if (reg == 15) { |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 908 | tmp = new_tmp(); |
| 909 | tcg_gen_andi_i32(tmp, cpu_T[t], ~1); |
| 910 | } else { |
| 911 | tmp = cpu_T[t]; |
| 912 | } |
| 913 | tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, regs[reg])); |
| 914 | if (reg == 15) { |
| 915 | dead_tmp(tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 916 | s->is_jmp = DISAS_JUMP; |
| 917 | } |
| 918 | } |
| 919 | |
| 920 | static inline void gen_movl_reg_T0(DisasContext *s, int reg) |
| 921 | { |
| 922 | gen_movl_reg_TN(s, reg, 0); |
| 923 | } |
| 924 | |
| 925 | static inline void gen_movl_reg_T1(DisasContext *s, int reg) |
| 926 | { |
| 927 | gen_movl_reg_TN(s, reg, 1); |
| 928 | } |
| 929 | |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 930 | /* Force a TB lookup after an instruction that changes the CPU state. */ |
| 931 | static inline void gen_lookup_tb(DisasContext *s) |
| 932 | { |
| 933 | gen_op_movl_T0_im(s->pc); |
| 934 | gen_movl_reg_T0(s, 15); |
| 935 | s->is_jmp = DISAS_UPDATE; |
| 936 | } |
| 937 | |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 938 | static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, |
| 939 | TCGv var) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 940 | { |
bellard | 1e8d4ee | 2004-12-08 23:40:14 +0000 | [diff] [blame] | 941 | int val, rm, shift, shiftop; |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 942 | TCGv offset; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 943 | |
| 944 | if (!(insn & (1 << 25))) { |
| 945 | /* immediate */ |
| 946 | val = insn & 0xfff; |
| 947 | if (!(insn & (1 << 23))) |
| 948 | val = -val; |
bellard | 537730b | 2004-02-22 13:40:57 +0000 | [diff] [blame] | 949 | if (val != 0) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 950 | tcg_gen_addi_i32(var, var, val); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 951 | } else { |
| 952 | /* shift/register */ |
| 953 | rm = (insn) & 0xf; |
| 954 | shift = (insn >> 7) & 0x1f; |
bellard | 1e8d4ee | 2004-12-08 23:40:14 +0000 | [diff] [blame] | 955 | shiftop = (insn >> 5) & 3; |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 956 | offset = load_reg(s, rm); |
pbrook | 9a119ff | 2008-03-31 03:45:35 +0000 | [diff] [blame] | 957 | gen_arm_shift_im(offset, shiftop, shift, 0); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 958 | if (!(insn & (1 << 23))) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 959 | tcg_gen_sub_i32(var, var, offset); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 960 | else |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 961 | tcg_gen_add_i32(var, var, offset); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 962 | dead_tmp(offset); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 963 | } |
| 964 | } |
| 965 | |
pbrook | 191f9a9 | 2006-06-14 14:36:07 +0000 | [diff] [blame] | 966 | static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn, |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 967 | int extra, TCGv var) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 968 | { |
| 969 | int val, rm; |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 970 | TCGv offset; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 971 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 972 | if (insn & (1 << 22)) { |
| 973 | /* immediate */ |
| 974 | val = (insn & 0xf) | ((insn >> 4) & 0xf0); |
| 975 | if (!(insn & (1 << 23))) |
| 976 | val = -val; |
pbrook | 18acad9 | 2007-02-14 20:17:03 +0000 | [diff] [blame] | 977 | val += extra; |
bellard | 537730b | 2004-02-22 13:40:57 +0000 | [diff] [blame] | 978 | if (val != 0) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 979 | tcg_gen_addi_i32(var, var, val); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 980 | } else { |
| 981 | /* register */ |
pbrook | 191f9a9 | 2006-06-14 14:36:07 +0000 | [diff] [blame] | 982 | if (extra) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 983 | tcg_gen_addi_i32(var, var, extra); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 984 | rm = (insn) & 0xf; |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 985 | offset = load_reg(s, rm); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 986 | if (!(insn & (1 << 23))) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 987 | tcg_gen_sub_i32(var, var, offset); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 988 | else |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 989 | tcg_gen_add_i32(var, var, offset); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 990 | dead_tmp(offset); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 991 | } |
| 992 | } |
| 993 | |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 994 | #define VFP_OP2(name) \ |
| 995 | static inline void gen_vfp_##name(int dp) \ |
| 996 | { \ |
| 997 | if (dp) \ |
| 998 | gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \ |
| 999 | else \ |
| 1000 | gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \ |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 1001 | } |
| 1002 | |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1003 | VFP_OP2(add) |
| 1004 | VFP_OP2(sub) |
| 1005 | VFP_OP2(mul) |
| 1006 | VFP_OP2(div) |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 1007 | |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1008 | #undef VFP_OP2 |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 1009 | |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1010 | static inline void gen_vfp_abs(int dp) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1011 | { |
| 1012 | if (dp) |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1013 | gen_helper_vfp_absd(cpu_F0d, cpu_F0d); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1014 | else |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1015 | gen_helper_vfp_abss(cpu_F0s, cpu_F0s); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1016 | } |
| 1017 | |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1018 | static inline void gen_vfp_neg(int dp) |
| 1019 | { |
| 1020 | if (dp) |
| 1021 | gen_helper_vfp_negd(cpu_F0d, cpu_F0d); |
| 1022 | else |
| 1023 | gen_helper_vfp_negs(cpu_F0s, cpu_F0s); |
| 1024 | } |
| 1025 | |
| 1026 | static inline void gen_vfp_sqrt(int dp) |
| 1027 | { |
| 1028 | if (dp) |
| 1029 | gen_helper_vfp_sqrtd(cpu_F0d, cpu_F0d, cpu_env); |
| 1030 | else |
| 1031 | gen_helper_vfp_sqrts(cpu_F0s, cpu_F0s, cpu_env); |
| 1032 | } |
| 1033 | |
| 1034 | static inline void gen_vfp_cmp(int dp) |
| 1035 | { |
| 1036 | if (dp) |
| 1037 | gen_helper_vfp_cmpd(cpu_F0d, cpu_F1d, cpu_env); |
| 1038 | else |
| 1039 | gen_helper_vfp_cmps(cpu_F0s, cpu_F1s, cpu_env); |
| 1040 | } |
| 1041 | |
| 1042 | static inline void gen_vfp_cmpe(int dp) |
| 1043 | { |
| 1044 | if (dp) |
| 1045 | gen_helper_vfp_cmped(cpu_F0d, cpu_F1d, cpu_env); |
| 1046 | else |
| 1047 | gen_helper_vfp_cmpes(cpu_F0s, cpu_F1s, cpu_env); |
| 1048 | } |
| 1049 | |
| 1050 | static inline void gen_vfp_F1_ld0(int dp) |
| 1051 | { |
| 1052 | if (dp) |
balrog | 5b340b5 | 2008-04-14 02:19:57 +0000 | [diff] [blame] | 1053 | tcg_gen_movi_i64(cpu_F1d, 0); |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1054 | else |
balrog | 5b340b5 | 2008-04-14 02:19:57 +0000 | [diff] [blame] | 1055 | tcg_gen_movi_i32(cpu_F1s, 0); |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1056 | } |
| 1057 | |
| 1058 | static inline void gen_vfp_uito(int dp) |
| 1059 | { |
| 1060 | if (dp) |
| 1061 | gen_helper_vfp_uitod(cpu_F0d, cpu_F0s, cpu_env); |
| 1062 | else |
| 1063 | gen_helper_vfp_uitos(cpu_F0s, cpu_F0s, cpu_env); |
| 1064 | } |
| 1065 | |
| 1066 | static inline void gen_vfp_sito(int dp) |
| 1067 | { |
| 1068 | if (dp) |
balrog | 66230e0 | 2008-04-20 00:58:01 +0000 | [diff] [blame] | 1069 | gen_helper_vfp_sitod(cpu_F0d, cpu_F0s, cpu_env); |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1070 | else |
balrog | 66230e0 | 2008-04-20 00:58:01 +0000 | [diff] [blame] | 1071 | gen_helper_vfp_sitos(cpu_F0s, cpu_F0s, cpu_env); |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1072 | } |
| 1073 | |
| 1074 | static inline void gen_vfp_toui(int dp) |
| 1075 | { |
| 1076 | if (dp) |
| 1077 | gen_helper_vfp_touid(cpu_F0s, cpu_F0d, cpu_env); |
| 1078 | else |
| 1079 | gen_helper_vfp_touis(cpu_F0s, cpu_F0s, cpu_env); |
| 1080 | } |
| 1081 | |
| 1082 | static inline void gen_vfp_touiz(int dp) |
| 1083 | { |
| 1084 | if (dp) |
| 1085 | gen_helper_vfp_touizd(cpu_F0s, cpu_F0d, cpu_env); |
| 1086 | else |
| 1087 | gen_helper_vfp_touizs(cpu_F0s, cpu_F0s, cpu_env); |
| 1088 | } |
| 1089 | |
| 1090 | static inline void gen_vfp_tosi(int dp) |
| 1091 | { |
| 1092 | if (dp) |
| 1093 | gen_helper_vfp_tosid(cpu_F0s, cpu_F0d, cpu_env); |
| 1094 | else |
| 1095 | gen_helper_vfp_tosis(cpu_F0s, cpu_F0s, cpu_env); |
| 1096 | } |
| 1097 | |
| 1098 | static inline void gen_vfp_tosiz(int dp) |
| 1099 | { |
| 1100 | if (dp) |
| 1101 | gen_helper_vfp_tosizd(cpu_F0s, cpu_F0d, cpu_env); |
| 1102 | else |
| 1103 | gen_helper_vfp_tosizs(cpu_F0s, cpu_F0s, cpu_env); |
| 1104 | } |
| 1105 | |
| 1106 | #define VFP_GEN_FIX(name) \ |
| 1107 | static inline void gen_vfp_##name(int dp, int shift) \ |
| 1108 | { \ |
| 1109 | if (dp) \ |
| 1110 | gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tcg_const_i32(shift), cpu_env);\ |
| 1111 | else \ |
| 1112 | gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tcg_const_i32(shift), cpu_env);\ |
| 1113 | } |
| 1114 | VFP_GEN_FIX(tosh) |
| 1115 | VFP_GEN_FIX(tosl) |
| 1116 | VFP_GEN_FIX(touh) |
| 1117 | VFP_GEN_FIX(toul) |
| 1118 | VFP_GEN_FIX(shto) |
| 1119 | VFP_GEN_FIX(slto) |
| 1120 | VFP_GEN_FIX(uhto) |
| 1121 | VFP_GEN_FIX(ulto) |
| 1122 | #undef VFP_GEN_FIX |
| 1123 | |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 1124 | static inline void gen_vfp_ld(DisasContext *s, int dp) |
| 1125 | { |
| 1126 | if (dp) |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1127 | tcg_gen_qemu_ld64(cpu_F0d, cpu_T[1], IS_USER(s)); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 1128 | else |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1129 | tcg_gen_qemu_ld32u(cpu_F0s, cpu_T[1], IS_USER(s)); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 1130 | } |
| 1131 | |
| 1132 | static inline void gen_vfp_st(DisasContext *s, int dp) |
| 1133 | { |
| 1134 | if (dp) |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1135 | tcg_gen_qemu_st64(cpu_F0d, cpu_T[1], IS_USER(s)); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 1136 | else |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1137 | tcg_gen_qemu_st32(cpu_F0s, cpu_T[1], IS_USER(s)); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 1138 | } |
| 1139 | |
bellard | 8e96005 | 2005-04-07 19:42:46 +0000 | [diff] [blame] | 1140 | static inline long |
| 1141 | vfp_reg_offset (int dp, int reg) |
| 1142 | { |
| 1143 | if (dp) |
| 1144 | return offsetof(CPUARMState, vfp.regs[reg]); |
| 1145 | else if (reg & 1) { |
| 1146 | return offsetof(CPUARMState, vfp.regs[reg >> 1]) |
| 1147 | + offsetof(CPU_DoubleU, l.upper); |
| 1148 | } else { |
| 1149 | return offsetof(CPUARMState, vfp.regs[reg >> 1]) |
| 1150 | + offsetof(CPU_DoubleU, l.lower); |
| 1151 | } |
| 1152 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1153 | |
| 1154 | /* Return the offset of a 32-bit piece of a NEON register. |
| 1155 | zero is the least significant end of the register. */ |
| 1156 | static inline long |
| 1157 | neon_reg_offset (int reg, int n) |
| 1158 | { |
| 1159 | int sreg; |
| 1160 | sreg = reg * 2 + n; |
| 1161 | return vfp_reg_offset(0, sreg); |
| 1162 | } |
| 1163 | |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 1164 | /* FIXME: Remove these. */ |
| 1165 | #define neon_T0 cpu_T[0] |
| 1166 | #define neon_T1 cpu_T[1] |
| 1167 | #define NEON_GET_REG(T, reg, n) \ |
| 1168 | tcg_gen_ld_i32(neon_##T, cpu_env, neon_reg_offset(reg, n)) |
| 1169 | #define NEON_SET_REG(T, reg, n) \ |
| 1170 | tcg_gen_st_i32(neon_##T, cpu_env, neon_reg_offset(reg, n)) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 1171 | |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 1172 | static TCGv neon_load_reg(int reg, int pass) |
| 1173 | { |
| 1174 | TCGv tmp = new_tmp(); |
| 1175 | tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass)); |
| 1176 | return tmp; |
| 1177 | } |
| 1178 | |
| 1179 | static void neon_store_reg(int reg, int pass, TCGv var) |
| 1180 | { |
| 1181 | tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass)); |
| 1182 | dead_tmp(var); |
| 1183 | } |
| 1184 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1185 | static inline void neon_load_reg64(TCGv_i64 var, int reg) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 1186 | { |
| 1187 | tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); |
| 1188 | } |
| 1189 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1190 | static inline void neon_store_reg64(TCGv_i64 var, int reg) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 1191 | { |
| 1192 | tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); |
| 1193 | } |
| 1194 | |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1195 | #define tcg_gen_ld_f32 tcg_gen_ld_i32 |
| 1196 | #define tcg_gen_ld_f64 tcg_gen_ld_i64 |
| 1197 | #define tcg_gen_st_f32 tcg_gen_st_i32 |
| 1198 | #define tcg_gen_st_f64 tcg_gen_st_i64 |
| 1199 | |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 1200 | static inline void gen_mov_F0_vreg(int dp, int reg) |
| 1201 | { |
| 1202 | if (dp) |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1203 | tcg_gen_ld_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg)); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 1204 | else |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1205 | tcg_gen_ld_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg)); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 1206 | } |
| 1207 | |
| 1208 | static inline void gen_mov_F1_vreg(int dp, int reg) |
| 1209 | { |
| 1210 | if (dp) |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1211 | tcg_gen_ld_f64(cpu_F1d, cpu_env, vfp_reg_offset(dp, reg)); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 1212 | else |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1213 | tcg_gen_ld_f32(cpu_F1s, cpu_env, vfp_reg_offset(dp, reg)); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 1214 | } |
| 1215 | |
| 1216 | static inline void gen_mov_vreg_F0(int dp, int reg) |
| 1217 | { |
| 1218 | if (dp) |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1219 | tcg_gen_st_f64(cpu_F0d, cpu_env, vfp_reg_offset(dp, reg)); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 1220 | else |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 1221 | tcg_gen_st_f32(cpu_F0s, cpu_env, vfp_reg_offset(dp, reg)); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 1222 | } |
| 1223 | |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1224 | #define ARM_CP_RW_BIT (1 << 20) |
| 1225 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1226 | static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1227 | { |
| 1228 | tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg])); |
| 1229 | } |
| 1230 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1231 | static inline void iwmmxt_store_reg(TCGv_i64 var, int reg) |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1232 | { |
| 1233 | tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg])); |
| 1234 | } |
| 1235 | |
| 1236 | static inline void gen_op_iwmmxt_movl_wCx_T0(int reg) |
| 1237 | { |
| 1238 | tcg_gen_st_i32(cpu_T[0], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg])); |
| 1239 | } |
| 1240 | |
| 1241 | static inline void gen_op_iwmmxt_movl_T0_wCx(int reg) |
| 1242 | { |
| 1243 | tcg_gen_ld_i32(cpu_T[0], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg])); |
| 1244 | } |
| 1245 | |
| 1246 | static inline void gen_op_iwmmxt_movl_T1_wCx(int reg) |
| 1247 | { |
| 1248 | tcg_gen_ld_i32(cpu_T[1], cpu_env, offsetof(CPUState, iwmmxt.cregs[reg])); |
| 1249 | } |
| 1250 | |
| 1251 | static inline void gen_op_iwmmxt_movq_wRn_M0(int rn) |
| 1252 | { |
| 1253 | iwmmxt_store_reg(cpu_M0, rn); |
| 1254 | } |
| 1255 | |
| 1256 | static inline void gen_op_iwmmxt_movq_M0_wRn(int rn) |
| 1257 | { |
| 1258 | iwmmxt_load_reg(cpu_M0, rn); |
| 1259 | } |
| 1260 | |
| 1261 | static inline void gen_op_iwmmxt_orq_M0_wRn(int rn) |
| 1262 | { |
| 1263 | iwmmxt_load_reg(cpu_V1, rn); |
| 1264 | tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1); |
| 1265 | } |
| 1266 | |
| 1267 | static inline void gen_op_iwmmxt_andq_M0_wRn(int rn) |
| 1268 | { |
| 1269 | iwmmxt_load_reg(cpu_V1, rn); |
| 1270 | tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1); |
| 1271 | } |
| 1272 | |
| 1273 | static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn) |
| 1274 | { |
| 1275 | iwmmxt_load_reg(cpu_V1, rn); |
| 1276 | tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1); |
| 1277 | } |
| 1278 | |
| 1279 | #define IWMMXT_OP(name) \ |
| 1280 | static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ |
| 1281 | { \ |
| 1282 | iwmmxt_load_reg(cpu_V1, rn); \ |
| 1283 | gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \ |
| 1284 | } |
| 1285 | |
| 1286 | #define IWMMXT_OP_ENV(name) \ |
| 1287 | static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ |
| 1288 | { \ |
| 1289 | iwmmxt_load_reg(cpu_V1, rn); \ |
| 1290 | gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \ |
| 1291 | } |
| 1292 | |
| 1293 | #define IWMMXT_OP_ENV_SIZE(name) \ |
| 1294 | IWMMXT_OP_ENV(name##b) \ |
| 1295 | IWMMXT_OP_ENV(name##w) \ |
| 1296 | IWMMXT_OP_ENV(name##l) |
| 1297 | |
| 1298 | #define IWMMXT_OP_ENV1(name) \ |
| 1299 | static inline void gen_op_iwmmxt_##name##_M0(void) \ |
| 1300 | { \ |
| 1301 | gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \ |
| 1302 | } |
| 1303 | |
| 1304 | IWMMXT_OP(maddsq) |
| 1305 | IWMMXT_OP(madduq) |
| 1306 | IWMMXT_OP(sadb) |
| 1307 | IWMMXT_OP(sadw) |
| 1308 | IWMMXT_OP(mulslw) |
| 1309 | IWMMXT_OP(mulshw) |
| 1310 | IWMMXT_OP(mululw) |
| 1311 | IWMMXT_OP(muluhw) |
| 1312 | IWMMXT_OP(macsw) |
| 1313 | IWMMXT_OP(macuw) |
| 1314 | |
| 1315 | IWMMXT_OP_ENV_SIZE(unpackl) |
| 1316 | IWMMXT_OP_ENV_SIZE(unpackh) |
| 1317 | |
| 1318 | IWMMXT_OP_ENV1(unpacklub) |
| 1319 | IWMMXT_OP_ENV1(unpackluw) |
| 1320 | IWMMXT_OP_ENV1(unpacklul) |
| 1321 | IWMMXT_OP_ENV1(unpackhub) |
| 1322 | IWMMXT_OP_ENV1(unpackhuw) |
| 1323 | IWMMXT_OP_ENV1(unpackhul) |
| 1324 | IWMMXT_OP_ENV1(unpacklsb) |
| 1325 | IWMMXT_OP_ENV1(unpacklsw) |
| 1326 | IWMMXT_OP_ENV1(unpacklsl) |
| 1327 | IWMMXT_OP_ENV1(unpackhsb) |
| 1328 | IWMMXT_OP_ENV1(unpackhsw) |
| 1329 | IWMMXT_OP_ENV1(unpackhsl) |
| 1330 | |
| 1331 | IWMMXT_OP_ENV_SIZE(cmpeq) |
| 1332 | IWMMXT_OP_ENV_SIZE(cmpgtu) |
| 1333 | IWMMXT_OP_ENV_SIZE(cmpgts) |
| 1334 | |
| 1335 | IWMMXT_OP_ENV_SIZE(mins) |
| 1336 | IWMMXT_OP_ENV_SIZE(minu) |
| 1337 | IWMMXT_OP_ENV_SIZE(maxs) |
| 1338 | IWMMXT_OP_ENV_SIZE(maxu) |
| 1339 | |
| 1340 | IWMMXT_OP_ENV_SIZE(subn) |
| 1341 | IWMMXT_OP_ENV_SIZE(addn) |
| 1342 | IWMMXT_OP_ENV_SIZE(subu) |
| 1343 | IWMMXT_OP_ENV_SIZE(addu) |
| 1344 | IWMMXT_OP_ENV_SIZE(subs) |
| 1345 | IWMMXT_OP_ENV_SIZE(adds) |
| 1346 | |
| 1347 | IWMMXT_OP_ENV(avgb0) |
| 1348 | IWMMXT_OP_ENV(avgb1) |
| 1349 | IWMMXT_OP_ENV(avgw0) |
| 1350 | IWMMXT_OP_ENV(avgw1) |
| 1351 | |
| 1352 | IWMMXT_OP(msadb) |
| 1353 | |
| 1354 | IWMMXT_OP_ENV(packuw) |
| 1355 | IWMMXT_OP_ENV(packul) |
| 1356 | IWMMXT_OP_ENV(packuq) |
| 1357 | IWMMXT_OP_ENV(packsw) |
| 1358 | IWMMXT_OP_ENV(packsl) |
| 1359 | IWMMXT_OP_ENV(packsq) |
| 1360 | |
| 1361 | static inline void gen_op_iwmmxt_muladdsl_M0_T0_T1(void) |
| 1362 | { |
| 1363 | gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]); |
| 1364 | } |
| 1365 | |
| 1366 | static inline void gen_op_iwmmxt_muladdsw_M0_T0_T1(void) |
| 1367 | { |
| 1368 | gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]); |
| 1369 | } |
| 1370 | |
| 1371 | static inline void gen_op_iwmmxt_muladdswl_M0_T0_T1(void) |
| 1372 | { |
| 1373 | gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1]); |
| 1374 | } |
| 1375 | |
| 1376 | static inline void gen_op_iwmmxt_align_M0_T0_wRn(int rn) |
| 1377 | { |
| 1378 | iwmmxt_load_reg(cpu_V1, rn); |
| 1379 | gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, cpu_T[0]); |
| 1380 | } |
| 1381 | |
| 1382 | static inline void gen_op_iwmmxt_insr_M0_T0_T1(int shift) |
| 1383 | { |
| 1384 | TCGv tmp = tcg_const_i32(shift); |
| 1385 | gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, cpu_T[0], cpu_T[1], tmp); |
| 1386 | } |
| 1387 | |
| 1388 | static inline void gen_op_iwmmxt_extrsb_T0_M0(int shift) |
| 1389 | { |
| 1390 | tcg_gen_shri_i64(cpu_M0, cpu_M0, shift); |
| 1391 | tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0); |
| 1392 | tcg_gen_ext8s_i32(cpu_T[0], cpu_T[0]); |
| 1393 | } |
| 1394 | |
| 1395 | static inline void gen_op_iwmmxt_extrsw_T0_M0(int shift) |
| 1396 | { |
| 1397 | tcg_gen_shri_i64(cpu_M0, cpu_M0, shift); |
| 1398 | tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0); |
| 1399 | tcg_gen_ext16s_i32(cpu_T[0], cpu_T[0]); |
| 1400 | } |
| 1401 | |
| 1402 | static inline void gen_op_iwmmxt_extru_T0_M0(int shift, uint32_t mask) |
| 1403 | { |
| 1404 | tcg_gen_shri_i64(cpu_M0, cpu_M0, shift); |
| 1405 | tcg_gen_trunc_i64_i32(cpu_T[0], cpu_M0); |
| 1406 | if (mask != ~0u) |
| 1407 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], mask); |
| 1408 | } |
| 1409 | |
| 1410 | static void gen_op_iwmmxt_set_mup(void) |
| 1411 | { |
| 1412 | TCGv tmp; |
| 1413 | tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); |
| 1414 | tcg_gen_ori_i32(tmp, tmp, 2); |
| 1415 | store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); |
| 1416 | } |
| 1417 | |
| 1418 | static void gen_op_iwmmxt_set_cup(void) |
| 1419 | { |
| 1420 | TCGv tmp; |
| 1421 | tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); |
| 1422 | tcg_gen_ori_i32(tmp, tmp, 1); |
| 1423 | store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); |
| 1424 | } |
| 1425 | |
| 1426 | static void gen_op_iwmmxt_setpsr_nz(void) |
| 1427 | { |
| 1428 | TCGv tmp = new_tmp(); |
| 1429 | gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0); |
| 1430 | store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]); |
| 1431 | } |
| 1432 | |
| 1433 | static inline void gen_op_iwmmxt_addl_M0_wRn(int rn) |
| 1434 | { |
| 1435 | iwmmxt_load_reg(cpu_V1, rn); |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 1436 | tcg_gen_ext32u_i64(cpu_V1, cpu_V1); |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1437 | tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); |
| 1438 | } |
| 1439 | |
| 1440 | |
| 1441 | static void gen_iwmmxt_movl_T0_T1_wRn(int rn) |
| 1442 | { |
| 1443 | iwmmxt_load_reg(cpu_V0, rn); |
| 1444 | tcg_gen_trunc_i64_i32(cpu_T[0], cpu_V0); |
| 1445 | tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); |
| 1446 | tcg_gen_trunc_i64_i32(cpu_T[1], cpu_V0); |
| 1447 | } |
| 1448 | |
| 1449 | static void gen_iwmmxt_movl_wRn_T0_T1(int rn) |
| 1450 | { |
pbrook | 36aa55d | 2008-09-21 13:48:32 +0000 | [diff] [blame] | 1451 | tcg_gen_concat_i32_i64(cpu_V0, cpu_T[0], cpu_T[1]); |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1452 | iwmmxt_store_reg(cpu_V0, rn); |
| 1453 | } |
| 1454 | |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1455 | static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn) |
| 1456 | { |
| 1457 | int rd; |
| 1458 | uint32_t offset; |
| 1459 | |
| 1460 | rd = (insn >> 16) & 0xf; |
| 1461 | gen_movl_T1_reg(s, rd); |
| 1462 | |
| 1463 | offset = (insn & 0xff) << ((insn >> 7) & 2); |
| 1464 | if (insn & (1 << 24)) { |
| 1465 | /* Pre indexed */ |
| 1466 | if (insn & (1 << 23)) |
| 1467 | gen_op_addl_T1_im(offset); |
| 1468 | else |
| 1469 | gen_op_addl_T1_im(-offset); |
| 1470 | |
| 1471 | if (insn & (1 << 21)) |
| 1472 | gen_movl_reg_T1(s, rd); |
| 1473 | } else if (insn & (1 << 21)) { |
| 1474 | /* Post indexed */ |
| 1475 | if (insn & (1 << 23)) |
| 1476 | gen_op_movl_T0_im(offset); |
| 1477 | else |
| 1478 | gen_op_movl_T0_im(- offset); |
| 1479 | gen_op_addl_T0_T1(); |
| 1480 | gen_movl_reg_T0(s, rd); |
| 1481 | } else if (!(insn & (1 << 23))) |
| 1482 | return 1; |
| 1483 | return 0; |
| 1484 | } |
| 1485 | |
| 1486 | static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask) |
| 1487 | { |
| 1488 | int rd = (insn >> 0) & 0xf; |
| 1489 | |
| 1490 | if (insn & (1 << 8)) |
| 1491 | if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) |
| 1492 | return 1; |
| 1493 | else |
| 1494 | gen_op_iwmmxt_movl_T0_wCx(rd); |
| 1495 | else |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1496 | gen_iwmmxt_movl_T0_T1_wRn(rd); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1497 | |
| 1498 | gen_op_movl_T1_im(mask); |
| 1499 | gen_op_andl_T0_T1(); |
| 1500 | return 0; |
| 1501 | } |
| 1502 | |
| 1503 | /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured |
| 1504 | (ie. an undefined instruction). */ |
| 1505 | static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) |
| 1506 | { |
| 1507 | int rd, wrd; |
| 1508 | int rdhi, rdlo, rd0, rd1, i; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 1509 | TCGv tmp; |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1510 | |
| 1511 | if ((insn & 0x0e000e00) == 0x0c000000) { |
| 1512 | if ((insn & 0x0fe00ff0) == 0x0c400000) { |
| 1513 | wrd = insn & 0xf; |
| 1514 | rdlo = (insn >> 12) & 0xf; |
| 1515 | rdhi = (insn >> 16) & 0xf; |
| 1516 | if (insn & ARM_CP_RW_BIT) { /* TMRRC */ |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1517 | gen_iwmmxt_movl_T0_T1_wRn(wrd); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1518 | gen_movl_reg_T0(s, rdlo); |
| 1519 | gen_movl_reg_T1(s, rdhi); |
| 1520 | } else { /* TMCRR */ |
| 1521 | gen_movl_T0_reg(s, rdlo); |
| 1522 | gen_movl_T1_reg(s, rdhi); |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1523 | gen_iwmmxt_movl_wRn_T0_T1(wrd); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1524 | gen_op_iwmmxt_set_mup(); |
| 1525 | } |
| 1526 | return 0; |
| 1527 | } |
| 1528 | |
| 1529 | wrd = (insn >> 12) & 0xf; |
| 1530 | if (gen_iwmmxt_address(s, insn)) |
| 1531 | return 1; |
| 1532 | if (insn & ARM_CP_RW_BIT) { |
| 1533 | if ((insn >> 28) == 0xf) { /* WLDRW wCx */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 1534 | tmp = gen_ld32(cpu_T[1], IS_USER(s)); |
| 1535 | tcg_gen_mov_i32(cpu_T[0], tmp); |
| 1536 | dead_tmp(tmp); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1537 | gen_op_iwmmxt_movl_wCx_T0(wrd); |
| 1538 | } else { |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1539 | i = 1; |
| 1540 | if (insn & (1 << 8)) { |
| 1541 | if (insn & (1 << 22)) { /* WLDRD */ |
| 1542 | tcg_gen_qemu_ld64(cpu_M0, cpu_T[1], IS_USER(s)); |
| 1543 | i = 0; |
| 1544 | } else { /* WLDRW wRd */ |
| 1545 | tmp = gen_ld32(cpu_T[1], IS_USER(s)); |
| 1546 | } |
| 1547 | } else { |
| 1548 | if (insn & (1 << 22)) { /* WLDRH */ |
| 1549 | tmp = gen_ld16u(cpu_T[1], IS_USER(s)); |
| 1550 | } else { /* WLDRB */ |
| 1551 | tmp = gen_ld8u(cpu_T[1], IS_USER(s)); |
| 1552 | } |
| 1553 | } |
| 1554 | if (i) { |
| 1555 | tcg_gen_extu_i32_i64(cpu_M0, tmp); |
| 1556 | dead_tmp(tmp); |
| 1557 | } |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1558 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1559 | } |
| 1560 | } else { |
| 1561 | if ((insn >> 28) == 0xf) { /* WSTRW wCx */ |
| 1562 | gen_op_iwmmxt_movl_T0_wCx(wrd); |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 1563 | tmp = new_tmp(); |
| 1564 | tcg_gen_mov_i32(tmp, cpu_T[0]); |
| 1565 | gen_st32(tmp, cpu_T[1], IS_USER(s)); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1566 | } else { |
| 1567 | gen_op_iwmmxt_movq_M0_wRn(wrd); |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1568 | tmp = new_tmp(); |
| 1569 | if (insn & (1 << 8)) { |
| 1570 | if (insn & (1 << 22)) { /* WSTRD */ |
| 1571 | dead_tmp(tmp); |
| 1572 | tcg_gen_qemu_st64(cpu_M0, cpu_T[1], IS_USER(s)); |
| 1573 | } else { /* WSTRW wRd */ |
| 1574 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); |
| 1575 | gen_st32(tmp, cpu_T[1], IS_USER(s)); |
| 1576 | } |
| 1577 | } else { |
| 1578 | if (insn & (1 << 22)) { /* WSTRH */ |
| 1579 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); |
| 1580 | gen_st16(tmp, cpu_T[1], IS_USER(s)); |
| 1581 | } else { /* WSTRB */ |
| 1582 | tcg_gen_trunc_i64_i32(tmp, cpu_M0); |
| 1583 | gen_st8(tmp, cpu_T[1], IS_USER(s)); |
| 1584 | } |
| 1585 | } |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1586 | } |
| 1587 | } |
| 1588 | return 0; |
| 1589 | } |
| 1590 | |
| 1591 | if ((insn & 0x0f000000) != 0x0e000000) |
| 1592 | return 1; |
| 1593 | |
| 1594 | switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) { |
| 1595 | case 0x000: /* WOR */ |
| 1596 | wrd = (insn >> 12) & 0xf; |
| 1597 | rd0 = (insn >> 0) & 0xf; |
| 1598 | rd1 = (insn >> 16) & 0xf; |
| 1599 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 1600 | gen_op_iwmmxt_orq_M0_wRn(rd1); |
| 1601 | gen_op_iwmmxt_setpsr_nz(); |
| 1602 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1603 | gen_op_iwmmxt_set_mup(); |
| 1604 | gen_op_iwmmxt_set_cup(); |
| 1605 | break; |
| 1606 | case 0x011: /* TMCR */ |
| 1607 | if (insn & 0xf) |
| 1608 | return 1; |
| 1609 | rd = (insn >> 12) & 0xf; |
| 1610 | wrd = (insn >> 16) & 0xf; |
| 1611 | switch (wrd) { |
| 1612 | case ARM_IWMMXT_wCID: |
| 1613 | case ARM_IWMMXT_wCASF: |
| 1614 | break; |
| 1615 | case ARM_IWMMXT_wCon: |
| 1616 | gen_op_iwmmxt_set_cup(); |
| 1617 | /* Fall through. */ |
| 1618 | case ARM_IWMMXT_wCSSF: |
| 1619 | gen_op_iwmmxt_movl_T0_wCx(wrd); |
| 1620 | gen_movl_T1_reg(s, rd); |
| 1621 | gen_op_bicl_T0_T1(); |
| 1622 | gen_op_iwmmxt_movl_wCx_T0(wrd); |
| 1623 | break; |
| 1624 | case ARM_IWMMXT_wCGR0: |
| 1625 | case ARM_IWMMXT_wCGR1: |
| 1626 | case ARM_IWMMXT_wCGR2: |
| 1627 | case ARM_IWMMXT_wCGR3: |
| 1628 | gen_op_iwmmxt_set_cup(); |
| 1629 | gen_movl_reg_T0(s, rd); |
| 1630 | gen_op_iwmmxt_movl_wCx_T0(wrd); |
| 1631 | break; |
| 1632 | default: |
| 1633 | return 1; |
| 1634 | } |
| 1635 | break; |
| 1636 | case 0x100: /* WXOR */ |
| 1637 | wrd = (insn >> 12) & 0xf; |
| 1638 | rd0 = (insn >> 0) & 0xf; |
| 1639 | rd1 = (insn >> 16) & 0xf; |
| 1640 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 1641 | gen_op_iwmmxt_xorq_M0_wRn(rd1); |
| 1642 | gen_op_iwmmxt_setpsr_nz(); |
| 1643 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1644 | gen_op_iwmmxt_set_mup(); |
| 1645 | gen_op_iwmmxt_set_cup(); |
| 1646 | break; |
| 1647 | case 0x111: /* TMRC */ |
| 1648 | if (insn & 0xf) |
| 1649 | return 1; |
| 1650 | rd = (insn >> 12) & 0xf; |
| 1651 | wrd = (insn >> 16) & 0xf; |
| 1652 | gen_op_iwmmxt_movl_T0_wCx(wrd); |
| 1653 | gen_movl_reg_T0(s, rd); |
| 1654 | break; |
| 1655 | case 0x300: /* WANDN */ |
| 1656 | wrd = (insn >> 12) & 0xf; |
| 1657 | rd0 = (insn >> 0) & 0xf; |
| 1658 | rd1 = (insn >> 16) & 0xf; |
| 1659 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1660 | tcg_gen_neg_i64(cpu_M0, cpu_M0); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1661 | gen_op_iwmmxt_andq_M0_wRn(rd1); |
| 1662 | gen_op_iwmmxt_setpsr_nz(); |
| 1663 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1664 | gen_op_iwmmxt_set_mup(); |
| 1665 | gen_op_iwmmxt_set_cup(); |
| 1666 | break; |
| 1667 | case 0x200: /* WAND */ |
| 1668 | wrd = (insn >> 12) & 0xf; |
| 1669 | rd0 = (insn >> 0) & 0xf; |
| 1670 | rd1 = (insn >> 16) & 0xf; |
| 1671 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 1672 | gen_op_iwmmxt_andq_M0_wRn(rd1); |
| 1673 | gen_op_iwmmxt_setpsr_nz(); |
| 1674 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1675 | gen_op_iwmmxt_set_mup(); |
| 1676 | gen_op_iwmmxt_set_cup(); |
| 1677 | break; |
| 1678 | case 0x810: case 0xa10: /* WMADD */ |
| 1679 | wrd = (insn >> 12) & 0xf; |
| 1680 | rd0 = (insn >> 0) & 0xf; |
| 1681 | rd1 = (insn >> 16) & 0xf; |
| 1682 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 1683 | if (insn & (1 << 21)) |
| 1684 | gen_op_iwmmxt_maddsq_M0_wRn(rd1); |
| 1685 | else |
| 1686 | gen_op_iwmmxt_madduq_M0_wRn(rd1); |
| 1687 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1688 | gen_op_iwmmxt_set_mup(); |
| 1689 | break; |
| 1690 | case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */ |
| 1691 | wrd = (insn >> 12) & 0xf; |
| 1692 | rd0 = (insn >> 16) & 0xf; |
| 1693 | rd1 = (insn >> 0) & 0xf; |
| 1694 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 1695 | switch ((insn >> 22) & 3) { |
| 1696 | case 0: |
| 1697 | gen_op_iwmmxt_unpacklb_M0_wRn(rd1); |
| 1698 | break; |
| 1699 | case 1: |
| 1700 | gen_op_iwmmxt_unpacklw_M0_wRn(rd1); |
| 1701 | break; |
| 1702 | case 2: |
| 1703 | gen_op_iwmmxt_unpackll_M0_wRn(rd1); |
| 1704 | break; |
| 1705 | case 3: |
| 1706 | return 1; |
| 1707 | } |
| 1708 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1709 | gen_op_iwmmxt_set_mup(); |
| 1710 | gen_op_iwmmxt_set_cup(); |
| 1711 | break; |
| 1712 | case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */ |
| 1713 | wrd = (insn >> 12) & 0xf; |
| 1714 | rd0 = (insn >> 16) & 0xf; |
| 1715 | rd1 = (insn >> 0) & 0xf; |
| 1716 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 1717 | switch ((insn >> 22) & 3) { |
| 1718 | case 0: |
| 1719 | gen_op_iwmmxt_unpackhb_M0_wRn(rd1); |
| 1720 | break; |
| 1721 | case 1: |
| 1722 | gen_op_iwmmxt_unpackhw_M0_wRn(rd1); |
| 1723 | break; |
| 1724 | case 2: |
| 1725 | gen_op_iwmmxt_unpackhl_M0_wRn(rd1); |
| 1726 | break; |
| 1727 | case 3: |
| 1728 | return 1; |
| 1729 | } |
| 1730 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1731 | gen_op_iwmmxt_set_mup(); |
| 1732 | gen_op_iwmmxt_set_cup(); |
| 1733 | break; |
| 1734 | case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */ |
| 1735 | wrd = (insn >> 12) & 0xf; |
| 1736 | rd0 = (insn >> 16) & 0xf; |
| 1737 | rd1 = (insn >> 0) & 0xf; |
| 1738 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 1739 | if (insn & (1 << 22)) |
| 1740 | gen_op_iwmmxt_sadw_M0_wRn(rd1); |
| 1741 | else |
| 1742 | gen_op_iwmmxt_sadb_M0_wRn(rd1); |
| 1743 | if (!(insn & (1 << 20))) |
| 1744 | gen_op_iwmmxt_addl_M0_wRn(wrd); |
| 1745 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1746 | gen_op_iwmmxt_set_mup(); |
| 1747 | break; |
| 1748 | case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */ |
| 1749 | wrd = (insn >> 12) & 0xf; |
| 1750 | rd0 = (insn >> 16) & 0xf; |
| 1751 | rd1 = (insn >> 0) & 0xf; |
| 1752 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1753 | if (insn & (1 << 21)) { |
| 1754 | if (insn & (1 << 20)) |
| 1755 | gen_op_iwmmxt_mulshw_M0_wRn(rd1); |
| 1756 | else |
| 1757 | gen_op_iwmmxt_mulslw_M0_wRn(rd1); |
| 1758 | } else { |
| 1759 | if (insn & (1 << 20)) |
| 1760 | gen_op_iwmmxt_muluhw_M0_wRn(rd1); |
| 1761 | else |
| 1762 | gen_op_iwmmxt_mululw_M0_wRn(rd1); |
| 1763 | } |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1764 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1765 | gen_op_iwmmxt_set_mup(); |
| 1766 | break; |
| 1767 | case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */ |
| 1768 | wrd = (insn >> 12) & 0xf; |
| 1769 | rd0 = (insn >> 16) & 0xf; |
| 1770 | rd1 = (insn >> 0) & 0xf; |
| 1771 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 1772 | if (insn & (1 << 21)) |
| 1773 | gen_op_iwmmxt_macsw_M0_wRn(rd1); |
| 1774 | else |
| 1775 | gen_op_iwmmxt_macuw_M0_wRn(rd1); |
| 1776 | if (!(insn & (1 << 20))) { |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1777 | iwmmxt_load_reg(cpu_V1, wrd); |
| 1778 | tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1779 | } |
| 1780 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1781 | gen_op_iwmmxt_set_mup(); |
| 1782 | break; |
| 1783 | case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */ |
| 1784 | wrd = (insn >> 12) & 0xf; |
| 1785 | rd0 = (insn >> 16) & 0xf; |
| 1786 | rd1 = (insn >> 0) & 0xf; |
| 1787 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 1788 | switch ((insn >> 22) & 3) { |
| 1789 | case 0: |
| 1790 | gen_op_iwmmxt_cmpeqb_M0_wRn(rd1); |
| 1791 | break; |
| 1792 | case 1: |
| 1793 | gen_op_iwmmxt_cmpeqw_M0_wRn(rd1); |
| 1794 | break; |
| 1795 | case 2: |
| 1796 | gen_op_iwmmxt_cmpeql_M0_wRn(rd1); |
| 1797 | break; |
| 1798 | case 3: |
| 1799 | return 1; |
| 1800 | } |
| 1801 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1802 | gen_op_iwmmxt_set_mup(); |
| 1803 | gen_op_iwmmxt_set_cup(); |
| 1804 | break; |
| 1805 | case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */ |
| 1806 | wrd = (insn >> 12) & 0xf; |
| 1807 | rd0 = (insn >> 16) & 0xf; |
| 1808 | rd1 = (insn >> 0) & 0xf; |
| 1809 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1810 | if (insn & (1 << 22)) { |
| 1811 | if (insn & (1 << 20)) |
| 1812 | gen_op_iwmmxt_avgw1_M0_wRn(rd1); |
| 1813 | else |
| 1814 | gen_op_iwmmxt_avgw0_M0_wRn(rd1); |
| 1815 | } else { |
| 1816 | if (insn & (1 << 20)) |
| 1817 | gen_op_iwmmxt_avgb1_M0_wRn(rd1); |
| 1818 | else |
| 1819 | gen_op_iwmmxt_avgb0_M0_wRn(rd1); |
| 1820 | } |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1821 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1822 | gen_op_iwmmxt_set_mup(); |
| 1823 | gen_op_iwmmxt_set_cup(); |
| 1824 | break; |
| 1825 | case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */ |
| 1826 | wrd = (insn >> 12) & 0xf; |
| 1827 | rd0 = (insn >> 16) & 0xf; |
| 1828 | rd1 = (insn >> 0) & 0xf; |
| 1829 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 1830 | gen_op_iwmmxt_movl_T0_wCx(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3)); |
| 1831 | gen_op_movl_T1_im(7); |
| 1832 | gen_op_andl_T0_T1(); |
| 1833 | gen_op_iwmmxt_align_M0_T0_wRn(rd1); |
| 1834 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1835 | gen_op_iwmmxt_set_mup(); |
| 1836 | break; |
| 1837 | case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */ |
| 1838 | rd = (insn >> 12) & 0xf; |
| 1839 | wrd = (insn >> 16) & 0xf; |
| 1840 | gen_movl_T0_reg(s, rd); |
| 1841 | gen_op_iwmmxt_movq_M0_wRn(wrd); |
| 1842 | switch ((insn >> 6) & 3) { |
| 1843 | case 0: |
| 1844 | gen_op_movl_T1_im(0xff); |
| 1845 | gen_op_iwmmxt_insr_M0_T0_T1((insn & 7) << 3); |
| 1846 | break; |
| 1847 | case 1: |
| 1848 | gen_op_movl_T1_im(0xffff); |
| 1849 | gen_op_iwmmxt_insr_M0_T0_T1((insn & 3) << 4); |
| 1850 | break; |
| 1851 | case 2: |
| 1852 | gen_op_movl_T1_im(0xffffffff); |
| 1853 | gen_op_iwmmxt_insr_M0_T0_T1((insn & 1) << 5); |
| 1854 | break; |
| 1855 | case 3: |
| 1856 | return 1; |
| 1857 | } |
| 1858 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1859 | gen_op_iwmmxt_set_mup(); |
| 1860 | break; |
| 1861 | case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */ |
| 1862 | rd = (insn >> 12) & 0xf; |
| 1863 | wrd = (insn >> 16) & 0xf; |
| 1864 | if (rd == 15) |
| 1865 | return 1; |
| 1866 | gen_op_iwmmxt_movq_M0_wRn(wrd); |
| 1867 | switch ((insn >> 22) & 3) { |
| 1868 | case 0: |
| 1869 | if (insn & 8) |
| 1870 | gen_op_iwmmxt_extrsb_T0_M0((insn & 7) << 3); |
| 1871 | else { |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1872 | gen_op_iwmmxt_extru_T0_M0((insn & 7) << 3, 0xff); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1873 | } |
| 1874 | break; |
| 1875 | case 1: |
| 1876 | if (insn & 8) |
| 1877 | gen_op_iwmmxt_extrsw_T0_M0((insn & 3) << 4); |
| 1878 | else { |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1879 | gen_op_iwmmxt_extru_T0_M0((insn & 3) << 4, 0xffff); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1880 | } |
| 1881 | break; |
| 1882 | case 2: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1883 | gen_op_iwmmxt_extru_T0_M0((insn & 1) << 5, ~0u); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1884 | break; |
| 1885 | case 3: |
| 1886 | return 1; |
| 1887 | } |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 1888 | gen_movl_reg_T0(s, rd); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1889 | break; |
| 1890 | case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */ |
| 1891 | if ((insn & 0x000ff008) != 0x0003f000) |
| 1892 | return 1; |
| 1893 | gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF); |
| 1894 | switch ((insn >> 22) & 3) { |
| 1895 | case 0: |
| 1896 | gen_op_shrl_T1_im(((insn & 7) << 2) + 0); |
| 1897 | break; |
| 1898 | case 1: |
| 1899 | gen_op_shrl_T1_im(((insn & 3) << 3) + 4); |
| 1900 | break; |
| 1901 | case 2: |
| 1902 | gen_op_shrl_T1_im(((insn & 1) << 4) + 12); |
| 1903 | break; |
| 1904 | case 3: |
| 1905 | return 1; |
| 1906 | } |
| 1907 | gen_op_shll_T1_im(28); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 1908 | gen_set_nzcv(cpu_T[1]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1909 | break; |
| 1910 | case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */ |
| 1911 | rd = (insn >> 12) & 0xf; |
| 1912 | wrd = (insn >> 16) & 0xf; |
| 1913 | gen_movl_T0_reg(s, rd); |
| 1914 | switch ((insn >> 6) & 3) { |
| 1915 | case 0: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1916 | gen_helper_iwmmxt_bcstb(cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1917 | break; |
| 1918 | case 1: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1919 | gen_helper_iwmmxt_bcstw(cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1920 | break; |
| 1921 | case 2: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1922 | gen_helper_iwmmxt_bcstl(cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1923 | break; |
| 1924 | case 3: |
| 1925 | return 1; |
| 1926 | } |
| 1927 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1928 | gen_op_iwmmxt_set_mup(); |
| 1929 | break; |
| 1930 | case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */ |
| 1931 | if ((insn & 0x000ff00f) != 0x0003f000) |
| 1932 | return 1; |
| 1933 | gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF); |
| 1934 | switch ((insn >> 22) & 3) { |
| 1935 | case 0: |
| 1936 | for (i = 0; i < 7; i ++) { |
| 1937 | gen_op_shll_T1_im(4); |
| 1938 | gen_op_andl_T0_T1(); |
| 1939 | } |
| 1940 | break; |
| 1941 | case 1: |
| 1942 | for (i = 0; i < 3; i ++) { |
| 1943 | gen_op_shll_T1_im(8); |
| 1944 | gen_op_andl_T0_T1(); |
| 1945 | } |
| 1946 | break; |
| 1947 | case 2: |
| 1948 | gen_op_shll_T1_im(16); |
| 1949 | gen_op_andl_T0_T1(); |
| 1950 | break; |
| 1951 | case 3: |
| 1952 | return 1; |
| 1953 | } |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 1954 | gen_set_nzcv(cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1955 | break; |
| 1956 | case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */ |
| 1957 | wrd = (insn >> 12) & 0xf; |
| 1958 | rd0 = (insn >> 16) & 0xf; |
| 1959 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 1960 | switch ((insn >> 22) & 3) { |
| 1961 | case 0: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1962 | gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1963 | break; |
| 1964 | case 1: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1965 | gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1966 | break; |
| 1967 | case 2: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 1968 | gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 1969 | break; |
| 1970 | case 3: |
| 1971 | return 1; |
| 1972 | } |
| 1973 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 1974 | gen_op_iwmmxt_set_mup(); |
| 1975 | break; |
| 1976 | case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */ |
| 1977 | if ((insn & 0x000ff00f) != 0x0003f000) |
| 1978 | return 1; |
| 1979 | gen_op_iwmmxt_movl_T1_wCx(ARM_IWMMXT_wCASF); |
| 1980 | switch ((insn >> 22) & 3) { |
| 1981 | case 0: |
| 1982 | for (i = 0; i < 7; i ++) { |
| 1983 | gen_op_shll_T1_im(4); |
| 1984 | gen_op_orl_T0_T1(); |
| 1985 | } |
| 1986 | break; |
| 1987 | case 1: |
| 1988 | for (i = 0; i < 3; i ++) { |
| 1989 | gen_op_shll_T1_im(8); |
| 1990 | gen_op_orl_T0_T1(); |
| 1991 | } |
| 1992 | break; |
| 1993 | case 2: |
| 1994 | gen_op_shll_T1_im(16); |
| 1995 | gen_op_orl_T0_T1(); |
| 1996 | break; |
| 1997 | case 3: |
| 1998 | return 1; |
| 1999 | } |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 2000 | gen_set_nzcv(cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2001 | break; |
| 2002 | case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */ |
| 2003 | rd = (insn >> 12) & 0xf; |
| 2004 | rd0 = (insn >> 16) & 0xf; |
| 2005 | if ((insn & 0xf) != 0) |
| 2006 | return 1; |
| 2007 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2008 | switch ((insn >> 22) & 3) { |
| 2009 | case 0: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2010 | gen_helper_iwmmxt_msbb(cpu_T[0], cpu_M0); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2011 | break; |
| 2012 | case 1: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2013 | gen_helper_iwmmxt_msbw(cpu_T[0], cpu_M0); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2014 | break; |
| 2015 | case 2: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2016 | gen_helper_iwmmxt_msbl(cpu_T[0], cpu_M0); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2017 | break; |
| 2018 | case 3: |
| 2019 | return 1; |
| 2020 | } |
| 2021 | gen_movl_reg_T0(s, rd); |
| 2022 | break; |
| 2023 | case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */ |
| 2024 | case 0x906: case 0xb06: case 0xd06: case 0xf06: |
| 2025 | wrd = (insn >> 12) & 0xf; |
| 2026 | rd0 = (insn >> 16) & 0xf; |
| 2027 | rd1 = (insn >> 0) & 0xf; |
| 2028 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2029 | switch ((insn >> 22) & 3) { |
| 2030 | case 0: |
| 2031 | if (insn & (1 << 21)) |
| 2032 | gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1); |
| 2033 | else |
| 2034 | gen_op_iwmmxt_cmpgtub_M0_wRn(rd1); |
| 2035 | break; |
| 2036 | case 1: |
| 2037 | if (insn & (1 << 21)) |
| 2038 | gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1); |
| 2039 | else |
| 2040 | gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1); |
| 2041 | break; |
| 2042 | case 2: |
| 2043 | if (insn & (1 << 21)) |
| 2044 | gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1); |
| 2045 | else |
| 2046 | gen_op_iwmmxt_cmpgtul_M0_wRn(rd1); |
| 2047 | break; |
| 2048 | case 3: |
| 2049 | return 1; |
| 2050 | } |
| 2051 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2052 | gen_op_iwmmxt_set_mup(); |
| 2053 | gen_op_iwmmxt_set_cup(); |
| 2054 | break; |
| 2055 | case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */ |
| 2056 | case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e: |
| 2057 | wrd = (insn >> 12) & 0xf; |
| 2058 | rd0 = (insn >> 16) & 0xf; |
| 2059 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2060 | switch ((insn >> 22) & 3) { |
| 2061 | case 0: |
| 2062 | if (insn & (1 << 21)) |
| 2063 | gen_op_iwmmxt_unpacklsb_M0(); |
| 2064 | else |
| 2065 | gen_op_iwmmxt_unpacklub_M0(); |
| 2066 | break; |
| 2067 | case 1: |
| 2068 | if (insn & (1 << 21)) |
| 2069 | gen_op_iwmmxt_unpacklsw_M0(); |
| 2070 | else |
| 2071 | gen_op_iwmmxt_unpackluw_M0(); |
| 2072 | break; |
| 2073 | case 2: |
| 2074 | if (insn & (1 << 21)) |
| 2075 | gen_op_iwmmxt_unpacklsl_M0(); |
| 2076 | else |
| 2077 | gen_op_iwmmxt_unpacklul_M0(); |
| 2078 | break; |
| 2079 | case 3: |
| 2080 | return 1; |
| 2081 | } |
| 2082 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2083 | gen_op_iwmmxt_set_mup(); |
| 2084 | gen_op_iwmmxt_set_cup(); |
| 2085 | break; |
| 2086 | case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */ |
| 2087 | case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c: |
| 2088 | wrd = (insn >> 12) & 0xf; |
| 2089 | rd0 = (insn >> 16) & 0xf; |
| 2090 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2091 | switch ((insn >> 22) & 3) { |
| 2092 | case 0: |
| 2093 | if (insn & (1 << 21)) |
| 2094 | gen_op_iwmmxt_unpackhsb_M0(); |
| 2095 | else |
| 2096 | gen_op_iwmmxt_unpackhub_M0(); |
| 2097 | break; |
| 2098 | case 1: |
| 2099 | if (insn & (1 << 21)) |
| 2100 | gen_op_iwmmxt_unpackhsw_M0(); |
| 2101 | else |
| 2102 | gen_op_iwmmxt_unpackhuw_M0(); |
| 2103 | break; |
| 2104 | case 2: |
| 2105 | if (insn & (1 << 21)) |
| 2106 | gen_op_iwmmxt_unpackhsl_M0(); |
| 2107 | else |
| 2108 | gen_op_iwmmxt_unpackhul_M0(); |
| 2109 | break; |
| 2110 | case 3: |
| 2111 | return 1; |
| 2112 | } |
| 2113 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2114 | gen_op_iwmmxt_set_mup(); |
| 2115 | gen_op_iwmmxt_set_cup(); |
| 2116 | break; |
| 2117 | case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */ |
| 2118 | case 0x214: case 0x614: case 0xa14: case 0xe14: |
| 2119 | wrd = (insn >> 12) & 0xf; |
| 2120 | rd0 = (insn >> 16) & 0xf; |
| 2121 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2122 | if (gen_iwmmxt_shift(insn, 0xff)) |
| 2123 | return 1; |
| 2124 | switch ((insn >> 22) & 3) { |
| 2125 | case 0: |
| 2126 | return 1; |
| 2127 | case 1: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2128 | gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2129 | break; |
| 2130 | case 2: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2131 | gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2132 | break; |
| 2133 | case 3: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2134 | gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2135 | break; |
| 2136 | } |
| 2137 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2138 | gen_op_iwmmxt_set_mup(); |
| 2139 | gen_op_iwmmxt_set_cup(); |
| 2140 | break; |
| 2141 | case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */ |
| 2142 | case 0x014: case 0x414: case 0x814: case 0xc14: |
| 2143 | wrd = (insn >> 12) & 0xf; |
| 2144 | rd0 = (insn >> 16) & 0xf; |
| 2145 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2146 | if (gen_iwmmxt_shift(insn, 0xff)) |
| 2147 | return 1; |
| 2148 | switch ((insn >> 22) & 3) { |
| 2149 | case 0: |
| 2150 | return 1; |
| 2151 | case 1: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2152 | gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2153 | break; |
| 2154 | case 2: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2155 | gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2156 | break; |
| 2157 | case 3: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2158 | gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2159 | break; |
| 2160 | } |
| 2161 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2162 | gen_op_iwmmxt_set_mup(); |
| 2163 | gen_op_iwmmxt_set_cup(); |
| 2164 | break; |
| 2165 | case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */ |
| 2166 | case 0x114: case 0x514: case 0x914: case 0xd14: |
| 2167 | wrd = (insn >> 12) & 0xf; |
| 2168 | rd0 = (insn >> 16) & 0xf; |
| 2169 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2170 | if (gen_iwmmxt_shift(insn, 0xff)) |
| 2171 | return 1; |
| 2172 | switch ((insn >> 22) & 3) { |
| 2173 | case 0: |
| 2174 | return 1; |
| 2175 | case 1: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2176 | gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2177 | break; |
| 2178 | case 2: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2179 | gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2180 | break; |
| 2181 | case 3: |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2182 | gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2183 | break; |
| 2184 | } |
| 2185 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2186 | gen_op_iwmmxt_set_mup(); |
| 2187 | gen_op_iwmmxt_set_cup(); |
| 2188 | break; |
| 2189 | case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */ |
| 2190 | case 0x314: case 0x714: case 0xb14: case 0xf14: |
| 2191 | wrd = (insn >> 12) & 0xf; |
| 2192 | rd0 = (insn >> 16) & 0xf; |
| 2193 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2194 | switch ((insn >> 22) & 3) { |
| 2195 | case 0: |
| 2196 | return 1; |
| 2197 | case 1: |
| 2198 | if (gen_iwmmxt_shift(insn, 0xf)) |
| 2199 | return 1; |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2200 | gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2201 | break; |
| 2202 | case 2: |
| 2203 | if (gen_iwmmxt_shift(insn, 0x1f)) |
| 2204 | return 1; |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2205 | gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2206 | break; |
| 2207 | case 3: |
| 2208 | if (gen_iwmmxt_shift(insn, 0x3f)) |
| 2209 | return 1; |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2210 | gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2211 | break; |
| 2212 | } |
| 2213 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2214 | gen_op_iwmmxt_set_mup(); |
| 2215 | gen_op_iwmmxt_set_cup(); |
| 2216 | break; |
| 2217 | case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */ |
| 2218 | case 0x916: case 0xb16: case 0xd16: case 0xf16: |
| 2219 | wrd = (insn >> 12) & 0xf; |
| 2220 | rd0 = (insn >> 16) & 0xf; |
| 2221 | rd1 = (insn >> 0) & 0xf; |
| 2222 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2223 | switch ((insn >> 22) & 3) { |
| 2224 | case 0: |
| 2225 | if (insn & (1 << 21)) |
| 2226 | gen_op_iwmmxt_minsb_M0_wRn(rd1); |
| 2227 | else |
| 2228 | gen_op_iwmmxt_minub_M0_wRn(rd1); |
| 2229 | break; |
| 2230 | case 1: |
| 2231 | if (insn & (1 << 21)) |
| 2232 | gen_op_iwmmxt_minsw_M0_wRn(rd1); |
| 2233 | else |
| 2234 | gen_op_iwmmxt_minuw_M0_wRn(rd1); |
| 2235 | break; |
| 2236 | case 2: |
| 2237 | if (insn & (1 << 21)) |
| 2238 | gen_op_iwmmxt_minsl_M0_wRn(rd1); |
| 2239 | else |
| 2240 | gen_op_iwmmxt_minul_M0_wRn(rd1); |
| 2241 | break; |
| 2242 | case 3: |
| 2243 | return 1; |
| 2244 | } |
| 2245 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2246 | gen_op_iwmmxt_set_mup(); |
| 2247 | break; |
| 2248 | case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */ |
| 2249 | case 0x816: case 0xa16: case 0xc16: case 0xe16: |
| 2250 | wrd = (insn >> 12) & 0xf; |
| 2251 | rd0 = (insn >> 16) & 0xf; |
| 2252 | rd1 = (insn >> 0) & 0xf; |
| 2253 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2254 | switch ((insn >> 22) & 3) { |
| 2255 | case 0: |
| 2256 | if (insn & (1 << 21)) |
| 2257 | gen_op_iwmmxt_maxsb_M0_wRn(rd1); |
| 2258 | else |
| 2259 | gen_op_iwmmxt_maxub_M0_wRn(rd1); |
| 2260 | break; |
| 2261 | case 1: |
| 2262 | if (insn & (1 << 21)) |
| 2263 | gen_op_iwmmxt_maxsw_M0_wRn(rd1); |
| 2264 | else |
| 2265 | gen_op_iwmmxt_maxuw_M0_wRn(rd1); |
| 2266 | break; |
| 2267 | case 2: |
| 2268 | if (insn & (1 << 21)) |
| 2269 | gen_op_iwmmxt_maxsl_M0_wRn(rd1); |
| 2270 | else |
| 2271 | gen_op_iwmmxt_maxul_M0_wRn(rd1); |
| 2272 | break; |
| 2273 | case 3: |
| 2274 | return 1; |
| 2275 | } |
| 2276 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2277 | gen_op_iwmmxt_set_mup(); |
| 2278 | break; |
| 2279 | case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */ |
| 2280 | case 0x402: case 0x502: case 0x602: case 0x702: |
| 2281 | wrd = (insn >> 12) & 0xf; |
| 2282 | rd0 = (insn >> 16) & 0xf; |
| 2283 | rd1 = (insn >> 0) & 0xf; |
| 2284 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2285 | gen_op_movl_T0_im((insn >> 20) & 3); |
| 2286 | gen_op_iwmmxt_align_M0_T0_wRn(rd1); |
| 2287 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2288 | gen_op_iwmmxt_set_mup(); |
| 2289 | break; |
| 2290 | case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */ |
| 2291 | case 0x41a: case 0x51a: case 0x61a: case 0x71a: |
| 2292 | case 0x81a: case 0x91a: case 0xa1a: case 0xb1a: |
| 2293 | case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a: |
| 2294 | wrd = (insn >> 12) & 0xf; |
| 2295 | rd0 = (insn >> 16) & 0xf; |
| 2296 | rd1 = (insn >> 0) & 0xf; |
| 2297 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2298 | switch ((insn >> 20) & 0xf) { |
| 2299 | case 0x0: |
| 2300 | gen_op_iwmmxt_subnb_M0_wRn(rd1); |
| 2301 | break; |
| 2302 | case 0x1: |
| 2303 | gen_op_iwmmxt_subub_M0_wRn(rd1); |
| 2304 | break; |
| 2305 | case 0x3: |
| 2306 | gen_op_iwmmxt_subsb_M0_wRn(rd1); |
| 2307 | break; |
| 2308 | case 0x4: |
| 2309 | gen_op_iwmmxt_subnw_M0_wRn(rd1); |
| 2310 | break; |
| 2311 | case 0x5: |
| 2312 | gen_op_iwmmxt_subuw_M0_wRn(rd1); |
| 2313 | break; |
| 2314 | case 0x7: |
| 2315 | gen_op_iwmmxt_subsw_M0_wRn(rd1); |
| 2316 | break; |
| 2317 | case 0x8: |
| 2318 | gen_op_iwmmxt_subnl_M0_wRn(rd1); |
| 2319 | break; |
| 2320 | case 0x9: |
| 2321 | gen_op_iwmmxt_subul_M0_wRn(rd1); |
| 2322 | break; |
| 2323 | case 0xb: |
| 2324 | gen_op_iwmmxt_subsl_M0_wRn(rd1); |
| 2325 | break; |
| 2326 | default: |
| 2327 | return 1; |
| 2328 | } |
| 2329 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2330 | gen_op_iwmmxt_set_mup(); |
| 2331 | gen_op_iwmmxt_set_cup(); |
| 2332 | break; |
| 2333 | case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */ |
| 2334 | case 0x41e: case 0x51e: case 0x61e: case 0x71e: |
| 2335 | case 0x81e: case 0x91e: case 0xa1e: case 0xb1e: |
| 2336 | case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e: |
| 2337 | wrd = (insn >> 12) & 0xf; |
| 2338 | rd0 = (insn >> 16) & 0xf; |
| 2339 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2340 | gen_op_movl_T0_im(((insn >> 16) & 0xf0) | (insn & 0x0f)); |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2341 | gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, cpu_T[0]); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2342 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2343 | gen_op_iwmmxt_set_mup(); |
| 2344 | gen_op_iwmmxt_set_cup(); |
| 2345 | break; |
| 2346 | case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */ |
| 2347 | case 0x418: case 0x518: case 0x618: case 0x718: |
| 2348 | case 0x818: case 0x918: case 0xa18: case 0xb18: |
| 2349 | case 0xc18: case 0xd18: case 0xe18: case 0xf18: |
| 2350 | wrd = (insn >> 12) & 0xf; |
| 2351 | rd0 = (insn >> 16) & 0xf; |
| 2352 | rd1 = (insn >> 0) & 0xf; |
| 2353 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2354 | switch ((insn >> 20) & 0xf) { |
| 2355 | case 0x0: |
| 2356 | gen_op_iwmmxt_addnb_M0_wRn(rd1); |
| 2357 | break; |
| 2358 | case 0x1: |
| 2359 | gen_op_iwmmxt_addub_M0_wRn(rd1); |
| 2360 | break; |
| 2361 | case 0x3: |
| 2362 | gen_op_iwmmxt_addsb_M0_wRn(rd1); |
| 2363 | break; |
| 2364 | case 0x4: |
| 2365 | gen_op_iwmmxt_addnw_M0_wRn(rd1); |
| 2366 | break; |
| 2367 | case 0x5: |
| 2368 | gen_op_iwmmxt_adduw_M0_wRn(rd1); |
| 2369 | break; |
| 2370 | case 0x7: |
| 2371 | gen_op_iwmmxt_addsw_M0_wRn(rd1); |
| 2372 | break; |
| 2373 | case 0x8: |
| 2374 | gen_op_iwmmxt_addnl_M0_wRn(rd1); |
| 2375 | break; |
| 2376 | case 0x9: |
| 2377 | gen_op_iwmmxt_addul_M0_wRn(rd1); |
| 2378 | break; |
| 2379 | case 0xb: |
| 2380 | gen_op_iwmmxt_addsl_M0_wRn(rd1); |
| 2381 | break; |
| 2382 | default: |
| 2383 | return 1; |
| 2384 | } |
| 2385 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2386 | gen_op_iwmmxt_set_mup(); |
| 2387 | gen_op_iwmmxt_set_cup(); |
| 2388 | break; |
| 2389 | case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */ |
| 2390 | case 0x408: case 0x508: case 0x608: case 0x708: |
| 2391 | case 0x808: case 0x908: case 0xa08: case 0xb08: |
| 2392 | case 0xc08: case 0xd08: case 0xe08: case 0xf08: |
| 2393 | wrd = (insn >> 12) & 0xf; |
| 2394 | rd0 = (insn >> 16) & 0xf; |
| 2395 | rd1 = (insn >> 0) & 0xf; |
| 2396 | gen_op_iwmmxt_movq_M0_wRn(rd0); |
| 2397 | if (!(insn & (1 << 20))) |
| 2398 | return 1; |
| 2399 | switch ((insn >> 22) & 3) { |
| 2400 | case 0: |
| 2401 | return 1; |
| 2402 | case 1: |
| 2403 | if (insn & (1 << 21)) |
| 2404 | gen_op_iwmmxt_packsw_M0_wRn(rd1); |
| 2405 | else |
| 2406 | gen_op_iwmmxt_packuw_M0_wRn(rd1); |
| 2407 | break; |
| 2408 | case 2: |
| 2409 | if (insn & (1 << 21)) |
| 2410 | gen_op_iwmmxt_packsl_M0_wRn(rd1); |
| 2411 | else |
| 2412 | gen_op_iwmmxt_packul_M0_wRn(rd1); |
| 2413 | break; |
| 2414 | case 3: |
| 2415 | if (insn & (1 << 21)) |
| 2416 | gen_op_iwmmxt_packsq_M0_wRn(rd1); |
| 2417 | else |
| 2418 | gen_op_iwmmxt_packuq_M0_wRn(rd1); |
| 2419 | break; |
| 2420 | } |
| 2421 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2422 | gen_op_iwmmxt_set_mup(); |
| 2423 | gen_op_iwmmxt_set_cup(); |
| 2424 | break; |
| 2425 | case 0x201: case 0x203: case 0x205: case 0x207: |
| 2426 | case 0x209: case 0x20b: case 0x20d: case 0x20f: |
| 2427 | case 0x211: case 0x213: case 0x215: case 0x217: |
| 2428 | case 0x219: case 0x21b: case 0x21d: case 0x21f: |
| 2429 | wrd = (insn >> 5) & 0xf; |
| 2430 | rd0 = (insn >> 12) & 0xf; |
| 2431 | rd1 = (insn >> 0) & 0xf; |
| 2432 | if (rd0 == 0xf || rd1 == 0xf) |
| 2433 | return 1; |
| 2434 | gen_op_iwmmxt_movq_M0_wRn(wrd); |
| 2435 | switch ((insn >> 16) & 0xf) { |
| 2436 | case 0x0: /* TMIA */ |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 2437 | gen_movl_T0_reg(s, rd0); |
| 2438 | gen_movl_T1_reg(s, rd1); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2439 | gen_op_iwmmxt_muladdsl_M0_T0_T1(); |
| 2440 | break; |
| 2441 | case 0x8: /* TMIAPH */ |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 2442 | gen_movl_T0_reg(s, rd0); |
| 2443 | gen_movl_T1_reg(s, rd1); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2444 | gen_op_iwmmxt_muladdsw_M0_T0_T1(); |
| 2445 | break; |
| 2446 | case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */ |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 2447 | gen_movl_T1_reg(s, rd0); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2448 | if (insn & (1 << 16)) |
| 2449 | gen_op_shrl_T1_im(16); |
| 2450 | gen_op_movl_T0_T1(); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 2451 | gen_movl_T1_reg(s, rd1); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2452 | if (insn & (1 << 17)) |
| 2453 | gen_op_shrl_T1_im(16); |
| 2454 | gen_op_iwmmxt_muladdswl_M0_T0_T1(); |
| 2455 | break; |
| 2456 | default: |
| 2457 | return 1; |
| 2458 | } |
| 2459 | gen_op_iwmmxt_movq_wRn_M0(wrd); |
| 2460 | gen_op_iwmmxt_set_mup(); |
| 2461 | break; |
| 2462 | default: |
| 2463 | return 1; |
| 2464 | } |
| 2465 | |
| 2466 | return 0; |
| 2467 | } |
| 2468 | |
| 2469 | /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured |
| 2470 | (ie. an undefined instruction). */ |
| 2471 | static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn) |
| 2472 | { |
| 2473 | int acc, rd0, rd1, rdhi, rdlo; |
| 2474 | |
| 2475 | if ((insn & 0x0ff00f10) == 0x0e200010) { |
| 2476 | /* Multiply with Internal Accumulate Format */ |
| 2477 | rd0 = (insn >> 12) & 0xf; |
| 2478 | rd1 = insn & 0xf; |
| 2479 | acc = (insn >> 5) & 7; |
| 2480 | |
| 2481 | if (acc != 0) |
| 2482 | return 1; |
| 2483 | |
| 2484 | switch ((insn >> 16) & 0xf) { |
| 2485 | case 0x0: /* MIA */ |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 2486 | gen_movl_T0_reg(s, rd0); |
| 2487 | gen_movl_T1_reg(s, rd1); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2488 | gen_op_iwmmxt_muladdsl_M0_T0_T1(); |
| 2489 | break; |
| 2490 | case 0x8: /* MIAPH */ |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 2491 | gen_movl_T0_reg(s, rd0); |
| 2492 | gen_movl_T1_reg(s, rd1); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2493 | gen_op_iwmmxt_muladdsw_M0_T0_T1(); |
| 2494 | break; |
| 2495 | case 0xc: /* MIABB */ |
| 2496 | case 0xd: /* MIABT */ |
| 2497 | case 0xe: /* MIATB */ |
| 2498 | case 0xf: /* MIATT */ |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 2499 | gen_movl_T1_reg(s, rd0); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2500 | if (insn & (1 << 16)) |
| 2501 | gen_op_shrl_T1_im(16); |
| 2502 | gen_op_movl_T0_T1(); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 2503 | gen_movl_T1_reg(s, rd1); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2504 | if (insn & (1 << 17)) |
| 2505 | gen_op_shrl_T1_im(16); |
| 2506 | gen_op_iwmmxt_muladdswl_M0_T0_T1(); |
| 2507 | break; |
| 2508 | default: |
| 2509 | return 1; |
| 2510 | } |
| 2511 | |
| 2512 | gen_op_iwmmxt_movq_wRn_M0(acc); |
| 2513 | return 0; |
| 2514 | } |
| 2515 | |
| 2516 | if ((insn & 0x0fe00ff8) == 0x0c400000) { |
| 2517 | /* Internal Accumulator Access Format */ |
| 2518 | rdhi = (insn >> 16) & 0xf; |
| 2519 | rdlo = (insn >> 12) & 0xf; |
| 2520 | acc = insn & 7; |
| 2521 | |
| 2522 | if (acc != 0) |
| 2523 | return 1; |
| 2524 | |
| 2525 | if (insn & ARM_CP_RW_BIT) { /* MRA */ |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2526 | gen_iwmmxt_movl_T0_T1_wRn(acc); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 2527 | gen_movl_reg_T0(s, rdlo); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2528 | gen_op_movl_T0_im((1 << (40 - 32)) - 1); |
| 2529 | gen_op_andl_T0_T1(); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 2530 | gen_movl_reg_T0(s, rdhi); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2531 | } else { /* MAR */ |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 2532 | gen_movl_T0_reg(s, rdlo); |
| 2533 | gen_movl_T1_reg(s, rdhi); |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 2534 | gen_iwmmxt_movl_wRn_T0_T1(acc); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2535 | } |
| 2536 | return 0; |
| 2537 | } |
| 2538 | |
| 2539 | return 1; |
| 2540 | } |
| 2541 | |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 2542 | /* Disassemble system coprocessor instruction. Return nonzero if |
| 2543 | instruction is not defined. */ |
| 2544 | static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn) |
| 2545 | { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 2546 | TCGv tmp; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 2547 | uint32_t rd = (insn >> 12) & 0xf; |
| 2548 | uint32_t cp = (insn >> 8) & 0xf; |
| 2549 | if (IS_USER(s)) { |
| 2550 | return 1; |
| 2551 | } |
| 2552 | |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2553 | if (insn & ARM_CP_RW_BIT) { |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 2554 | if (!env->cp[cp].cp_read) |
| 2555 | return 1; |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 2556 | gen_set_pc_im(s->pc); |
| 2557 | tmp = new_tmp(); |
| 2558 | gen_helper_get_cp(tmp, cpu_env, tcg_const_i32(insn)); |
| 2559 | store_reg(s, rd, tmp); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 2560 | } else { |
| 2561 | if (!env->cp[cp].cp_write) |
| 2562 | return 1; |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 2563 | gen_set_pc_im(s->pc); |
| 2564 | tmp = load_reg(s, rd); |
| 2565 | gen_helper_set_cp(cpu_env, tcg_const_i32(insn), tmp); |
balrog | a60de94 | 2008-06-02 02:29:26 +0000 | [diff] [blame] | 2566 | dead_tmp(tmp); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 2567 | } |
| 2568 | return 0; |
| 2569 | } |
| 2570 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2571 | static int cp15_user_ok(uint32_t insn) |
| 2572 | { |
| 2573 | int cpn = (insn >> 16) & 0xf; |
| 2574 | int cpm = insn & 0xf; |
| 2575 | int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38); |
| 2576 | |
| 2577 | if (cpn == 13 && cpm == 0) { |
| 2578 | /* TLS register. */ |
| 2579 | if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT))) |
| 2580 | return 1; |
| 2581 | } |
| 2582 | if (cpn == 7) { |
| 2583 | /* ISB, DSB, DMB. */ |
| 2584 | if ((cpm == 5 && op == 4) |
| 2585 | || (cpm == 10 && (op == 4 || op == 5))) |
| 2586 | return 1; |
| 2587 | } |
| 2588 | return 0; |
| 2589 | } |
| 2590 | |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 2591 | /* Disassemble system coprocessor (cp15) instruction. Return nonzero if |
| 2592 | instruction is not defined. */ |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 2593 | static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn) |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 2594 | { |
| 2595 | uint32_t rd; |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 2596 | TCGv tmp; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 2597 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2598 | /* M profile cores use memory mapped registers instead of cp15. */ |
| 2599 | if (arm_feature(env, ARM_FEATURE_M)) |
| 2600 | return 1; |
| 2601 | |
| 2602 | if ((insn & (1 << 25)) == 0) { |
| 2603 | if (insn & (1 << 20)) { |
| 2604 | /* mrrc */ |
| 2605 | return 1; |
| 2606 | } |
| 2607 | /* mcrr. Used for block cache operations, so implement as no-op. */ |
| 2608 | return 0; |
| 2609 | } |
| 2610 | if ((insn & (1 << 4)) == 0) { |
| 2611 | /* cdp */ |
| 2612 | return 1; |
| 2613 | } |
| 2614 | if (IS_USER(s) && !cp15_user_ok(insn)) { |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 2615 | return 1; |
| 2616 | } |
bellard | 9332f9d | 2005-11-26 10:46:39 +0000 | [diff] [blame] | 2617 | if ((insn & 0x0fff0fff) == 0x0e070f90 |
| 2618 | || (insn & 0x0fff0fff) == 0x0e070f58) { |
| 2619 | /* Wait for interrupt. */ |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 2620 | gen_set_pc_im(s->pc); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2621 | s->is_jmp = DISAS_WFI; |
bellard | 9332f9d | 2005-11-26 10:46:39 +0000 | [diff] [blame] | 2622 | return 0; |
| 2623 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 2624 | rd = (insn >> 12) & 0xf; |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2625 | if (insn & ARM_CP_RW_BIT) { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 2626 | tmp = new_tmp(); |
| 2627 | gen_helper_get_cp15(tmp, cpu_env, tcg_const_i32(insn)); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 2628 | /* If the destination register is r15 then sets condition codes. */ |
| 2629 | if (rd != 15) |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 2630 | store_reg(s, rd, tmp); |
| 2631 | else |
| 2632 | dead_tmp(tmp); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 2633 | } else { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 2634 | tmp = load_reg(s, rd); |
| 2635 | gen_helper_set_cp15(cpu_env, tcg_const_i32(insn), tmp); |
| 2636 | dead_tmp(tmp); |
balrog | a90b731 | 2007-05-01 01:28:01 +0000 | [diff] [blame] | 2637 | /* Normally we would always end the TB here, but Linux |
| 2638 | * arch/arm/mach-pxa/sleep.S expects two instructions following |
| 2639 | * an MMU enable to execute from cache. Imitate this behaviour. */ |
| 2640 | if (!arm_feature(env, ARM_FEATURE_XSCALE) || |
| 2641 | (insn & 0x0fff0fff) != 0x0e010f10) |
| 2642 | gen_lookup_tb(s); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 2643 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 2644 | return 0; |
| 2645 | } |
| 2646 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2647 | #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n)) |
| 2648 | #define VFP_SREG(insn, bigbit, smallbit) \ |
| 2649 | ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1)) |
| 2650 | #define VFP_DREG(reg, insn, bigbit, smallbit) do { \ |
| 2651 | if (arm_feature(env, ARM_FEATURE_VFP3)) { \ |
| 2652 | reg = (((insn) >> (bigbit)) & 0x0f) \ |
| 2653 | | (((insn) >> ((smallbit) - 4)) & 0x10); \ |
| 2654 | } else { \ |
| 2655 | if (insn & (1 << (smallbit))) \ |
| 2656 | return 1; \ |
| 2657 | reg = ((insn) >> (bigbit)) & 0x0f; \ |
| 2658 | }} while (0) |
| 2659 | |
| 2660 | #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22) |
| 2661 | #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22) |
| 2662 | #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7) |
| 2663 | #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7) |
| 2664 | #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5) |
| 2665 | #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5) |
| 2666 | |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2667 | /* Move between integer and VFP cores. */ |
| 2668 | static TCGv gen_vfp_mrs(void) |
| 2669 | { |
| 2670 | TCGv tmp = new_tmp(); |
| 2671 | tcg_gen_mov_i32(tmp, cpu_F0s); |
| 2672 | return tmp; |
| 2673 | } |
| 2674 | |
| 2675 | static void gen_vfp_msr(TCGv tmp) |
| 2676 | { |
| 2677 | tcg_gen_mov_i32(cpu_F0s, tmp); |
| 2678 | dead_tmp(tmp); |
| 2679 | } |
| 2680 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2681 | static inline int |
| 2682 | vfp_enabled(CPUState * env) |
| 2683 | { |
| 2684 | return ((env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) != 0); |
| 2685 | } |
| 2686 | |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2687 | static void gen_neon_dup_u8(TCGv var, int shift) |
| 2688 | { |
| 2689 | TCGv tmp = new_tmp(); |
| 2690 | if (shift) |
| 2691 | tcg_gen_shri_i32(var, var, shift); |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 2692 | tcg_gen_ext8u_i32(var, var); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2693 | tcg_gen_shli_i32(tmp, var, 8); |
| 2694 | tcg_gen_or_i32(var, var, tmp); |
| 2695 | tcg_gen_shli_i32(tmp, var, 16); |
| 2696 | tcg_gen_or_i32(var, var, tmp); |
| 2697 | dead_tmp(tmp); |
| 2698 | } |
| 2699 | |
| 2700 | static void gen_neon_dup_low16(TCGv var) |
| 2701 | { |
| 2702 | TCGv tmp = new_tmp(); |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 2703 | tcg_gen_ext16u_i32(var, var); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2704 | tcg_gen_shli_i32(tmp, var, 16); |
| 2705 | tcg_gen_or_i32(var, var, tmp); |
| 2706 | dead_tmp(tmp); |
| 2707 | } |
| 2708 | |
| 2709 | static void gen_neon_dup_high16(TCGv var) |
| 2710 | { |
| 2711 | TCGv tmp = new_tmp(); |
| 2712 | tcg_gen_andi_i32(var, var, 0xffff0000); |
| 2713 | tcg_gen_shri_i32(tmp, var, 16); |
| 2714 | tcg_gen_or_i32(var, var, tmp); |
| 2715 | dead_tmp(tmp); |
| 2716 | } |
| 2717 | |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2718 | /* Disassemble a VFP instruction. Returns nonzero if an error occured |
| 2719 | (ie. an undefined instruction). */ |
| 2720 | static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) |
| 2721 | { |
| 2722 | uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask; |
| 2723 | int dp, veclen; |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2724 | TCGv tmp; |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2725 | TCGv tmp2; |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2726 | |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 2727 | if (!arm_feature(env, ARM_FEATURE_VFP)) |
| 2728 | return 1; |
| 2729 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2730 | if (!vfp_enabled(env)) { |
| 2731 | /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */ |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 2732 | if ((insn & 0x0fe00fff) != 0x0ee00a10) |
| 2733 | return 1; |
| 2734 | rn = (insn >> 16) & 0xf; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2735 | if (rn != ARM_VFP_FPSID && rn != ARM_VFP_FPEXC |
| 2736 | && rn != ARM_VFP_MVFR1 && rn != ARM_VFP_MVFR0) |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 2737 | return 1; |
| 2738 | } |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2739 | dp = ((insn & 0xf00) == 0xb00); |
| 2740 | switch ((insn >> 24) & 0xf) { |
| 2741 | case 0xe: |
| 2742 | if (insn & (1 << 4)) { |
| 2743 | /* single register transfer */ |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2744 | rd = (insn >> 12) & 0xf; |
| 2745 | if (dp) { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2746 | int size; |
| 2747 | int pass; |
| 2748 | |
| 2749 | VFP_DREG_N(rn, insn); |
| 2750 | if (insn & 0xf) |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2751 | return 1; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2752 | if (insn & 0x00c00060 |
| 2753 | && !arm_feature(env, ARM_FEATURE_NEON)) |
| 2754 | return 1; |
| 2755 | |
| 2756 | pass = (insn >> 21) & 1; |
| 2757 | if (insn & (1 << 22)) { |
| 2758 | size = 0; |
| 2759 | offset = ((insn >> 5) & 3) * 8; |
| 2760 | } else if (insn & (1 << 5)) { |
| 2761 | size = 1; |
| 2762 | offset = (insn & (1 << 6)) ? 16 : 0; |
| 2763 | } else { |
| 2764 | size = 2; |
| 2765 | offset = 0; |
| 2766 | } |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2767 | if (insn & ARM_CP_RW_BIT) { |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2768 | /* vfp->arm */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2769 | tmp = neon_load_reg(rn, pass); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2770 | switch (size) { |
| 2771 | case 0: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2772 | if (offset) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2773 | tcg_gen_shri_i32(tmp, tmp, offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2774 | if (insn & (1 << 23)) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2775 | gen_uxtb(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2776 | else |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2777 | gen_sxtb(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2778 | break; |
| 2779 | case 1: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2780 | if (insn & (1 << 23)) { |
| 2781 | if (offset) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2782 | tcg_gen_shri_i32(tmp, tmp, 16); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2783 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2784 | gen_uxth(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2785 | } |
| 2786 | } else { |
| 2787 | if (offset) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2788 | tcg_gen_sari_i32(tmp, tmp, 16); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2789 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2790 | gen_sxth(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2791 | } |
| 2792 | } |
| 2793 | break; |
| 2794 | case 2: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2795 | break; |
| 2796 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2797 | store_reg(s, rd, tmp); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2798 | } else { |
| 2799 | /* arm->vfp */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2800 | tmp = load_reg(s, rd); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2801 | if (insn & (1 << 23)) { |
| 2802 | /* VDUP */ |
| 2803 | if (size == 0) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2804 | gen_neon_dup_u8(tmp, 0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2805 | } else if (size == 1) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2806 | gen_neon_dup_low16(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2807 | } |
pbrook | cbbccff | 2009-03-17 12:19:58 +0000 | [diff] [blame] | 2808 | for (n = 0; n <= pass * 2; n++) { |
| 2809 | tmp2 = new_tmp(); |
| 2810 | tcg_gen_mov_i32(tmp2, tmp); |
| 2811 | neon_store_reg(rn, n, tmp2); |
| 2812 | } |
| 2813 | neon_store_reg(rn, n, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2814 | } else { |
| 2815 | /* VMOV */ |
| 2816 | switch (size) { |
| 2817 | case 0: |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2818 | tmp2 = neon_load_reg(rn, pass); |
| 2819 | gen_bfi(tmp, tmp2, tmp, offset, 0xff); |
| 2820 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2821 | break; |
| 2822 | case 1: |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2823 | tmp2 = neon_load_reg(rn, pass); |
| 2824 | gen_bfi(tmp, tmp2, tmp, offset, 0xffff); |
| 2825 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2826 | break; |
| 2827 | case 2: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2828 | break; |
| 2829 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 2830 | neon_store_reg(rn, pass, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2831 | } |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2832 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2833 | } else { /* !dp */ |
| 2834 | if ((insn & 0x6f) != 0x00) |
| 2835 | return 1; |
| 2836 | rn = VFP_SREG_N(insn); |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 2837 | if (insn & ARM_CP_RW_BIT) { |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2838 | /* vfp->arm */ |
| 2839 | if (insn & (1 << 21)) { |
| 2840 | /* system register */ |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 2841 | rn >>= 1; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2842 | |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2843 | switch (rn) { |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 2844 | case ARM_VFP_FPSID: |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2845 | /* VFP2 allows access to FSID from userspace. |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2846 | VFP3 restricts all id registers to privileged |
| 2847 | accesses. */ |
| 2848 | if (IS_USER(s) |
| 2849 | && arm_feature(env, ARM_FEATURE_VFP3)) |
| 2850 | return 1; |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2851 | tmp = load_cpu_field(vfp.xregs[rn]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2852 | break; |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 2853 | case ARM_VFP_FPEXC: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2854 | if (IS_USER(s)) |
| 2855 | return 1; |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2856 | tmp = load_cpu_field(vfp.xregs[rn]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2857 | break; |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 2858 | case ARM_VFP_FPINST: |
| 2859 | case ARM_VFP_FPINST2: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2860 | /* Not present in VFP3. */ |
| 2861 | if (IS_USER(s) |
| 2862 | || arm_feature(env, ARM_FEATURE_VFP3)) |
| 2863 | return 1; |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2864 | tmp = load_cpu_field(vfp.xregs[rn]); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2865 | break; |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 2866 | case ARM_VFP_FPSCR: |
balrog | 601d70b | 2008-04-20 01:03:45 +0000 | [diff] [blame] | 2867 | if (rd == 15) { |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2868 | tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); |
| 2869 | tcg_gen_andi_i32(tmp, tmp, 0xf0000000); |
| 2870 | } else { |
| 2871 | tmp = new_tmp(); |
| 2872 | gen_helper_vfp_get_fpscr(tmp, cpu_env); |
| 2873 | } |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2874 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2875 | case ARM_VFP_MVFR0: |
| 2876 | case ARM_VFP_MVFR1: |
| 2877 | if (IS_USER(s) |
| 2878 | || !arm_feature(env, ARM_FEATURE_VFP3)) |
| 2879 | return 1; |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2880 | tmp = load_cpu_field(vfp.xregs[rn]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2881 | break; |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2882 | default: |
| 2883 | return 1; |
| 2884 | } |
| 2885 | } else { |
| 2886 | gen_mov_F0_vreg(0, rn); |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2887 | tmp = gen_vfp_mrs(); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2888 | } |
| 2889 | if (rd == 15) { |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 2890 | /* Set the 4 flag bits in the CPSR. */ |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2891 | gen_set_nzcv(tmp); |
| 2892 | dead_tmp(tmp); |
| 2893 | } else { |
| 2894 | store_reg(s, rd, tmp); |
| 2895 | } |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2896 | } else { |
| 2897 | /* arm->vfp */ |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2898 | tmp = load_reg(s, rd); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2899 | if (insn & (1 << 21)) { |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 2900 | rn >>= 1; |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2901 | /* system register */ |
| 2902 | switch (rn) { |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 2903 | case ARM_VFP_FPSID: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2904 | case ARM_VFP_MVFR0: |
| 2905 | case ARM_VFP_MVFR1: |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2906 | /* Writes are ignored. */ |
| 2907 | break; |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 2908 | case ARM_VFP_FPSCR: |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2909 | gen_helper_vfp_set_fpscr(cpu_env, tmp); |
| 2910 | dead_tmp(tmp); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 2911 | gen_lookup_tb(s); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2912 | break; |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 2913 | case ARM_VFP_FPEXC: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2914 | if (IS_USER(s)) |
| 2915 | return 1; |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2916 | store_cpu_field(tmp, vfp.xregs[rn]); |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 2917 | gen_lookup_tb(s); |
| 2918 | break; |
| 2919 | case ARM_VFP_FPINST: |
| 2920 | case ARM_VFP_FPINST2: |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2921 | store_cpu_field(tmp, vfp.xregs[rn]); |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 2922 | break; |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2923 | default: |
| 2924 | return 1; |
| 2925 | } |
| 2926 | } else { |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 2927 | gen_vfp_msr(tmp); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2928 | gen_mov_vreg_F0(0, rn); |
| 2929 | } |
| 2930 | } |
| 2931 | } |
| 2932 | } else { |
| 2933 | /* data processing */ |
| 2934 | /* The opcode is in bits 23, 21, 20 and 6. */ |
| 2935 | op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1); |
| 2936 | if (dp) { |
| 2937 | if (op == 15) { |
| 2938 | /* rn is opcode */ |
| 2939 | rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1); |
| 2940 | } else { |
| 2941 | /* rn is register number */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2942 | VFP_DREG_N(rn, insn); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2943 | } |
| 2944 | |
| 2945 | if (op == 15 && (rn == 15 || rn > 17)) { |
| 2946 | /* Integer or single precision destination. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2947 | rd = VFP_SREG_D(insn); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2948 | } else { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2949 | VFP_DREG_D(rd, insn); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2950 | } |
| 2951 | |
| 2952 | if (op == 15 && (rn == 16 || rn == 17)) { |
| 2953 | /* Integer source. */ |
| 2954 | rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1); |
| 2955 | } else { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2956 | VFP_DREG_M(rm, insn); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2957 | } |
| 2958 | } else { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2959 | rn = VFP_SREG_N(insn); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2960 | if (op == 15 && rn == 15) { |
| 2961 | /* Double precision destination. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 2962 | VFP_DREG_D(rd, insn); |
| 2963 | } else { |
| 2964 | rd = VFP_SREG_D(insn); |
| 2965 | } |
| 2966 | rm = VFP_SREG_M(insn); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2967 | } |
| 2968 | |
| 2969 | veclen = env->vfp.vec_len; |
| 2970 | if (op == 15 && rn > 3) |
| 2971 | veclen = 0; |
| 2972 | |
| 2973 | /* Shut up compiler warnings. */ |
| 2974 | delta_m = 0; |
| 2975 | delta_d = 0; |
| 2976 | bank_mask = 0; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 2977 | |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 2978 | if (veclen > 0) { |
| 2979 | if (dp) |
| 2980 | bank_mask = 0xc; |
| 2981 | else |
| 2982 | bank_mask = 0x18; |
| 2983 | |
| 2984 | /* Figure out what type of vector operation this is. */ |
| 2985 | if ((rd & bank_mask) == 0) { |
| 2986 | /* scalar */ |
| 2987 | veclen = 0; |
| 2988 | } else { |
| 2989 | if (dp) |
| 2990 | delta_d = (env->vfp.vec_stride >> 1) + 1; |
| 2991 | else |
| 2992 | delta_d = env->vfp.vec_stride + 1; |
| 2993 | |
| 2994 | if ((rm & bank_mask) == 0) { |
| 2995 | /* mixed scalar/vector */ |
| 2996 | delta_m = 0; |
| 2997 | } else { |
| 2998 | /* vector */ |
| 2999 | delta_m = delta_d; |
| 3000 | } |
| 3001 | } |
| 3002 | } |
| 3003 | |
| 3004 | /* Load the initial operands. */ |
| 3005 | if (op == 15) { |
| 3006 | switch (rn) { |
| 3007 | case 16: |
| 3008 | case 17: |
| 3009 | /* Integer source */ |
| 3010 | gen_mov_F0_vreg(0, rm); |
| 3011 | break; |
| 3012 | case 8: |
| 3013 | case 9: |
| 3014 | /* Compare */ |
| 3015 | gen_mov_F0_vreg(dp, rd); |
| 3016 | gen_mov_F1_vreg(dp, rm); |
| 3017 | break; |
| 3018 | case 10: |
| 3019 | case 11: |
| 3020 | /* Compare with zero */ |
| 3021 | gen_mov_F0_vreg(dp, rd); |
| 3022 | gen_vfp_F1_ld0(dp); |
| 3023 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3024 | case 20: |
| 3025 | case 21: |
| 3026 | case 22: |
| 3027 | case 23: |
pbrook | 644ad80 | 2008-12-19 13:02:08 +0000 | [diff] [blame] | 3028 | case 28: |
| 3029 | case 29: |
| 3030 | case 30: |
| 3031 | case 31: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3032 | /* Source and destination the same. */ |
| 3033 | gen_mov_F0_vreg(dp, rd); |
| 3034 | break; |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3035 | default: |
| 3036 | /* One source operand. */ |
| 3037 | gen_mov_F0_vreg(dp, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3038 | break; |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3039 | } |
| 3040 | } else { |
| 3041 | /* Two source operands. */ |
| 3042 | gen_mov_F0_vreg(dp, rn); |
| 3043 | gen_mov_F1_vreg(dp, rm); |
| 3044 | } |
| 3045 | |
| 3046 | for (;;) { |
| 3047 | /* Perform the calculation. */ |
| 3048 | switch (op) { |
| 3049 | case 0: /* mac: fd + (fn * fm) */ |
| 3050 | gen_vfp_mul(dp); |
| 3051 | gen_mov_F1_vreg(dp, rd); |
| 3052 | gen_vfp_add(dp); |
| 3053 | break; |
| 3054 | case 1: /* nmac: fd - (fn * fm) */ |
| 3055 | gen_vfp_mul(dp); |
| 3056 | gen_vfp_neg(dp); |
| 3057 | gen_mov_F1_vreg(dp, rd); |
| 3058 | gen_vfp_add(dp); |
| 3059 | break; |
| 3060 | case 2: /* msc: -fd + (fn * fm) */ |
| 3061 | gen_vfp_mul(dp); |
| 3062 | gen_mov_F1_vreg(dp, rd); |
| 3063 | gen_vfp_sub(dp); |
| 3064 | break; |
| 3065 | case 3: /* nmsc: -fd - (fn * fm) */ |
| 3066 | gen_vfp_mul(dp); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3067 | gen_vfp_neg(dp); |
pbrook | c9fb531 | 2008-11-03 19:09:29 +0000 | [diff] [blame] | 3068 | gen_mov_F1_vreg(dp, rd); |
| 3069 | gen_vfp_sub(dp); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3070 | break; |
| 3071 | case 4: /* mul: fn * fm */ |
| 3072 | gen_vfp_mul(dp); |
| 3073 | break; |
| 3074 | case 5: /* nmul: -(fn * fm) */ |
| 3075 | gen_vfp_mul(dp); |
| 3076 | gen_vfp_neg(dp); |
| 3077 | break; |
| 3078 | case 6: /* add: fn + fm */ |
| 3079 | gen_vfp_add(dp); |
| 3080 | break; |
| 3081 | case 7: /* sub: fn - fm */ |
| 3082 | gen_vfp_sub(dp); |
| 3083 | break; |
| 3084 | case 8: /* div: fn / fm */ |
| 3085 | gen_vfp_div(dp); |
| 3086 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3087 | case 14: /* fconst */ |
| 3088 | if (!arm_feature(env, ARM_FEATURE_VFP3)) |
| 3089 | return 1; |
| 3090 | |
| 3091 | n = (insn << 12) & 0x80000000; |
| 3092 | i = ((insn >> 12) & 0x70) | (insn & 0xf); |
| 3093 | if (dp) { |
| 3094 | if (i & 0x40) |
| 3095 | i |= 0x3f80; |
| 3096 | else |
| 3097 | i |= 0x4000; |
| 3098 | n |= i << 16; |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 3099 | tcg_gen_movi_i64(cpu_F0d, ((uint64_t)n) << 32); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3100 | } else { |
| 3101 | if (i & 0x40) |
| 3102 | i |= 0x780; |
| 3103 | else |
| 3104 | i |= 0x800; |
| 3105 | n |= i << 19; |
balrog | 5b340b5 | 2008-04-14 02:19:57 +0000 | [diff] [blame] | 3106 | tcg_gen_movi_i32(cpu_F0s, n); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3107 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3108 | break; |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3109 | case 15: /* extension space */ |
| 3110 | switch (rn) { |
| 3111 | case 0: /* cpy */ |
| 3112 | /* no-op */ |
| 3113 | break; |
| 3114 | case 1: /* abs */ |
| 3115 | gen_vfp_abs(dp); |
| 3116 | break; |
| 3117 | case 2: /* neg */ |
| 3118 | gen_vfp_neg(dp); |
| 3119 | break; |
| 3120 | case 3: /* sqrt */ |
| 3121 | gen_vfp_sqrt(dp); |
| 3122 | break; |
| 3123 | case 8: /* cmp */ |
| 3124 | gen_vfp_cmp(dp); |
| 3125 | break; |
| 3126 | case 9: /* cmpe */ |
| 3127 | gen_vfp_cmpe(dp); |
| 3128 | break; |
| 3129 | case 10: /* cmpz */ |
| 3130 | gen_vfp_cmp(dp); |
| 3131 | break; |
| 3132 | case 11: /* cmpez */ |
| 3133 | gen_vfp_F1_ld0(dp); |
| 3134 | gen_vfp_cmpe(dp); |
| 3135 | break; |
| 3136 | case 15: /* single<->double conversion */ |
| 3137 | if (dp) |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 3138 | gen_helper_vfp_fcvtsd(cpu_F0s, cpu_F0d, cpu_env); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3139 | else |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 3140 | gen_helper_vfp_fcvtds(cpu_F0d, cpu_F0s, cpu_env); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3141 | break; |
| 3142 | case 16: /* fuito */ |
| 3143 | gen_vfp_uito(dp); |
| 3144 | break; |
| 3145 | case 17: /* fsito */ |
| 3146 | gen_vfp_sito(dp); |
| 3147 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3148 | case 20: /* fshto */ |
| 3149 | if (!arm_feature(env, ARM_FEATURE_VFP3)) |
| 3150 | return 1; |
pbrook | 644ad80 | 2008-12-19 13:02:08 +0000 | [diff] [blame] | 3151 | gen_vfp_shto(dp, 16 - rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3152 | break; |
| 3153 | case 21: /* fslto */ |
| 3154 | if (!arm_feature(env, ARM_FEATURE_VFP3)) |
| 3155 | return 1; |
pbrook | 644ad80 | 2008-12-19 13:02:08 +0000 | [diff] [blame] | 3156 | gen_vfp_slto(dp, 32 - rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3157 | break; |
| 3158 | case 22: /* fuhto */ |
| 3159 | if (!arm_feature(env, ARM_FEATURE_VFP3)) |
| 3160 | return 1; |
pbrook | 644ad80 | 2008-12-19 13:02:08 +0000 | [diff] [blame] | 3161 | gen_vfp_uhto(dp, 16 - rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3162 | break; |
| 3163 | case 23: /* fulto */ |
| 3164 | if (!arm_feature(env, ARM_FEATURE_VFP3)) |
| 3165 | return 1; |
pbrook | 644ad80 | 2008-12-19 13:02:08 +0000 | [diff] [blame] | 3166 | gen_vfp_ulto(dp, 32 - rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3167 | break; |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3168 | case 24: /* ftoui */ |
| 3169 | gen_vfp_toui(dp); |
| 3170 | break; |
| 3171 | case 25: /* ftouiz */ |
| 3172 | gen_vfp_touiz(dp); |
| 3173 | break; |
| 3174 | case 26: /* ftosi */ |
| 3175 | gen_vfp_tosi(dp); |
| 3176 | break; |
| 3177 | case 27: /* ftosiz */ |
| 3178 | gen_vfp_tosiz(dp); |
| 3179 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3180 | case 28: /* ftosh */ |
| 3181 | if (!arm_feature(env, ARM_FEATURE_VFP3)) |
| 3182 | return 1; |
pbrook | 644ad80 | 2008-12-19 13:02:08 +0000 | [diff] [blame] | 3183 | gen_vfp_tosh(dp, 16 - rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3184 | break; |
| 3185 | case 29: /* ftosl */ |
| 3186 | if (!arm_feature(env, ARM_FEATURE_VFP3)) |
| 3187 | return 1; |
pbrook | 644ad80 | 2008-12-19 13:02:08 +0000 | [diff] [blame] | 3188 | gen_vfp_tosl(dp, 32 - rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3189 | break; |
| 3190 | case 30: /* ftouh */ |
| 3191 | if (!arm_feature(env, ARM_FEATURE_VFP3)) |
| 3192 | return 1; |
pbrook | 644ad80 | 2008-12-19 13:02:08 +0000 | [diff] [blame] | 3193 | gen_vfp_touh(dp, 16 - rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3194 | break; |
| 3195 | case 31: /* ftoul */ |
| 3196 | if (!arm_feature(env, ARM_FEATURE_VFP3)) |
| 3197 | return 1; |
pbrook | 644ad80 | 2008-12-19 13:02:08 +0000 | [diff] [blame] | 3198 | gen_vfp_toul(dp, 32 - rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3199 | break; |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3200 | default: /* undefined */ |
| 3201 | printf ("rn:%d\n", rn); |
| 3202 | return 1; |
| 3203 | } |
| 3204 | break; |
| 3205 | default: /* undefined */ |
| 3206 | printf ("op:%d\n", op); |
| 3207 | return 1; |
| 3208 | } |
| 3209 | |
| 3210 | /* Write back the result. */ |
| 3211 | if (op == 15 && (rn >= 8 && rn <= 11)) |
| 3212 | ; /* Comparison, do nothing. */ |
| 3213 | else if (op == 15 && rn > 17) |
| 3214 | /* Integer result. */ |
| 3215 | gen_mov_vreg_F0(0, rd); |
| 3216 | else if (op == 15 && rn == 15) |
| 3217 | /* conversion */ |
| 3218 | gen_mov_vreg_F0(!dp, rd); |
| 3219 | else |
| 3220 | gen_mov_vreg_F0(dp, rd); |
| 3221 | |
| 3222 | /* break out of the loop if we have finished */ |
| 3223 | if (veclen == 0) |
| 3224 | break; |
| 3225 | |
| 3226 | if (op == 15 && delta_m == 0) { |
| 3227 | /* single source one-many */ |
| 3228 | while (veclen--) { |
| 3229 | rd = ((rd + delta_d) & (bank_mask - 1)) |
| 3230 | | (rd & bank_mask); |
| 3231 | gen_mov_vreg_F0(dp, rd); |
| 3232 | } |
| 3233 | break; |
| 3234 | } |
| 3235 | /* Setup the next operands. */ |
| 3236 | veclen--; |
| 3237 | rd = ((rd + delta_d) & (bank_mask - 1)) |
| 3238 | | (rd & bank_mask); |
| 3239 | |
| 3240 | if (op == 15) { |
| 3241 | /* One source operand. */ |
| 3242 | rm = ((rm + delta_m) & (bank_mask - 1)) |
| 3243 | | (rm & bank_mask); |
| 3244 | gen_mov_F0_vreg(dp, rm); |
| 3245 | } else { |
| 3246 | /* Two source operands. */ |
| 3247 | rn = ((rn + delta_d) & (bank_mask - 1)) |
| 3248 | | (rn & bank_mask); |
| 3249 | gen_mov_F0_vreg(dp, rn); |
| 3250 | if (delta_m) { |
| 3251 | rm = ((rm + delta_m) & (bank_mask - 1)) |
| 3252 | | (rm & bank_mask); |
| 3253 | gen_mov_F1_vreg(dp, rm); |
| 3254 | } |
| 3255 | } |
| 3256 | } |
| 3257 | } |
| 3258 | break; |
| 3259 | case 0xc: |
| 3260 | case 0xd: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3261 | if (dp && (insn & 0x03e00000) == 0x00400000) { |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3262 | /* two-register transfer */ |
| 3263 | rn = (insn >> 16) & 0xf; |
| 3264 | rd = (insn >> 12) & 0xf; |
| 3265 | if (dp) { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3266 | VFP_DREG_M(rm, insn); |
| 3267 | } else { |
| 3268 | rm = VFP_SREG_M(insn); |
| 3269 | } |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3270 | |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 3271 | if (insn & ARM_CP_RW_BIT) { |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3272 | /* vfp->arm */ |
| 3273 | if (dp) { |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 3274 | gen_mov_F0_vreg(0, rm * 2); |
| 3275 | tmp = gen_vfp_mrs(); |
| 3276 | store_reg(s, rd, tmp); |
| 3277 | gen_mov_F0_vreg(0, rm * 2 + 1); |
| 3278 | tmp = gen_vfp_mrs(); |
| 3279 | store_reg(s, rn, tmp); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3280 | } else { |
| 3281 | gen_mov_F0_vreg(0, rm); |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 3282 | tmp = gen_vfp_mrs(); |
| 3283 | store_reg(s, rn, tmp); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3284 | gen_mov_F0_vreg(0, rm + 1); |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 3285 | tmp = gen_vfp_mrs(); |
| 3286 | store_reg(s, rd, tmp); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3287 | } |
| 3288 | } else { |
| 3289 | /* arm->vfp */ |
| 3290 | if (dp) { |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 3291 | tmp = load_reg(s, rd); |
| 3292 | gen_vfp_msr(tmp); |
| 3293 | gen_mov_vreg_F0(0, rm * 2); |
| 3294 | tmp = load_reg(s, rn); |
| 3295 | gen_vfp_msr(tmp); |
| 3296 | gen_mov_vreg_F0(0, rm * 2 + 1); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3297 | } else { |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 3298 | tmp = load_reg(s, rn); |
| 3299 | gen_vfp_msr(tmp); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3300 | gen_mov_vreg_F0(0, rm); |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 3301 | tmp = load_reg(s, rd); |
| 3302 | gen_vfp_msr(tmp); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3303 | gen_mov_vreg_F0(0, rm + 1); |
| 3304 | } |
| 3305 | } |
| 3306 | } else { |
| 3307 | /* Load/store */ |
| 3308 | rn = (insn >> 16) & 0xf; |
| 3309 | if (dp) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3310 | VFP_DREG_D(rd, insn); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3311 | else |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3312 | rd = VFP_SREG_D(insn); |
| 3313 | if (s->thumb && rn == 15) { |
| 3314 | gen_op_movl_T1_im(s->pc & ~2); |
| 3315 | } else { |
| 3316 | gen_movl_T1_reg(s, rn); |
| 3317 | } |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3318 | if ((insn & 0x01200000) == 0x01000000) { |
| 3319 | /* Single load/store */ |
| 3320 | offset = (insn & 0xff) << 2; |
| 3321 | if ((insn & (1 << 23)) == 0) |
| 3322 | offset = -offset; |
| 3323 | gen_op_addl_T1_im(offset); |
| 3324 | if (insn & (1 << 20)) { |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3325 | gen_vfp_ld(s, dp); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3326 | gen_mov_vreg_F0(dp, rd); |
| 3327 | } else { |
| 3328 | gen_mov_F0_vreg(dp, rd); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3329 | gen_vfp_st(s, dp); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3330 | } |
| 3331 | } else { |
| 3332 | /* load/store multiple */ |
| 3333 | if (dp) |
| 3334 | n = (insn >> 1) & 0x7f; |
| 3335 | else |
| 3336 | n = insn & 0xff; |
| 3337 | |
| 3338 | if (insn & (1 << 24)) /* pre-decrement */ |
| 3339 | gen_op_addl_T1_im(-((insn & 0xff) << 2)); |
| 3340 | |
| 3341 | if (dp) |
| 3342 | offset = 8; |
| 3343 | else |
| 3344 | offset = 4; |
| 3345 | for (i = 0; i < n; i++) { |
balrog | 18c9b56 | 2007-04-30 02:02:17 +0000 | [diff] [blame] | 3346 | if (insn & ARM_CP_RW_BIT) { |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3347 | /* load */ |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3348 | gen_vfp_ld(s, dp); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3349 | gen_mov_vreg_F0(dp, rd + i); |
| 3350 | } else { |
| 3351 | /* store */ |
| 3352 | gen_mov_F0_vreg(dp, rd + i); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3353 | gen_vfp_st(s, dp); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 3354 | } |
| 3355 | gen_op_addl_T1_im(offset); |
| 3356 | } |
| 3357 | if (insn & (1 << 21)) { |
| 3358 | /* writeback */ |
| 3359 | if (insn & (1 << 24)) |
| 3360 | offset = -offset * n; |
| 3361 | else if (dp && (insn & 1)) |
| 3362 | offset = 4; |
| 3363 | else |
| 3364 | offset = 0; |
| 3365 | |
| 3366 | if (offset != 0) |
| 3367 | gen_op_addl_T1_im(offset); |
| 3368 | gen_movl_reg_T1(s, rn); |
| 3369 | } |
| 3370 | } |
| 3371 | } |
| 3372 | break; |
| 3373 | default: |
| 3374 | /* Should never happen. */ |
| 3375 | return 1; |
| 3376 | } |
| 3377 | return 0; |
| 3378 | } |
| 3379 | |
bellard | 6e256c9 | 2005-11-20 10:32:05 +0000 | [diff] [blame] | 3380 | static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest) |
bellard | c53be33 | 2005-10-30 21:39:19 +0000 | [diff] [blame] | 3381 | { |
bellard | 6e256c9 | 2005-11-20 10:32:05 +0000 | [diff] [blame] | 3382 | TranslationBlock *tb; |
| 3383 | |
| 3384 | tb = s->tb; |
| 3385 | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 3386 | tcg_gen_goto_tb(n); |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 3387 | gen_set_pc_im(dest); |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 3388 | tcg_gen_exit_tb((long)tb + n); |
bellard | 6e256c9 | 2005-11-20 10:32:05 +0000 | [diff] [blame] | 3389 | } else { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 3390 | gen_set_pc_im(dest); |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 3391 | tcg_gen_exit_tb(0); |
bellard | 6e256c9 | 2005-11-20 10:32:05 +0000 | [diff] [blame] | 3392 | } |
bellard | c53be33 | 2005-10-30 21:39:19 +0000 | [diff] [blame] | 3393 | } |
| 3394 | |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 3395 | static inline void gen_jmp (DisasContext *s, uint32_t dest) |
| 3396 | { |
ths | 551bd27 | 2008-07-03 17:57:36 +0000 | [diff] [blame] | 3397 | if (unlikely(s->singlestep_enabled)) { |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 3398 | /* An indirect jump so that we still trigger the debug exception. */ |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 3399 | if (s->thumb) |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 3400 | dest |= 1; |
| 3401 | gen_bx_im(s, dest); |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 3402 | } else { |
bellard | 6e256c9 | 2005-11-20 10:32:05 +0000 | [diff] [blame] | 3403 | gen_goto_tb(s, 0, dest); |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 3404 | s->is_jmp = DISAS_TB_JUMP; |
| 3405 | } |
| 3406 | } |
| 3407 | |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 3408 | static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y) |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3409 | { |
bellard | ee09718 | 2005-12-04 18:56:28 +0000 | [diff] [blame] | 3410 | if (x) |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 3411 | tcg_gen_sari_i32(t0, t0, 16); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3412 | else |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 3413 | gen_sxth(t0); |
bellard | ee09718 | 2005-12-04 18:56:28 +0000 | [diff] [blame] | 3414 | if (y) |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 3415 | tcg_gen_sari_i32(t1, t1, 16); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3416 | else |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 3417 | gen_sxth(t1); |
| 3418 | tcg_gen_mul_i32(t0, t0, t1); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3419 | } |
| 3420 | |
| 3421 | /* Return the mask of PSR bits set by a MSR instruction. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3422 | static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) { |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3423 | uint32_t mask; |
| 3424 | |
| 3425 | mask = 0; |
| 3426 | if (flags & (1 << 0)) |
| 3427 | mask |= 0xff; |
| 3428 | if (flags & (1 << 1)) |
| 3429 | mask |= 0xff00; |
| 3430 | if (flags & (1 << 2)) |
| 3431 | mask |= 0xff0000; |
| 3432 | if (flags & (1 << 3)) |
| 3433 | mask |= 0xff000000; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3434 | |
pbrook | 2ae23e7 | 2006-02-11 16:20:39 +0000 | [diff] [blame] | 3435 | /* Mask out undefined bits. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3436 | mask &= ~CPSR_RESERVED; |
| 3437 | if (!arm_feature(env, ARM_FEATURE_V6)) |
pbrook | e160c51 | 2007-11-11 14:36:36 +0000 | [diff] [blame] | 3438 | mask &= ~(CPSR_E | CPSR_GE); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3439 | if (!arm_feature(env, ARM_FEATURE_THUMB2)) |
pbrook | e160c51 | 2007-11-11 14:36:36 +0000 | [diff] [blame] | 3440 | mask &= ~CPSR_IT; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3441 | /* Mask out execution state bits. */ |
pbrook | 2ae23e7 | 2006-02-11 16:20:39 +0000 | [diff] [blame] | 3442 | if (!spsr) |
pbrook | e160c51 | 2007-11-11 14:36:36 +0000 | [diff] [blame] | 3443 | mask &= ~CPSR_EXEC; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3444 | /* Mask out privileged bits. */ |
| 3445 | if (IS_USER(s)) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3446 | mask &= CPSR_USER; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3447 | return mask; |
| 3448 | } |
| 3449 | |
| 3450 | /* Returns nonzero if access to the PSR is not permitted. */ |
| 3451 | static int gen_set_psr_T0(DisasContext *s, uint32_t mask, int spsr) |
| 3452 | { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 3453 | TCGv tmp; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3454 | if (spsr) { |
| 3455 | /* ??? This is also undefined in system mode. */ |
| 3456 | if (IS_USER(s)) |
| 3457 | return 1; |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 3458 | |
| 3459 | tmp = load_cpu_field(spsr); |
| 3460 | tcg_gen_andi_i32(tmp, tmp, ~mask); |
| 3461 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], mask); |
| 3462 | tcg_gen_or_i32(tmp, tmp, cpu_T[0]); |
| 3463 | store_cpu_field(tmp, spsr); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3464 | } else { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 3465 | gen_set_cpsr(cpu_T[0], mask); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3466 | } |
| 3467 | gen_lookup_tb(s); |
| 3468 | return 0; |
| 3469 | } |
| 3470 | |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 3471 | /* Generate an old-style exception return. Marks pc as dead. */ |
| 3472 | static void gen_exception_return(DisasContext *s, TCGv pc) |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3473 | { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 3474 | TCGv tmp; |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 3475 | store_reg(s, 15, pc); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 3476 | tmp = load_cpu_field(spsr); |
| 3477 | gen_set_cpsr(tmp, 0xffffffff); |
| 3478 | dead_tmp(tmp); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 3479 | s->is_jmp = DISAS_UPDATE; |
| 3480 | } |
| 3481 | |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3482 | /* Generate a v6 exception return. Marks both values as dead. */ |
| 3483 | static void gen_rfe(DisasContext *s, TCGv pc, TCGv cpsr) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3484 | { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3485 | gen_set_cpsr(cpsr, 0xffffffff); |
| 3486 | dead_tmp(cpsr); |
| 3487 | store_reg(s, 15, pc); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3488 | s->is_jmp = DISAS_UPDATE; |
| 3489 | } |
| 3490 | |
| 3491 | static inline void |
| 3492 | gen_set_condexec (DisasContext *s) |
| 3493 | { |
| 3494 | if (s->condexec_mask) { |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 3495 | uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1); |
| 3496 | TCGv tmp = new_tmp(); |
| 3497 | tcg_gen_movi_i32(tmp, val); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 3498 | store_cpu_field(tmp, condexec_bits); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3499 | } |
| 3500 | } |
| 3501 | |
| 3502 | static void gen_nop_hint(DisasContext *s, int val) |
| 3503 | { |
| 3504 | switch (val) { |
| 3505 | case 3: /* wfi */ |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 3506 | gen_set_pc_im(s->pc); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3507 | s->is_jmp = DISAS_WFI; |
| 3508 | break; |
| 3509 | case 2: /* wfe */ |
| 3510 | case 4: /* sev */ |
| 3511 | /* TODO: Implement SEV and WFE. May help SMP performance. */ |
| 3512 | default: /* nop */ |
| 3513 | break; |
| 3514 | } |
| 3515 | } |
| 3516 | |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3517 | /* These macros help make the code more readable when migrating from the |
| 3518 | old dyngen helpers. They should probably be removed when |
| 3519 | T0/T1 are removed. */ |
| 3520 | #define CPU_T001 cpu_T[0], cpu_T[0], cpu_T[1] |
| 3521 | #define CPU_T0E01 cpu_T[0], cpu_env, cpu_T[0], cpu_T[1] |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3522 | |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3523 | #define CPU_V001 cpu_V0, cpu_V0, cpu_V1 |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3524 | |
| 3525 | static inline int gen_neon_add(int size) |
| 3526 | { |
| 3527 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3528 | case 0: gen_helper_neon_add_u8(CPU_T001); break; |
| 3529 | case 1: gen_helper_neon_add_u16(CPU_T001); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3530 | case 2: gen_op_addl_T0_T1(); break; |
| 3531 | default: return 1; |
| 3532 | } |
| 3533 | return 0; |
| 3534 | } |
| 3535 | |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3536 | static inline void gen_neon_rsb(int size) |
| 3537 | { |
| 3538 | switch (size) { |
| 3539 | case 0: gen_helper_neon_sub_u8(cpu_T[0], cpu_T[1], cpu_T[0]); break; |
| 3540 | case 1: gen_helper_neon_sub_u16(cpu_T[0], cpu_T[1], cpu_T[0]); break; |
| 3541 | case 2: gen_op_rsbl_T0_T1(); break; |
| 3542 | default: return; |
| 3543 | } |
| 3544 | } |
| 3545 | |
| 3546 | /* 32-bit pairwise ops end up the same as the elementwise versions. */ |
| 3547 | #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32 |
| 3548 | #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32 |
| 3549 | #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32 |
| 3550 | #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32 |
| 3551 | |
| 3552 | /* FIXME: This is wrong. They set the wrong overflow bit. */ |
| 3553 | #define gen_helper_neon_qadd_s32(a, e, b, c) gen_helper_add_saturate(a, b, c) |
| 3554 | #define gen_helper_neon_qadd_u32(a, e, b, c) gen_helper_add_usaturate(a, b, c) |
| 3555 | #define gen_helper_neon_qsub_s32(a, e, b, c) gen_helper_sub_saturate(a, b, c) |
| 3556 | #define gen_helper_neon_qsub_u32(a, e, b, c) gen_helper_sub_usaturate(a, b, c) |
| 3557 | |
| 3558 | #define GEN_NEON_INTEGER_OP_ENV(name) do { \ |
| 3559 | switch ((size << 1) | u) { \ |
| 3560 | case 0: \ |
| 3561 | gen_helper_neon_##name##_s8(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \ |
| 3562 | break; \ |
| 3563 | case 1: \ |
| 3564 | gen_helper_neon_##name##_u8(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \ |
| 3565 | break; \ |
| 3566 | case 2: \ |
| 3567 | gen_helper_neon_##name##_s16(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \ |
| 3568 | break; \ |
| 3569 | case 3: \ |
| 3570 | gen_helper_neon_##name##_u16(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \ |
| 3571 | break; \ |
| 3572 | case 4: \ |
| 3573 | gen_helper_neon_##name##_s32(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \ |
| 3574 | break; \ |
| 3575 | case 5: \ |
| 3576 | gen_helper_neon_##name##_u32(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]); \ |
| 3577 | break; \ |
| 3578 | default: return 1; \ |
| 3579 | }} while (0) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3580 | |
| 3581 | #define GEN_NEON_INTEGER_OP(name) do { \ |
| 3582 | switch ((size << 1) | u) { \ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3583 | case 0: \ |
| 3584 | gen_helper_neon_##name##_s8(cpu_T[0], cpu_T[0], cpu_T[1]); \ |
| 3585 | break; \ |
| 3586 | case 1: \ |
| 3587 | gen_helper_neon_##name##_u8(cpu_T[0], cpu_T[0], cpu_T[1]); \ |
| 3588 | break; \ |
| 3589 | case 2: \ |
| 3590 | gen_helper_neon_##name##_s16(cpu_T[0], cpu_T[0], cpu_T[1]); \ |
| 3591 | break; \ |
| 3592 | case 3: \ |
| 3593 | gen_helper_neon_##name##_u16(cpu_T[0], cpu_T[0], cpu_T[1]); \ |
| 3594 | break; \ |
| 3595 | case 4: \ |
| 3596 | gen_helper_neon_##name##_s32(cpu_T[0], cpu_T[0], cpu_T[1]); \ |
| 3597 | break; \ |
| 3598 | case 5: \ |
| 3599 | gen_helper_neon_##name##_u32(cpu_T[0], cpu_T[0], cpu_T[1]); \ |
| 3600 | break; \ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3601 | default: return 1; \ |
| 3602 | }} while (0) |
| 3603 | |
| 3604 | static inline void |
| 3605 | gen_neon_movl_scratch_T0(int scratch) |
| 3606 | { |
| 3607 | uint32_t offset; |
| 3608 | |
| 3609 | offset = offsetof(CPUARMState, vfp.scratch[scratch]); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3610 | tcg_gen_st_i32(cpu_T[0], cpu_env, offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3611 | } |
| 3612 | |
| 3613 | static inline void |
| 3614 | gen_neon_movl_scratch_T1(int scratch) |
| 3615 | { |
| 3616 | uint32_t offset; |
| 3617 | |
| 3618 | offset = offsetof(CPUARMState, vfp.scratch[scratch]); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3619 | tcg_gen_st_i32(cpu_T[1], cpu_env, offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3620 | } |
| 3621 | |
| 3622 | static inline void |
| 3623 | gen_neon_movl_T0_scratch(int scratch) |
| 3624 | { |
| 3625 | uint32_t offset; |
| 3626 | |
| 3627 | offset = offsetof(CPUARMState, vfp.scratch[scratch]); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3628 | tcg_gen_ld_i32(cpu_T[0], cpu_env, offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3629 | } |
| 3630 | |
| 3631 | static inline void |
| 3632 | gen_neon_movl_T1_scratch(int scratch) |
| 3633 | { |
| 3634 | uint32_t offset; |
| 3635 | |
| 3636 | offset = offsetof(CPUARMState, vfp.scratch[scratch]); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3637 | tcg_gen_ld_i32(cpu_T[1], cpu_env, offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3638 | } |
| 3639 | |
| 3640 | static inline void gen_neon_get_scalar(int size, int reg) |
| 3641 | { |
| 3642 | if (size == 1) { |
| 3643 | NEON_GET_REG(T0, reg >> 1, reg & 1); |
| 3644 | } else { |
| 3645 | NEON_GET_REG(T0, reg >> 2, (reg >> 1) & 1); |
| 3646 | if (reg & 1) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3647 | gen_neon_dup_low16(cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3648 | else |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3649 | gen_neon_dup_high16(cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3650 | } |
| 3651 | } |
| 3652 | |
| 3653 | static void gen_neon_unzip(int reg, int q, int tmp, int size) |
| 3654 | { |
| 3655 | int n; |
| 3656 | |
| 3657 | for (n = 0; n < q + 1; n += 2) { |
| 3658 | NEON_GET_REG(T0, reg, n); |
| 3659 | NEON_GET_REG(T0, reg, n + n); |
| 3660 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3661 | case 0: gen_helper_neon_unzip_u8(); break; |
| 3662 | case 1: gen_helper_neon_zip_u16(); break; /* zip and unzip are the same. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3663 | case 2: /* no-op */; break; |
| 3664 | default: abort(); |
| 3665 | } |
| 3666 | gen_neon_movl_scratch_T0(tmp + n); |
| 3667 | gen_neon_movl_scratch_T1(tmp + n + 1); |
| 3668 | } |
| 3669 | } |
| 3670 | |
| 3671 | static struct { |
| 3672 | int nregs; |
| 3673 | int interleave; |
| 3674 | int spacing; |
| 3675 | } neon_ls_element_type[11] = { |
| 3676 | {4, 4, 1}, |
| 3677 | {4, 4, 2}, |
| 3678 | {4, 1, 1}, |
| 3679 | {4, 2, 1}, |
| 3680 | {3, 3, 1}, |
| 3681 | {3, 3, 2}, |
| 3682 | {3, 1, 1}, |
| 3683 | {1, 1, 1}, |
| 3684 | {2, 2, 1}, |
| 3685 | {2, 2, 2}, |
| 3686 | {2, 1, 1} |
| 3687 | }; |
| 3688 | |
| 3689 | /* Translate a NEON load/store element instruction. Return nonzero if the |
| 3690 | instruction is invalid. */ |
| 3691 | static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn) |
| 3692 | { |
| 3693 | int rd, rn, rm; |
| 3694 | int op; |
| 3695 | int nregs; |
| 3696 | int interleave; |
| 3697 | int stride; |
| 3698 | int size; |
| 3699 | int reg; |
| 3700 | int pass; |
| 3701 | int load; |
| 3702 | int shift; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3703 | int n; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3704 | TCGv tmp; |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3705 | TCGv tmp2; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3706 | |
| 3707 | if (!vfp_enabled(env)) |
| 3708 | return 1; |
| 3709 | VFP_DREG_D(rd, insn); |
| 3710 | rn = (insn >> 16) & 0xf; |
| 3711 | rm = insn & 0xf; |
| 3712 | load = (insn & (1 << 21)) != 0; |
| 3713 | if ((insn & (1 << 23)) == 0) { |
| 3714 | /* Load store all elements. */ |
| 3715 | op = (insn >> 8) & 0xf; |
| 3716 | size = (insn >> 6) & 3; |
| 3717 | if (op > 10 || size == 3) |
| 3718 | return 1; |
| 3719 | nregs = neon_ls_element_type[op].nregs; |
| 3720 | interleave = neon_ls_element_type[op].interleave; |
| 3721 | gen_movl_T1_reg(s, rn); |
| 3722 | stride = (1 << size) * interleave; |
| 3723 | for (reg = 0; reg < nregs; reg++) { |
| 3724 | if (interleave > 2 || (interleave == 2 && nregs == 2)) { |
| 3725 | gen_movl_T1_reg(s, rn); |
| 3726 | gen_op_addl_T1_im((1 << size) * reg); |
| 3727 | } else if (interleave == 2 && nregs == 4 && reg == 2) { |
| 3728 | gen_movl_T1_reg(s, rn); |
| 3729 | gen_op_addl_T1_im(1 << size); |
| 3730 | } |
| 3731 | for (pass = 0; pass < 2; pass++) { |
| 3732 | if (size == 2) { |
| 3733 | if (load) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3734 | tmp = gen_ld32(cpu_T[1], IS_USER(s)); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3735 | neon_store_reg(rd, pass, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3736 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3737 | tmp = neon_load_reg(rd, pass); |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3738 | gen_st32(tmp, cpu_T[1], IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3739 | } |
| 3740 | gen_op_addl_T1_im(stride); |
| 3741 | } else if (size == 1) { |
| 3742 | if (load) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3743 | tmp = gen_ld16u(cpu_T[1], IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3744 | gen_op_addl_T1_im(stride); |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3745 | tmp2 = gen_ld16u(cpu_T[1], IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3746 | gen_op_addl_T1_im(stride); |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3747 | gen_bfi(tmp, tmp, tmp2, 16, 0xffff); |
| 3748 | dead_tmp(tmp2); |
| 3749 | neon_store_reg(rd, pass, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3750 | } else { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3751 | tmp = neon_load_reg(rd, pass); |
| 3752 | tmp2 = new_tmp(); |
| 3753 | tcg_gen_shri_i32(tmp2, tmp, 16); |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3754 | gen_st16(tmp, cpu_T[1], IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3755 | gen_op_addl_T1_im(stride); |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3756 | gen_st16(tmp2, cpu_T[1], IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3757 | gen_op_addl_T1_im(stride); |
| 3758 | } |
| 3759 | } else /* size == 0 */ { |
| 3760 | if (load) { |
pbrook | a50f5b9 | 2008-06-29 15:25:29 +0000 | [diff] [blame] | 3761 | TCGV_UNUSED(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3762 | for (n = 0; n < 4; n++) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3763 | tmp = gen_ld8u(cpu_T[1], IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3764 | gen_op_addl_T1_im(stride); |
| 3765 | if (n == 0) { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3766 | tmp2 = tmp; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3767 | } else { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3768 | gen_bfi(tmp2, tmp2, tmp, n * 8, 0xff); |
| 3769 | dead_tmp(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3770 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3771 | } |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3772 | neon_store_reg(rd, pass, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3773 | } else { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3774 | tmp2 = neon_load_reg(rd, pass); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3775 | for (n = 0; n < 4; n++) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3776 | tmp = new_tmp(); |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3777 | if (n == 0) { |
| 3778 | tcg_gen_mov_i32(tmp, tmp2); |
| 3779 | } else { |
| 3780 | tcg_gen_shri_i32(tmp, tmp2, n * 8); |
| 3781 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3782 | gen_st8(tmp, cpu_T[1], IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3783 | gen_op_addl_T1_im(stride); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3784 | } |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3785 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3786 | } |
| 3787 | } |
| 3788 | } |
| 3789 | rd += neon_ls_element_type[op].spacing; |
| 3790 | } |
| 3791 | stride = nregs * 8; |
| 3792 | } else { |
| 3793 | size = (insn >> 10) & 3; |
| 3794 | if (size == 3) { |
| 3795 | /* Load single element to all lanes. */ |
| 3796 | if (!load) |
| 3797 | return 1; |
| 3798 | size = (insn >> 6) & 3; |
| 3799 | nregs = ((insn >> 8) & 3) + 1; |
| 3800 | stride = (insn & (1 << 5)) ? 2 : 1; |
| 3801 | gen_movl_T1_reg(s, rn); |
| 3802 | for (reg = 0; reg < nregs; reg++) { |
| 3803 | switch (size) { |
| 3804 | case 0: |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3805 | tmp = gen_ld8u(cpu_T[1], IS_USER(s)); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3806 | gen_neon_dup_u8(tmp, 0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3807 | break; |
| 3808 | case 1: |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3809 | tmp = gen_ld16u(cpu_T[1], IS_USER(s)); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3810 | gen_neon_dup_low16(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3811 | break; |
| 3812 | case 2: |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3813 | tmp = gen_ld32(cpu_T[0], IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3814 | break; |
| 3815 | case 3: |
| 3816 | return 1; |
pbrook | a50f5b9 | 2008-06-29 15:25:29 +0000 | [diff] [blame] | 3817 | default: /* Avoid compiler warnings. */ |
| 3818 | abort(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3819 | } |
| 3820 | gen_op_addl_T1_im(1 << size); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3821 | tmp2 = new_tmp(); |
| 3822 | tcg_gen_mov_i32(tmp2, tmp); |
| 3823 | neon_store_reg(rd, 0, tmp2); |
pbrook | 3018f25 | 2008-09-22 00:52:42 +0000 | [diff] [blame] | 3824 | neon_store_reg(rd, 1, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3825 | rd += stride; |
| 3826 | } |
| 3827 | stride = (1 << size) * nregs; |
| 3828 | } else { |
| 3829 | /* Single element. */ |
| 3830 | pass = (insn >> 7) & 1; |
| 3831 | switch (size) { |
| 3832 | case 0: |
| 3833 | shift = ((insn >> 5) & 3) * 8; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3834 | stride = 1; |
| 3835 | break; |
| 3836 | case 1: |
| 3837 | shift = ((insn >> 6) & 1) * 16; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3838 | stride = (insn & (1 << 5)) ? 2 : 1; |
| 3839 | break; |
| 3840 | case 2: |
| 3841 | shift = 0; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3842 | stride = (insn & (1 << 6)) ? 2 : 1; |
| 3843 | break; |
| 3844 | default: |
| 3845 | abort(); |
| 3846 | } |
| 3847 | nregs = ((insn >> 8) & 3) + 1; |
| 3848 | gen_movl_T1_reg(s, rn); |
| 3849 | for (reg = 0; reg < nregs; reg++) { |
| 3850 | if (load) { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3851 | switch (size) { |
| 3852 | case 0: |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3853 | tmp = gen_ld8u(cpu_T[1], IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3854 | break; |
| 3855 | case 1: |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3856 | tmp = gen_ld16u(cpu_T[1], IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3857 | break; |
| 3858 | case 2: |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3859 | tmp = gen_ld32(cpu_T[1], IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3860 | break; |
pbrook | a50f5b9 | 2008-06-29 15:25:29 +0000 | [diff] [blame] | 3861 | default: /* Avoid compiler warnings. */ |
| 3862 | abort(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3863 | } |
| 3864 | if (size != 2) { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3865 | tmp2 = neon_load_reg(rd, pass); |
| 3866 | gen_bfi(tmp, tmp2, tmp, shift, size ? 0xffff : 0xff); |
| 3867 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3868 | } |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3869 | neon_store_reg(rd, pass, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3870 | } else { /* Store */ |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3871 | tmp = neon_load_reg(rd, pass); |
| 3872 | if (shift) |
| 3873 | tcg_gen_shri_i32(tmp, tmp, shift); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3874 | switch (size) { |
| 3875 | case 0: |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3876 | gen_st8(tmp, cpu_T[1], IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3877 | break; |
| 3878 | case 1: |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3879 | gen_st16(tmp, cpu_T[1], IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3880 | break; |
| 3881 | case 2: |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 3882 | gen_st32(tmp, cpu_T[1], IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3883 | break; |
| 3884 | } |
| 3885 | } |
| 3886 | rd += stride; |
| 3887 | gen_op_addl_T1_im(1 << size); |
| 3888 | } |
| 3889 | stride = nregs * (1 << size); |
| 3890 | } |
| 3891 | } |
| 3892 | if (rm != 15) { |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 3893 | TCGv base; |
| 3894 | |
| 3895 | base = load_reg(s, rn); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3896 | if (rm == 13) { |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 3897 | tcg_gen_addi_i32(base, base, stride); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3898 | } else { |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 3899 | TCGv index; |
| 3900 | index = load_reg(s, rm); |
| 3901 | tcg_gen_add_i32(base, base, index); |
| 3902 | dead_tmp(index); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3903 | } |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 3904 | store_reg(s, rn, base); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 3905 | } |
| 3906 | return 0; |
| 3907 | } |
| 3908 | |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 3909 | /* Bitwise select. dest = c ? t : f. Clobbers T and F. */ |
| 3910 | static void gen_neon_bsl(TCGv dest, TCGv t, TCGv f, TCGv c) |
| 3911 | { |
| 3912 | tcg_gen_and_i32(t, t, c); |
| 3913 | tcg_gen_bic_i32(f, f, c); |
| 3914 | tcg_gen_or_i32(dest, t, f); |
| 3915 | } |
| 3916 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 3917 | static inline void gen_neon_narrow(int size, TCGv dest, TCGv_i64 src) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3918 | { |
| 3919 | switch (size) { |
| 3920 | case 0: gen_helper_neon_narrow_u8(dest, src); break; |
| 3921 | case 1: gen_helper_neon_narrow_u16(dest, src); break; |
| 3922 | case 2: tcg_gen_trunc_i64_i32(dest, src); break; |
| 3923 | default: abort(); |
| 3924 | } |
| 3925 | } |
| 3926 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 3927 | static inline void gen_neon_narrow_sats(int size, TCGv dest, TCGv_i64 src) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3928 | { |
| 3929 | switch (size) { |
| 3930 | case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break; |
| 3931 | case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break; |
| 3932 | case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break; |
| 3933 | default: abort(); |
| 3934 | } |
| 3935 | } |
| 3936 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 3937 | static inline void gen_neon_narrow_satu(int size, TCGv dest, TCGv_i64 src) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3938 | { |
| 3939 | switch (size) { |
| 3940 | case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break; |
| 3941 | case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break; |
| 3942 | case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break; |
| 3943 | default: abort(); |
| 3944 | } |
| 3945 | } |
| 3946 | |
| 3947 | static inline void gen_neon_shift_narrow(int size, TCGv var, TCGv shift, |
| 3948 | int q, int u) |
| 3949 | { |
| 3950 | if (q) { |
| 3951 | if (u) { |
| 3952 | switch (size) { |
| 3953 | case 1: gen_helper_neon_rshl_u16(var, var, shift); break; |
| 3954 | case 2: gen_helper_neon_rshl_u32(var, var, shift); break; |
| 3955 | default: abort(); |
| 3956 | } |
| 3957 | } else { |
| 3958 | switch (size) { |
| 3959 | case 1: gen_helper_neon_rshl_s16(var, var, shift); break; |
| 3960 | case 2: gen_helper_neon_rshl_s32(var, var, shift); break; |
| 3961 | default: abort(); |
| 3962 | } |
| 3963 | } |
| 3964 | } else { |
| 3965 | if (u) { |
| 3966 | switch (size) { |
| 3967 | case 1: gen_helper_neon_rshl_u16(var, var, shift); break; |
| 3968 | case 2: gen_helper_neon_rshl_u32(var, var, shift); break; |
| 3969 | default: abort(); |
| 3970 | } |
| 3971 | } else { |
| 3972 | switch (size) { |
| 3973 | case 1: gen_helper_neon_shl_s16(var, var, shift); break; |
| 3974 | case 2: gen_helper_neon_shl_s32(var, var, shift); break; |
| 3975 | default: abort(); |
| 3976 | } |
| 3977 | } |
| 3978 | } |
| 3979 | } |
| 3980 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 3981 | static inline void gen_neon_widen(TCGv_i64 dest, TCGv src, int size, int u) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 3982 | { |
| 3983 | if (u) { |
| 3984 | switch (size) { |
| 3985 | case 0: gen_helper_neon_widen_u8(dest, src); break; |
| 3986 | case 1: gen_helper_neon_widen_u16(dest, src); break; |
| 3987 | case 2: tcg_gen_extu_i32_i64(dest, src); break; |
| 3988 | default: abort(); |
| 3989 | } |
| 3990 | } else { |
| 3991 | switch (size) { |
| 3992 | case 0: gen_helper_neon_widen_s8(dest, src); break; |
| 3993 | case 1: gen_helper_neon_widen_s16(dest, src); break; |
| 3994 | case 2: tcg_gen_ext_i32_i64(dest, src); break; |
| 3995 | default: abort(); |
| 3996 | } |
| 3997 | } |
| 3998 | dead_tmp(src); |
| 3999 | } |
| 4000 | |
| 4001 | static inline void gen_neon_addl(int size) |
| 4002 | { |
| 4003 | switch (size) { |
| 4004 | case 0: gen_helper_neon_addl_u16(CPU_V001); break; |
| 4005 | case 1: gen_helper_neon_addl_u32(CPU_V001); break; |
| 4006 | case 2: tcg_gen_add_i64(CPU_V001); break; |
| 4007 | default: abort(); |
| 4008 | } |
| 4009 | } |
| 4010 | |
| 4011 | static inline void gen_neon_subl(int size) |
| 4012 | { |
| 4013 | switch (size) { |
| 4014 | case 0: gen_helper_neon_subl_u16(CPU_V001); break; |
| 4015 | case 1: gen_helper_neon_subl_u32(CPU_V001); break; |
| 4016 | case 2: tcg_gen_sub_i64(CPU_V001); break; |
| 4017 | default: abort(); |
| 4018 | } |
| 4019 | } |
| 4020 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 4021 | static inline void gen_neon_negl(TCGv_i64 var, int size) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4022 | { |
| 4023 | switch (size) { |
| 4024 | case 0: gen_helper_neon_negl_u16(var, var); break; |
| 4025 | case 1: gen_helper_neon_negl_u32(var, var); break; |
| 4026 | case 2: gen_helper_neon_negl_u64(var, var); break; |
| 4027 | default: abort(); |
| 4028 | } |
| 4029 | } |
| 4030 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 4031 | static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4032 | { |
| 4033 | switch (size) { |
| 4034 | case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break; |
| 4035 | case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break; |
| 4036 | default: abort(); |
| 4037 | } |
| 4038 | } |
| 4039 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 4040 | static inline void gen_neon_mull(TCGv_i64 dest, TCGv a, TCGv b, int size, int u) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4041 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 4042 | TCGv_i64 tmp; |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4043 | |
| 4044 | switch ((size << 1) | u) { |
| 4045 | case 0: gen_helper_neon_mull_s8(dest, a, b); break; |
| 4046 | case 1: gen_helper_neon_mull_u8(dest, a, b); break; |
| 4047 | case 2: gen_helper_neon_mull_s16(dest, a, b); break; |
| 4048 | case 3: gen_helper_neon_mull_u16(dest, a, b); break; |
| 4049 | case 4: |
| 4050 | tmp = gen_muls_i64_i32(a, b); |
| 4051 | tcg_gen_mov_i64(dest, tmp); |
| 4052 | break; |
| 4053 | case 5: |
| 4054 | tmp = gen_mulu_i64_i32(a, b); |
| 4055 | tcg_gen_mov_i64(dest, tmp); |
| 4056 | break; |
| 4057 | default: abort(); |
| 4058 | } |
| 4059 | if (size < 2) { |
| 4060 | dead_tmp(b); |
| 4061 | dead_tmp(a); |
| 4062 | } |
| 4063 | } |
| 4064 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4065 | /* Translate a NEON data processing instruction. Return nonzero if the |
| 4066 | instruction is invalid. |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4067 | We process data in a mixture of 32-bit and 64-bit chunks. |
| 4068 | Mostly we use 32-bit chunks so we can use normal scalar instructions. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4069 | |
| 4070 | static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) |
| 4071 | { |
| 4072 | int op; |
| 4073 | int q; |
| 4074 | int rd, rn, rm; |
| 4075 | int size; |
| 4076 | int shift; |
| 4077 | int pass; |
| 4078 | int count; |
| 4079 | int pairwise; |
| 4080 | int u; |
| 4081 | int n; |
| 4082 | uint32_t imm; |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 4083 | TCGv tmp; |
| 4084 | TCGv tmp2; |
| 4085 | TCGv tmp3; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 4086 | TCGv_i64 tmp64; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4087 | |
| 4088 | if (!vfp_enabled(env)) |
| 4089 | return 1; |
| 4090 | q = (insn & (1 << 6)) != 0; |
| 4091 | u = (insn >> 24) & 1; |
| 4092 | VFP_DREG_D(rd, insn); |
| 4093 | VFP_DREG_N(rn, insn); |
| 4094 | VFP_DREG_M(rm, insn); |
| 4095 | size = (insn >> 20) & 3; |
| 4096 | if ((insn & (1 << 23)) == 0) { |
| 4097 | /* Three register same length. */ |
| 4098 | op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4099 | if (size == 3 && (op == 1 || op == 5 || op == 8 || op == 9 |
| 4100 | || op == 10 || op == 11 || op == 16)) { |
| 4101 | /* 64-bit element instructions. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4102 | for (pass = 0; pass < (q ? 2 : 1); pass++) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4103 | neon_load_reg64(cpu_V0, rn + pass); |
| 4104 | neon_load_reg64(cpu_V1, rm + pass); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4105 | switch (op) { |
| 4106 | case 1: /* VQADD */ |
| 4107 | if (u) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4108 | gen_helper_neon_add_saturate_u64(CPU_V001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4109 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4110 | gen_helper_neon_add_saturate_s64(CPU_V001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4111 | } |
| 4112 | break; |
| 4113 | case 5: /* VQSUB */ |
| 4114 | if (u) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4115 | gen_helper_neon_sub_saturate_u64(CPU_V001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4116 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4117 | gen_helper_neon_sub_saturate_s64(CPU_V001); |
| 4118 | } |
| 4119 | break; |
| 4120 | case 8: /* VSHL */ |
| 4121 | if (u) { |
| 4122 | gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0); |
| 4123 | } else { |
| 4124 | gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0); |
| 4125 | } |
| 4126 | break; |
| 4127 | case 9: /* VQSHL */ |
| 4128 | if (u) { |
| 4129 | gen_helper_neon_qshl_u64(cpu_V0, cpu_env, |
| 4130 | cpu_V0, cpu_V0); |
| 4131 | } else { |
| 4132 | gen_helper_neon_qshl_s64(cpu_V1, cpu_env, |
| 4133 | cpu_V1, cpu_V0); |
| 4134 | } |
| 4135 | break; |
| 4136 | case 10: /* VRSHL */ |
| 4137 | if (u) { |
| 4138 | gen_helper_neon_rshl_u64(cpu_V0, cpu_V1, cpu_V0); |
| 4139 | } else { |
| 4140 | gen_helper_neon_rshl_s64(cpu_V0, cpu_V1, cpu_V0); |
| 4141 | } |
| 4142 | break; |
| 4143 | case 11: /* VQRSHL */ |
| 4144 | if (u) { |
| 4145 | gen_helper_neon_qrshl_u64(cpu_V0, cpu_env, |
| 4146 | cpu_V1, cpu_V0); |
| 4147 | } else { |
| 4148 | gen_helper_neon_qrshl_s64(cpu_V0, cpu_env, |
| 4149 | cpu_V1, cpu_V0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4150 | } |
| 4151 | break; |
| 4152 | case 16: |
| 4153 | if (u) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4154 | tcg_gen_sub_i64(CPU_V001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4155 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4156 | tcg_gen_add_i64(CPU_V001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4157 | } |
| 4158 | break; |
| 4159 | default: |
| 4160 | abort(); |
| 4161 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4162 | neon_store_reg64(cpu_V0, rd + pass); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4163 | } |
| 4164 | return 0; |
| 4165 | } |
| 4166 | switch (op) { |
| 4167 | case 8: /* VSHL */ |
| 4168 | case 9: /* VQSHL */ |
| 4169 | case 10: /* VRSHL */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4170 | case 11: /* VQRSHL */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4171 | { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4172 | int rtmp; |
| 4173 | /* Shift instruction operands are reversed. */ |
| 4174 | rtmp = rn; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4175 | rn = rm; |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4176 | rm = rtmp; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4177 | pairwise = 0; |
| 4178 | } |
| 4179 | break; |
| 4180 | case 20: /* VPMAX */ |
| 4181 | case 21: /* VPMIN */ |
| 4182 | case 23: /* VPADD */ |
| 4183 | pairwise = 1; |
| 4184 | break; |
| 4185 | case 26: /* VPADD (float) */ |
| 4186 | pairwise = (u && size < 2); |
| 4187 | break; |
| 4188 | case 30: /* VPMIN/VPMAX (float) */ |
| 4189 | pairwise = u; |
| 4190 | break; |
| 4191 | default: |
| 4192 | pairwise = 0; |
| 4193 | break; |
| 4194 | } |
| 4195 | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
| 4196 | |
| 4197 | if (pairwise) { |
| 4198 | /* Pairwise. */ |
| 4199 | if (q) |
| 4200 | n = (pass & 1) * 2; |
| 4201 | else |
| 4202 | n = 0; |
| 4203 | if (pass < q + 1) { |
| 4204 | NEON_GET_REG(T0, rn, n); |
| 4205 | NEON_GET_REG(T1, rn, n + 1); |
| 4206 | } else { |
| 4207 | NEON_GET_REG(T0, rm, n); |
| 4208 | NEON_GET_REG(T1, rm, n + 1); |
| 4209 | } |
| 4210 | } else { |
| 4211 | /* Elementwise. */ |
| 4212 | NEON_GET_REG(T0, rn, pass); |
| 4213 | NEON_GET_REG(T1, rm, pass); |
| 4214 | } |
| 4215 | switch (op) { |
| 4216 | case 0: /* VHADD */ |
| 4217 | GEN_NEON_INTEGER_OP(hadd); |
| 4218 | break; |
| 4219 | case 1: /* VQADD */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4220 | GEN_NEON_INTEGER_OP_ENV(qadd); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4221 | break; |
| 4222 | case 2: /* VRHADD */ |
| 4223 | GEN_NEON_INTEGER_OP(rhadd); |
| 4224 | break; |
| 4225 | case 3: /* Logic ops. */ |
| 4226 | switch ((u << 2) | size) { |
| 4227 | case 0: /* VAND */ |
| 4228 | gen_op_andl_T0_T1(); |
| 4229 | break; |
| 4230 | case 1: /* BIC */ |
| 4231 | gen_op_bicl_T0_T1(); |
| 4232 | break; |
| 4233 | case 2: /* VORR */ |
| 4234 | gen_op_orl_T0_T1(); |
| 4235 | break; |
| 4236 | case 3: /* VORN */ |
| 4237 | gen_op_notl_T1(); |
| 4238 | gen_op_orl_T0_T1(); |
| 4239 | break; |
| 4240 | case 4: /* VEOR */ |
| 4241 | gen_op_xorl_T0_T1(); |
| 4242 | break; |
| 4243 | case 5: /* VBSL */ |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 4244 | tmp = neon_load_reg(rd, pass); |
| 4245 | gen_neon_bsl(cpu_T[0], cpu_T[0], cpu_T[1], tmp); |
| 4246 | dead_tmp(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4247 | break; |
| 4248 | case 6: /* VBIT */ |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 4249 | tmp = neon_load_reg(rd, pass); |
| 4250 | gen_neon_bsl(cpu_T[0], cpu_T[0], tmp, cpu_T[1]); |
| 4251 | dead_tmp(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4252 | break; |
| 4253 | case 7: /* VBIF */ |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 4254 | tmp = neon_load_reg(rd, pass); |
| 4255 | gen_neon_bsl(cpu_T[0], tmp, cpu_T[0], cpu_T[1]); |
| 4256 | dead_tmp(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4257 | break; |
| 4258 | } |
| 4259 | break; |
| 4260 | case 4: /* VHSUB */ |
| 4261 | GEN_NEON_INTEGER_OP(hsub); |
| 4262 | break; |
| 4263 | case 5: /* VQSUB */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4264 | GEN_NEON_INTEGER_OP_ENV(qsub); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4265 | break; |
| 4266 | case 6: /* VCGT */ |
| 4267 | GEN_NEON_INTEGER_OP(cgt); |
| 4268 | break; |
| 4269 | case 7: /* VCGE */ |
| 4270 | GEN_NEON_INTEGER_OP(cge); |
| 4271 | break; |
| 4272 | case 8: /* VSHL */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4273 | GEN_NEON_INTEGER_OP(shl); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4274 | break; |
| 4275 | case 9: /* VQSHL */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4276 | GEN_NEON_INTEGER_OP_ENV(qshl); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4277 | break; |
| 4278 | case 10: /* VRSHL */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4279 | GEN_NEON_INTEGER_OP(rshl); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4280 | break; |
| 4281 | case 11: /* VQRSHL */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4282 | GEN_NEON_INTEGER_OP_ENV(qrshl); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4283 | break; |
| 4284 | case 12: /* VMAX */ |
| 4285 | GEN_NEON_INTEGER_OP(max); |
| 4286 | break; |
| 4287 | case 13: /* VMIN */ |
| 4288 | GEN_NEON_INTEGER_OP(min); |
| 4289 | break; |
| 4290 | case 14: /* VABD */ |
| 4291 | GEN_NEON_INTEGER_OP(abd); |
| 4292 | break; |
| 4293 | case 15: /* VABA */ |
| 4294 | GEN_NEON_INTEGER_OP(abd); |
| 4295 | NEON_GET_REG(T1, rd, pass); |
| 4296 | gen_neon_add(size); |
| 4297 | break; |
| 4298 | case 16: |
| 4299 | if (!u) { /* VADD */ |
| 4300 | if (gen_neon_add(size)) |
| 4301 | return 1; |
| 4302 | } else { /* VSUB */ |
| 4303 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4304 | case 0: gen_helper_neon_sub_u8(CPU_T001); break; |
| 4305 | case 1: gen_helper_neon_sub_u16(CPU_T001); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4306 | case 2: gen_op_subl_T0_T1(); break; |
| 4307 | default: return 1; |
| 4308 | } |
| 4309 | } |
| 4310 | break; |
| 4311 | case 17: |
| 4312 | if (!u) { /* VTST */ |
| 4313 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4314 | case 0: gen_helper_neon_tst_u8(CPU_T001); break; |
| 4315 | case 1: gen_helper_neon_tst_u16(CPU_T001); break; |
| 4316 | case 2: gen_helper_neon_tst_u32(CPU_T001); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4317 | default: return 1; |
| 4318 | } |
| 4319 | } else { /* VCEQ */ |
| 4320 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4321 | case 0: gen_helper_neon_ceq_u8(CPU_T001); break; |
| 4322 | case 1: gen_helper_neon_ceq_u16(CPU_T001); break; |
| 4323 | case 2: gen_helper_neon_ceq_u32(CPU_T001); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4324 | default: return 1; |
| 4325 | } |
| 4326 | } |
| 4327 | break; |
| 4328 | case 18: /* Multiply. */ |
| 4329 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4330 | case 0: gen_helper_neon_mul_u8(CPU_T001); break; |
| 4331 | case 1: gen_helper_neon_mul_u16(CPU_T001); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4332 | case 2: gen_op_mul_T0_T1(); break; |
| 4333 | default: return 1; |
| 4334 | } |
| 4335 | NEON_GET_REG(T1, rd, pass); |
| 4336 | if (u) { /* VMLS */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4337 | gen_neon_rsb(size); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4338 | } else { /* VMLA */ |
| 4339 | gen_neon_add(size); |
| 4340 | } |
| 4341 | break; |
| 4342 | case 19: /* VMUL */ |
| 4343 | if (u) { /* polynomial */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4344 | gen_helper_neon_mul_p8(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4345 | } else { /* Integer */ |
| 4346 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4347 | case 0: gen_helper_neon_mul_u8(CPU_T001); break; |
| 4348 | case 1: gen_helper_neon_mul_u16(CPU_T001); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4349 | case 2: gen_op_mul_T0_T1(); break; |
| 4350 | default: return 1; |
| 4351 | } |
| 4352 | } |
| 4353 | break; |
| 4354 | case 20: /* VPMAX */ |
| 4355 | GEN_NEON_INTEGER_OP(pmax); |
| 4356 | break; |
| 4357 | case 21: /* VPMIN */ |
| 4358 | GEN_NEON_INTEGER_OP(pmin); |
| 4359 | break; |
| 4360 | case 22: /* Hultiply high. */ |
| 4361 | if (!u) { /* VQDMULH */ |
| 4362 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4363 | case 1: gen_helper_neon_qdmulh_s16(CPU_T0E01); break; |
| 4364 | case 2: gen_helper_neon_qdmulh_s32(CPU_T0E01); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4365 | default: return 1; |
| 4366 | } |
| 4367 | } else { /* VQRDHMUL */ |
| 4368 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4369 | case 1: gen_helper_neon_qrdmulh_s16(CPU_T0E01); break; |
| 4370 | case 2: gen_helper_neon_qrdmulh_s32(CPU_T0E01); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4371 | default: return 1; |
| 4372 | } |
| 4373 | } |
| 4374 | break; |
| 4375 | case 23: /* VPADD */ |
| 4376 | if (u) |
| 4377 | return 1; |
| 4378 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4379 | case 0: gen_helper_neon_padd_u8(CPU_T001); break; |
| 4380 | case 1: gen_helper_neon_padd_u16(CPU_T001); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4381 | case 2: gen_op_addl_T0_T1(); break; |
| 4382 | default: return 1; |
| 4383 | } |
| 4384 | break; |
| 4385 | case 26: /* Floating point arithnetic. */ |
| 4386 | switch ((u << 2) | size) { |
| 4387 | case 0: /* VADD */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4388 | gen_helper_neon_add_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4389 | break; |
| 4390 | case 2: /* VSUB */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4391 | gen_helper_neon_sub_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4392 | break; |
| 4393 | case 4: /* VPADD */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4394 | gen_helper_neon_add_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4395 | break; |
| 4396 | case 6: /* VABD */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4397 | gen_helper_neon_abd_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4398 | break; |
| 4399 | default: |
| 4400 | return 1; |
| 4401 | } |
| 4402 | break; |
| 4403 | case 27: /* Float multiply. */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4404 | gen_helper_neon_mul_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4405 | if (!u) { |
| 4406 | NEON_GET_REG(T1, rd, pass); |
| 4407 | if (size == 0) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4408 | gen_helper_neon_add_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4409 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4410 | gen_helper_neon_sub_f32(cpu_T[0], cpu_T[1], cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4411 | } |
| 4412 | } |
| 4413 | break; |
| 4414 | case 28: /* Float compare. */ |
| 4415 | if (!u) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4416 | gen_helper_neon_ceq_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4417 | } else { |
| 4418 | if (size == 0) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4419 | gen_helper_neon_cge_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4420 | else |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4421 | gen_helper_neon_cgt_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4422 | } |
| 4423 | break; |
| 4424 | case 29: /* Float compare absolute. */ |
| 4425 | if (!u) |
| 4426 | return 1; |
| 4427 | if (size == 0) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4428 | gen_helper_neon_acge_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4429 | else |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4430 | gen_helper_neon_acgt_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4431 | break; |
| 4432 | case 30: /* Float min/max. */ |
| 4433 | if (size == 0) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4434 | gen_helper_neon_max_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4435 | else |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4436 | gen_helper_neon_min_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4437 | break; |
| 4438 | case 31: |
| 4439 | if (size == 0) |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 4440 | gen_helper_recps_f32(cpu_T[0], cpu_T[0], cpu_T[1], cpu_env); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4441 | else |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 4442 | gen_helper_rsqrts_f32(cpu_T[0], cpu_T[0], cpu_T[1], cpu_env); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4443 | break; |
| 4444 | default: |
| 4445 | abort(); |
| 4446 | } |
| 4447 | /* Save the result. For elementwise operations we can put it |
| 4448 | straight into the destination register. For pairwise operations |
| 4449 | we have to be careful to avoid clobbering the source operands. */ |
| 4450 | if (pairwise && rd == rm) { |
| 4451 | gen_neon_movl_scratch_T0(pass); |
| 4452 | } else { |
| 4453 | NEON_SET_REG(T0, rd, pass); |
| 4454 | } |
| 4455 | |
| 4456 | } /* for pass */ |
| 4457 | if (pairwise && rd == rm) { |
| 4458 | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
| 4459 | gen_neon_movl_T0_scratch(pass); |
| 4460 | NEON_SET_REG(T0, rd, pass); |
| 4461 | } |
| 4462 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4463 | /* End of 3 register same size operations. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4464 | } else if (insn & (1 << 4)) { |
| 4465 | if ((insn & 0x00380080) != 0) { |
| 4466 | /* Two registers and shift. */ |
| 4467 | op = (insn >> 8) & 0xf; |
| 4468 | if (insn & (1 << 7)) { |
| 4469 | /* 64-bit shift. */ |
| 4470 | size = 3; |
| 4471 | } else { |
| 4472 | size = 2; |
| 4473 | while ((insn & (1 << (size + 19))) == 0) |
| 4474 | size--; |
| 4475 | } |
| 4476 | shift = (insn >> 16) & ((1 << (3 + size)) - 1); |
| 4477 | /* To avoid excessive dumplication of ops we implement shift |
| 4478 | by immediate using the variable shift operations. */ |
| 4479 | if (op < 8) { |
| 4480 | /* Shift by immediate: |
| 4481 | VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */ |
| 4482 | /* Right shifts are encoded as N - shift, where N is the |
| 4483 | element size in bits. */ |
| 4484 | if (op <= 4) |
| 4485 | shift = shift - (1 << (size + 3)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4486 | if (size == 3) { |
| 4487 | count = q + 1; |
| 4488 | } else { |
| 4489 | count = q ? 4: 2; |
| 4490 | } |
| 4491 | switch (size) { |
| 4492 | case 0: |
| 4493 | imm = (uint8_t) shift; |
| 4494 | imm |= imm << 8; |
| 4495 | imm |= imm << 16; |
| 4496 | break; |
| 4497 | case 1: |
| 4498 | imm = (uint16_t) shift; |
| 4499 | imm |= imm << 16; |
| 4500 | break; |
| 4501 | case 2: |
| 4502 | case 3: |
| 4503 | imm = shift; |
| 4504 | break; |
| 4505 | default: |
| 4506 | abort(); |
| 4507 | } |
| 4508 | |
| 4509 | for (pass = 0; pass < count; pass++) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4510 | if (size == 3) { |
| 4511 | neon_load_reg64(cpu_V0, rm + pass); |
| 4512 | tcg_gen_movi_i64(cpu_V1, imm); |
| 4513 | switch (op) { |
| 4514 | case 0: /* VSHR */ |
| 4515 | case 1: /* VSRA */ |
| 4516 | if (u) |
| 4517 | gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1); |
| 4518 | else |
| 4519 | gen_helper_neon_shl_s64(cpu_V0, cpu_V0, cpu_V1); |
| 4520 | break; |
| 4521 | case 2: /* VRSHR */ |
| 4522 | case 3: /* VRSRA */ |
| 4523 | if (u) |
| 4524 | gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, cpu_V1); |
| 4525 | else |
| 4526 | gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, cpu_V1); |
| 4527 | break; |
| 4528 | case 4: /* VSRI */ |
| 4529 | if (!u) |
| 4530 | return 1; |
| 4531 | gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1); |
| 4532 | break; |
| 4533 | case 5: /* VSHL, VSLI */ |
| 4534 | gen_helper_neon_shl_u64(cpu_V0, cpu_V0, cpu_V1); |
| 4535 | break; |
| 4536 | case 6: /* VQSHL */ |
| 4537 | if (u) |
| 4538 | gen_helper_neon_qshl_u64(cpu_V0, cpu_env, cpu_V0, cpu_V1); |
| 4539 | else |
| 4540 | gen_helper_neon_qshl_s64(cpu_V0, cpu_env, cpu_V0, cpu_V1); |
| 4541 | break; |
| 4542 | case 7: /* VQSHLU */ |
| 4543 | gen_helper_neon_qshl_u64(cpu_V0, cpu_env, cpu_V0, cpu_V1); |
| 4544 | break; |
| 4545 | } |
| 4546 | if (op == 1 || op == 3) { |
| 4547 | /* Accumulate. */ |
| 4548 | neon_load_reg64(cpu_V0, rd + pass); |
| 4549 | tcg_gen_add_i64(cpu_V0, cpu_V0, cpu_V1); |
| 4550 | } else if (op == 4 || (op == 5 && u)) { |
| 4551 | /* Insert */ |
| 4552 | cpu_abort(env, "VS[LR]I.64 not implemented"); |
| 4553 | } |
| 4554 | neon_store_reg64(cpu_V0, rd + pass); |
| 4555 | } else { /* size < 3 */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4556 | /* Operands in T0 and T1. */ |
| 4557 | gen_op_movl_T1_im(imm); |
| 4558 | NEON_GET_REG(T0, rm, pass); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4559 | switch (op) { |
| 4560 | case 0: /* VSHR */ |
| 4561 | case 1: /* VSRA */ |
| 4562 | GEN_NEON_INTEGER_OP(shl); |
| 4563 | break; |
| 4564 | case 2: /* VRSHR */ |
| 4565 | case 3: /* VRSRA */ |
| 4566 | GEN_NEON_INTEGER_OP(rshl); |
| 4567 | break; |
| 4568 | case 4: /* VSRI */ |
| 4569 | if (!u) |
| 4570 | return 1; |
| 4571 | GEN_NEON_INTEGER_OP(shl); |
| 4572 | break; |
| 4573 | case 5: /* VSHL, VSLI */ |
| 4574 | switch (size) { |
| 4575 | case 0: gen_helper_neon_shl_u8(CPU_T001); break; |
| 4576 | case 1: gen_helper_neon_shl_u16(CPU_T001); break; |
| 4577 | case 2: gen_helper_neon_shl_u32(CPU_T001); break; |
| 4578 | default: return 1; |
| 4579 | } |
| 4580 | break; |
| 4581 | case 6: /* VQSHL */ |
| 4582 | GEN_NEON_INTEGER_OP_ENV(qshl); |
| 4583 | break; |
| 4584 | case 7: /* VQSHLU */ |
| 4585 | switch (size) { |
| 4586 | case 0: gen_helper_neon_qshl_u8(CPU_T0E01); break; |
| 4587 | case 1: gen_helper_neon_qshl_u16(CPU_T0E01); break; |
| 4588 | case 2: gen_helper_neon_qshl_u32(CPU_T0E01); break; |
| 4589 | default: return 1; |
| 4590 | } |
| 4591 | break; |
| 4592 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4593 | |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4594 | if (op == 1 || op == 3) { |
| 4595 | /* Accumulate. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4596 | NEON_GET_REG(T1, rd, pass); |
| 4597 | gen_neon_add(size); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4598 | } else if (op == 4 || (op == 5 && u)) { |
| 4599 | /* Insert */ |
| 4600 | switch (size) { |
| 4601 | case 0: |
| 4602 | if (op == 4) |
| 4603 | imm = 0xff >> -shift; |
| 4604 | else |
| 4605 | imm = (uint8_t)(0xff << shift); |
| 4606 | imm |= imm << 8; |
| 4607 | imm |= imm << 16; |
| 4608 | break; |
| 4609 | case 1: |
| 4610 | if (op == 4) |
| 4611 | imm = 0xffff >> -shift; |
| 4612 | else |
| 4613 | imm = (uint16_t)(0xffff << shift); |
| 4614 | imm |= imm << 16; |
| 4615 | break; |
| 4616 | case 2: |
| 4617 | if (op == 4) |
| 4618 | imm = 0xffffffffu >> -shift; |
| 4619 | else |
| 4620 | imm = 0xffffffffu << shift; |
| 4621 | break; |
| 4622 | default: |
| 4623 | abort(); |
| 4624 | } |
| 4625 | tmp = neon_load_reg(rd, pass); |
| 4626 | tcg_gen_andi_i32(cpu_T[0], cpu_T[0], imm); |
| 4627 | tcg_gen_andi_i32(tmp, tmp, ~imm); |
| 4628 | tcg_gen_or_i32(cpu_T[0], cpu_T[0], tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4629 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4630 | NEON_SET_REG(T0, rd, pass); |
| 4631 | } |
| 4632 | } /* for pass */ |
| 4633 | } else if (op < 10) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4634 | /* Shift by immediate and narrow: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4635 | VSHRN, VRSHRN, VQSHRN, VQRSHRN. */ |
| 4636 | shift = shift - (1 << (size + 3)); |
| 4637 | size++; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4638 | switch (size) { |
| 4639 | case 1: |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4640 | imm = (uint16_t)shift; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4641 | imm |= imm << 16; |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4642 | tmp2 = tcg_const_i32(imm); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 4643 | TCGV_UNUSED_I64(tmp64); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4644 | break; |
| 4645 | case 2: |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4646 | imm = (uint32_t)shift; |
| 4647 | tmp2 = tcg_const_i32(imm); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 4648 | TCGV_UNUSED_I64(tmp64); |
balrog | 4cc633c | 2008-12-07 13:32:09 +0000 | [diff] [blame] | 4649 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4650 | case 3: |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 4651 | tmp64 = tcg_const_i64(shift); |
| 4652 | TCGV_UNUSED(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4653 | break; |
| 4654 | default: |
| 4655 | abort(); |
| 4656 | } |
| 4657 | |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4658 | for (pass = 0; pass < 2; pass++) { |
| 4659 | if (size == 3) { |
| 4660 | neon_load_reg64(cpu_V0, rm + pass); |
| 4661 | if (q) { |
| 4662 | if (u) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 4663 | gen_helper_neon_rshl_u64(cpu_V0, cpu_V0, tmp64); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4664 | else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 4665 | gen_helper_neon_rshl_s64(cpu_V0, cpu_V0, tmp64); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4666 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4667 | if (u) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 4668 | gen_helper_neon_shl_u64(cpu_V0, cpu_V0, tmp64); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4669 | else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 4670 | gen_helper_neon_shl_s64(cpu_V0, cpu_V0, tmp64); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4671 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4672 | } else { |
| 4673 | tmp = neon_load_reg(rm + pass, 0); |
| 4674 | gen_neon_shift_narrow(size, tmp, tmp2, q, u); |
pbrook | 36aa55d | 2008-09-21 13:48:32 +0000 | [diff] [blame] | 4675 | tmp3 = neon_load_reg(rm + pass, 1); |
| 4676 | gen_neon_shift_narrow(size, tmp3, tmp2, q, u); |
| 4677 | tcg_gen_concat_i32_i64(cpu_V0, tmp, tmp3); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4678 | dead_tmp(tmp); |
pbrook | 36aa55d | 2008-09-21 13:48:32 +0000 | [diff] [blame] | 4679 | dead_tmp(tmp3); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4680 | } |
| 4681 | tmp = new_tmp(); |
| 4682 | if (op == 8 && !u) { |
| 4683 | gen_neon_narrow(size - 1, tmp, cpu_V0); |
| 4684 | } else { |
| 4685 | if (op == 8) |
| 4686 | gen_neon_narrow_sats(size - 1, tmp, cpu_V0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4687 | else |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4688 | gen_neon_narrow_satu(size - 1, tmp, cpu_V0); |
| 4689 | } |
| 4690 | if (pass == 0) { |
| 4691 | tmp2 = tmp; |
| 4692 | } else { |
| 4693 | neon_store_reg(rd, 0, tmp2); |
| 4694 | neon_store_reg(rd, 1, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4695 | } |
| 4696 | } /* for pass */ |
| 4697 | } else if (op == 10) { |
| 4698 | /* VSHLL */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4699 | if (q || size == 3) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4700 | return 1; |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4701 | tmp = neon_load_reg(rm, 0); |
| 4702 | tmp2 = neon_load_reg(rm, 1); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4703 | for (pass = 0; pass < 2; pass++) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4704 | if (pass == 1) |
| 4705 | tmp = tmp2; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4706 | |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4707 | gen_neon_widen(cpu_V0, tmp, size, u); |
| 4708 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4709 | if (shift != 0) { |
| 4710 | /* The shift is less than the width of the source |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4711 | type, so we can just shift the whole register. */ |
| 4712 | tcg_gen_shli_i64(cpu_V0, cpu_V0, shift); |
| 4713 | if (size < 2 || !u) { |
| 4714 | uint64_t imm64; |
| 4715 | if (size == 0) { |
| 4716 | imm = (0xffu >> (8 - shift)); |
| 4717 | imm |= imm << 16; |
| 4718 | } else { |
| 4719 | imm = 0xffff >> (16 - shift); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4720 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4721 | imm64 = imm | (((uint64_t)imm) << 32); |
| 4722 | tcg_gen_andi_i64(cpu_V0, cpu_V0, imm64); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4723 | } |
| 4724 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4725 | neon_store_reg64(cpu_V0, rd + pass); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4726 | } |
| 4727 | } else if (op == 15 || op == 16) { |
| 4728 | /* VCVT fixed-point. */ |
| 4729 | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 4730 | tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4731 | if (op & 1) { |
| 4732 | if (u) |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 4733 | gen_vfp_ulto(0, shift); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4734 | else |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 4735 | gen_vfp_slto(0, shift); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4736 | } else { |
| 4737 | if (u) |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 4738 | gen_vfp_toul(0, shift); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4739 | else |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 4740 | gen_vfp_tosl(0, shift); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4741 | } |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 4742 | tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4743 | } |
| 4744 | } else { |
| 4745 | return 1; |
| 4746 | } |
| 4747 | } else { /* (insn & 0x00380080) == 0 */ |
| 4748 | int invert; |
| 4749 | |
| 4750 | op = (insn >> 8) & 0xf; |
| 4751 | /* One register and immediate. */ |
| 4752 | imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf); |
| 4753 | invert = (insn & (1 << 5)) != 0; |
| 4754 | switch (op) { |
| 4755 | case 0: case 1: |
| 4756 | /* no-op */ |
| 4757 | break; |
| 4758 | case 2: case 3: |
| 4759 | imm <<= 8; |
| 4760 | break; |
| 4761 | case 4: case 5: |
| 4762 | imm <<= 16; |
| 4763 | break; |
| 4764 | case 6: case 7: |
| 4765 | imm <<= 24; |
| 4766 | break; |
| 4767 | case 8: case 9: |
| 4768 | imm |= imm << 16; |
| 4769 | break; |
| 4770 | case 10: case 11: |
| 4771 | imm = (imm << 8) | (imm << 24); |
| 4772 | break; |
| 4773 | case 12: |
| 4774 | imm = (imm < 8) | 0xff; |
| 4775 | break; |
| 4776 | case 13: |
| 4777 | imm = (imm << 16) | 0xffff; |
| 4778 | break; |
| 4779 | case 14: |
| 4780 | imm |= (imm << 8) | (imm << 16) | (imm << 24); |
| 4781 | if (invert) |
| 4782 | imm = ~imm; |
| 4783 | break; |
| 4784 | case 15: |
| 4785 | imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) |
| 4786 | | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); |
| 4787 | break; |
| 4788 | } |
| 4789 | if (invert) |
| 4790 | imm = ~imm; |
| 4791 | |
| 4792 | if (op != 14 || !invert) |
| 4793 | gen_op_movl_T1_im(imm); |
| 4794 | |
| 4795 | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
| 4796 | if (op & 1 && op < 12) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4797 | tmp = neon_load_reg(rd, pass); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4798 | if (invert) { |
| 4799 | /* The immediate value has already been inverted, so |
| 4800 | BIC becomes AND. */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4801 | tcg_gen_andi_i32(tmp, tmp, imm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4802 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4803 | tcg_gen_ori_i32(tmp, tmp, imm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4804 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4805 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4806 | /* VMOV, VMVN. */ |
| 4807 | tmp = new_tmp(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4808 | if (op == 14 && invert) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4809 | uint32_t val; |
| 4810 | val = 0; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4811 | for (n = 0; n < 4; n++) { |
| 4812 | if (imm & (1 << (n + (pass & 1) * 4))) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4813 | val |= 0xff << (n * 8); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4814 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4815 | tcg_gen_movi_i32(tmp, val); |
| 4816 | } else { |
| 4817 | tcg_gen_movi_i32(tmp, imm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4818 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4819 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4820 | neon_store_reg(rd, pass, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4821 | } |
| 4822 | } |
pbrook | e4b3861 | 2008-09-21 23:15:38 +0000 | [diff] [blame] | 4823 | } else { /* (insn & 0x00800010 == 0x00800000) */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4824 | if (size != 3) { |
| 4825 | op = (insn >> 8) & 0xf; |
| 4826 | if ((insn & (1 << 6)) == 0) { |
| 4827 | /* Three registers of different lengths. */ |
| 4828 | int src1_wide; |
| 4829 | int src2_wide; |
| 4830 | int prewiden; |
| 4831 | /* prewiden, src1_wide, src2_wide */ |
| 4832 | static const int neon_3reg_wide[16][3] = { |
| 4833 | {1, 0, 0}, /* VADDL */ |
| 4834 | {1, 1, 0}, /* VADDW */ |
| 4835 | {1, 0, 0}, /* VSUBL */ |
| 4836 | {1, 1, 0}, /* VSUBW */ |
| 4837 | {0, 1, 1}, /* VADDHN */ |
| 4838 | {0, 0, 0}, /* VABAL */ |
| 4839 | {0, 1, 1}, /* VSUBHN */ |
| 4840 | {0, 0, 0}, /* VABDL */ |
| 4841 | {0, 0, 0}, /* VMLAL */ |
| 4842 | {0, 0, 0}, /* VQDMLAL */ |
| 4843 | {0, 0, 0}, /* VMLSL */ |
| 4844 | {0, 0, 0}, /* VQDMLSL */ |
| 4845 | {0, 0, 0}, /* Integer VMULL */ |
| 4846 | {0, 0, 0}, /* VQDMULL */ |
| 4847 | {0, 0, 0} /* Polynomial VMULL */ |
| 4848 | }; |
| 4849 | |
| 4850 | prewiden = neon_3reg_wide[op][0]; |
| 4851 | src1_wide = neon_3reg_wide[op][1]; |
| 4852 | src2_wide = neon_3reg_wide[op][2]; |
| 4853 | |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4854 | if (size == 0 && (op == 9 || op == 11 || op == 13)) |
| 4855 | return 1; |
| 4856 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4857 | /* Avoid overlapping operands. Wide source operands are |
| 4858 | always aligned so will never overlap with wide |
| 4859 | destinations in problematic ways. */ |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 4860 | if (rd == rm && !src2_wide) { |
| 4861 | NEON_GET_REG(T0, rm, 1); |
| 4862 | gen_neon_movl_scratch_T0(2); |
| 4863 | } else if (rd == rn && !src1_wide) { |
| 4864 | NEON_GET_REG(T0, rn, 1); |
| 4865 | gen_neon_movl_scratch_T0(2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4866 | } |
pbrook | a50f5b9 | 2008-06-29 15:25:29 +0000 | [diff] [blame] | 4867 | TCGV_UNUSED(tmp3); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4868 | for (pass = 0; pass < 2; pass++) { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 4869 | if (src1_wide) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4870 | neon_load_reg64(cpu_V0, rn + pass); |
pbrook | a50f5b9 | 2008-06-29 15:25:29 +0000 | [diff] [blame] | 4871 | TCGV_UNUSED(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4872 | } else { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 4873 | if (pass == 1 && rd == rn) { |
| 4874 | gen_neon_movl_T0_scratch(2); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4875 | tmp = new_tmp(); |
| 4876 | tcg_gen_mov_i32(tmp, cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4877 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4878 | tmp = neon_load_reg(rn, pass); |
| 4879 | } |
| 4880 | if (prewiden) { |
| 4881 | gen_neon_widen(cpu_V0, tmp, size, u); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4882 | } |
| 4883 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4884 | if (src2_wide) { |
| 4885 | neon_load_reg64(cpu_V1, rm + pass); |
pbrook | a50f5b9 | 2008-06-29 15:25:29 +0000 | [diff] [blame] | 4886 | TCGV_UNUSED(tmp2); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4887 | } else { |
| 4888 | if (pass == 1 && rd == rm) { |
| 4889 | gen_neon_movl_T0_scratch(2); |
| 4890 | tmp2 = new_tmp(); |
| 4891 | tcg_gen_mov_i32(tmp2, cpu_T[0]); |
| 4892 | } else { |
| 4893 | tmp2 = neon_load_reg(rm, pass); |
| 4894 | } |
| 4895 | if (prewiden) { |
| 4896 | gen_neon_widen(cpu_V1, tmp2, size, u); |
| 4897 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4898 | } |
| 4899 | switch (op) { |
| 4900 | case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4901 | gen_neon_addl(size); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4902 | break; |
| 4903 | case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHL, VRSUBHL */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4904 | gen_neon_subl(size); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4905 | break; |
| 4906 | case 5: case 7: /* VABAL, VABDL */ |
| 4907 | switch ((size << 1) | u) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4908 | case 0: |
| 4909 | gen_helper_neon_abdl_s16(cpu_V0, tmp, tmp2); |
| 4910 | break; |
| 4911 | case 1: |
| 4912 | gen_helper_neon_abdl_u16(cpu_V0, tmp, tmp2); |
| 4913 | break; |
| 4914 | case 2: |
| 4915 | gen_helper_neon_abdl_s32(cpu_V0, tmp, tmp2); |
| 4916 | break; |
| 4917 | case 3: |
| 4918 | gen_helper_neon_abdl_u32(cpu_V0, tmp, tmp2); |
| 4919 | break; |
| 4920 | case 4: |
| 4921 | gen_helper_neon_abdl_s64(cpu_V0, tmp, tmp2); |
| 4922 | break; |
| 4923 | case 5: |
| 4924 | gen_helper_neon_abdl_u64(cpu_V0, tmp, tmp2); |
| 4925 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4926 | default: abort(); |
| 4927 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4928 | dead_tmp(tmp2); |
| 4929 | dead_tmp(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4930 | break; |
| 4931 | case 8: case 9: case 10: case 11: case 12: case 13: |
| 4932 | /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4933 | gen_neon_mull(cpu_V0, tmp, tmp2, size, u); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4934 | break; |
| 4935 | case 14: /* Polynomial VMULL */ |
| 4936 | cpu_abort(env, "Polynomial VMULL not implemented"); |
| 4937 | |
| 4938 | default: /* 15 is RESERVED. */ |
| 4939 | return 1; |
| 4940 | } |
| 4941 | if (op == 5 || op == 13 || (op >= 8 && op <= 11)) { |
| 4942 | /* Accumulate. */ |
| 4943 | if (op == 10 || op == 11) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4944 | gen_neon_negl(cpu_V0, size); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4945 | } |
| 4946 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4947 | if (op != 13) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4948 | neon_load_reg64(cpu_V1, rd + pass); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4949 | } |
| 4950 | |
| 4951 | switch (op) { |
| 4952 | case 5: case 8: case 10: /* VABAL, VMLAL, VMLSL */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4953 | gen_neon_addl(size); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4954 | break; |
| 4955 | case 9: case 11: /* VQDMLAL, VQDMLSL */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4956 | gen_neon_addl_saturate(cpu_V0, cpu_V0, size); |
| 4957 | gen_neon_addl_saturate(cpu_V0, cpu_V1, size); |
| 4958 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4959 | /* Fall through. */ |
| 4960 | case 13: /* VQDMULL */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4961 | gen_neon_addl_saturate(cpu_V0, cpu_V0, size); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4962 | break; |
| 4963 | default: |
| 4964 | abort(); |
| 4965 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4966 | neon_store_reg64(cpu_V0, rd + pass); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4967 | } else if (op == 4 || op == 6) { |
| 4968 | /* Narrowing operation. */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4969 | tmp = new_tmp(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4970 | if (u) { |
| 4971 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4972 | case 0: |
| 4973 | gen_helper_neon_narrow_high_u8(tmp, cpu_V0); |
| 4974 | break; |
| 4975 | case 1: |
| 4976 | gen_helper_neon_narrow_high_u16(tmp, cpu_V0); |
| 4977 | break; |
| 4978 | case 2: |
| 4979 | tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); |
| 4980 | tcg_gen_trunc_i64_i32(tmp, cpu_V0); |
| 4981 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4982 | default: abort(); |
| 4983 | } |
| 4984 | } else { |
| 4985 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 4986 | case 0: |
| 4987 | gen_helper_neon_narrow_round_high_u8(tmp, cpu_V0); |
| 4988 | break; |
| 4989 | case 1: |
| 4990 | gen_helper_neon_narrow_round_high_u16(tmp, cpu_V0); |
| 4991 | break; |
| 4992 | case 2: |
| 4993 | tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31); |
| 4994 | tcg_gen_shri_i64(cpu_V0, cpu_V0, 32); |
| 4995 | tcg_gen_trunc_i64_i32(tmp, cpu_V0); |
| 4996 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 4997 | default: abort(); |
| 4998 | } |
| 4999 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5000 | if (pass == 0) { |
| 5001 | tmp3 = tmp; |
| 5002 | } else { |
| 5003 | neon_store_reg(rd, 0, tmp3); |
| 5004 | neon_store_reg(rd, 1, tmp); |
| 5005 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5006 | } else { |
| 5007 | /* Write back the result. */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5008 | neon_store_reg64(cpu_V0, rd + pass); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5009 | } |
| 5010 | } |
| 5011 | } else { |
| 5012 | /* Two registers and a scalar. */ |
| 5013 | switch (op) { |
| 5014 | case 0: /* Integer VMLA scalar */ |
| 5015 | case 1: /* Float VMLA scalar */ |
| 5016 | case 4: /* Integer VMLS scalar */ |
| 5017 | case 5: /* Floating point VMLS scalar */ |
| 5018 | case 8: /* Integer VMUL scalar */ |
| 5019 | case 9: /* Floating point VMUL scalar */ |
| 5020 | case 12: /* VQDMULH scalar */ |
| 5021 | case 13: /* VQRDMULH scalar */ |
| 5022 | gen_neon_get_scalar(size, rm); |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 5023 | gen_neon_movl_scratch_T0(0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5024 | for (pass = 0; pass < (u ? 4 : 2); pass++) { |
| 5025 | if (pass != 0) |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 5026 | gen_neon_movl_T0_scratch(0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5027 | NEON_GET_REG(T1, rn, pass); |
| 5028 | if (op == 12) { |
| 5029 | if (size == 1) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5030 | gen_helper_neon_qdmulh_s16(CPU_T0E01); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5031 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5032 | gen_helper_neon_qdmulh_s32(CPU_T0E01); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5033 | } |
| 5034 | } else if (op == 13) { |
| 5035 | if (size == 1) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5036 | gen_helper_neon_qrdmulh_s16(CPU_T0E01); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5037 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5038 | gen_helper_neon_qrdmulh_s32(CPU_T0E01); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5039 | } |
| 5040 | } else if (op & 1) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5041 | gen_helper_neon_mul_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5042 | } else { |
| 5043 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5044 | case 0: gen_helper_neon_mul_u8(CPU_T001); break; |
| 5045 | case 1: gen_helper_neon_mul_u16(CPU_T001); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5046 | case 2: gen_op_mul_T0_T1(); break; |
| 5047 | default: return 1; |
| 5048 | } |
| 5049 | } |
| 5050 | if (op < 8) { |
| 5051 | /* Accumulate. */ |
| 5052 | NEON_GET_REG(T1, rd, pass); |
| 5053 | switch (op) { |
| 5054 | case 0: |
| 5055 | gen_neon_add(size); |
| 5056 | break; |
| 5057 | case 1: |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5058 | gen_helper_neon_add_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5059 | break; |
| 5060 | case 4: |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5061 | gen_neon_rsb(size); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5062 | break; |
| 5063 | case 5: |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5064 | gen_helper_neon_sub_f32(cpu_T[0], cpu_T[1], cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5065 | break; |
| 5066 | default: |
| 5067 | abort(); |
| 5068 | } |
| 5069 | } |
| 5070 | NEON_SET_REG(T0, rd, pass); |
| 5071 | } |
| 5072 | break; |
| 5073 | case 2: /* VMLAL sclar */ |
| 5074 | case 3: /* VQDMLAL scalar */ |
| 5075 | case 6: /* VMLSL scalar */ |
| 5076 | case 7: /* VQDMLSL scalar */ |
| 5077 | case 10: /* VMULL scalar */ |
| 5078 | case 11: /* VQDMULL scalar */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5079 | if (size == 0 && (op == 3 || op == 7 || op == 11)) |
| 5080 | return 1; |
| 5081 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5082 | gen_neon_get_scalar(size, rm); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5083 | NEON_GET_REG(T1, rn, 1); |
| 5084 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5085 | for (pass = 0; pass < 2; pass++) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5086 | if (pass == 0) { |
| 5087 | tmp = neon_load_reg(rn, 0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5088 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5089 | tmp = new_tmp(); |
| 5090 | tcg_gen_mov_i32(tmp, cpu_T[1]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5091 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5092 | tmp2 = new_tmp(); |
| 5093 | tcg_gen_mov_i32(tmp2, cpu_T[0]); |
| 5094 | gen_neon_mull(cpu_V0, tmp, tmp2, size, u); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5095 | if (op == 6 || op == 7) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5096 | gen_neon_negl(cpu_V0, size); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5097 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5098 | if (op != 11) { |
| 5099 | neon_load_reg64(cpu_V1, rd + pass); |
| 5100 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5101 | switch (op) { |
| 5102 | case 2: case 6: |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5103 | gen_neon_addl(size); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5104 | break; |
| 5105 | case 3: case 7: |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5106 | gen_neon_addl_saturate(cpu_V0, cpu_V0, size); |
| 5107 | gen_neon_addl_saturate(cpu_V0, cpu_V1, size); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5108 | break; |
| 5109 | case 10: |
| 5110 | /* no-op */ |
| 5111 | break; |
| 5112 | case 11: |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5113 | gen_neon_addl_saturate(cpu_V0, cpu_V0, size); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5114 | break; |
| 5115 | default: |
| 5116 | abort(); |
| 5117 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5118 | neon_store_reg64(cpu_V0, rd + pass); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5119 | } |
| 5120 | break; |
| 5121 | default: /* 14 and 15 are RESERVED */ |
| 5122 | return 1; |
| 5123 | } |
| 5124 | } |
| 5125 | } else { /* size == 3 */ |
| 5126 | if (!u) { |
| 5127 | /* Extract. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5128 | imm = (insn >> 8) & 0xf; |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5129 | count = q + 1; |
| 5130 | |
| 5131 | if (imm > 7 && !q) |
| 5132 | return 1; |
| 5133 | |
| 5134 | if (imm == 0) { |
| 5135 | neon_load_reg64(cpu_V0, rn); |
| 5136 | if (q) { |
| 5137 | neon_load_reg64(cpu_V1, rn + 1); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5138 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5139 | } else if (imm == 8) { |
| 5140 | neon_load_reg64(cpu_V0, rn + 1); |
| 5141 | if (q) { |
| 5142 | neon_load_reg64(cpu_V1, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5143 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5144 | } else if (q) { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5145 | tmp64 = tcg_temp_new_i64(); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5146 | if (imm < 8) { |
| 5147 | neon_load_reg64(cpu_V0, rn); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5148 | neon_load_reg64(tmp64, rn + 1); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5149 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5150 | neon_load_reg64(cpu_V0, rn + 1); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5151 | neon_load_reg64(tmp64, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5152 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5153 | tcg_gen_shri_i64(cpu_V0, cpu_V0, (imm & 7) * 8); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5154 | tcg_gen_shli_i64(cpu_V1, tmp64, 64 - ((imm & 7) * 8)); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5155 | tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); |
| 5156 | if (imm < 8) { |
| 5157 | neon_load_reg64(cpu_V1, rm); |
| 5158 | } else { |
| 5159 | neon_load_reg64(cpu_V1, rm + 1); |
| 5160 | imm -= 8; |
| 5161 | } |
| 5162 | tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8)); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5163 | tcg_gen_shri_i64(tmp64, tmp64, imm * 8); |
| 5164 | tcg_gen_or_i64(cpu_V1, cpu_V1, tmp64); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5165 | } else { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5166 | /* BUGFIX */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5167 | neon_load_reg64(cpu_V0, rn); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5168 | tcg_gen_shri_i64(cpu_V0, cpu_V0, imm * 8); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5169 | neon_load_reg64(cpu_V1, rm); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5170 | tcg_gen_shli_i64(cpu_V1, cpu_V1, 64 - (imm * 8)); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5171 | tcg_gen_or_i64(cpu_V0, cpu_V0, cpu_V1); |
| 5172 | } |
| 5173 | neon_store_reg64(cpu_V0, rd); |
| 5174 | if (q) { |
| 5175 | neon_store_reg64(cpu_V1, rd + 1); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5176 | } |
| 5177 | } else if ((insn & (1 << 11)) == 0) { |
| 5178 | /* Two register misc. */ |
| 5179 | op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf); |
| 5180 | size = (insn >> 18) & 3; |
| 5181 | switch (op) { |
| 5182 | case 0: /* VREV64 */ |
| 5183 | if (size == 3) |
| 5184 | return 1; |
| 5185 | for (pass = 0; pass < (q ? 2 : 1); pass++) { |
| 5186 | NEON_GET_REG(T0, rm, pass * 2); |
| 5187 | NEON_GET_REG(T1, rm, pass * 2 + 1); |
| 5188 | switch (size) { |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 5189 | case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break; |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 5190 | case 1: gen_swap_half(cpu_T[0]); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5191 | case 2: /* no-op */ break; |
| 5192 | default: abort(); |
| 5193 | } |
| 5194 | NEON_SET_REG(T0, rd, pass * 2 + 1); |
| 5195 | if (size == 2) { |
| 5196 | NEON_SET_REG(T1, rd, pass * 2); |
| 5197 | } else { |
| 5198 | gen_op_movl_T0_T1(); |
| 5199 | switch (size) { |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 5200 | case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break; |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 5201 | case 1: gen_swap_half(cpu_T[0]); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5202 | default: abort(); |
| 5203 | } |
| 5204 | NEON_SET_REG(T0, rd, pass * 2); |
| 5205 | } |
| 5206 | } |
| 5207 | break; |
| 5208 | case 4: case 5: /* VPADDL */ |
| 5209 | case 12: case 13: /* VPADAL */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5210 | if (size == 3) |
| 5211 | return 1; |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5212 | for (pass = 0; pass < q + 1; pass++) { |
| 5213 | tmp = neon_load_reg(rm, pass * 2); |
| 5214 | gen_neon_widen(cpu_V0, tmp, size, op & 1); |
| 5215 | tmp = neon_load_reg(rm, pass * 2 + 1); |
| 5216 | gen_neon_widen(cpu_V1, tmp, size, op & 1); |
| 5217 | switch (size) { |
| 5218 | case 0: gen_helper_neon_paddl_u16(CPU_V001); break; |
| 5219 | case 1: gen_helper_neon_paddl_u32(CPU_V001); break; |
| 5220 | case 2: tcg_gen_add_i64(CPU_V001); break; |
| 5221 | default: abort(); |
| 5222 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5223 | if (op >= 12) { |
| 5224 | /* Accumulate. */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5225 | neon_load_reg64(cpu_V1, rd + pass); |
| 5226 | gen_neon_addl(size); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5227 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5228 | neon_store_reg64(cpu_V0, rd + pass); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5229 | } |
| 5230 | break; |
| 5231 | case 33: /* VTRN */ |
| 5232 | if (size == 2) { |
| 5233 | for (n = 0; n < (q ? 4 : 2); n += 2) { |
| 5234 | NEON_GET_REG(T0, rm, n); |
| 5235 | NEON_GET_REG(T1, rd, n + 1); |
| 5236 | NEON_SET_REG(T1, rm, n); |
| 5237 | NEON_SET_REG(T0, rd, n + 1); |
| 5238 | } |
| 5239 | } else { |
| 5240 | goto elementwise; |
| 5241 | } |
| 5242 | break; |
| 5243 | case 34: /* VUZP */ |
| 5244 | /* Reg Before After |
| 5245 | Rd A3 A2 A1 A0 B2 B0 A2 A0 |
| 5246 | Rm B3 B2 B1 B0 B3 B1 A3 A1 |
| 5247 | */ |
| 5248 | if (size == 3) |
| 5249 | return 1; |
| 5250 | gen_neon_unzip(rd, q, 0, size); |
| 5251 | gen_neon_unzip(rm, q, 4, size); |
| 5252 | if (q) { |
| 5253 | static int unzip_order_q[8] = |
| 5254 | {0, 2, 4, 6, 1, 3, 5, 7}; |
| 5255 | for (n = 0; n < 8; n++) { |
| 5256 | int reg = (n < 4) ? rd : rm; |
| 5257 | gen_neon_movl_T0_scratch(unzip_order_q[n]); |
| 5258 | NEON_SET_REG(T0, reg, n % 4); |
| 5259 | } |
| 5260 | } else { |
| 5261 | static int unzip_order[4] = |
| 5262 | {0, 4, 1, 5}; |
| 5263 | for (n = 0; n < 4; n++) { |
| 5264 | int reg = (n < 2) ? rd : rm; |
| 5265 | gen_neon_movl_T0_scratch(unzip_order[n]); |
| 5266 | NEON_SET_REG(T0, reg, n % 2); |
| 5267 | } |
| 5268 | } |
| 5269 | break; |
| 5270 | case 35: /* VZIP */ |
| 5271 | /* Reg Before After |
| 5272 | Rd A3 A2 A1 A0 B1 A1 B0 A0 |
| 5273 | Rm B3 B2 B1 B0 B3 A3 B2 A2 |
| 5274 | */ |
| 5275 | if (size == 3) |
| 5276 | return 1; |
| 5277 | count = (q ? 4 : 2); |
| 5278 | for (n = 0; n < count; n++) { |
| 5279 | NEON_GET_REG(T0, rd, n); |
| 5280 | NEON_GET_REG(T1, rd, n); |
| 5281 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5282 | case 0: gen_helper_neon_zip_u8(); break; |
| 5283 | case 1: gen_helper_neon_zip_u16(); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5284 | case 2: /* no-op */; break; |
| 5285 | default: abort(); |
| 5286 | } |
| 5287 | gen_neon_movl_scratch_T0(n * 2); |
| 5288 | gen_neon_movl_scratch_T1(n * 2 + 1); |
| 5289 | } |
| 5290 | for (n = 0; n < count * 2; n++) { |
| 5291 | int reg = (n < count) ? rd : rm; |
| 5292 | gen_neon_movl_T0_scratch(n); |
| 5293 | NEON_SET_REG(T0, reg, n % count); |
| 5294 | } |
| 5295 | break; |
| 5296 | case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5297 | if (size == 3) |
| 5298 | return 1; |
pbrook | a50f5b9 | 2008-06-29 15:25:29 +0000 | [diff] [blame] | 5299 | TCGV_UNUSED(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5300 | for (pass = 0; pass < 2; pass++) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5301 | neon_load_reg64(cpu_V0, rm + pass); |
| 5302 | tmp = new_tmp(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5303 | if (op == 36 && q == 0) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5304 | gen_neon_narrow(size, tmp, cpu_V0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5305 | } else if (q) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5306 | gen_neon_narrow_satu(size, tmp, cpu_V0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5307 | } else { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5308 | gen_neon_narrow_sats(size, tmp, cpu_V0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5309 | } |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5310 | if (pass == 0) { |
| 5311 | tmp2 = tmp; |
| 5312 | } else { |
| 5313 | neon_store_reg(rd, 0, tmp2); |
| 5314 | neon_store_reg(rd, 1, tmp); |
| 5315 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5316 | } |
| 5317 | break; |
| 5318 | case 38: /* VSHLL */ |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5319 | if (q || size == 3) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5320 | return 1; |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5321 | tmp = neon_load_reg(rm, 0); |
| 5322 | tmp2 = neon_load_reg(rm, 1); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5323 | for (pass = 0; pass < 2; pass++) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5324 | if (pass == 1) |
| 5325 | tmp = tmp2; |
| 5326 | gen_neon_widen(cpu_V0, tmp, size, 1); |
| 5327 | neon_store_reg64(cpu_V0, rd + pass); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5328 | } |
| 5329 | break; |
| 5330 | default: |
| 5331 | elementwise: |
| 5332 | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
| 5333 | if (op == 30 || op == 31 || op >= 58) { |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 5334 | tcg_gen_ld_f32(cpu_F0s, cpu_env, |
| 5335 | neon_reg_offset(rm, pass)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5336 | } else { |
| 5337 | NEON_GET_REG(T0, rm, pass); |
| 5338 | } |
| 5339 | switch (op) { |
| 5340 | case 1: /* VREV32 */ |
| 5341 | switch (size) { |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 5342 | case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break; |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 5343 | case 1: gen_swap_half(cpu_T[0]); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5344 | default: return 1; |
| 5345 | } |
| 5346 | break; |
| 5347 | case 2: /* VREV16 */ |
| 5348 | if (size != 0) |
| 5349 | return 1; |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 5350 | gen_rev16(cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5351 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5352 | case 8: /* CLS */ |
| 5353 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5354 | case 0: gen_helper_neon_cls_s8(cpu_T[0], cpu_T[0]); break; |
| 5355 | case 1: gen_helper_neon_cls_s16(cpu_T[0], cpu_T[0]); break; |
| 5356 | case 2: gen_helper_neon_cls_s32(cpu_T[0], cpu_T[0]); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5357 | default: return 1; |
| 5358 | } |
| 5359 | break; |
| 5360 | case 9: /* CLZ */ |
| 5361 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5362 | case 0: gen_helper_neon_clz_u8(cpu_T[0], cpu_T[0]); break; |
| 5363 | case 1: gen_helper_neon_clz_u16(cpu_T[0], cpu_T[0]); break; |
pbrook | 1497c96 | 2008-03-31 03:45:50 +0000 | [diff] [blame] | 5364 | case 2: gen_helper_clz(cpu_T[0], cpu_T[0]); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5365 | default: return 1; |
| 5366 | } |
| 5367 | break; |
| 5368 | case 10: /* CNT */ |
| 5369 | if (size != 0) |
| 5370 | return 1; |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5371 | gen_helper_neon_cnt_u8(cpu_T[0], cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5372 | break; |
| 5373 | case 11: /* VNOT */ |
| 5374 | if (size != 0) |
| 5375 | return 1; |
| 5376 | gen_op_notl_T0(); |
| 5377 | break; |
| 5378 | case 14: /* VQABS */ |
| 5379 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5380 | case 0: gen_helper_neon_qabs_s8(cpu_T[0], cpu_env, cpu_T[0]); break; |
| 5381 | case 1: gen_helper_neon_qabs_s16(cpu_T[0], cpu_env, cpu_T[0]); break; |
| 5382 | case 2: gen_helper_neon_qabs_s32(cpu_T[0], cpu_env, cpu_T[0]); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5383 | default: return 1; |
| 5384 | } |
| 5385 | break; |
| 5386 | case 15: /* VQNEG */ |
| 5387 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5388 | case 0: gen_helper_neon_qneg_s8(cpu_T[0], cpu_env, cpu_T[0]); break; |
| 5389 | case 1: gen_helper_neon_qneg_s16(cpu_T[0], cpu_env, cpu_T[0]); break; |
| 5390 | case 2: gen_helper_neon_qneg_s32(cpu_T[0], cpu_env, cpu_T[0]); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5391 | default: return 1; |
| 5392 | } |
| 5393 | break; |
| 5394 | case 16: case 19: /* VCGT #0, VCLE #0 */ |
| 5395 | gen_op_movl_T1_im(0); |
| 5396 | switch(size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5397 | case 0: gen_helper_neon_cgt_s8(CPU_T001); break; |
| 5398 | case 1: gen_helper_neon_cgt_s16(CPU_T001); break; |
| 5399 | case 2: gen_helper_neon_cgt_s32(CPU_T001); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5400 | default: return 1; |
| 5401 | } |
| 5402 | if (op == 19) |
| 5403 | gen_op_notl_T0(); |
| 5404 | break; |
| 5405 | case 17: case 20: /* VCGE #0, VCLT #0 */ |
| 5406 | gen_op_movl_T1_im(0); |
| 5407 | switch(size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5408 | case 0: gen_helper_neon_cge_s8(CPU_T001); break; |
| 5409 | case 1: gen_helper_neon_cge_s16(CPU_T001); break; |
| 5410 | case 2: gen_helper_neon_cge_s32(CPU_T001); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5411 | default: return 1; |
| 5412 | } |
| 5413 | if (op == 20) |
| 5414 | gen_op_notl_T0(); |
| 5415 | break; |
| 5416 | case 18: /* VCEQ #0 */ |
| 5417 | gen_op_movl_T1_im(0); |
| 5418 | switch(size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5419 | case 0: gen_helper_neon_ceq_u8(CPU_T001); break; |
| 5420 | case 1: gen_helper_neon_ceq_u16(CPU_T001); break; |
| 5421 | case 2: gen_helper_neon_ceq_u32(CPU_T001); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5422 | default: return 1; |
| 5423 | } |
| 5424 | break; |
| 5425 | case 22: /* VABS */ |
| 5426 | switch(size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5427 | case 0: gen_helper_neon_abs_s8(cpu_T[0], cpu_T[0]); break; |
| 5428 | case 1: gen_helper_neon_abs_s16(cpu_T[0], cpu_T[0]); break; |
| 5429 | case 2: tcg_gen_abs_i32(cpu_T[0], cpu_T[0]); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5430 | default: return 1; |
| 5431 | } |
| 5432 | break; |
| 5433 | case 23: /* VNEG */ |
| 5434 | gen_op_movl_T1_im(0); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5435 | if (size == 3) |
| 5436 | return 1; |
| 5437 | gen_neon_rsb(size); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5438 | break; |
| 5439 | case 24: case 27: /* Float VCGT #0, Float VCLE #0 */ |
| 5440 | gen_op_movl_T1_im(0); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5441 | gen_helper_neon_cgt_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5442 | if (op == 27) |
| 5443 | gen_op_notl_T0(); |
| 5444 | break; |
| 5445 | case 25: case 28: /* Float VCGE #0, Float VCLT #0 */ |
| 5446 | gen_op_movl_T1_im(0); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5447 | gen_helper_neon_cge_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5448 | if (op == 28) |
| 5449 | gen_op_notl_T0(); |
| 5450 | break; |
| 5451 | case 26: /* Float VCEQ #0 */ |
| 5452 | gen_op_movl_T1_im(0); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5453 | gen_helper_neon_ceq_f32(CPU_T001); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5454 | break; |
| 5455 | case 30: /* Float VABS */ |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 5456 | gen_vfp_abs(0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5457 | break; |
| 5458 | case 31: /* Float VNEG */ |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 5459 | gen_vfp_neg(0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5460 | break; |
| 5461 | case 32: /* VSWP */ |
| 5462 | NEON_GET_REG(T1, rd, pass); |
| 5463 | NEON_SET_REG(T1, rm, pass); |
| 5464 | break; |
| 5465 | case 33: /* VTRN */ |
| 5466 | NEON_GET_REG(T1, rd, pass); |
| 5467 | switch (size) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5468 | case 0: gen_helper_neon_trn_u8(); break; |
| 5469 | case 1: gen_helper_neon_trn_u16(); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5470 | case 2: abort(); |
| 5471 | default: return 1; |
| 5472 | } |
| 5473 | NEON_SET_REG(T1, rm, pass); |
| 5474 | break; |
| 5475 | case 56: /* Integer VRECPE */ |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 5476 | gen_helper_recpe_u32(cpu_T[0], cpu_T[0], cpu_env); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5477 | break; |
| 5478 | case 57: /* Integer VRSQRTE */ |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 5479 | gen_helper_rsqrte_u32(cpu_T[0], cpu_T[0], cpu_env); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5480 | break; |
| 5481 | case 58: /* Float VRECPE */ |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 5482 | gen_helper_recpe_f32(cpu_F0s, cpu_F0s, cpu_env); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5483 | break; |
| 5484 | case 59: /* Float VRSQRTE */ |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 5485 | gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, cpu_env); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5486 | break; |
| 5487 | case 60: /* VCVT.F32.S32 */ |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 5488 | gen_vfp_tosiz(0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5489 | break; |
| 5490 | case 61: /* VCVT.F32.U32 */ |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 5491 | gen_vfp_touiz(0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5492 | break; |
| 5493 | case 62: /* VCVT.S32.F32 */ |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 5494 | gen_vfp_sito(0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5495 | break; |
| 5496 | case 63: /* VCVT.U32.F32 */ |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 5497 | gen_vfp_uito(0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5498 | break; |
| 5499 | default: |
| 5500 | /* Reserved: 21, 29, 39-56 */ |
| 5501 | return 1; |
| 5502 | } |
| 5503 | if (op == 30 || op == 31 || op >= 58) { |
pbrook | 4373f3c | 2008-03-31 03:47:19 +0000 | [diff] [blame] | 5504 | tcg_gen_st_f32(cpu_F0s, cpu_env, |
| 5505 | neon_reg_offset(rd, pass)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5506 | } else { |
| 5507 | NEON_SET_REG(T0, rd, pass); |
| 5508 | } |
| 5509 | } |
| 5510 | break; |
| 5511 | } |
| 5512 | } else if ((insn & (1 << 10)) == 0) { |
| 5513 | /* VTBL, VTBX. */ |
pbrook | 3018f25 | 2008-09-22 00:52:42 +0000 | [diff] [blame] | 5514 | n = ((insn >> 5) & 0x18) + 8; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5515 | if (insn & (1 << 6)) { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 5516 | tmp = neon_load_reg(rd, 0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5517 | } else { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 5518 | tmp = new_tmp(); |
| 5519 | tcg_gen_movi_i32(tmp, 0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5520 | } |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 5521 | tmp2 = neon_load_reg(rm, 0); |
| 5522 | gen_helper_neon_tbl(tmp2, tmp2, tmp, tcg_const_i32(rn), |
| 5523 | tcg_const_i32(n)); |
pbrook | 3018f25 | 2008-09-22 00:52:42 +0000 | [diff] [blame] | 5524 | dead_tmp(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5525 | if (insn & (1 << 6)) { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 5526 | tmp = neon_load_reg(rd, 1); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5527 | } else { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 5528 | tmp = new_tmp(); |
| 5529 | tcg_gen_movi_i32(tmp, 0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5530 | } |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 5531 | tmp3 = neon_load_reg(rm, 1); |
| 5532 | gen_helper_neon_tbl(tmp3, tmp3, tmp, tcg_const_i32(rn), |
| 5533 | tcg_const_i32(n)); |
| 5534 | neon_store_reg(rd, 0, tmp2); |
pbrook | 3018f25 | 2008-09-22 00:52:42 +0000 | [diff] [blame] | 5535 | neon_store_reg(rd, 1, tmp3); |
| 5536 | dead_tmp(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5537 | } else if ((insn & 0x380) == 0) { |
| 5538 | /* VDUP */ |
| 5539 | if (insn & (1 << 19)) { |
| 5540 | NEON_SET_REG(T0, rm, 1); |
| 5541 | } else { |
| 5542 | NEON_SET_REG(T0, rm, 0); |
| 5543 | } |
| 5544 | if (insn & (1 << 16)) { |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5545 | gen_neon_dup_u8(cpu_T[0], ((insn >> 17) & 3) * 8); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5546 | } else if (insn & (1 << 17)) { |
| 5547 | if ((insn >> 18) & 1) |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5548 | gen_neon_dup_high16(cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5549 | else |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 5550 | gen_neon_dup_low16(cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5551 | } |
| 5552 | for (pass = 0; pass < (q ? 4 : 2); pass++) { |
| 5553 | NEON_SET_REG(T0, rd, pass); |
| 5554 | } |
| 5555 | } else { |
| 5556 | return 1; |
| 5557 | } |
| 5558 | } |
| 5559 | } |
| 5560 | return 0; |
| 5561 | } |
| 5562 | |
pbrook | fe1479c | 2008-12-19 13:18:36 +0000 | [diff] [blame] | 5563 | static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn) |
| 5564 | { |
| 5565 | int crn = (insn >> 16) & 0xf; |
| 5566 | int crm = insn & 0xf; |
| 5567 | int op1 = (insn >> 21) & 7; |
| 5568 | int op2 = (insn >> 5) & 7; |
| 5569 | int rt = (insn >> 12) & 0xf; |
| 5570 | TCGv tmp; |
| 5571 | |
| 5572 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
| 5573 | if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) { |
| 5574 | /* TEECR */ |
| 5575 | if (IS_USER(s)) |
| 5576 | return 1; |
| 5577 | tmp = load_cpu_field(teecr); |
| 5578 | store_reg(s, rt, tmp); |
| 5579 | return 0; |
| 5580 | } |
| 5581 | if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) { |
| 5582 | /* TEEHBR */ |
| 5583 | if (IS_USER(s) && (env->teecr & 1)) |
| 5584 | return 1; |
| 5585 | tmp = load_cpu_field(teehbr); |
| 5586 | store_reg(s, rt, tmp); |
| 5587 | return 0; |
| 5588 | } |
| 5589 | } |
| 5590 | fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n", |
| 5591 | op1, crn, crm, op2); |
| 5592 | return 1; |
| 5593 | } |
| 5594 | |
| 5595 | static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn) |
| 5596 | { |
| 5597 | int crn = (insn >> 16) & 0xf; |
| 5598 | int crm = insn & 0xf; |
| 5599 | int op1 = (insn >> 21) & 7; |
| 5600 | int op2 = (insn >> 5) & 7; |
| 5601 | int rt = (insn >> 12) & 0xf; |
| 5602 | TCGv tmp; |
| 5603 | |
| 5604 | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { |
| 5605 | if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) { |
| 5606 | /* TEECR */ |
| 5607 | if (IS_USER(s)) |
| 5608 | return 1; |
| 5609 | tmp = load_reg(s, rt); |
| 5610 | gen_helper_set_teecr(cpu_env, tmp); |
| 5611 | dead_tmp(tmp); |
| 5612 | return 0; |
| 5613 | } |
| 5614 | if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) { |
| 5615 | /* TEEHBR */ |
| 5616 | if (IS_USER(s) && (env->teecr & 1)) |
| 5617 | return 1; |
| 5618 | tmp = load_reg(s, rt); |
| 5619 | store_cpu_field(tmp, teehbr); |
| 5620 | return 0; |
| 5621 | } |
| 5622 | } |
| 5623 | fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n", |
| 5624 | op1, crn, crm, op2); |
| 5625 | return 1; |
| 5626 | } |
| 5627 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5628 | static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn) |
| 5629 | { |
| 5630 | int cpnum; |
| 5631 | |
| 5632 | cpnum = (insn >> 8) & 0xf; |
| 5633 | if (arm_feature(env, ARM_FEATURE_XSCALE) |
| 5634 | && ((env->cp15.c15_cpar ^ 0x3fff) & (1 << cpnum))) |
| 5635 | return 1; |
| 5636 | |
| 5637 | switch (cpnum) { |
| 5638 | case 0: |
| 5639 | case 1: |
| 5640 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { |
| 5641 | return disas_iwmmxt_insn(env, s, insn); |
| 5642 | } else if (arm_feature(env, ARM_FEATURE_XSCALE)) { |
| 5643 | return disas_dsp_insn(env, s, insn); |
| 5644 | } |
| 5645 | return 1; |
| 5646 | case 10: |
| 5647 | case 11: |
| 5648 | return disas_vfp_insn (env, s, insn); |
pbrook | fe1479c | 2008-12-19 13:18:36 +0000 | [diff] [blame] | 5649 | case 14: |
| 5650 | /* Coprocessors 7-15 are architecturally reserved by ARM. |
| 5651 | Unfortunately Intel decided to ignore this. */ |
| 5652 | if (arm_feature(env, ARM_FEATURE_XSCALE)) |
| 5653 | goto board; |
| 5654 | if (insn & (1 << 20)) |
| 5655 | return disas_cp14_read(env, s, insn); |
| 5656 | else |
| 5657 | return disas_cp14_write(env, s, insn); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5658 | case 15: |
| 5659 | return disas_cp15_insn (env, s, insn); |
| 5660 | default: |
pbrook | fe1479c | 2008-12-19 13:18:36 +0000 | [diff] [blame] | 5661 | board: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5662 | /* Unknown coprocessor. See if the board has hooked it. */ |
| 5663 | return disas_cp_insn (env, s, insn); |
| 5664 | } |
| 5665 | } |
| 5666 | |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 5667 | |
| 5668 | /* Store a 64-bit value to a register pair. Clobbers val. */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5669 | static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 5670 | { |
| 5671 | TCGv tmp; |
| 5672 | tmp = new_tmp(); |
| 5673 | tcg_gen_trunc_i64_i32(tmp, val); |
| 5674 | store_reg(s, rlow, tmp); |
| 5675 | tmp = new_tmp(); |
| 5676 | tcg_gen_shri_i64(val, val, 32); |
| 5677 | tcg_gen_trunc_i64_i32(tmp, val); |
| 5678 | store_reg(s, rhigh, tmp); |
| 5679 | } |
| 5680 | |
| 5681 | /* load a 32-bit value from a register and perform a 64-bit accumulate. */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5682 | static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 5683 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5684 | TCGv_i64 tmp; |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 5685 | TCGv tmp2; |
| 5686 | |
pbrook | 36aa55d | 2008-09-21 13:48:32 +0000 | [diff] [blame] | 5687 | /* Load value and extend to 64 bits. */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5688 | tmp = tcg_temp_new_i64(); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 5689 | tmp2 = load_reg(s, rlow); |
| 5690 | tcg_gen_extu_i32_i64(tmp, tmp2); |
| 5691 | dead_tmp(tmp2); |
| 5692 | tcg_gen_add_i64(val, val, tmp); |
| 5693 | } |
| 5694 | |
| 5695 | /* load and add a 64-bit value from a register pair. */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5696 | static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 5697 | { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5698 | TCGv_i64 tmp; |
pbrook | 36aa55d | 2008-09-21 13:48:32 +0000 | [diff] [blame] | 5699 | TCGv tmpl; |
| 5700 | TCGv tmph; |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 5701 | |
| 5702 | /* Load 64-bit value rd:rn. */ |
pbrook | 36aa55d | 2008-09-21 13:48:32 +0000 | [diff] [blame] | 5703 | tmpl = load_reg(s, rlow); |
| 5704 | tmph = load_reg(s, rhigh); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5705 | tmp = tcg_temp_new_i64(); |
pbrook | 36aa55d | 2008-09-21 13:48:32 +0000 | [diff] [blame] | 5706 | tcg_gen_concat_i32_i64(tmp, tmpl, tmph); |
| 5707 | dead_tmp(tmpl); |
| 5708 | dead_tmp(tmph); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 5709 | tcg_gen_add_i64(val, val, tmp); |
| 5710 | } |
| 5711 | |
| 5712 | /* Set N and Z flags from a 64-bit value. */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5713 | static void gen_logicq_cc(TCGv_i64 val) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 5714 | { |
| 5715 | TCGv tmp = new_tmp(); |
| 5716 | gen_helper_logicq_cc(tmp, val); |
pbrook | 6fbe23d | 2008-04-01 17:19:11 +0000 | [diff] [blame] | 5717 | gen_logic_CC(tmp); |
| 5718 | dead_tmp(tmp); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 5719 | } |
| 5720 | |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 5721 | static void disas_arm_insn(CPUState * env, DisasContext *s) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 5722 | { |
| 5723 | unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh; |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 5724 | TCGv tmp; |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 5725 | TCGv tmp2; |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 5726 | TCGv tmp3; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 5727 | TCGv addr; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 5728 | TCGv_i64 tmp64; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 5729 | |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 5730 | insn = ldl_code(s->pc); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 5731 | s->pc += 4; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 5732 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5733 | /* M variants do not implement ARM mode. */ |
| 5734 | if (IS_M(env)) |
| 5735 | goto illegal_op; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 5736 | cond = insn >> 28; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5737 | if (cond == 0xf){ |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 5738 | /* Unconditional instructions. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5739 | if (((insn >> 25) & 7) == 1) { |
| 5740 | /* NEON Data processing. */ |
| 5741 | if (!arm_feature(env, ARM_FEATURE_NEON)) |
| 5742 | goto illegal_op; |
| 5743 | |
| 5744 | if (disas_neon_data_insn(env, s, insn)) |
| 5745 | goto illegal_op; |
| 5746 | return; |
| 5747 | } |
| 5748 | if ((insn & 0x0f100000) == 0x04000000) { |
| 5749 | /* NEON load/store. */ |
| 5750 | if (!arm_feature(env, ARM_FEATURE_NEON)) |
| 5751 | goto illegal_op; |
| 5752 | |
| 5753 | if (disas_neon_ls_insn(env, s, insn)) |
| 5754 | goto illegal_op; |
| 5755 | return; |
| 5756 | } |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5757 | if ((insn & 0x0d70f000) == 0x0550f000) |
| 5758 | return; /* PLD */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5759 | else if ((insn & 0x0ffffdff) == 0x01010000) { |
| 5760 | ARCH(6); |
| 5761 | /* setend */ |
| 5762 | if (insn & (1 << 9)) { |
| 5763 | /* BE8 mode not implemented. */ |
| 5764 | goto illegal_op; |
| 5765 | } |
| 5766 | return; |
| 5767 | } else if ((insn & 0x0fffff00) == 0x057ff000) { |
| 5768 | switch ((insn >> 4) & 0xf) { |
| 5769 | case 1: /* clrex */ |
| 5770 | ARCH(6K); |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 5771 | gen_helper_clrex(cpu_env); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5772 | return; |
| 5773 | case 4: /* dsb */ |
| 5774 | case 5: /* dmb */ |
| 5775 | case 6: /* isb */ |
| 5776 | ARCH(7); |
| 5777 | /* We don't emulate caches so these are a no-op. */ |
| 5778 | return; |
| 5779 | default: |
| 5780 | goto illegal_op; |
| 5781 | } |
| 5782 | } else if ((insn & 0x0e5fffe0) == 0x084d0500) { |
| 5783 | /* srs */ |
| 5784 | uint32_t offset; |
| 5785 | if (IS_USER(s)) |
| 5786 | goto illegal_op; |
| 5787 | ARCH(6); |
| 5788 | op1 = (insn & 0x1f); |
| 5789 | if (op1 == (env->uncached_cpsr & CPSR_M)) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 5790 | addr = load_reg(s, 13); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5791 | } else { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 5792 | addr = new_tmp(); |
| 5793 | gen_helper_get_r13_banked(addr, cpu_env, tcg_const_i32(op1)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5794 | } |
| 5795 | i = (insn >> 23) & 3; |
| 5796 | switch (i) { |
| 5797 | case 0: offset = -4; break; /* DA */ |
| 5798 | case 1: offset = -8; break; /* DB */ |
| 5799 | case 2: offset = 0; break; /* IA */ |
| 5800 | case 3: offset = 4; break; /* IB */ |
| 5801 | default: abort(); |
| 5802 | } |
| 5803 | if (offset) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 5804 | tcg_gen_addi_i32(addr, addr, offset); |
| 5805 | tmp = load_reg(s, 14); |
| 5806 | gen_st32(tmp, addr, 0); |
| 5807 | tmp = new_tmp(); |
| 5808 | gen_helper_cpsr_read(tmp); |
| 5809 | tcg_gen_addi_i32(addr, addr, 4); |
| 5810 | gen_st32(tmp, addr, 0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5811 | if (insn & (1 << 21)) { |
| 5812 | /* Base writeback. */ |
| 5813 | switch (i) { |
| 5814 | case 0: offset = -8; break; |
| 5815 | case 1: offset = -4; break; |
| 5816 | case 2: offset = 4; break; |
| 5817 | case 3: offset = 0; break; |
| 5818 | default: abort(); |
| 5819 | } |
| 5820 | if (offset) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 5821 | tcg_gen_addi_i32(addr, tmp, offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5822 | if (op1 == (env->uncached_cpsr & CPSR_M)) { |
| 5823 | gen_movl_reg_T1(s, 13); |
| 5824 | } else { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 5825 | gen_helper_set_r13_banked(cpu_env, tcg_const_i32(op1), cpu_T[1]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5826 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 5827 | } else { |
| 5828 | dead_tmp(addr); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5829 | } |
| 5830 | } else if ((insn & 0x0e5fffe0) == 0x081d0a00) { |
| 5831 | /* rfe */ |
| 5832 | uint32_t offset; |
| 5833 | if (IS_USER(s)) |
| 5834 | goto illegal_op; |
| 5835 | ARCH(6); |
| 5836 | rn = (insn >> 16) & 0xf; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 5837 | addr = load_reg(s, rn); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5838 | i = (insn >> 23) & 3; |
| 5839 | switch (i) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 5840 | case 0: offset = -4; break; /* DA */ |
| 5841 | case 1: offset = -8; break; /* DB */ |
| 5842 | case 2: offset = 0; break; /* IA */ |
| 5843 | case 3: offset = 4; break; /* IB */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5844 | default: abort(); |
| 5845 | } |
| 5846 | if (offset) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 5847 | tcg_gen_addi_i32(addr, addr, offset); |
| 5848 | /* Load PC into tmp and CPSR into tmp2. */ |
| 5849 | tmp = gen_ld32(addr, 0); |
| 5850 | tcg_gen_addi_i32(addr, addr, 4); |
| 5851 | tmp2 = gen_ld32(addr, 0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5852 | if (insn & (1 << 21)) { |
| 5853 | /* Base writeback. */ |
| 5854 | switch (i) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 5855 | case 0: offset = -8; break; |
| 5856 | case 1: offset = -4; break; |
| 5857 | case 2: offset = 4; break; |
| 5858 | case 3: offset = 0; break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5859 | default: abort(); |
| 5860 | } |
| 5861 | if (offset) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 5862 | tcg_gen_addi_i32(addr, addr, offset); |
| 5863 | store_reg(s, rn, addr); |
| 5864 | } else { |
| 5865 | dead_tmp(addr); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5866 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 5867 | gen_rfe(s, tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5868 | } else if ((insn & 0x0e000000) == 0x0a000000) { |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5869 | /* branch link and change to thumb (blx <offset>) */ |
| 5870 | int32_t offset; |
| 5871 | |
| 5872 | val = (uint32_t)s->pc; |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 5873 | tmp = new_tmp(); |
| 5874 | tcg_gen_movi_i32(tmp, val); |
| 5875 | store_reg(s, 14, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5876 | /* Sign-extend the 24-bit offset */ |
| 5877 | offset = (((int32_t)insn) << 8) >> 8; |
| 5878 | /* offset * 4 + bit24 * 2 + (thumb bit) */ |
| 5879 | val += (offset << 2) | ((insn >> 23) & 2) | 1; |
| 5880 | /* pipeline offset */ |
| 5881 | val += 4; |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 5882 | gen_bx_im(s, val); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5883 | return; |
balrog | 2e23213 | 2007-08-01 02:31:54 +0000 | [diff] [blame] | 5884 | } else if ((insn & 0x0e000f00) == 0x0c000100) { |
| 5885 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) { |
| 5886 | /* iWMMXt register transfer. */ |
| 5887 | if (env->cp15.c15_cpar & (1 << 1)) |
| 5888 | if (!disas_iwmmxt_insn(env, s, insn)) |
| 5889 | return; |
| 5890 | } |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 5891 | } else if ((insn & 0x0fe00000) == 0x0c400000) { |
| 5892 | /* Coprocessor double register transfer. */ |
| 5893 | } else if ((insn & 0x0f000010) == 0x0e000010) { |
| 5894 | /* Additional coprocessor register transfer. */ |
balrog | 7997d92 | 2008-07-19 10:34:35 +0000 | [diff] [blame] | 5895 | } else if ((insn & 0x0ff10020) == 0x01000000) { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5896 | uint32_t mask; |
| 5897 | uint32_t val; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 5898 | /* cps (privileged) */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5899 | if (IS_USER(s)) |
| 5900 | return; |
| 5901 | mask = val = 0; |
| 5902 | if (insn & (1 << 19)) { |
| 5903 | if (insn & (1 << 8)) |
| 5904 | mask |= CPSR_A; |
| 5905 | if (insn & (1 << 7)) |
| 5906 | mask |= CPSR_I; |
| 5907 | if (insn & (1 << 6)) |
| 5908 | mask |= CPSR_F; |
| 5909 | if (insn & (1 << 18)) |
| 5910 | val |= mask; |
| 5911 | } |
balrog | 7997d92 | 2008-07-19 10:34:35 +0000 | [diff] [blame] | 5912 | if (insn & (1 << 17)) { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5913 | mask |= CPSR_M; |
| 5914 | val |= (insn & 0x1f); |
| 5915 | } |
| 5916 | if (mask) { |
| 5917 | gen_op_movl_T0_im(val); |
| 5918 | gen_set_psr_T0(s, mask, 0); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 5919 | } |
| 5920 | return; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5921 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 5922 | goto illegal_op; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5923 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 5924 | if (cond != 0xe) { |
| 5925 | /* if not always execute, we generate a conditional jump to |
| 5926 | next instruction */ |
bellard | e50e6a2 | 2005-04-26 20:36:11 +0000 | [diff] [blame] | 5927 | s->condlabel = gen_new_label(); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 5928 | gen_test_cc(cond ^ 1, s->condlabel); |
bellard | e50e6a2 | 2005-04-26 20:36:11 +0000 | [diff] [blame] | 5929 | s->condjmp = 1; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 5930 | } |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5931 | if ((insn & 0x0f900000) == 0x03000000) { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5932 | if ((insn & (1 << 21)) == 0) { |
| 5933 | ARCH(6T2); |
| 5934 | rd = (insn >> 12) & 0xf; |
| 5935 | val = ((insn >> 4) & 0xf000) | (insn & 0xfff); |
| 5936 | if ((insn & (1 << 22)) == 0) { |
| 5937 | /* MOVW */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 5938 | tmp = new_tmp(); |
| 5939 | tcg_gen_movi_i32(tmp, val); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5940 | } else { |
| 5941 | /* MOVT */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 5942 | tmp = load_reg(s, rd); |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 5943 | tcg_gen_ext16u_i32(tmp, tmp); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 5944 | tcg_gen_ori_i32(tmp, tmp, val << 16); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5945 | } |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 5946 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5947 | } else { |
| 5948 | if (((insn >> 12) & 0xf) != 0xf) |
| 5949 | goto illegal_op; |
| 5950 | if (((insn >> 16) & 0xf) == 0) { |
| 5951 | gen_nop_hint(s, insn & 0xff); |
| 5952 | } else { |
| 5953 | /* CPSR = immediate */ |
| 5954 | val = insn & 0xff; |
| 5955 | shift = ((insn >> 8) & 0xf) * 2; |
| 5956 | if (shift) |
| 5957 | val = (val >> shift) | (val << (32 - shift)); |
| 5958 | gen_op_movl_T0_im(val); |
| 5959 | i = ((insn & (1 << 22)) != 0); |
| 5960 | if (gen_set_psr_T0(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i)) |
| 5961 | goto illegal_op; |
| 5962 | } |
| 5963 | } |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5964 | } else if ((insn & 0x0f900000) == 0x01000000 |
| 5965 | && (insn & 0x00000090) != 0x00000090) { |
| 5966 | /* miscellaneous instructions */ |
| 5967 | op1 = (insn >> 21) & 3; |
| 5968 | sh = (insn >> 4) & 0xf; |
| 5969 | rm = insn & 0xf; |
| 5970 | switch (sh) { |
| 5971 | case 0x0: /* move program status register */ |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5972 | if (op1 & 1) { |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 5973 | /* PSR = reg */ |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5974 | gen_movl_T0_reg(s, rm); |
pbrook | 2ae23e7 | 2006-02-11 16:20:39 +0000 | [diff] [blame] | 5975 | i = ((op1 & 2) != 0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 5976 | if (gen_set_psr_T0(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i)) |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 5977 | goto illegal_op; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5978 | } else { |
pbrook | 2ae23e7 | 2006-02-11 16:20:39 +0000 | [diff] [blame] | 5979 | /* reg = PSR */ |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5980 | rd = (insn >> 12) & 0xf; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 5981 | if (op1 & 2) { |
| 5982 | if (IS_USER(s)) |
| 5983 | goto illegal_op; |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 5984 | tmp = load_cpu_field(spsr); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 5985 | } else { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 5986 | tmp = new_tmp(); |
| 5987 | gen_helper_cpsr_read(tmp); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 5988 | } |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 5989 | store_reg(s, rd, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5990 | } |
bellard | b8a9e8f | 2005-02-07 23:10:07 +0000 | [diff] [blame] | 5991 | break; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5992 | case 0x1: |
| 5993 | if (op1 == 1) { |
| 5994 | /* branch/exchange thumb (bx). */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 5995 | tmp = load_reg(s, rm); |
| 5996 | gen_bx(s, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 5997 | } else if (op1 == 3) { |
| 5998 | /* clz */ |
| 5999 | rd = (insn >> 12) & 0xf; |
pbrook | 1497c96 | 2008-03-31 03:45:50 +0000 | [diff] [blame] | 6000 | tmp = load_reg(s, rm); |
| 6001 | gen_helper_clz(tmp, tmp); |
| 6002 | store_reg(s, rd, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6003 | } else { |
| 6004 | goto illegal_op; |
| 6005 | } |
| 6006 | break; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6007 | case 0x2: |
| 6008 | if (op1 == 1) { |
| 6009 | ARCH(5J); /* bxj */ |
| 6010 | /* Trivial implementation equivalent to bx. */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 6011 | tmp = load_reg(s, rm); |
| 6012 | gen_bx(s, tmp); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6013 | } else { |
| 6014 | goto illegal_op; |
| 6015 | } |
| 6016 | break; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6017 | case 0x3: |
| 6018 | if (op1 != 1) |
| 6019 | goto illegal_op; |
| 6020 | |
| 6021 | /* branch link/exchange thumb (blx) */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 6022 | tmp = load_reg(s, rm); |
| 6023 | tmp2 = new_tmp(); |
| 6024 | tcg_gen_movi_i32(tmp2, s->pc); |
| 6025 | store_reg(s, 14, tmp2); |
| 6026 | gen_bx(s, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6027 | break; |
| 6028 | case 0x5: /* saturating add/subtract */ |
| 6029 | rd = (insn >> 12) & 0xf; |
| 6030 | rn = (insn >> 16) & 0xf; |
balrog | b40d035 | 2008-09-20 03:18:07 +0000 | [diff] [blame] | 6031 | tmp = load_reg(s, rm); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6032 | tmp2 = load_reg(s, rn); |
bellard | ff8263a | 2005-05-13 22:45:23 +0000 | [diff] [blame] | 6033 | if (op1 & 2) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6034 | gen_helper_double_saturate(tmp2, tmp2); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6035 | if (op1 & 1) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6036 | gen_helper_sub_saturate(tmp, tmp, tmp2); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6037 | else |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6038 | gen_helper_add_saturate(tmp, tmp, tmp2); |
| 6039 | dead_tmp(tmp2); |
| 6040 | store_reg(s, rd, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6041 | break; |
pbrook | 06c949e | 2006-02-04 19:35:26 +0000 | [diff] [blame] | 6042 | case 7: /* bkpt */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6043 | gen_set_condexec(s); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6044 | gen_set_pc_im(s->pc - 4); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 6045 | gen_exception(EXCP_BKPT); |
pbrook | 06c949e | 2006-02-04 19:35:26 +0000 | [diff] [blame] | 6046 | s->is_jmp = DISAS_JUMP; |
| 6047 | break; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6048 | case 0x8: /* signed multiply */ |
| 6049 | case 0xa: |
| 6050 | case 0xc: |
| 6051 | case 0xe: |
| 6052 | rs = (insn >> 8) & 0xf; |
| 6053 | rn = (insn >> 12) & 0xf; |
| 6054 | rd = (insn >> 16) & 0xf; |
| 6055 | if (op1 == 1) { |
| 6056 | /* (32 * 16) >> 16 */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6057 | tmp = load_reg(s, rm); |
| 6058 | tmp2 = load_reg(s, rs); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6059 | if (sh & 4) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6060 | tcg_gen_sari_i32(tmp2, tmp2, 16); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6061 | else |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6062 | gen_sxth(tmp2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6063 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
| 6064 | tcg_gen_shri_i64(tmp64, tmp64, 16); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6065 | tmp = new_tmp(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6066 | tcg_gen_trunc_i64_i32(tmp, tmp64); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6067 | if ((sh & 2) == 0) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6068 | tmp2 = load_reg(s, rn); |
| 6069 | gen_helper_add_setq(tmp, tmp, tmp2); |
| 6070 | dead_tmp(tmp2); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6071 | } |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6072 | store_reg(s, rd, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6073 | } else { |
| 6074 | /* 16 * 16 */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6075 | tmp = load_reg(s, rm); |
| 6076 | tmp2 = load_reg(s, rs); |
| 6077 | gen_mulxy(tmp, tmp2, sh & 2, sh & 4); |
| 6078 | dead_tmp(tmp2); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6079 | if (op1 == 2) { |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6080 | tmp64 = tcg_temp_new_i64(); |
| 6081 | tcg_gen_ext_i32_i64(tmp64, tmp); |
balrog | 22478e7 | 2008-07-19 10:12:22 +0000 | [diff] [blame] | 6082 | dead_tmp(tmp); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6083 | gen_addq(s, tmp64, rn, rd); |
| 6084 | gen_storeq_reg(s, rn, rd, tmp64); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6085 | } else { |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6086 | if (op1 == 0) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6087 | tmp2 = load_reg(s, rn); |
| 6088 | gen_helper_add_setq(tmp, tmp, tmp2); |
| 6089 | dead_tmp(tmp2); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6090 | } |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6091 | store_reg(s, rd, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6092 | } |
| 6093 | } |
| 6094 | break; |
| 6095 | default: |
| 6096 | goto illegal_op; |
| 6097 | } |
| 6098 | } else if (((insn & 0x0e000000) == 0 && |
| 6099 | (insn & 0x00000090) != 0x90) || |
| 6100 | ((insn & 0x0e000000) == (1 << 25))) { |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6101 | int set_cc, logic_cc, shiftop; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 6102 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6103 | op1 = (insn >> 21) & 0xf; |
| 6104 | set_cc = (insn >> 20) & 1; |
| 6105 | logic_cc = table_logic_cc[op1] & set_cc; |
| 6106 | |
| 6107 | /* data processing instruction */ |
| 6108 | if (insn & (1 << 25)) { |
| 6109 | /* immediate operand */ |
| 6110 | val = insn & 0xff; |
| 6111 | shift = ((insn >> 8) & 0xf) * 2; |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6112 | if (shift) { |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6113 | val = (val >> shift) | (val << (32 - shift)); |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6114 | } |
| 6115 | tmp2 = new_tmp(); |
| 6116 | tcg_gen_movi_i32(tmp2, val); |
| 6117 | if (logic_cc && shift) { |
| 6118 | gen_set_CF_bit31(tmp2); |
| 6119 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6120 | } else { |
| 6121 | /* register */ |
| 6122 | rm = (insn) & 0xf; |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6123 | tmp2 = load_reg(s, rm); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6124 | shiftop = (insn >> 5) & 3; |
| 6125 | if (!(insn & (1 << 4))) { |
| 6126 | shift = (insn >> 7) & 0x1f; |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6127 | gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6128 | } else { |
| 6129 | rs = (insn >> 8) & 0xf; |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 6130 | tmp = load_reg(s, rs); |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6131 | gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6132 | } |
| 6133 | } |
| 6134 | if (op1 != 0x0f && op1 != 0x0d) { |
| 6135 | rn = (insn >> 16) & 0xf; |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6136 | tmp = load_reg(s, rn); |
| 6137 | } else { |
| 6138 | TCGV_UNUSED(tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6139 | } |
| 6140 | rd = (insn >> 12) & 0xf; |
| 6141 | switch(op1) { |
| 6142 | case 0x00: |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6143 | tcg_gen_and_i32(tmp, tmp, tmp2); |
| 6144 | if (logic_cc) { |
| 6145 | gen_logic_CC(tmp); |
| 6146 | } |
Juha Riihimäki | 21aeb34 | 2009-05-06 09:16:12 +0300 | [diff] [blame] | 6147 | store_reg_bx(env, s, rd, tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6148 | break; |
| 6149 | case 0x01: |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6150 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
| 6151 | if (logic_cc) { |
| 6152 | gen_logic_CC(tmp); |
| 6153 | } |
Juha Riihimäki | 21aeb34 | 2009-05-06 09:16:12 +0300 | [diff] [blame] | 6154 | store_reg_bx(env, s, rd, tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6155 | break; |
| 6156 | case 0x02: |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6157 | if (set_cc && rd == 15) { |
| 6158 | /* SUBS r15, ... is used for exception return. */ |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6159 | if (IS_USER(s)) { |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6160 | goto illegal_op; |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6161 | } |
| 6162 | gen_helper_sub_cc(tmp, tmp, tmp2); |
| 6163 | gen_exception_return(s, tmp); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6164 | } else { |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6165 | if (set_cc) { |
| 6166 | gen_helper_sub_cc(tmp, tmp, tmp2); |
| 6167 | } else { |
| 6168 | tcg_gen_sub_i32(tmp, tmp, tmp2); |
| 6169 | } |
Juha Riihimäki | 21aeb34 | 2009-05-06 09:16:12 +0300 | [diff] [blame] | 6170 | store_reg_bx(env, s, rd, tmp); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6171 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6172 | break; |
| 6173 | case 0x03: |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6174 | if (set_cc) { |
| 6175 | gen_helper_sub_cc(tmp, tmp2, tmp); |
| 6176 | } else { |
| 6177 | tcg_gen_sub_i32(tmp, tmp2, tmp); |
| 6178 | } |
Juha Riihimäki | 21aeb34 | 2009-05-06 09:16:12 +0300 | [diff] [blame] | 6179 | store_reg_bx(env, s, rd, tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6180 | break; |
| 6181 | case 0x04: |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6182 | if (set_cc) { |
| 6183 | gen_helper_add_cc(tmp, tmp, tmp2); |
| 6184 | } else { |
| 6185 | tcg_gen_add_i32(tmp, tmp, tmp2); |
| 6186 | } |
Juha Riihimäki | 21aeb34 | 2009-05-06 09:16:12 +0300 | [diff] [blame] | 6187 | store_reg_bx(env, s, rd, tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6188 | break; |
| 6189 | case 0x05: |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6190 | if (set_cc) { |
| 6191 | gen_helper_adc_cc(tmp, tmp, tmp2); |
| 6192 | } else { |
| 6193 | gen_add_carry(tmp, tmp, tmp2); |
| 6194 | } |
Juha Riihimäki | 21aeb34 | 2009-05-06 09:16:12 +0300 | [diff] [blame] | 6195 | store_reg_bx(env, s, rd, tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6196 | break; |
| 6197 | case 0x06: |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6198 | if (set_cc) { |
| 6199 | gen_helper_sbc_cc(tmp, tmp, tmp2); |
| 6200 | } else { |
| 6201 | gen_sub_carry(tmp, tmp, tmp2); |
| 6202 | } |
Juha Riihimäki | 21aeb34 | 2009-05-06 09:16:12 +0300 | [diff] [blame] | 6203 | store_reg_bx(env, s, rd, tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6204 | break; |
| 6205 | case 0x07: |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6206 | if (set_cc) { |
| 6207 | gen_helper_sbc_cc(tmp, tmp2, tmp); |
| 6208 | } else { |
| 6209 | gen_sub_carry(tmp, tmp2, tmp); |
| 6210 | } |
Juha Riihimäki | 21aeb34 | 2009-05-06 09:16:12 +0300 | [diff] [blame] | 6211 | store_reg_bx(env, s, rd, tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6212 | break; |
| 6213 | case 0x08: |
| 6214 | if (set_cc) { |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6215 | tcg_gen_and_i32(tmp, tmp, tmp2); |
| 6216 | gen_logic_CC(tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6217 | } |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6218 | dead_tmp(tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6219 | break; |
| 6220 | case 0x09: |
| 6221 | if (set_cc) { |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6222 | tcg_gen_xor_i32(tmp, tmp, tmp2); |
| 6223 | gen_logic_CC(tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6224 | } |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6225 | dead_tmp(tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6226 | break; |
| 6227 | case 0x0a: |
| 6228 | if (set_cc) { |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6229 | gen_helper_sub_cc(tmp, tmp, tmp2); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6230 | } |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6231 | dead_tmp(tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6232 | break; |
| 6233 | case 0x0b: |
| 6234 | if (set_cc) { |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6235 | gen_helper_add_cc(tmp, tmp, tmp2); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6236 | } |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6237 | dead_tmp(tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6238 | break; |
| 6239 | case 0x0c: |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6240 | tcg_gen_or_i32(tmp, tmp, tmp2); |
| 6241 | if (logic_cc) { |
| 6242 | gen_logic_CC(tmp); |
| 6243 | } |
Juha Riihimäki | 21aeb34 | 2009-05-06 09:16:12 +0300 | [diff] [blame] | 6244 | store_reg_bx(env, s, rd, tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6245 | break; |
| 6246 | case 0x0d: |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6247 | if (logic_cc && rd == 15) { |
| 6248 | /* MOVS r15, ... is used for exception return. */ |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6249 | if (IS_USER(s)) { |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6250 | goto illegal_op; |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6251 | } |
| 6252 | gen_exception_return(s, tmp2); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6253 | } else { |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6254 | if (logic_cc) { |
| 6255 | gen_logic_CC(tmp2); |
| 6256 | } |
Juha Riihimäki | 21aeb34 | 2009-05-06 09:16:12 +0300 | [diff] [blame] | 6257 | store_reg_bx(env, s, rd, tmp2); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6258 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6259 | break; |
| 6260 | case 0x0e: |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6261 | tcg_gen_bic_i32(tmp, tmp, tmp2); |
| 6262 | if (logic_cc) { |
| 6263 | gen_logic_CC(tmp); |
| 6264 | } |
Juha Riihimäki | 21aeb34 | 2009-05-06 09:16:12 +0300 | [diff] [blame] | 6265 | store_reg_bx(env, s, rd, tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6266 | break; |
| 6267 | default: |
| 6268 | case 0x0f: |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6269 | tcg_gen_not_i32(tmp2, tmp2); |
| 6270 | if (logic_cc) { |
| 6271 | gen_logic_CC(tmp2); |
| 6272 | } |
Juha Riihimäki | 21aeb34 | 2009-05-06 09:16:12 +0300 | [diff] [blame] | 6273 | store_reg_bx(env, s, rd, tmp2); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6274 | break; |
| 6275 | } |
Juha Riihimäki | e9bb4aa | 2009-05-06 09:15:38 +0300 | [diff] [blame] | 6276 | if (op1 != 0x0f && op1 != 0x0d) { |
| 6277 | dead_tmp(tmp2); |
| 6278 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6279 | } else { |
| 6280 | /* other instructions */ |
| 6281 | op1 = (insn >> 24) & 0xf; |
| 6282 | switch(op1) { |
| 6283 | case 0x0: |
| 6284 | case 0x1: |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6285 | /* multiplies, extra load/stores */ |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6286 | sh = (insn >> 5) & 3; |
| 6287 | if (sh == 0) { |
| 6288 | if (op1 == 0x0) { |
| 6289 | rd = (insn >> 16) & 0xf; |
| 6290 | rn = (insn >> 12) & 0xf; |
| 6291 | rs = (insn >> 8) & 0xf; |
| 6292 | rm = (insn) & 0xf; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6293 | op1 = (insn >> 20) & 0xf; |
| 6294 | switch (op1) { |
| 6295 | case 0: case 1: case 2: case 3: case 6: |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6296 | /* 32 bit mul */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6297 | tmp = load_reg(s, rs); |
| 6298 | tmp2 = load_reg(s, rm); |
| 6299 | tcg_gen_mul_i32(tmp, tmp, tmp2); |
| 6300 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6301 | if (insn & (1 << 22)) { |
| 6302 | /* Subtract (mls) */ |
| 6303 | ARCH(6T2); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6304 | tmp2 = load_reg(s, rn); |
| 6305 | tcg_gen_sub_i32(tmp, tmp2, tmp); |
| 6306 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6307 | } else if (insn & (1 << 21)) { |
| 6308 | /* Add */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6309 | tmp2 = load_reg(s, rn); |
| 6310 | tcg_gen_add_i32(tmp, tmp, tmp2); |
| 6311 | dead_tmp(tmp2); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6312 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 6313 | if (insn & (1 << 20)) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6314 | gen_logic_CC(tmp); |
| 6315 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6316 | break; |
| 6317 | default: |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6318 | /* 64 bit mul */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6319 | tmp = load_reg(s, rs); |
| 6320 | tmp2 = load_reg(s, rm); |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 6321 | if (insn & (1 << 22)) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6322 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
bellard | 2e134c9 | 2003-11-11 13:55:33 +0000 | [diff] [blame] | 6323 | else |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6324 | tmp64 = gen_mulu_i64_i32(tmp, tmp2); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6325 | if (insn & (1 << 21)) /* mult accumulate */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6326 | gen_addq(s, tmp64, rn, rd); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6327 | if (!(insn & (1 << 23))) { /* double accumulate */ |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6328 | ARCH(6); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6329 | gen_addq_lo(s, tmp64, rn); |
| 6330 | gen_addq_lo(s, tmp64, rd); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6331 | } |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 6332 | if (insn & (1 << 20)) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6333 | gen_logicq_cc(tmp64); |
| 6334 | gen_storeq_reg(s, rn, rd, tmp64); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6335 | break; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6336 | } |
| 6337 | } else { |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6338 | rn = (insn >> 16) & 0xf; |
| 6339 | rd = (insn >> 12) & 0xf; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6340 | if (insn & (1 << 23)) { |
| 6341 | /* load/store exclusive */ |
pbrook | 8675340 | 2008-10-22 20:35:54 +0000 | [diff] [blame] | 6342 | op1 = (insn >> 21) & 0x3; |
| 6343 | if (op1) |
pbrook | a47f43d | 2008-10-22 21:42:54 +0000 | [diff] [blame] | 6344 | ARCH(6K); |
pbrook | 8675340 | 2008-10-22 20:35:54 +0000 | [diff] [blame] | 6345 | else |
| 6346 | ARCH(6); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6347 | gen_movl_T1_reg(s, rn); |
balrog | 72f1c62 | 2008-04-13 01:53:27 +0000 | [diff] [blame] | 6348 | addr = cpu_T[1]; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6349 | if (insn & (1 << 20)) { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 6350 | gen_helper_mark_exclusive(cpu_env, cpu_T[1]); |
pbrook | 8675340 | 2008-10-22 20:35:54 +0000 | [diff] [blame] | 6351 | switch (op1) { |
| 6352 | case 0: /* ldrex */ |
| 6353 | tmp = gen_ld32(addr, IS_USER(s)); |
| 6354 | break; |
| 6355 | case 1: /* ldrexd */ |
| 6356 | tmp = gen_ld32(addr, IS_USER(s)); |
| 6357 | store_reg(s, rd, tmp); |
| 6358 | tcg_gen_addi_i32(addr, addr, 4); |
| 6359 | tmp = gen_ld32(addr, IS_USER(s)); |
| 6360 | rd++; |
| 6361 | break; |
| 6362 | case 2: /* ldrexb */ |
| 6363 | tmp = gen_ld8u(addr, IS_USER(s)); |
| 6364 | break; |
| 6365 | case 3: /* ldrexh */ |
| 6366 | tmp = gen_ld16u(addr, IS_USER(s)); |
| 6367 | break; |
| 6368 | default: |
| 6369 | abort(); |
| 6370 | } |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 6371 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6372 | } else { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 6373 | int label = gen_new_label(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6374 | rm = insn & 0xf; |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 6375 | gen_helper_test_exclusive(cpu_T[0], cpu_env, addr); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 6376 | tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0], |
| 6377 | 0, label); |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 6378 | tmp = load_reg(s,rm); |
pbrook | 8675340 | 2008-10-22 20:35:54 +0000 | [diff] [blame] | 6379 | switch (op1) { |
| 6380 | case 0: /* strex */ |
| 6381 | gen_st32(tmp, addr, IS_USER(s)); |
| 6382 | break; |
| 6383 | case 1: /* strexd */ |
| 6384 | gen_st32(tmp, addr, IS_USER(s)); |
| 6385 | tcg_gen_addi_i32(addr, addr, 4); |
| 6386 | tmp = load_reg(s, rm + 1); |
| 6387 | gen_st32(tmp, addr, IS_USER(s)); |
| 6388 | break; |
| 6389 | case 2: /* strexb */ |
| 6390 | gen_st8(tmp, addr, IS_USER(s)); |
| 6391 | break; |
| 6392 | case 3: /* strexh */ |
| 6393 | gen_st16(tmp, addr, IS_USER(s)); |
| 6394 | break; |
| 6395 | default: |
| 6396 | abort(); |
| 6397 | } |
balrog | 2637a3b | 2008-04-13 03:15:14 +0000 | [diff] [blame] | 6398 | gen_set_label(label); |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 6399 | gen_movl_reg_T0(s, rd); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6400 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6401 | } else { |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6402 | /* SWP instruction */ |
| 6403 | rm = (insn) & 0xf; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 6404 | |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 6405 | /* ??? This is not really atomic. However we know |
| 6406 | we never have multiple CPUs running in parallel, |
| 6407 | so it is good enough. */ |
| 6408 | addr = load_reg(s, rn); |
| 6409 | tmp = load_reg(s, rm); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6410 | if (insn & (1 << 22)) { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 6411 | tmp2 = gen_ld8u(addr, IS_USER(s)); |
| 6412 | gen_st8(tmp, addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6413 | } else { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 6414 | tmp2 = gen_ld32(addr, IS_USER(s)); |
| 6415 | gen_st32(tmp, addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6416 | } |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 6417 | dead_tmp(addr); |
| 6418 | store_reg(s, rd, tmp2); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6419 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6420 | } |
| 6421 | } else { |
pbrook | 191f9a9 | 2006-06-14 14:36:07 +0000 | [diff] [blame] | 6422 | int address_offset; |
pbrook | 5fd4686 | 2007-03-17 01:43:01 +0000 | [diff] [blame] | 6423 | int load; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6424 | /* Misc load/store */ |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6425 | rn = (insn >> 16) & 0xf; |
| 6426 | rd = (insn >> 12) & 0xf; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6427 | addr = load_reg(s, rn); |
bellard | beddab7 | 2004-05-05 18:36:10 +0000 | [diff] [blame] | 6428 | if (insn & (1 << 24)) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6429 | gen_add_datah_offset(s, insn, 0, addr); |
pbrook | 191f9a9 | 2006-06-14 14:36:07 +0000 | [diff] [blame] | 6430 | address_offset = 0; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6431 | if (insn & (1 << 20)) { |
| 6432 | /* load */ |
| 6433 | switch(sh) { |
| 6434 | case 1: |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6435 | tmp = gen_ld16u(addr, IS_USER(s)); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6436 | break; |
| 6437 | case 2: |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6438 | tmp = gen_ld8s(addr, IS_USER(s)); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6439 | break; |
| 6440 | default: |
| 6441 | case 3: |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6442 | tmp = gen_ld16s(addr, IS_USER(s)); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6443 | break; |
| 6444 | } |
pbrook | 5fd4686 | 2007-03-17 01:43:01 +0000 | [diff] [blame] | 6445 | load = 1; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6446 | } else if (sh & 2) { |
| 6447 | /* doubleword */ |
| 6448 | if (sh & 1) { |
| 6449 | /* store */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6450 | tmp = load_reg(s, rd); |
| 6451 | gen_st32(tmp, addr, IS_USER(s)); |
| 6452 | tcg_gen_addi_i32(addr, addr, 4); |
| 6453 | tmp = load_reg(s, rd + 1); |
| 6454 | gen_st32(tmp, addr, IS_USER(s)); |
pbrook | 5fd4686 | 2007-03-17 01:43:01 +0000 | [diff] [blame] | 6455 | load = 0; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6456 | } else { |
| 6457 | /* load */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6458 | tmp = gen_ld32(addr, IS_USER(s)); |
| 6459 | store_reg(s, rd, tmp); |
| 6460 | tcg_gen_addi_i32(addr, addr, 4); |
| 6461 | tmp = gen_ld32(addr, IS_USER(s)); |
pbrook | 5fd4686 | 2007-03-17 01:43:01 +0000 | [diff] [blame] | 6462 | rd++; |
| 6463 | load = 1; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6464 | } |
pbrook | 191f9a9 | 2006-06-14 14:36:07 +0000 | [diff] [blame] | 6465 | address_offset = -4; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6466 | } else { |
| 6467 | /* store */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6468 | tmp = load_reg(s, rd); |
| 6469 | gen_st16(tmp, addr, IS_USER(s)); |
pbrook | 5fd4686 | 2007-03-17 01:43:01 +0000 | [diff] [blame] | 6470 | load = 0; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6471 | } |
pbrook | 5fd4686 | 2007-03-17 01:43:01 +0000 | [diff] [blame] | 6472 | /* Perform base writeback before the loaded value to |
| 6473 | ensure correct behavior with overlapping index registers. |
| 6474 | ldrd with base writeback is is undefined if the |
| 6475 | destination and index registers overlap. */ |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6476 | if (!(insn & (1 << 24))) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6477 | gen_add_datah_offset(s, insn, address_offset, addr); |
| 6478 | store_reg(s, rn, addr); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6479 | } else if (insn & (1 << 21)) { |
pbrook | 191f9a9 | 2006-06-14 14:36:07 +0000 | [diff] [blame] | 6480 | if (address_offset) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6481 | tcg_gen_addi_i32(addr, addr, address_offset); |
| 6482 | store_reg(s, rn, addr); |
| 6483 | } else { |
| 6484 | dead_tmp(addr); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6485 | } |
pbrook | 5fd4686 | 2007-03-17 01:43:01 +0000 | [diff] [blame] | 6486 | if (load) { |
| 6487 | /* Complete the load. */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6488 | store_reg(s, rd, tmp); |
pbrook | 5fd4686 | 2007-03-17 01:43:01 +0000 | [diff] [blame] | 6489 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6490 | } |
| 6491 | break; |
| 6492 | case 0x4: |
| 6493 | case 0x5: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6494 | goto do_ldst; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6495 | case 0x6: |
| 6496 | case 0x7: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6497 | if (insn & (1 << 4)) { |
| 6498 | ARCH(6); |
| 6499 | /* Armv6 Media instructions. */ |
| 6500 | rm = insn & 0xf; |
| 6501 | rn = (insn >> 16) & 0xf; |
| 6502 | rd = (insn >> 12) & 0xf; |
| 6503 | rs = (insn >> 8) & 0xf; |
| 6504 | switch ((insn >> 23) & 3) { |
| 6505 | case 0: /* Parallel add/subtract. */ |
| 6506 | op1 = (insn >> 20) & 7; |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6507 | tmp = load_reg(s, rn); |
| 6508 | tmp2 = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6509 | sh = (insn >> 5) & 7; |
| 6510 | if ((op1 & 3) == 0 || sh == 5 || sh == 6) |
| 6511 | goto illegal_op; |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6512 | gen_arm_parallel_addsub(op1, sh, tmp, tmp2); |
| 6513 | dead_tmp(tmp2); |
| 6514 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6515 | break; |
| 6516 | case 1: |
| 6517 | if ((insn & 0x00700020) == 0) { |
balrog | 6c95676 | 2008-04-13 00:57:49 +0000 | [diff] [blame] | 6518 | /* Halfword pack. */ |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 6519 | tmp = load_reg(s, rn); |
| 6520 | tmp2 = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6521 | shift = (insn >> 7) & 0x1f; |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 6522 | if (insn & (1 << 6)) { |
| 6523 | /* pkhtb */ |
balrog | 22478e7 | 2008-07-19 10:12:22 +0000 | [diff] [blame] | 6524 | if (shift == 0) |
| 6525 | shift = 31; |
| 6526 | tcg_gen_sari_i32(tmp2, tmp2, shift); |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 6527 | tcg_gen_andi_i32(tmp, tmp, 0xffff0000); |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 6528 | tcg_gen_ext16u_i32(tmp2, tmp2); |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 6529 | } else { |
| 6530 | /* pkhbt */ |
balrog | 22478e7 | 2008-07-19 10:12:22 +0000 | [diff] [blame] | 6531 | if (shift) |
| 6532 | tcg_gen_shli_i32(tmp2, tmp2, shift); |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 6533 | tcg_gen_ext16u_i32(tmp, tmp); |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 6534 | tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); |
| 6535 | } |
| 6536 | tcg_gen_or_i32(tmp, tmp, tmp2); |
balrog | 22478e7 | 2008-07-19 10:12:22 +0000 | [diff] [blame] | 6537 | dead_tmp(tmp2); |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 6538 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6539 | } else if ((insn & 0x00200020) == 0x00200000) { |
| 6540 | /* [us]sat */ |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6541 | tmp = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6542 | shift = (insn >> 7) & 0x1f; |
| 6543 | if (insn & (1 << 6)) { |
| 6544 | if (shift == 0) |
| 6545 | shift = 31; |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6546 | tcg_gen_sari_i32(tmp, tmp, shift); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6547 | } else { |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6548 | tcg_gen_shli_i32(tmp, tmp, shift); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6549 | } |
| 6550 | sh = (insn >> 16) & 0x1f; |
| 6551 | if (sh != 0) { |
| 6552 | if (insn & (1 << 22)) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6553 | gen_helper_usat(tmp, tmp, tcg_const_i32(sh)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6554 | else |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6555 | gen_helper_ssat(tmp, tmp, tcg_const_i32(sh)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6556 | } |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6557 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6558 | } else if ((insn & 0x00300fe0) == 0x00200f20) { |
| 6559 | /* [us]sat16 */ |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6560 | tmp = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6561 | sh = (insn >> 16) & 0x1f; |
| 6562 | if (sh != 0) { |
| 6563 | if (insn & (1 << 22)) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6564 | gen_helper_usat16(tmp, tmp, tcg_const_i32(sh)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6565 | else |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6566 | gen_helper_ssat16(tmp, tmp, tcg_const_i32(sh)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6567 | } |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6568 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6569 | } else if ((insn & 0x00700fe0) == 0x00000fa0) { |
| 6570 | /* Select bytes. */ |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6571 | tmp = load_reg(s, rn); |
| 6572 | tmp2 = load_reg(s, rm); |
| 6573 | tmp3 = new_tmp(); |
| 6574 | tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE)); |
| 6575 | gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); |
| 6576 | dead_tmp(tmp3); |
| 6577 | dead_tmp(tmp2); |
| 6578 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6579 | } else if ((insn & 0x000003e0) == 0x00000060) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6580 | tmp = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6581 | shift = (insn >> 10) & 3; |
| 6582 | /* ??? In many cases it's not neccessary to do a |
| 6583 | rotate, a shift is sufficient. */ |
| 6584 | if (shift != 0) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6585 | tcg_gen_rori_i32(tmp, tmp, shift * 8); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6586 | op1 = (insn >> 20) & 7; |
| 6587 | switch (op1) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6588 | case 0: gen_sxtb16(tmp); break; |
| 6589 | case 2: gen_sxtb(tmp); break; |
| 6590 | case 3: gen_sxth(tmp); break; |
| 6591 | case 4: gen_uxtb16(tmp); break; |
| 6592 | case 6: gen_uxtb(tmp); break; |
| 6593 | case 7: gen_uxth(tmp); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6594 | default: goto illegal_op; |
| 6595 | } |
| 6596 | if (rn != 15) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6597 | tmp2 = load_reg(s, rn); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6598 | if ((op1 & 3) == 0) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6599 | gen_add16(tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6600 | } else { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6601 | tcg_gen_add_i32(tmp, tmp, tmp2); |
| 6602 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6603 | } |
| 6604 | } |
balrog | 6c95676 | 2008-04-13 00:57:49 +0000 | [diff] [blame] | 6605 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6606 | } else if ((insn & 0x003f0f60) == 0x003f0f20) { |
| 6607 | /* rev */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6608 | tmp = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6609 | if (insn & (1 << 22)) { |
| 6610 | if (insn & (1 << 7)) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6611 | gen_revsh(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6612 | } else { |
| 6613 | ARCH(6T2); |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6614 | gen_helper_rbit(tmp, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6615 | } |
| 6616 | } else { |
| 6617 | if (insn & (1 << 7)) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6618 | gen_rev16(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6619 | else |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 6620 | tcg_gen_bswap32_i32(tmp, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6621 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6622 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6623 | } else { |
| 6624 | goto illegal_op; |
| 6625 | } |
| 6626 | break; |
| 6627 | case 2: /* Multiplies (Type 3). */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6628 | tmp = load_reg(s, rm); |
| 6629 | tmp2 = load_reg(s, rs); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6630 | if (insn & (1 << 20)) { |
| 6631 | /* Signed multiply most significant [accumulate]. */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6632 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6633 | if (insn & (1 << 5)) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6634 | tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u); |
| 6635 | tcg_gen_shri_i64(tmp64, tmp64, 32); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6636 | tmp = new_tmp(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6637 | tcg_gen_trunc_i64_i32(tmp, tmp64); |
balrog | 955a7dd | 2008-12-07 14:18:02 +0000 | [diff] [blame] | 6638 | if (rd != 15) { |
| 6639 | tmp2 = load_reg(s, rd); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6640 | if (insn & (1 << 6)) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6641 | tcg_gen_sub_i32(tmp, tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6642 | } else { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6643 | tcg_gen_add_i32(tmp, tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6644 | } |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6645 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6646 | } |
balrog | 955a7dd | 2008-12-07 14:18:02 +0000 | [diff] [blame] | 6647 | store_reg(s, rn, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6648 | } else { |
| 6649 | if (insn & (1 << 5)) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6650 | gen_swap_half(tmp2); |
| 6651 | gen_smul_dual(tmp, tmp2); |
| 6652 | /* This addition cannot overflow. */ |
| 6653 | if (insn & (1 << 6)) { |
| 6654 | tcg_gen_sub_i32(tmp, tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6655 | } else { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6656 | tcg_gen_add_i32(tmp, tmp, tmp2); |
| 6657 | } |
| 6658 | dead_tmp(tmp2); |
| 6659 | if (insn & (1 << 22)) { |
| 6660 | /* smlald, smlsld */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6661 | tmp64 = tcg_temp_new_i64(); |
| 6662 | tcg_gen_ext_i32_i64(tmp64, tmp); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6663 | dead_tmp(tmp); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 6664 | gen_addq(s, tmp64, rd, rn); |
| 6665 | gen_storeq_reg(s, rd, rn, tmp64); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6666 | } else { |
| 6667 | /* smuad, smusd, smlad, smlsd */ |
balrog | 22478e7 | 2008-07-19 10:12:22 +0000 | [diff] [blame] | 6668 | if (rd != 15) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6669 | { |
balrog | 22478e7 | 2008-07-19 10:12:22 +0000 | [diff] [blame] | 6670 | tmp2 = load_reg(s, rd); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6671 | gen_helper_add_setq(tmp, tmp, tmp2); |
| 6672 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6673 | } |
balrog | 22478e7 | 2008-07-19 10:12:22 +0000 | [diff] [blame] | 6674 | store_reg(s, rn, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6675 | } |
| 6676 | } |
| 6677 | break; |
| 6678 | case 3: |
| 6679 | op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7); |
| 6680 | switch (op1) { |
| 6681 | case 0: /* Unsigned sum of absolute differences. */ |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6682 | ARCH(6); |
| 6683 | tmp = load_reg(s, rm); |
| 6684 | tmp2 = load_reg(s, rs); |
| 6685 | gen_helper_usad8(tmp, tmp, tmp2); |
| 6686 | dead_tmp(tmp2); |
balrog | ded9d29 | 2008-12-07 14:03:27 +0000 | [diff] [blame] | 6687 | if (rd != 15) { |
| 6688 | tmp2 = load_reg(s, rd); |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 6689 | tcg_gen_add_i32(tmp, tmp, tmp2); |
| 6690 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6691 | } |
balrog | ded9d29 | 2008-12-07 14:03:27 +0000 | [diff] [blame] | 6692 | store_reg(s, rn, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6693 | break; |
| 6694 | case 0x20: case 0x24: case 0x28: case 0x2c: |
| 6695 | /* Bitfield insert/clear. */ |
| 6696 | ARCH(6T2); |
| 6697 | shift = (insn >> 7) & 0x1f; |
| 6698 | i = (insn >> 16) & 0x1f; |
| 6699 | i = i + 1 - shift; |
| 6700 | if (rm == 15) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6701 | tmp = new_tmp(); |
| 6702 | tcg_gen_movi_i32(tmp, 0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6703 | } else { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6704 | tmp = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6705 | } |
| 6706 | if (i != 32) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6707 | tmp2 = load_reg(s, rd); |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 6708 | gen_bfi(tmp, tmp2, tmp, shift, (1u << i) - 1); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6709 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6710 | } |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6711 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6712 | break; |
| 6713 | case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */ |
| 6714 | case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */ |
balrog | 4cc633c | 2008-12-07 13:32:09 +0000 | [diff] [blame] | 6715 | ARCH(6T2); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6716 | tmp = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6717 | shift = (insn >> 7) & 0x1f; |
| 6718 | i = ((insn >> 16) & 0x1f) + 1; |
| 6719 | if (shift + i > 32) |
| 6720 | goto illegal_op; |
| 6721 | if (i < 32) { |
| 6722 | if (op1 & 0x20) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6723 | gen_ubfx(tmp, shift, (1u << i) - 1); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6724 | } else { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6725 | gen_sbfx(tmp, shift, i); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6726 | } |
| 6727 | } |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6728 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6729 | break; |
| 6730 | default: |
| 6731 | goto illegal_op; |
| 6732 | } |
| 6733 | break; |
| 6734 | } |
| 6735 | break; |
| 6736 | } |
| 6737 | do_ldst: |
bellard | 159f366 | 2006-05-22 23:06:04 +0000 | [diff] [blame] | 6738 | /* Check for undefined extension instructions |
| 6739 | * per the ARM Bible IE: |
| 6740 | * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx |
| 6741 | */ |
| 6742 | sh = (0xf << 20) | (0xf << 4); |
| 6743 | if (op1 == 0x7 && ((insn & sh) == sh)) |
| 6744 | { |
| 6745 | goto illegal_op; |
| 6746 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6747 | /* load/store byte/word */ |
| 6748 | rn = (insn >> 16) & 0xf; |
| 6749 | rd = (insn >> 12) & 0xf; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6750 | tmp2 = load_reg(s, rn); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6751 | i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6752 | if (insn & (1 << 24)) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6753 | gen_add_data_offset(s, insn, tmp2); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6754 | if (insn & (1 << 20)) { |
| 6755 | /* load */ |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6756 | if (insn & (1 << 22)) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6757 | tmp = gen_ld8u(tmp2, i); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6758 | } else { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6759 | tmp = gen_ld32(tmp2, i); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6760 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6761 | } else { |
| 6762 | /* store */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6763 | tmp = load_reg(s, rd); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6764 | if (insn & (1 << 22)) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6765 | gen_st8(tmp, tmp2, i); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6766 | else |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6767 | gen_st32(tmp, tmp2, i); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6768 | } |
| 6769 | if (!(insn & (1 << 24))) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6770 | gen_add_data_offset(s, insn, tmp2); |
| 6771 | store_reg(s, rn, tmp2); |
| 6772 | } else if (insn & (1 << 21)) { |
| 6773 | store_reg(s, rn, tmp2); |
| 6774 | } else { |
| 6775 | dead_tmp(tmp2); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6776 | } |
pbrook | 5fd4686 | 2007-03-17 01:43:01 +0000 | [diff] [blame] | 6777 | if (insn & (1 << 20)) { |
| 6778 | /* Complete the load. */ |
| 6779 | if (rd == 15) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6780 | gen_bx(s, tmp); |
pbrook | 5fd4686 | 2007-03-17 01:43:01 +0000 | [diff] [blame] | 6781 | else |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6782 | store_reg(s, rd, tmp); |
pbrook | 5fd4686 | 2007-03-17 01:43:01 +0000 | [diff] [blame] | 6783 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6784 | break; |
| 6785 | case 0x08: |
| 6786 | case 0x09: |
| 6787 | { |
pbrook | 191abaa | 2006-02-04 21:50:36 +0000 | [diff] [blame] | 6788 | int j, n, user, loaded_base; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6789 | TCGv loaded_var; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6790 | /* load/store multiple words */ |
| 6791 | /* XXX: store correct base if write back */ |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6792 | user = 0; |
| 6793 | if (insn & (1 << 22)) { |
| 6794 | if (IS_USER(s)) |
| 6795 | goto illegal_op; /* only usable in supervisor mode */ |
| 6796 | |
| 6797 | if ((insn & (1 << 15)) == 0) |
| 6798 | user = 1; |
| 6799 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6800 | rn = (insn >> 16) & 0xf; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6801 | addr = load_reg(s, rn); |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 6802 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6803 | /* compute total size */ |
pbrook | 191abaa | 2006-02-04 21:50:36 +0000 | [diff] [blame] | 6804 | loaded_base = 0; |
pbrook | a50f5b9 | 2008-06-29 15:25:29 +0000 | [diff] [blame] | 6805 | TCGV_UNUSED(loaded_var); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6806 | n = 0; |
| 6807 | for(i=0;i<16;i++) { |
| 6808 | if (insn & (1 << i)) |
| 6809 | n++; |
| 6810 | } |
| 6811 | /* XXX: test invalid n == 0 case ? */ |
| 6812 | if (insn & (1 << 23)) { |
| 6813 | if (insn & (1 << 24)) { |
| 6814 | /* pre increment */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6815 | tcg_gen_addi_i32(addr, addr, 4); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6816 | } else { |
| 6817 | /* post increment */ |
| 6818 | } |
| 6819 | } else { |
| 6820 | if (insn & (1 << 24)) { |
| 6821 | /* pre decrement */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6822 | tcg_gen_addi_i32(addr, addr, -(n * 4)); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6823 | } else { |
| 6824 | /* post decrement */ |
| 6825 | if (n != 1) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6826 | tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6827 | } |
| 6828 | } |
| 6829 | j = 0; |
| 6830 | for(i=0;i<16;i++) { |
| 6831 | if (insn & (1 << i)) { |
| 6832 | if (insn & (1 << 20)) { |
| 6833 | /* load */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6834 | tmp = gen_ld32(addr, IS_USER(s)); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6835 | if (i == 15) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6836 | gen_bx(s, tmp); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6837 | } else if (user) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6838 | gen_helper_set_user_reg(tcg_const_i32(i), tmp); |
| 6839 | dead_tmp(tmp); |
pbrook | 191abaa | 2006-02-04 21:50:36 +0000 | [diff] [blame] | 6840 | } else if (i == rn) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6841 | loaded_var = tmp; |
pbrook | 191abaa | 2006-02-04 21:50:36 +0000 | [diff] [blame] | 6842 | loaded_base = 1; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6843 | } else { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6844 | store_reg(s, i, tmp); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6845 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6846 | } else { |
| 6847 | /* store */ |
| 6848 | if (i == 15) { |
balrog | 7a774c8 | 2007-06-10 13:53:18 +0000 | [diff] [blame] | 6849 | /* special case: r15 = PC + 8 */ |
| 6850 | val = (long)s->pc + 4; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6851 | tmp = new_tmp(); |
| 6852 | tcg_gen_movi_i32(tmp, val); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6853 | } else if (user) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6854 | tmp = new_tmp(); |
| 6855 | gen_helper_get_user_reg(tmp, tcg_const_i32(i)); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6856 | } else { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6857 | tmp = load_reg(s, i); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6858 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6859 | gen_st32(tmp, addr, IS_USER(s)); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6860 | } |
| 6861 | j++; |
| 6862 | /* no need to add after the last transfer */ |
| 6863 | if (j != n) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6864 | tcg_gen_addi_i32(addr, addr, 4); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6865 | } |
| 6866 | } |
| 6867 | if (insn & (1 << 21)) { |
| 6868 | /* write back */ |
| 6869 | if (insn & (1 << 23)) { |
| 6870 | if (insn & (1 << 24)) { |
| 6871 | /* pre increment */ |
| 6872 | } else { |
| 6873 | /* post increment */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6874 | tcg_gen_addi_i32(addr, addr, 4); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6875 | } |
| 6876 | } else { |
| 6877 | if (insn & (1 << 24)) { |
| 6878 | /* pre decrement */ |
| 6879 | if (n != 1) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6880 | tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6881 | } else { |
| 6882 | /* post decrement */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6883 | tcg_gen_addi_i32(addr, addr, -(n * 4)); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6884 | } |
| 6885 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6886 | store_reg(s, rn, addr); |
| 6887 | } else { |
| 6888 | dead_tmp(addr); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6889 | } |
pbrook | 191abaa | 2006-02-04 21:50:36 +0000 | [diff] [blame] | 6890 | if (loaded_base) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 6891 | store_reg(s, rn, loaded_var); |
pbrook | 191abaa | 2006-02-04 21:50:36 +0000 | [diff] [blame] | 6892 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6893 | if ((insn & (1 << 22)) && !user) { |
| 6894 | /* Restore CPSR from SPSR. */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 6895 | tmp = load_cpu_field(spsr); |
| 6896 | gen_set_cpsr(tmp, 0xffffffff); |
| 6897 | dead_tmp(tmp); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 6898 | s->is_jmp = DISAS_UPDATE; |
| 6899 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6900 | } |
| 6901 | break; |
| 6902 | case 0xa: |
| 6903 | case 0xb: |
| 6904 | { |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6905 | int32_t offset; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 6906 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6907 | /* branch (and link) */ |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6908 | val = (int32_t)s->pc; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6909 | if (insn & (1 << 24)) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6910 | tmp = new_tmp(); |
| 6911 | tcg_gen_movi_i32(tmp, val); |
| 6912 | store_reg(s, 14, tmp); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6913 | } |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 6914 | offset = (((int32_t)insn << 8) >> 8); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6915 | val += (offset << 2) + 4; |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 6916 | gen_jmp(s, val); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6917 | } |
| 6918 | break; |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 6919 | case 0xc: |
| 6920 | case 0xd: |
| 6921 | case 0xe: |
| 6922 | /* Coprocessor. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6923 | if (disas_coproc_insn(env, s, insn)) |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 6924 | goto illegal_op; |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 6925 | break; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6926 | case 0xf: |
| 6927 | /* swi */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6928 | gen_set_pc_im(s->pc); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6929 | s->is_jmp = DISAS_SWI; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6930 | break; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6931 | default: |
| 6932 | illegal_op: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6933 | gen_set_condexec(s); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 6934 | gen_set_pc_im(s->pc - 4); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 6935 | gen_exception(EXCP_UDEF); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 6936 | s->is_jmp = DISAS_JUMP; |
| 6937 | break; |
| 6938 | } |
| 6939 | } |
| 6940 | } |
| 6941 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6942 | /* Return true if this is a Thumb-2 logical op. */ |
| 6943 | static int |
| 6944 | thumb2_logic_op(int op) |
| 6945 | { |
| 6946 | return (op < 8); |
| 6947 | } |
| 6948 | |
| 6949 | /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero |
| 6950 | then set condition code flags based on the result of the operation. |
| 6951 | If SHIFTER_OUT is nonzero then set the carry flag for logical operations |
| 6952 | to the high bit of T1. |
| 6953 | Returns zero if the opcode is valid. */ |
| 6954 | |
| 6955 | static int |
| 6956 | gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out) |
| 6957 | { |
| 6958 | int logic_cc; |
| 6959 | |
| 6960 | logic_cc = 0; |
| 6961 | switch (op) { |
| 6962 | case 0: /* and */ |
| 6963 | gen_op_andl_T0_T1(); |
| 6964 | logic_cc = conds; |
| 6965 | break; |
| 6966 | case 1: /* bic */ |
| 6967 | gen_op_bicl_T0_T1(); |
| 6968 | logic_cc = conds; |
| 6969 | break; |
| 6970 | case 2: /* orr */ |
| 6971 | gen_op_orl_T0_T1(); |
| 6972 | logic_cc = conds; |
| 6973 | break; |
| 6974 | case 3: /* orn */ |
| 6975 | gen_op_notl_T1(); |
| 6976 | gen_op_orl_T0_T1(); |
| 6977 | logic_cc = conds; |
| 6978 | break; |
| 6979 | case 4: /* eor */ |
| 6980 | gen_op_xorl_T0_T1(); |
| 6981 | logic_cc = conds; |
| 6982 | break; |
| 6983 | case 8: /* add */ |
| 6984 | if (conds) |
| 6985 | gen_op_addl_T0_T1_cc(); |
| 6986 | else |
| 6987 | gen_op_addl_T0_T1(); |
| 6988 | break; |
| 6989 | case 10: /* adc */ |
| 6990 | if (conds) |
| 6991 | gen_op_adcl_T0_T1_cc(); |
| 6992 | else |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 6993 | gen_adc_T0_T1(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 6994 | break; |
| 6995 | case 11: /* sbc */ |
| 6996 | if (conds) |
| 6997 | gen_op_sbcl_T0_T1_cc(); |
| 6998 | else |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 6999 | gen_sbc_T0_T1(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7000 | break; |
| 7001 | case 13: /* sub */ |
| 7002 | if (conds) |
| 7003 | gen_op_subl_T0_T1_cc(); |
| 7004 | else |
| 7005 | gen_op_subl_T0_T1(); |
| 7006 | break; |
| 7007 | case 14: /* rsb */ |
| 7008 | if (conds) |
| 7009 | gen_op_rsbl_T0_T1_cc(); |
| 7010 | else |
| 7011 | gen_op_rsbl_T0_T1(); |
| 7012 | break; |
| 7013 | default: /* 5, 6, 7, 9, 12, 15. */ |
| 7014 | return 1; |
| 7015 | } |
| 7016 | if (logic_cc) { |
| 7017 | gen_op_logic_T0_cc(); |
| 7018 | if (shifter_out) |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 7019 | gen_set_CF_bit31(cpu_T[1]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7020 | } |
| 7021 | return 0; |
| 7022 | } |
| 7023 | |
| 7024 | /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction |
| 7025 | is not legal. */ |
| 7026 | static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) |
| 7027 | { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7028 | uint32_t insn, imm, shift, offset; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7029 | uint32_t rd, rn, rm, rs; |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 7030 | TCGv tmp; |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7031 | TCGv tmp2; |
| 7032 | TCGv tmp3; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7033 | TCGv addr; |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7034 | TCGv_i64 tmp64; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7035 | int op; |
| 7036 | int shiftop; |
| 7037 | int conds; |
| 7038 | int logic_cc; |
| 7039 | |
| 7040 | if (!(arm_feature(env, ARM_FEATURE_THUMB2) |
| 7041 | || arm_feature (env, ARM_FEATURE_M))) { |
balrog | 601d70b | 2008-04-20 01:03:45 +0000 | [diff] [blame] | 7042 | /* Thumb-1 cores may need to treat bl and blx as a pair of |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7043 | 16-bit instructions to get correct prefetch abort behavior. */ |
| 7044 | insn = insn_hw1; |
| 7045 | if ((insn & (1 << 12)) == 0) { |
| 7046 | /* Second half of blx. */ |
| 7047 | offset = ((insn & 0x7ff) << 1); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7048 | tmp = load_reg(s, 14); |
| 7049 | tcg_gen_addi_i32(tmp, tmp, offset); |
| 7050 | tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7051 | |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7052 | tmp2 = new_tmp(); |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7053 | tcg_gen_movi_i32(tmp2, s->pc | 1); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7054 | store_reg(s, 14, tmp2); |
| 7055 | gen_bx(s, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7056 | return 0; |
| 7057 | } |
| 7058 | if (insn & (1 << 11)) { |
| 7059 | /* Second half of bl. */ |
| 7060 | offset = ((insn & 0x7ff) << 1) | 1; |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7061 | tmp = load_reg(s, 14); |
balrog | 6a0d8a1 | 2008-04-13 13:25:31 +0000 | [diff] [blame] | 7062 | tcg_gen_addi_i32(tmp, tmp, offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7063 | |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7064 | tmp2 = new_tmp(); |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7065 | tcg_gen_movi_i32(tmp2, s->pc | 1); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7066 | store_reg(s, 14, tmp2); |
| 7067 | gen_bx(s, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7068 | return 0; |
| 7069 | } |
| 7070 | if ((s->pc & ~TARGET_PAGE_MASK) == 0) { |
| 7071 | /* Instruction spans a page boundary. Implement it as two |
| 7072 | 16-bit instructions in case the second half causes an |
| 7073 | prefetch abort. */ |
| 7074 | offset = ((int32_t)insn << 21) >> 9; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7075 | gen_op_movl_T0_im(s->pc + 2 + offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7076 | gen_movl_reg_T0(s, 14); |
| 7077 | return 0; |
| 7078 | } |
| 7079 | /* Fall through to 32-bit decode. */ |
| 7080 | } |
| 7081 | |
| 7082 | insn = lduw_code(s->pc); |
| 7083 | s->pc += 2; |
| 7084 | insn |= (uint32_t)insn_hw1 << 16; |
| 7085 | |
| 7086 | if ((insn & 0xf800e800) != 0xf000e800) { |
| 7087 | ARCH(6T2); |
| 7088 | } |
| 7089 | |
| 7090 | rn = (insn >> 16) & 0xf; |
| 7091 | rs = (insn >> 12) & 0xf; |
| 7092 | rd = (insn >> 8) & 0xf; |
| 7093 | rm = insn & 0xf; |
| 7094 | switch ((insn >> 25) & 0xf) { |
| 7095 | case 0: case 1: case 2: case 3: |
| 7096 | /* 16-bit instructions. Should never happen. */ |
| 7097 | abort(); |
| 7098 | case 4: |
| 7099 | if (insn & (1 << 22)) { |
| 7100 | /* Other load/store, table branch. */ |
| 7101 | if (insn & 0x01200000) { |
| 7102 | /* Load/store doubleword. */ |
| 7103 | if (rn == 15) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7104 | addr = new_tmp(); |
| 7105 | tcg_gen_movi_i32(addr, s->pc & ~3); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7106 | } else { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7107 | addr = load_reg(s, rn); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7108 | } |
| 7109 | offset = (insn & 0xff) * 4; |
| 7110 | if ((insn & (1 << 23)) == 0) |
| 7111 | offset = -offset; |
| 7112 | if (insn & (1 << 24)) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7113 | tcg_gen_addi_i32(addr, addr, offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7114 | offset = 0; |
| 7115 | } |
| 7116 | if (insn & (1 << 20)) { |
| 7117 | /* ldrd */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7118 | tmp = gen_ld32(addr, IS_USER(s)); |
| 7119 | store_reg(s, rs, tmp); |
| 7120 | tcg_gen_addi_i32(addr, addr, 4); |
| 7121 | tmp = gen_ld32(addr, IS_USER(s)); |
| 7122 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7123 | } else { |
| 7124 | /* strd */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7125 | tmp = load_reg(s, rs); |
| 7126 | gen_st32(tmp, addr, IS_USER(s)); |
| 7127 | tcg_gen_addi_i32(addr, addr, 4); |
| 7128 | tmp = load_reg(s, rd); |
| 7129 | gen_st32(tmp, addr, IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7130 | } |
| 7131 | if (insn & (1 << 21)) { |
| 7132 | /* Base writeback. */ |
| 7133 | if (rn == 15) |
| 7134 | goto illegal_op; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7135 | tcg_gen_addi_i32(addr, addr, offset - 4); |
| 7136 | store_reg(s, rn, addr); |
| 7137 | } else { |
| 7138 | dead_tmp(addr); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7139 | } |
| 7140 | } else if ((insn & (1 << 23)) == 0) { |
| 7141 | /* Load/store exclusive word. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7142 | gen_movl_T1_reg(s, rn); |
balrog | 72f1c62 | 2008-04-13 01:53:27 +0000 | [diff] [blame] | 7143 | addr = cpu_T[1]; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7144 | if (insn & (1 << 20)) { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7145 | gen_helper_mark_exclusive(cpu_env, cpu_T[1]); |
| 7146 | tmp = gen_ld32(addr, IS_USER(s)); |
| 7147 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7148 | } else { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7149 | int label = gen_new_label(); |
| 7150 | gen_helper_test_exclusive(cpu_T[0], cpu_env, addr); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 7151 | tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0], |
| 7152 | 0, label); |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7153 | tmp = load_reg(s, rs); |
| 7154 | gen_st32(tmp, cpu_T[1], IS_USER(s)); |
| 7155 | gen_set_label(label); |
| 7156 | gen_movl_reg_T0(s, rd); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7157 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7158 | } else if ((insn & (1 << 6)) == 0) { |
| 7159 | /* Table Branch. */ |
| 7160 | if (rn == 15) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7161 | addr = new_tmp(); |
| 7162 | tcg_gen_movi_i32(addr, s->pc); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7163 | } else { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7164 | addr = load_reg(s, rn); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7165 | } |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 7166 | tmp = load_reg(s, rm); |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7167 | tcg_gen_add_i32(addr, addr, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7168 | if (insn & (1 << 4)) { |
| 7169 | /* tbh */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7170 | tcg_gen_add_i32(addr, addr, tmp); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 7171 | dead_tmp(tmp); |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7172 | tmp = gen_ld16u(addr, IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7173 | } else { /* tbb */ |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 7174 | dead_tmp(tmp); |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7175 | tmp = gen_ld8u(addr, IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7176 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7177 | dead_tmp(addr); |
| 7178 | tcg_gen_shli_i32(tmp, tmp, 1); |
| 7179 | tcg_gen_addi_i32(tmp, tmp, s->pc); |
| 7180 | store_reg(s, 15, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7181 | } else { |
| 7182 | /* Load/store exclusive byte/halfword/doubleword. */ |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7183 | /* ??? These are not really atomic. However we know |
| 7184 | we never have multiple CPUs running in parallel, |
| 7185 | so it is good enough. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7186 | op = (insn >> 4) & 0x3; |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7187 | /* Must use a global reg for the address because we have |
| 7188 | a conditional branch in the store instruction. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7189 | gen_movl_T1_reg(s, rn); |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7190 | addr = cpu_T[1]; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7191 | if (insn & (1 << 20)) { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7192 | gen_helper_mark_exclusive(cpu_env, addr); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7193 | switch (op) { |
| 7194 | case 0: |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7195 | tmp = gen_ld8u(addr, IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7196 | break; |
| 7197 | case 1: |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7198 | tmp = gen_ld16u(addr, IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7199 | break; |
| 7200 | case 3: |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7201 | tmp = gen_ld32(addr, IS_USER(s)); |
| 7202 | tcg_gen_addi_i32(addr, addr, 4); |
| 7203 | tmp2 = gen_ld32(addr, IS_USER(s)); |
| 7204 | store_reg(s, rd, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7205 | break; |
| 7206 | default: |
| 7207 | goto illegal_op; |
| 7208 | } |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7209 | store_reg(s, rs, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7210 | } else { |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7211 | int label = gen_new_label(); |
| 7212 | /* Must use a global that is not killed by the branch. */ |
| 7213 | gen_helper_test_exclusive(cpu_T[0], cpu_env, addr); |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 7214 | tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0], 0, label); |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7215 | tmp = load_reg(s, rs); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7216 | switch (op) { |
| 7217 | case 0: |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7218 | gen_st8(tmp, addr, IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7219 | break; |
| 7220 | case 1: |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7221 | gen_st16(tmp, addr, IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7222 | break; |
| 7223 | case 3: |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7224 | gen_st32(tmp, addr, IS_USER(s)); |
| 7225 | tcg_gen_addi_i32(addr, addr, 4); |
| 7226 | tmp = load_reg(s, rd); |
| 7227 | gen_st32(tmp, addr, IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7228 | break; |
| 7229 | default: |
| 7230 | goto illegal_op; |
| 7231 | } |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7232 | gen_set_label(label); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7233 | gen_movl_reg_T0(s, rm); |
| 7234 | } |
| 7235 | } |
| 7236 | } else { |
| 7237 | /* Load/store multiple, RFE, SRS. */ |
| 7238 | if (((insn >> 23) & 1) == ((insn >> 24) & 1)) { |
| 7239 | /* Not available in user mode. */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7240 | if (IS_USER(s)) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7241 | goto illegal_op; |
| 7242 | if (insn & (1 << 20)) { |
| 7243 | /* rfe */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7244 | addr = load_reg(s, rn); |
| 7245 | if ((insn & (1 << 24)) == 0) |
| 7246 | tcg_gen_addi_i32(addr, addr, -8); |
| 7247 | /* Load PC into tmp and CPSR into tmp2. */ |
| 7248 | tmp = gen_ld32(addr, 0); |
| 7249 | tcg_gen_addi_i32(addr, addr, 4); |
| 7250 | tmp2 = gen_ld32(addr, 0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7251 | if (insn & (1 << 21)) { |
| 7252 | /* Base writeback. */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7253 | if (insn & (1 << 24)) { |
| 7254 | tcg_gen_addi_i32(addr, addr, 4); |
| 7255 | } else { |
| 7256 | tcg_gen_addi_i32(addr, addr, -4); |
| 7257 | } |
| 7258 | store_reg(s, rn, addr); |
| 7259 | } else { |
| 7260 | dead_tmp(addr); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7261 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7262 | gen_rfe(s, tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7263 | } else { |
| 7264 | /* srs */ |
| 7265 | op = (insn & 0x1f); |
| 7266 | if (op == (env->uncached_cpsr & CPSR_M)) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7267 | addr = load_reg(s, 13); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7268 | } else { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7269 | addr = new_tmp(); |
| 7270 | gen_helper_get_r13_banked(addr, cpu_env, tcg_const_i32(op)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7271 | } |
| 7272 | if ((insn & (1 << 24)) == 0) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7273 | tcg_gen_addi_i32(addr, addr, -8); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7274 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7275 | tmp = load_reg(s, 14); |
| 7276 | gen_st32(tmp, addr, 0); |
| 7277 | tcg_gen_addi_i32(addr, addr, 4); |
| 7278 | tmp = new_tmp(); |
| 7279 | gen_helper_cpsr_read(tmp); |
| 7280 | gen_st32(tmp, addr, 0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7281 | if (insn & (1 << 21)) { |
| 7282 | if ((insn & (1 << 24)) == 0) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7283 | tcg_gen_addi_i32(addr, addr, -4); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7284 | } else { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7285 | tcg_gen_addi_i32(addr, addr, 4); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7286 | } |
| 7287 | if (op == (env->uncached_cpsr & CPSR_M)) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7288 | store_reg(s, 13, addr); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7289 | } else { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7290 | gen_helper_set_r13_banked(cpu_env, |
| 7291 | tcg_const_i32(op), addr); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7292 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7293 | } else { |
| 7294 | dead_tmp(addr); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7295 | } |
| 7296 | } |
| 7297 | } else { |
| 7298 | int i; |
| 7299 | /* Load/store multiple. */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7300 | addr = load_reg(s, rn); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7301 | offset = 0; |
| 7302 | for (i = 0; i < 16; i++) { |
| 7303 | if (insn & (1 << i)) |
| 7304 | offset += 4; |
| 7305 | } |
| 7306 | if (insn & (1 << 24)) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7307 | tcg_gen_addi_i32(addr, addr, -offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7308 | } |
| 7309 | |
| 7310 | for (i = 0; i < 16; i++) { |
| 7311 | if ((insn & (1 << i)) == 0) |
| 7312 | continue; |
| 7313 | if (insn & (1 << 20)) { |
| 7314 | /* Load. */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7315 | tmp = gen_ld32(addr, IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7316 | if (i == 15) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7317 | gen_bx(s, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7318 | } else { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7319 | store_reg(s, i, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7320 | } |
| 7321 | } else { |
| 7322 | /* Store. */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7323 | tmp = load_reg(s, i); |
| 7324 | gen_st32(tmp, addr, IS_USER(s)); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7325 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7326 | tcg_gen_addi_i32(addr, addr, 4); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7327 | } |
| 7328 | if (insn & (1 << 21)) { |
| 7329 | /* Base register writeback. */ |
| 7330 | if (insn & (1 << 24)) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7331 | tcg_gen_addi_i32(addr, addr, -offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7332 | } |
| 7333 | /* Fault if writeback register is in register list. */ |
| 7334 | if (insn & (1 << rn)) |
| 7335 | goto illegal_op; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7336 | store_reg(s, rn, addr); |
| 7337 | } else { |
| 7338 | dead_tmp(addr); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7339 | } |
| 7340 | } |
| 7341 | } |
| 7342 | break; |
| 7343 | case 5: /* Data processing register constant shift. */ |
| 7344 | if (rn == 15) |
| 7345 | gen_op_movl_T0_im(0); |
| 7346 | else |
| 7347 | gen_movl_T0_reg(s, rn); |
| 7348 | gen_movl_T1_reg(s, rm); |
| 7349 | op = (insn >> 21) & 0xf; |
| 7350 | shiftop = (insn >> 4) & 3; |
| 7351 | shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); |
| 7352 | conds = (insn & (1 << 20)) != 0; |
| 7353 | logic_cc = (conds && thumb2_logic_op(op)); |
pbrook | 9a119ff | 2008-03-31 03:45:35 +0000 | [diff] [blame] | 7354 | gen_arm_shift_im(cpu_T[1], shiftop, shift, logic_cc); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7355 | if (gen_thumb2_data_op(s, op, conds, 0)) |
| 7356 | goto illegal_op; |
| 7357 | if (rd != 15) |
| 7358 | gen_movl_reg_T0(s, rd); |
| 7359 | break; |
| 7360 | case 13: /* Misc data processing. */ |
| 7361 | op = ((insn >> 22) & 6) | ((insn >> 7) & 1); |
| 7362 | if (op < 4 && (insn & 0xf000) != 0xf000) |
| 7363 | goto illegal_op; |
| 7364 | switch (op) { |
| 7365 | case 0: /* Register controlled shift. */ |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 7366 | tmp = load_reg(s, rn); |
| 7367 | tmp2 = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7368 | if ((insn & 0x70) != 0) |
| 7369 | goto illegal_op; |
| 7370 | op = (insn >> 21) & 3; |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 7371 | logic_cc = (insn & (1 << 20)) != 0; |
| 7372 | gen_arm_shift_reg(tmp, op, tmp2, logic_cc); |
| 7373 | if (logic_cc) |
| 7374 | gen_logic_CC(tmp); |
Juha Riihimäki | 21aeb34 | 2009-05-06 09:16:12 +0300 | [diff] [blame] | 7375 | store_reg_bx(env, s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7376 | break; |
| 7377 | case 1: /* Sign/zero extend. */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7378 | tmp = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7379 | shift = (insn >> 4) & 3; |
| 7380 | /* ??? In many cases it's not neccessary to do a |
| 7381 | rotate, a shift is sufficient. */ |
| 7382 | if (shift != 0) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7383 | tcg_gen_rori_i32(tmp, tmp, shift * 8); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7384 | op = (insn >> 20) & 7; |
| 7385 | switch (op) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7386 | case 0: gen_sxth(tmp); break; |
| 7387 | case 1: gen_uxth(tmp); break; |
| 7388 | case 2: gen_sxtb16(tmp); break; |
| 7389 | case 3: gen_uxtb16(tmp); break; |
| 7390 | case 4: gen_sxtb(tmp); break; |
| 7391 | case 5: gen_uxtb(tmp); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7392 | default: goto illegal_op; |
| 7393 | } |
| 7394 | if (rn != 15) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7395 | tmp2 = load_reg(s, rn); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7396 | if ((op >> 1) == 1) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7397 | gen_add16(tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7398 | } else { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7399 | tcg_gen_add_i32(tmp, tmp, tmp2); |
| 7400 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7401 | } |
| 7402 | } |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7403 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7404 | break; |
| 7405 | case 2: /* SIMD add/subtract. */ |
| 7406 | op = (insn >> 20) & 7; |
| 7407 | shift = (insn >> 4) & 7; |
| 7408 | if ((op & 3) == 3 || (shift & 3) == 3) |
| 7409 | goto illegal_op; |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7410 | tmp = load_reg(s, rn); |
| 7411 | tmp2 = load_reg(s, rm); |
| 7412 | gen_thumb2_parallel_addsub(op, shift, tmp, tmp2); |
| 7413 | dead_tmp(tmp2); |
| 7414 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7415 | break; |
| 7416 | case 3: /* Other data processing. */ |
| 7417 | op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); |
| 7418 | if (op < 4) { |
| 7419 | /* Saturating add/subtract. */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7420 | tmp = load_reg(s, rn); |
| 7421 | tmp2 = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7422 | if (op & 2) |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7423 | gen_helper_double_saturate(tmp, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7424 | if (op & 1) |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7425 | gen_helper_sub_saturate(tmp, tmp2, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7426 | else |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7427 | gen_helper_add_saturate(tmp, tmp, tmp2); |
| 7428 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7429 | } else { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7430 | tmp = load_reg(s, rn); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7431 | switch (op) { |
| 7432 | case 0x0a: /* rbit */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7433 | gen_helper_rbit(tmp, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7434 | break; |
| 7435 | case 0x08: /* rev */ |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 7436 | tcg_gen_bswap32_i32(tmp, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7437 | break; |
| 7438 | case 0x09: /* rev16 */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7439 | gen_rev16(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7440 | break; |
| 7441 | case 0x0b: /* revsh */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7442 | gen_revsh(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7443 | break; |
| 7444 | case 0x10: /* sel */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7445 | tmp2 = load_reg(s, rm); |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7446 | tmp3 = new_tmp(); |
| 7447 | tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE)); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7448 | gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7449 | dead_tmp(tmp3); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7450 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7451 | break; |
| 7452 | case 0x18: /* clz */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7453 | gen_helper_clz(tmp, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7454 | break; |
| 7455 | default: |
| 7456 | goto illegal_op; |
| 7457 | } |
| 7458 | } |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7459 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7460 | break; |
| 7461 | case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ |
| 7462 | op = (insn >> 4) & 0xf; |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7463 | tmp = load_reg(s, rn); |
| 7464 | tmp2 = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7465 | switch ((insn >> 20) & 7) { |
| 7466 | case 0: /* 32 x 32 -> 32 */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7467 | tcg_gen_mul_i32(tmp, tmp, tmp2); |
| 7468 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7469 | if (rs != 15) { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7470 | tmp2 = load_reg(s, rs); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7471 | if (op) |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7472 | tcg_gen_sub_i32(tmp, tmp2, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7473 | else |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7474 | tcg_gen_add_i32(tmp, tmp, tmp2); |
| 7475 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7476 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7477 | break; |
| 7478 | case 1: /* 16 x 16 -> 32 */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7479 | gen_mulxy(tmp, tmp2, op & 2, op & 1); |
| 7480 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7481 | if (rs != 15) { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7482 | tmp2 = load_reg(s, rs); |
| 7483 | gen_helper_add_setq(tmp, tmp, tmp2); |
| 7484 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7485 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7486 | break; |
| 7487 | case 2: /* Dual multiply add. */ |
| 7488 | case 4: /* Dual multiply subtract. */ |
| 7489 | if (op) |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7490 | gen_swap_half(tmp2); |
| 7491 | gen_smul_dual(tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7492 | /* This addition cannot overflow. */ |
| 7493 | if (insn & (1 << 22)) { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7494 | tcg_gen_sub_i32(tmp, tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7495 | } else { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7496 | tcg_gen_add_i32(tmp, tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7497 | } |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7498 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7499 | if (rs != 15) |
| 7500 | { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7501 | tmp2 = load_reg(s, rs); |
| 7502 | gen_helper_add_setq(tmp, tmp, tmp2); |
| 7503 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7504 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7505 | break; |
| 7506 | case 3: /* 32 * 16 -> 32msb */ |
| 7507 | if (op) |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7508 | tcg_gen_sari_i32(tmp2, tmp2, 16); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7509 | else |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7510 | gen_sxth(tmp2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7511 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
| 7512 | tcg_gen_shri_i64(tmp64, tmp64, 16); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7513 | tmp = new_tmp(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7514 | tcg_gen_trunc_i64_i32(tmp, tmp64); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7515 | if (rs != 15) |
| 7516 | { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7517 | tmp2 = load_reg(s, rs); |
| 7518 | gen_helper_add_setq(tmp, tmp, tmp2); |
| 7519 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7520 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7521 | break; |
| 7522 | case 5: case 6: /* 32 * 32 -> 32msb */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7523 | gen_imull(tmp, tmp2); |
| 7524 | if (insn & (1 << 5)) { |
| 7525 | gen_roundqd(tmp, tmp2); |
| 7526 | dead_tmp(tmp2); |
| 7527 | } else { |
| 7528 | dead_tmp(tmp); |
| 7529 | tmp = tmp2; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7530 | } |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7531 | if (rs != 15) { |
| 7532 | tmp2 = load_reg(s, rs); |
| 7533 | if (insn & (1 << 21)) { |
| 7534 | tcg_gen_add_i32(tmp, tmp, tmp2); |
| 7535 | } else { |
| 7536 | tcg_gen_sub_i32(tmp, tmp2, tmp); |
| 7537 | } |
| 7538 | dead_tmp(tmp2); |
| 7539 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7540 | break; |
| 7541 | case 7: /* Unsigned sum of absolute differences. */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7542 | gen_helper_usad8(tmp, tmp, tmp2); |
| 7543 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7544 | if (rs != 15) { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7545 | tmp2 = load_reg(s, rs); |
| 7546 | tcg_gen_add_i32(tmp, tmp, tmp2); |
| 7547 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7548 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7549 | break; |
| 7550 | } |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7551 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7552 | break; |
| 7553 | case 6: case 7: /* 64-bit multiply, Divide. */ |
| 7554 | op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7555 | tmp = load_reg(s, rn); |
| 7556 | tmp2 = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7557 | if ((op & 0x50) == 0x10) { |
| 7558 | /* sdiv, udiv */ |
| 7559 | if (!arm_feature(env, ARM_FEATURE_DIV)) |
| 7560 | goto illegal_op; |
| 7561 | if (op & 0x20) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7562 | gen_helper_udiv(tmp, tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7563 | else |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7564 | gen_helper_sdiv(tmp, tmp, tmp2); |
| 7565 | dead_tmp(tmp2); |
| 7566 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7567 | } else if ((op & 0xe) == 0xc) { |
| 7568 | /* Dual multiply accumulate long. */ |
| 7569 | if (op & 1) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7570 | gen_swap_half(tmp2); |
| 7571 | gen_smul_dual(tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7572 | if (op & 0x10) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7573 | tcg_gen_sub_i32(tmp, tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7574 | } else { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7575 | tcg_gen_add_i32(tmp, tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7576 | } |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7577 | dead_tmp(tmp2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7578 | /* BUGFIX */ |
| 7579 | tmp64 = tcg_temp_new_i64(); |
| 7580 | tcg_gen_ext_i32_i64(tmp64, tmp); |
| 7581 | dead_tmp(tmp); |
| 7582 | gen_addq(s, tmp64, rs, rd); |
| 7583 | gen_storeq_reg(s, rs, rd, tmp64); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7584 | } else { |
| 7585 | if (op & 0x20) { |
| 7586 | /* Unsigned 64-bit multiply */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7587 | tmp64 = gen_mulu_i64_i32(tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7588 | } else { |
| 7589 | if (op & 8) { |
| 7590 | /* smlalxy */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7591 | gen_mulxy(tmp, tmp2, op & 2, op & 1); |
| 7592 | dead_tmp(tmp2); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7593 | tmp64 = tcg_temp_new_i64(); |
| 7594 | tcg_gen_ext_i32_i64(tmp64, tmp); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7595 | dead_tmp(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7596 | } else { |
| 7597 | /* Signed 64-bit multiply */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7598 | tmp64 = gen_muls_i64_i32(tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7599 | } |
| 7600 | } |
| 7601 | if (op & 4) { |
| 7602 | /* umaal */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7603 | gen_addq_lo(s, tmp64, rs); |
| 7604 | gen_addq_lo(s, tmp64, rd); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7605 | } else if (op & 0x40) { |
| 7606 | /* 64-bit accumulate. */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7607 | gen_addq(s, tmp64, rs, rd); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7608 | } |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 7609 | gen_storeq_reg(s, rs, rd, tmp64); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7610 | } |
| 7611 | break; |
| 7612 | } |
| 7613 | break; |
| 7614 | case 6: case 7: case 14: case 15: |
| 7615 | /* Coprocessor. */ |
| 7616 | if (((insn >> 24) & 3) == 3) { |
| 7617 | /* Translate into the equivalent ARM encoding. */ |
| 7618 | insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4); |
| 7619 | if (disas_neon_data_insn(env, s, insn)) |
| 7620 | goto illegal_op; |
| 7621 | } else { |
| 7622 | if (insn & (1 << 28)) |
| 7623 | goto illegal_op; |
| 7624 | if (disas_coproc_insn (env, s, insn)) |
| 7625 | goto illegal_op; |
| 7626 | } |
| 7627 | break; |
| 7628 | case 8: case 9: case 10: case 11: |
| 7629 | if (insn & (1 << 15)) { |
| 7630 | /* Branches, misc control. */ |
| 7631 | if (insn & 0x5000) { |
| 7632 | /* Unconditional branch. */ |
| 7633 | /* signextend(hw1[10:0]) -> offset[:12]. */ |
| 7634 | offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff; |
| 7635 | /* hw1[10:0] -> offset[11:1]. */ |
| 7636 | offset |= (insn & 0x7ff) << 1; |
| 7637 | /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22] |
| 7638 | offset[24:22] already have the same value because of the |
| 7639 | sign extension above. */ |
| 7640 | offset ^= ((~insn) & (1 << 13)) << 10; |
| 7641 | offset ^= ((~insn) & (1 << 11)) << 11; |
| 7642 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7643 | if (insn & (1 << 14)) { |
| 7644 | /* Branch and link. */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7645 | gen_op_movl_T1_im(s->pc | 1); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7646 | gen_movl_reg_T1(s, 14); |
| 7647 | } |
| 7648 | |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7649 | offset += s->pc; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7650 | if (insn & (1 << 12)) { |
| 7651 | /* b/bl */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7652 | gen_jmp(s, offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7653 | } else { |
| 7654 | /* blx */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7655 | offset &= ~(uint32_t)2; |
| 7656 | gen_bx_im(s, offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7657 | } |
| 7658 | } else if (((insn >> 23) & 7) == 7) { |
| 7659 | /* Misc control */ |
| 7660 | if (insn & (1 << 13)) |
| 7661 | goto illegal_op; |
| 7662 | |
| 7663 | if (insn & (1 << 26)) { |
| 7664 | /* Secure monitor call (v6Z) */ |
| 7665 | goto illegal_op; /* not implemented. */ |
| 7666 | } else { |
| 7667 | op = (insn >> 20) & 7; |
| 7668 | switch (op) { |
| 7669 | case 0: /* msr cpsr. */ |
| 7670 | if (IS_M(env)) { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 7671 | tmp = load_reg(s, rn); |
| 7672 | addr = tcg_const_i32(insn & 0xff); |
| 7673 | gen_helper_v7m_msr(cpu_env, addr, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7674 | gen_lookup_tb(s); |
| 7675 | break; |
| 7676 | } |
| 7677 | /* fall through */ |
| 7678 | case 1: /* msr spsr. */ |
| 7679 | if (IS_M(env)) |
| 7680 | goto illegal_op; |
| 7681 | gen_movl_T0_reg(s, rn); |
| 7682 | if (gen_set_psr_T0(s, |
| 7683 | msr_mask(env, s, (insn >> 8) & 0xf, op == 1), |
| 7684 | op == 1)) |
| 7685 | goto illegal_op; |
| 7686 | break; |
| 7687 | case 2: /* cps, nop-hint. */ |
| 7688 | if (((insn >> 8) & 7) == 0) { |
| 7689 | gen_nop_hint(s, insn & 0xff); |
| 7690 | } |
| 7691 | /* Implemented as NOP in user mode. */ |
| 7692 | if (IS_USER(s)) |
| 7693 | break; |
| 7694 | offset = 0; |
| 7695 | imm = 0; |
| 7696 | if (insn & (1 << 10)) { |
| 7697 | if (insn & (1 << 7)) |
| 7698 | offset |= CPSR_A; |
| 7699 | if (insn & (1 << 6)) |
| 7700 | offset |= CPSR_I; |
| 7701 | if (insn & (1 << 5)) |
| 7702 | offset |= CPSR_F; |
| 7703 | if (insn & (1 << 9)) |
| 7704 | imm = CPSR_A | CPSR_I | CPSR_F; |
| 7705 | } |
| 7706 | if (insn & (1 << 8)) { |
| 7707 | offset |= 0x1f; |
| 7708 | imm |= (insn & 0x1f); |
| 7709 | } |
| 7710 | if (offset) { |
| 7711 | gen_op_movl_T0_im(imm); |
| 7712 | gen_set_psr_T0(s, offset, 0); |
| 7713 | } |
| 7714 | break; |
| 7715 | case 3: /* Special control operations. */ |
| 7716 | op = (insn >> 4) & 0xf; |
| 7717 | switch (op) { |
| 7718 | case 2: /* clrex */ |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7719 | gen_helper_clrex(cpu_env); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7720 | break; |
| 7721 | case 4: /* dsb */ |
| 7722 | case 5: /* dmb */ |
| 7723 | case 6: /* isb */ |
| 7724 | /* These execute as NOPs. */ |
| 7725 | ARCH(7); |
| 7726 | break; |
| 7727 | default: |
| 7728 | goto illegal_op; |
| 7729 | } |
| 7730 | break; |
| 7731 | case 4: /* bxj */ |
| 7732 | /* Trivial implementation equivalent to bx. */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7733 | tmp = load_reg(s, rn); |
| 7734 | gen_bx(s, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7735 | break; |
| 7736 | case 5: /* Exception return. */ |
| 7737 | /* Unpredictable in user mode. */ |
| 7738 | goto illegal_op; |
| 7739 | case 6: /* mrs cpsr. */ |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 7740 | tmp = new_tmp(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7741 | if (IS_M(env)) { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 7742 | addr = tcg_const_i32(insn & 0xff); |
| 7743 | gen_helper_v7m_mrs(tmp, cpu_env, addr); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7744 | } else { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 7745 | gen_helper_cpsr_read(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7746 | } |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 7747 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7748 | break; |
| 7749 | case 7: /* mrs spsr. */ |
| 7750 | /* Not accessible in user mode. */ |
| 7751 | if (IS_USER(s) || IS_M(env)) |
| 7752 | goto illegal_op; |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7753 | tmp = load_cpu_field(spsr); |
| 7754 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7755 | break; |
| 7756 | } |
| 7757 | } |
| 7758 | } else { |
| 7759 | /* Conditional branch. */ |
| 7760 | op = (insn >> 22) & 0xf; |
| 7761 | /* Generate a conditional jump to next instruction. */ |
| 7762 | s->condlabel = gen_new_label(); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 7763 | gen_test_cc(op ^ 1, s->condlabel); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7764 | s->condjmp = 1; |
| 7765 | |
| 7766 | /* offset[11:1] = insn[10:0] */ |
| 7767 | offset = (insn & 0x7ff) << 1; |
| 7768 | /* offset[17:12] = insn[21:16]. */ |
| 7769 | offset |= (insn & 0x003f0000) >> 4; |
| 7770 | /* offset[31:20] = insn[26]. */ |
| 7771 | offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11; |
| 7772 | /* offset[18] = insn[13]. */ |
| 7773 | offset |= (insn & (1 << 13)) << 5; |
| 7774 | /* offset[19] = insn[11]. */ |
| 7775 | offset |= (insn & (1 << 11)) << 8; |
| 7776 | |
| 7777 | /* jump to the offset */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7778 | gen_jmp(s, s->pc + offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7779 | } |
| 7780 | } else { |
| 7781 | /* Data processing immediate. */ |
| 7782 | if (insn & (1 << 25)) { |
| 7783 | if (insn & (1 << 24)) { |
| 7784 | if (insn & (1 << 20)) |
| 7785 | goto illegal_op; |
| 7786 | /* Bitfield/Saturate. */ |
| 7787 | op = (insn >> 21) & 7; |
| 7788 | imm = insn & 0x1f; |
| 7789 | shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7790 | if (rn == 15) { |
| 7791 | tmp = new_tmp(); |
| 7792 | tcg_gen_movi_i32(tmp, 0); |
| 7793 | } else { |
| 7794 | tmp = load_reg(s, rn); |
| 7795 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7796 | switch (op) { |
| 7797 | case 2: /* Signed bitfield extract. */ |
| 7798 | imm++; |
| 7799 | if (shift + imm > 32) |
| 7800 | goto illegal_op; |
| 7801 | if (imm < 32) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7802 | gen_sbfx(tmp, shift, imm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7803 | break; |
| 7804 | case 6: /* Unsigned bitfield extract. */ |
| 7805 | imm++; |
| 7806 | if (shift + imm > 32) |
| 7807 | goto illegal_op; |
| 7808 | if (imm < 32) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7809 | gen_ubfx(tmp, shift, (1u << imm) - 1); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7810 | break; |
| 7811 | case 3: /* Bitfield insert/clear. */ |
| 7812 | if (imm < shift) |
| 7813 | goto illegal_op; |
| 7814 | imm = imm + 1 - shift; |
| 7815 | if (imm != 32) { |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7816 | tmp2 = load_reg(s, rd); |
pbrook | 8f8e3aa | 2008-03-31 03:48:01 +0000 | [diff] [blame] | 7817 | gen_bfi(tmp, tmp2, tmp, shift, (1u << imm) - 1); |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7818 | dead_tmp(tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7819 | } |
| 7820 | break; |
| 7821 | case 7: |
| 7822 | goto illegal_op; |
| 7823 | default: /* Saturate. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7824 | if (shift) { |
| 7825 | if (op & 1) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7826 | tcg_gen_sari_i32(tmp, tmp, shift); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7827 | else |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7828 | tcg_gen_shli_i32(tmp, tmp, shift); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7829 | } |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7830 | tmp2 = tcg_const_i32(imm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7831 | if (op & 4) { |
| 7832 | /* Unsigned. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7833 | if ((op & 1) && shift == 0) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7834 | gen_helper_usat16(tmp, tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7835 | else |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7836 | gen_helper_usat(tmp, tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7837 | } else { |
| 7838 | /* Signed. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7839 | if ((op & 1) && shift == 0) |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7840 | gen_helper_ssat16(tmp, tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7841 | else |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7842 | gen_helper_ssat(tmp, tmp, tmp2); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7843 | } |
| 7844 | break; |
| 7845 | } |
pbrook | 6ddbc6e | 2008-03-31 03:46:33 +0000 | [diff] [blame] | 7846 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7847 | } else { |
| 7848 | imm = ((insn & 0x04000000) >> 15) |
| 7849 | | ((insn & 0x7000) >> 4) | (insn & 0xff); |
| 7850 | if (insn & (1 << 22)) { |
| 7851 | /* 16-bit immediate. */ |
| 7852 | imm |= (insn >> 4) & 0xf000; |
| 7853 | if (insn & (1 << 23)) { |
| 7854 | /* movt */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7855 | tmp = load_reg(s, rd); |
pbrook | 8683143 | 2008-05-11 12:22:01 +0000 | [diff] [blame] | 7856 | tcg_gen_ext16u_i32(tmp, tmp); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7857 | tcg_gen_ori_i32(tmp, tmp, imm << 16); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7858 | } else { |
| 7859 | /* movw */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7860 | tmp = new_tmp(); |
| 7861 | tcg_gen_movi_i32(tmp, imm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7862 | } |
| 7863 | } else { |
| 7864 | /* Add/sub 12-bit immediate. */ |
| 7865 | if (rn == 15) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7866 | offset = s->pc & ~(uint32_t)3; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7867 | if (insn & (1 << 23)) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7868 | offset -= imm; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7869 | else |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7870 | offset += imm; |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7871 | tmp = new_tmp(); |
| 7872 | tcg_gen_movi_i32(tmp, offset); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7873 | } else { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7874 | tmp = load_reg(s, rn); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7875 | if (insn & (1 << 23)) |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7876 | tcg_gen_subi_i32(tmp, tmp, imm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7877 | else |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7878 | tcg_gen_addi_i32(tmp, tmp, imm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7879 | } |
| 7880 | } |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 7881 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7882 | } |
| 7883 | } else { |
| 7884 | int shifter_out = 0; |
| 7885 | /* modified 12-bit immediate. */ |
| 7886 | shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12); |
| 7887 | imm = (insn & 0xff); |
| 7888 | switch (shift) { |
| 7889 | case 0: /* XY */ |
| 7890 | /* Nothing to do. */ |
| 7891 | break; |
| 7892 | case 1: /* 00XY00XY */ |
| 7893 | imm |= imm << 16; |
| 7894 | break; |
| 7895 | case 2: /* XY00XY00 */ |
| 7896 | imm |= imm << 16; |
| 7897 | imm <<= 8; |
| 7898 | break; |
| 7899 | case 3: /* XYXYXYXY */ |
| 7900 | imm |= imm << 16; |
| 7901 | imm |= imm << 8; |
| 7902 | break; |
| 7903 | default: /* Rotated constant. */ |
| 7904 | shift = (shift << 1) | (imm >> 7); |
| 7905 | imm |= 0x80; |
| 7906 | imm = imm << (32 - shift); |
| 7907 | shifter_out = 1; |
| 7908 | break; |
| 7909 | } |
| 7910 | gen_op_movl_T1_im(imm); |
| 7911 | rn = (insn >> 16) & 0xf; |
| 7912 | if (rn == 15) |
| 7913 | gen_op_movl_T0_im(0); |
| 7914 | else |
| 7915 | gen_movl_T0_reg(s, rn); |
| 7916 | op = (insn >> 21) & 0xf; |
| 7917 | if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0, |
| 7918 | shifter_out)) |
| 7919 | goto illegal_op; |
| 7920 | rd = (insn >> 8) & 0xf; |
| 7921 | if (rd != 15) { |
| 7922 | gen_movl_reg_T0(s, rd); |
| 7923 | } |
| 7924 | } |
| 7925 | } |
| 7926 | break; |
| 7927 | case 12: /* Load/store single data item. */ |
| 7928 | { |
| 7929 | int postinc = 0; |
| 7930 | int writeback = 0; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7931 | int user; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7932 | if ((insn & 0x01100000) == 0x01000000) { |
| 7933 | if (disas_neon_ls_insn(env, s, insn)) |
| 7934 | goto illegal_op; |
| 7935 | break; |
| 7936 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7937 | user = IS_USER(s); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7938 | if (rn == 15) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7939 | addr = new_tmp(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7940 | /* PC relative. */ |
| 7941 | /* s->pc has already been incremented by 4. */ |
| 7942 | imm = s->pc & 0xfffffffc; |
| 7943 | if (insn & (1 << 23)) |
| 7944 | imm += insn & 0xfff; |
| 7945 | else |
| 7946 | imm -= insn & 0xfff; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7947 | tcg_gen_movi_i32(addr, imm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7948 | } else { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7949 | addr = load_reg(s, rn); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7950 | if (insn & (1 << 23)) { |
| 7951 | /* Positive offset. */ |
| 7952 | imm = insn & 0xfff; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7953 | tcg_gen_addi_i32(addr, addr, imm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7954 | } else { |
| 7955 | op = (insn >> 8) & 7; |
| 7956 | imm = insn & 0xff; |
| 7957 | switch (op) { |
| 7958 | case 0: case 8: /* Shifted Register. */ |
| 7959 | shift = (insn >> 4) & 0xf; |
| 7960 | if (shift > 3) |
| 7961 | goto illegal_op; |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 7962 | tmp = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7963 | if (shift) |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 7964 | tcg_gen_shli_i32(tmp, tmp, shift); |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7965 | tcg_gen_add_i32(addr, addr, tmp); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 7966 | dead_tmp(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7967 | break; |
| 7968 | case 4: /* Negative offset. */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7969 | tcg_gen_addi_i32(addr, addr, -imm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7970 | break; |
| 7971 | case 6: /* User privilege. */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7972 | tcg_gen_addi_i32(addr, addr, imm); |
| 7973 | user = 1; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7974 | break; |
| 7975 | case 1: /* Post-decrement. */ |
| 7976 | imm = -imm; |
| 7977 | /* Fall through. */ |
| 7978 | case 3: /* Post-increment. */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7979 | postinc = 1; |
| 7980 | writeback = 1; |
| 7981 | break; |
| 7982 | case 5: /* Pre-decrement. */ |
| 7983 | imm = -imm; |
| 7984 | /* Fall through. */ |
| 7985 | case 7: /* Pre-increment. */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 7986 | tcg_gen_addi_i32(addr, addr, imm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 7987 | writeback = 1; |
| 7988 | break; |
| 7989 | default: |
| 7990 | goto illegal_op; |
| 7991 | } |
| 7992 | } |
| 7993 | } |
| 7994 | op = ((insn >> 21) & 3) | ((insn >> 22) & 4); |
| 7995 | if (insn & (1 << 20)) { |
| 7996 | /* Load. */ |
| 7997 | if (rs == 15 && op != 2) { |
| 7998 | if (op & 2) |
| 7999 | goto illegal_op; |
| 8000 | /* Memory hint. Implemented as NOP. */ |
| 8001 | } else { |
| 8002 | switch (op) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8003 | case 0: tmp = gen_ld8u(addr, user); break; |
| 8004 | case 4: tmp = gen_ld8s(addr, user); break; |
| 8005 | case 1: tmp = gen_ld16u(addr, user); break; |
| 8006 | case 5: tmp = gen_ld16s(addr, user); break; |
| 8007 | case 2: tmp = gen_ld32(addr, user); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8008 | default: goto illegal_op; |
| 8009 | } |
| 8010 | if (rs == 15) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8011 | gen_bx(s, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8012 | } else { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8013 | store_reg(s, rs, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8014 | } |
| 8015 | } |
| 8016 | } else { |
| 8017 | /* Store. */ |
| 8018 | if (rs == 15) |
| 8019 | goto illegal_op; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8020 | tmp = load_reg(s, rs); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8021 | switch (op) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8022 | case 0: gen_st8(tmp, addr, user); break; |
| 8023 | case 1: gen_st16(tmp, addr, user); break; |
| 8024 | case 2: gen_st32(tmp, addr, user); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8025 | default: goto illegal_op; |
| 8026 | } |
| 8027 | } |
| 8028 | if (postinc) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8029 | tcg_gen_addi_i32(addr, addr, imm); |
| 8030 | if (writeback) { |
| 8031 | store_reg(s, rn, addr); |
| 8032 | } else { |
| 8033 | dead_tmp(addr); |
| 8034 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8035 | } |
| 8036 | break; |
| 8037 | default: |
| 8038 | goto illegal_op; |
| 8039 | } |
| 8040 | return 0; |
| 8041 | illegal_op: |
| 8042 | return 1; |
| 8043 | } |
| 8044 | |
| 8045 | static void disas_thumb_insn(CPUState *env, DisasContext *s) |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8046 | { |
| 8047 | uint32_t val, insn, op, rm, rn, rd, shift, cond; |
| 8048 | int32_t offset; |
| 8049 | int i; |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 8050 | TCGv tmp; |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8051 | TCGv tmp2; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8052 | TCGv addr; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8053 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8054 | if (s->condexec_mask) { |
| 8055 | cond = s->condexec_cond; |
| 8056 | s->condlabel = gen_new_label(); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8057 | gen_test_cc(cond ^ 1, s->condlabel); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8058 | s->condjmp = 1; |
| 8059 | } |
| 8060 | |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8061 | insn = lduw_code(s->pc); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8062 | s->pc += 2; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8063 | |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8064 | switch (insn >> 12) { |
| 8065 | case 0: case 1: |
| 8066 | rd = insn & 7; |
| 8067 | op = (insn >> 11) & 3; |
| 8068 | if (op == 3) { |
| 8069 | /* add/subtract */ |
| 8070 | rn = (insn >> 3) & 7; |
| 8071 | gen_movl_T0_reg(s, rn); |
| 8072 | if (insn & (1 << 10)) { |
| 8073 | /* immediate */ |
| 8074 | gen_op_movl_T1_im((insn >> 6) & 7); |
| 8075 | } else { |
| 8076 | /* reg */ |
| 8077 | rm = (insn >> 6) & 7; |
| 8078 | gen_movl_T1_reg(s, rm); |
| 8079 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8080 | if (insn & (1 << 9)) { |
| 8081 | if (s->condexec_mask) |
| 8082 | gen_op_subl_T0_T1(); |
| 8083 | else |
| 8084 | gen_op_subl_T0_T1_cc(); |
| 8085 | } else { |
| 8086 | if (s->condexec_mask) |
| 8087 | gen_op_addl_T0_T1(); |
| 8088 | else |
| 8089 | gen_op_addl_T0_T1_cc(); |
| 8090 | } |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8091 | gen_movl_reg_T0(s, rd); |
| 8092 | } else { |
| 8093 | /* shift immediate */ |
| 8094 | rm = (insn >> 3) & 7; |
| 8095 | shift = (insn >> 6) & 0x1f; |
pbrook | 9a119ff | 2008-03-31 03:45:35 +0000 | [diff] [blame] | 8096 | tmp = load_reg(s, rm); |
| 8097 | gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0); |
| 8098 | if (!s->condexec_mask) |
| 8099 | gen_logic_CC(tmp); |
| 8100 | store_reg(s, rd, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8101 | } |
| 8102 | break; |
| 8103 | case 2: case 3: |
| 8104 | /* arithmetic large immediate */ |
| 8105 | op = (insn >> 11) & 3; |
| 8106 | rd = (insn >> 8) & 0x7; |
| 8107 | if (op == 0) { |
| 8108 | gen_op_movl_T0_im(insn & 0xff); |
| 8109 | } else { |
| 8110 | gen_movl_T0_reg(s, rd); |
| 8111 | gen_op_movl_T1_im(insn & 0xff); |
| 8112 | } |
| 8113 | switch (op) { |
| 8114 | case 0: /* mov */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8115 | if (!s->condexec_mask) |
| 8116 | gen_op_logic_T0_cc(); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8117 | break; |
| 8118 | case 1: /* cmp */ |
| 8119 | gen_op_subl_T0_T1_cc(); |
| 8120 | break; |
| 8121 | case 2: /* add */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8122 | if (s->condexec_mask) |
| 8123 | gen_op_addl_T0_T1(); |
| 8124 | else |
| 8125 | gen_op_addl_T0_T1_cc(); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8126 | break; |
| 8127 | case 3: /* sub */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8128 | if (s->condexec_mask) |
| 8129 | gen_op_subl_T0_T1(); |
| 8130 | else |
| 8131 | gen_op_subl_T0_T1_cc(); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8132 | break; |
| 8133 | } |
| 8134 | if (op != 1) |
| 8135 | gen_movl_reg_T0(s, rd); |
| 8136 | break; |
| 8137 | case 4: |
| 8138 | if (insn & (1 << 11)) { |
| 8139 | rd = (insn >> 8) & 7; |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8140 | /* load pc-relative. Bit 1 of PC is ignored. */ |
| 8141 | val = s->pc + 2 + ((insn & 0xff) * 4); |
| 8142 | val &= ~(uint32_t)2; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8143 | addr = new_tmp(); |
| 8144 | tcg_gen_movi_i32(addr, val); |
| 8145 | tmp = gen_ld32(addr, IS_USER(s)); |
| 8146 | dead_tmp(addr); |
| 8147 | store_reg(s, rd, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8148 | break; |
| 8149 | } |
| 8150 | if (insn & (1 << 10)) { |
| 8151 | /* data processing extended or blx */ |
| 8152 | rd = (insn & 7) | ((insn >> 4) & 8); |
| 8153 | rm = (insn >> 3) & 0xf; |
| 8154 | op = (insn >> 8) & 3; |
| 8155 | switch (op) { |
| 8156 | case 0: /* add */ |
| 8157 | gen_movl_T0_reg(s, rd); |
| 8158 | gen_movl_T1_reg(s, rm); |
| 8159 | gen_op_addl_T0_T1(); |
| 8160 | gen_movl_reg_T0(s, rd); |
| 8161 | break; |
| 8162 | case 1: /* cmp */ |
| 8163 | gen_movl_T0_reg(s, rd); |
| 8164 | gen_movl_T1_reg(s, rm); |
| 8165 | gen_op_subl_T0_T1_cc(); |
| 8166 | break; |
| 8167 | case 2: /* mov/cpy */ |
| 8168 | gen_movl_T0_reg(s, rm); |
| 8169 | gen_movl_reg_T0(s, rd); |
| 8170 | break; |
| 8171 | case 3:/* branch [and link] exchange thumb register */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8172 | tmp = load_reg(s, rm); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8173 | if (insn & (1 << 7)) { |
| 8174 | val = (uint32_t)s->pc | 1; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8175 | tmp2 = new_tmp(); |
| 8176 | tcg_gen_movi_i32(tmp2, val); |
| 8177 | store_reg(s, 14, tmp2); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8178 | } |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8179 | gen_bx(s, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8180 | break; |
| 8181 | } |
| 8182 | break; |
| 8183 | } |
| 8184 | |
| 8185 | /* data processing register */ |
| 8186 | rd = insn & 7; |
| 8187 | rm = (insn >> 3) & 7; |
| 8188 | op = (insn >> 6) & 0xf; |
| 8189 | if (op == 2 || op == 3 || op == 4 || op == 7) { |
| 8190 | /* the shift/rotate ops want the operands backwards */ |
| 8191 | val = rm; |
| 8192 | rm = rd; |
| 8193 | rd = val; |
| 8194 | val = 1; |
| 8195 | } else { |
| 8196 | val = 0; |
| 8197 | } |
| 8198 | |
| 8199 | if (op == 9) /* neg */ |
| 8200 | gen_op_movl_T0_im(0); |
| 8201 | else if (op != 0xf) /* mvn doesn't read its first operand */ |
| 8202 | gen_movl_T0_reg(s, rd); |
| 8203 | |
| 8204 | gen_movl_T1_reg(s, rm); |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8205 | switch (op) { |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8206 | case 0x0: /* and */ |
| 8207 | gen_op_andl_T0_T1(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8208 | if (!s->condexec_mask) |
| 8209 | gen_op_logic_T0_cc(); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8210 | break; |
| 8211 | case 0x1: /* eor */ |
| 8212 | gen_op_xorl_T0_T1(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8213 | if (!s->condexec_mask) |
| 8214 | gen_op_logic_T0_cc(); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8215 | break; |
| 8216 | case 0x2: /* lsl */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8217 | if (s->condexec_mask) { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 8218 | gen_helper_shl(cpu_T[1], cpu_T[1], cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8219 | } else { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 8220 | gen_helper_shl_cc(cpu_T[1], cpu_T[1], cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8221 | gen_op_logic_T1_cc(); |
| 8222 | } |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8223 | break; |
| 8224 | case 0x3: /* lsr */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8225 | if (s->condexec_mask) { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 8226 | gen_helper_shr(cpu_T[1], cpu_T[1], cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8227 | } else { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 8228 | gen_helper_shr_cc(cpu_T[1], cpu_T[1], cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8229 | gen_op_logic_T1_cc(); |
| 8230 | } |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8231 | break; |
| 8232 | case 0x4: /* asr */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8233 | if (s->condexec_mask) { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 8234 | gen_helper_sar(cpu_T[1], cpu_T[1], cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8235 | } else { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 8236 | gen_helper_sar_cc(cpu_T[1], cpu_T[1], cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8237 | gen_op_logic_T1_cc(); |
| 8238 | } |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8239 | break; |
| 8240 | case 0x5: /* adc */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8241 | if (s->condexec_mask) |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 8242 | gen_adc_T0_T1(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8243 | else |
| 8244 | gen_op_adcl_T0_T1_cc(); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8245 | break; |
| 8246 | case 0x6: /* sbc */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8247 | if (s->condexec_mask) |
pbrook | 3670669 | 2008-03-31 03:46:19 +0000 | [diff] [blame] | 8248 | gen_sbc_T0_T1(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8249 | else |
| 8250 | gen_op_sbcl_T0_T1_cc(); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8251 | break; |
| 8252 | case 0x7: /* ror */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8253 | if (s->condexec_mask) { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 8254 | gen_helper_ror(cpu_T[1], cpu_T[1], cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8255 | } else { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 8256 | gen_helper_ror_cc(cpu_T[1], cpu_T[1], cpu_T[0]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8257 | gen_op_logic_T1_cc(); |
| 8258 | } |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8259 | break; |
| 8260 | case 0x8: /* tst */ |
| 8261 | gen_op_andl_T0_T1(); |
| 8262 | gen_op_logic_T0_cc(); |
| 8263 | rd = 16; |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8264 | break; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8265 | case 0x9: /* neg */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8266 | if (s->condexec_mask) |
pbrook | 390efc5 | 2008-05-11 14:35:37 +0000 | [diff] [blame] | 8267 | tcg_gen_neg_i32(cpu_T[0], cpu_T[1]); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8268 | else |
| 8269 | gen_op_subl_T0_T1_cc(); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8270 | break; |
| 8271 | case 0xa: /* cmp */ |
| 8272 | gen_op_subl_T0_T1_cc(); |
| 8273 | rd = 16; |
| 8274 | break; |
| 8275 | case 0xb: /* cmn */ |
| 8276 | gen_op_addl_T0_T1_cc(); |
| 8277 | rd = 16; |
| 8278 | break; |
| 8279 | case 0xc: /* orr */ |
| 8280 | gen_op_orl_T0_T1(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8281 | if (!s->condexec_mask) |
| 8282 | gen_op_logic_T0_cc(); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8283 | break; |
| 8284 | case 0xd: /* mul */ |
| 8285 | gen_op_mull_T0_T1(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8286 | if (!s->condexec_mask) |
| 8287 | gen_op_logic_T0_cc(); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8288 | break; |
| 8289 | case 0xe: /* bic */ |
| 8290 | gen_op_bicl_T0_T1(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8291 | if (!s->condexec_mask) |
| 8292 | gen_op_logic_T0_cc(); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8293 | break; |
| 8294 | case 0xf: /* mvn */ |
| 8295 | gen_op_notl_T1(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8296 | if (!s->condexec_mask) |
| 8297 | gen_op_logic_T1_cc(); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8298 | val = 1; |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8299 | rm = rd; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8300 | break; |
| 8301 | } |
| 8302 | if (rd != 16) { |
| 8303 | if (val) |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8304 | gen_movl_reg_T1(s, rm); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8305 | else |
| 8306 | gen_movl_reg_T0(s, rd); |
| 8307 | } |
| 8308 | break; |
| 8309 | |
| 8310 | case 5: |
| 8311 | /* load/store register offset. */ |
| 8312 | rd = insn & 7; |
| 8313 | rn = (insn >> 3) & 7; |
| 8314 | rm = (insn >> 6) & 7; |
| 8315 | op = (insn >> 9) & 7; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8316 | addr = load_reg(s, rn); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 8317 | tmp = load_reg(s, rm); |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8318 | tcg_gen_add_i32(addr, addr, tmp); |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 8319 | dead_tmp(tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8320 | |
| 8321 | if (op < 3) /* store */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8322 | tmp = load_reg(s, rd); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8323 | |
| 8324 | switch (op) { |
| 8325 | case 0: /* str */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8326 | gen_st32(tmp, addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8327 | break; |
| 8328 | case 1: /* strh */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8329 | gen_st16(tmp, addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8330 | break; |
| 8331 | case 2: /* strb */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8332 | gen_st8(tmp, addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8333 | break; |
| 8334 | case 3: /* ldrsb */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8335 | tmp = gen_ld8s(addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8336 | break; |
| 8337 | case 4: /* ldr */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8338 | tmp = gen_ld32(addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8339 | break; |
| 8340 | case 5: /* ldrh */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8341 | tmp = gen_ld16u(addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8342 | break; |
| 8343 | case 6: /* ldrb */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8344 | tmp = gen_ld8u(addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8345 | break; |
| 8346 | case 7: /* ldrsh */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8347 | tmp = gen_ld16s(addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8348 | break; |
| 8349 | } |
| 8350 | if (op >= 3) /* load */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8351 | store_reg(s, rd, tmp); |
| 8352 | dead_tmp(addr); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8353 | break; |
| 8354 | |
| 8355 | case 6: |
| 8356 | /* load/store word immediate offset */ |
| 8357 | rd = insn & 7; |
| 8358 | rn = (insn >> 3) & 7; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8359 | addr = load_reg(s, rn); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8360 | val = (insn >> 4) & 0x7c; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8361 | tcg_gen_addi_i32(addr, addr, val); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8362 | |
| 8363 | if (insn & (1 << 11)) { |
| 8364 | /* load */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8365 | tmp = gen_ld32(addr, IS_USER(s)); |
| 8366 | store_reg(s, rd, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8367 | } else { |
| 8368 | /* store */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8369 | tmp = load_reg(s, rd); |
| 8370 | gen_st32(tmp, addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8371 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8372 | dead_tmp(addr); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8373 | break; |
| 8374 | |
| 8375 | case 7: |
| 8376 | /* load/store byte immediate offset */ |
| 8377 | rd = insn & 7; |
| 8378 | rn = (insn >> 3) & 7; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8379 | addr = load_reg(s, rn); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8380 | val = (insn >> 6) & 0x1f; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8381 | tcg_gen_addi_i32(addr, addr, val); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8382 | |
| 8383 | if (insn & (1 << 11)) { |
| 8384 | /* load */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8385 | tmp = gen_ld8u(addr, IS_USER(s)); |
| 8386 | store_reg(s, rd, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8387 | } else { |
| 8388 | /* store */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8389 | tmp = load_reg(s, rd); |
| 8390 | gen_st8(tmp, addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8391 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8392 | dead_tmp(addr); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8393 | break; |
| 8394 | |
| 8395 | case 8: |
| 8396 | /* load/store halfword immediate offset */ |
| 8397 | rd = insn & 7; |
| 8398 | rn = (insn >> 3) & 7; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8399 | addr = load_reg(s, rn); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8400 | val = (insn >> 5) & 0x3e; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8401 | tcg_gen_addi_i32(addr, addr, val); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8402 | |
| 8403 | if (insn & (1 << 11)) { |
| 8404 | /* load */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8405 | tmp = gen_ld16u(addr, IS_USER(s)); |
| 8406 | store_reg(s, rd, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8407 | } else { |
| 8408 | /* store */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8409 | tmp = load_reg(s, rd); |
| 8410 | gen_st16(tmp, addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8411 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8412 | dead_tmp(addr); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8413 | break; |
| 8414 | |
| 8415 | case 9: |
| 8416 | /* load/store from stack */ |
| 8417 | rd = (insn >> 8) & 7; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8418 | addr = load_reg(s, 13); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8419 | val = (insn & 0xff) * 4; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8420 | tcg_gen_addi_i32(addr, addr, val); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8421 | |
| 8422 | if (insn & (1 << 11)) { |
| 8423 | /* load */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8424 | tmp = gen_ld32(addr, IS_USER(s)); |
| 8425 | store_reg(s, rd, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8426 | } else { |
| 8427 | /* store */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8428 | tmp = load_reg(s, rd); |
| 8429 | gen_st32(tmp, addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8430 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8431 | dead_tmp(addr); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8432 | break; |
| 8433 | |
| 8434 | case 10: |
| 8435 | /* add to high reg */ |
| 8436 | rd = (insn >> 8) & 7; |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8437 | if (insn & (1 << 11)) { |
| 8438 | /* SP */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 8439 | tmp = load_reg(s, 13); |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8440 | } else { |
| 8441 | /* PC. bit 1 is ignored. */ |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 8442 | tmp = new_tmp(); |
| 8443 | tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2); |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8444 | } |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8445 | val = (insn & 0xff) * 4; |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 8446 | tcg_gen_addi_i32(tmp, tmp, val); |
| 8447 | store_reg(s, rd, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8448 | break; |
| 8449 | |
| 8450 | case 11: |
| 8451 | /* misc */ |
| 8452 | op = (insn >> 8) & 0xf; |
| 8453 | switch (op) { |
| 8454 | case 0: |
| 8455 | /* adjust stack pointer */ |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 8456 | tmp = load_reg(s, 13); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8457 | val = (insn & 0x7f) * 4; |
| 8458 | if (insn & (1 << 7)) |
balrog | 6a0d8a1 | 2008-04-13 13:25:31 +0000 | [diff] [blame] | 8459 | val = -(int32_t)val; |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 8460 | tcg_gen_addi_i32(tmp, tmp, val); |
| 8461 | store_reg(s, 13, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8462 | break; |
| 8463 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8464 | case 2: /* sign/zero extend. */ |
| 8465 | ARCH(6); |
| 8466 | rd = insn & 7; |
| 8467 | rm = (insn >> 3) & 7; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8468 | tmp = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8469 | switch ((insn >> 6) & 3) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8470 | case 0: gen_sxth(tmp); break; |
| 8471 | case 1: gen_sxtb(tmp); break; |
| 8472 | case 2: gen_uxth(tmp); break; |
| 8473 | case 3: gen_uxtb(tmp); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8474 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8475 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8476 | break; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8477 | case 4: case 5: case 0xc: case 0xd: |
| 8478 | /* push/pop */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8479 | addr = load_reg(s, 13); |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8480 | if (insn & (1 << 8)) |
| 8481 | offset = 4; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8482 | else |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8483 | offset = 0; |
| 8484 | for (i = 0; i < 8; i++) { |
| 8485 | if (insn & (1 << i)) |
| 8486 | offset += 4; |
| 8487 | } |
| 8488 | if ((insn & (1 << 11)) == 0) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8489 | tcg_gen_addi_i32(addr, addr, -offset); |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8490 | } |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8491 | for (i = 0; i < 8; i++) { |
| 8492 | if (insn & (1 << i)) { |
| 8493 | if (insn & (1 << 11)) { |
| 8494 | /* pop */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8495 | tmp = gen_ld32(addr, IS_USER(s)); |
| 8496 | store_reg(s, i, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8497 | } else { |
| 8498 | /* push */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8499 | tmp = load_reg(s, i); |
| 8500 | gen_st32(tmp, addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8501 | } |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8502 | /* advance to the next address. */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8503 | tcg_gen_addi_i32(addr, addr, 4); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8504 | } |
| 8505 | } |
pbrook | a50f5b9 | 2008-06-29 15:25:29 +0000 | [diff] [blame] | 8506 | TCGV_UNUSED(tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8507 | if (insn & (1 << 8)) { |
| 8508 | if (insn & (1 << 11)) { |
| 8509 | /* pop pc */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8510 | tmp = gen_ld32(addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8511 | /* don't set the pc until the rest of the instruction |
| 8512 | has completed */ |
| 8513 | } else { |
| 8514 | /* push lr */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8515 | tmp = load_reg(s, 14); |
| 8516 | gen_st32(tmp, addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8517 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8518 | tcg_gen_addi_i32(addr, addr, 4); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8519 | } |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8520 | if ((insn & (1 << 11)) == 0) { |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8521 | tcg_gen_addi_i32(addr, addr, -offset); |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8522 | } |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8523 | /* write back the new stack pointer */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8524 | store_reg(s, 13, addr); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8525 | /* set the new PC value */ |
| 8526 | if ((insn & 0x0900) == 0x0900) |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8527 | gen_bx(s, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8528 | break; |
| 8529 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8530 | case 1: case 3: case 9: case 11: /* czb */ |
| 8531 | rm = insn & 7; |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8532 | tmp = load_reg(s, rm); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8533 | s->condlabel = gen_new_label(); |
| 8534 | s->condjmp = 1; |
| 8535 | if (insn & (1 << 11)) |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 8536 | tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8537 | else |
pbrook | cb63669 | 2008-05-24 02:22:00 +0000 | [diff] [blame] | 8538 | tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8539 | dead_tmp(tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8540 | offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3; |
| 8541 | val = (uint32_t)s->pc + 2; |
| 8542 | val += offset; |
| 8543 | gen_jmp(s, val); |
| 8544 | break; |
| 8545 | |
| 8546 | case 15: /* IT, nop-hint. */ |
| 8547 | if ((insn & 0xf) == 0) { |
| 8548 | gen_nop_hint(s, (insn >> 4) & 0xf); |
| 8549 | break; |
| 8550 | } |
| 8551 | /* If Then. */ |
| 8552 | s->condexec_cond = (insn >> 4) & 0xe; |
| 8553 | s->condexec_mask = insn & 0x1f; |
| 8554 | /* No actual code generated for this insn, just setup state. */ |
| 8555 | break; |
| 8556 | |
pbrook | 06c949e | 2006-02-04 19:35:26 +0000 | [diff] [blame] | 8557 | case 0xe: /* bkpt */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8558 | gen_set_condexec(s); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 8559 | gen_set_pc_im(s->pc - 2); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8560 | gen_exception(EXCP_BKPT); |
pbrook | 06c949e | 2006-02-04 19:35:26 +0000 | [diff] [blame] | 8561 | s->is_jmp = DISAS_JUMP; |
| 8562 | break; |
| 8563 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8564 | case 0xa: /* rev */ |
| 8565 | ARCH(6); |
| 8566 | rn = (insn >> 3) & 0x7; |
| 8567 | rd = insn & 0x7; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8568 | tmp = load_reg(s, rn); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8569 | switch ((insn >> 6) & 3) { |
aurel32 | 66896cb | 2009-03-13 09:34:48 +0000 | [diff] [blame] | 8570 | case 0: tcg_gen_bswap32_i32(tmp, tmp); break; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8571 | case 1: gen_rev16(tmp); break; |
| 8572 | case 3: gen_revsh(tmp); break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8573 | default: goto illegal_op; |
| 8574 | } |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8575 | store_reg(s, rd, tmp); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8576 | break; |
| 8577 | |
| 8578 | case 6: /* cps */ |
| 8579 | ARCH(6); |
| 8580 | if (IS_USER(s)) |
| 8581 | break; |
| 8582 | if (IS_M(env)) { |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 8583 | tmp = tcg_const_i32((insn & (1 << 4)) != 0); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8584 | /* PRIMASK */ |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 8585 | if (insn & 1) { |
| 8586 | addr = tcg_const_i32(16); |
| 8587 | gen_helper_v7m_msr(cpu_env, addr, tmp); |
| 8588 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8589 | /* FAULTMASK */ |
pbrook | 8984bd2 | 2008-03-31 03:47:48 +0000 | [diff] [blame] | 8590 | if (insn & 2) { |
| 8591 | addr = tcg_const_i32(17); |
| 8592 | gen_helper_v7m_msr(cpu_env, addr, tmp); |
| 8593 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8594 | gen_lookup_tb(s); |
| 8595 | } else { |
| 8596 | if (insn & (1 << 4)) |
| 8597 | shift = CPSR_A | CPSR_I | CPSR_F; |
| 8598 | else |
| 8599 | shift = 0; |
| 8600 | |
| 8601 | val = ((insn & 7) << 6) & shift; |
| 8602 | gen_op_movl_T0_im(val); |
| 8603 | gen_set_psr_T0(s, shift, 0); |
| 8604 | } |
| 8605 | break; |
| 8606 | |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8607 | default: |
| 8608 | goto undef; |
| 8609 | } |
| 8610 | break; |
| 8611 | |
| 8612 | case 12: |
| 8613 | /* load/store multiple */ |
| 8614 | rn = (insn >> 8) & 0x7; |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8615 | addr = load_reg(s, rn); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8616 | for (i = 0; i < 8; i++) { |
| 8617 | if (insn & (1 << i)) { |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8618 | if (insn & (1 << 11)) { |
| 8619 | /* load */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8620 | tmp = gen_ld32(addr, IS_USER(s)); |
| 8621 | store_reg(s, i, tmp); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8622 | } else { |
| 8623 | /* store */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8624 | tmp = load_reg(s, i); |
| 8625 | gen_st32(tmp, addr, IS_USER(s)); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8626 | } |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8627 | /* advance to the next address */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8628 | tcg_gen_addi_i32(addr, addr, 4); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8629 | } |
| 8630 | } |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8631 | /* Base register writeback. */ |
pbrook | b010980 | 2008-03-31 03:47:03 +0000 | [diff] [blame] | 8632 | if ((insn & (1 << rn)) == 0) { |
| 8633 | store_reg(s, rn, addr); |
| 8634 | } else { |
| 8635 | dead_tmp(addr); |
| 8636 | } |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8637 | break; |
| 8638 | |
| 8639 | case 13: |
| 8640 | /* conditional branch or swi */ |
| 8641 | cond = (insn >> 8) & 0xf; |
| 8642 | if (cond == 0xe) |
| 8643 | goto undef; |
| 8644 | |
| 8645 | if (cond == 0xf) { |
| 8646 | /* swi */ |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8647 | gen_set_condexec(s); |
balrog | 422ebf6 | 2008-04-16 23:17:02 +0000 | [diff] [blame] | 8648 | gen_set_pc_im(s->pc); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8649 | s->is_jmp = DISAS_SWI; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8650 | break; |
| 8651 | } |
| 8652 | /* generate a conditional jump to next instruction */ |
bellard | e50e6a2 | 2005-04-26 20:36:11 +0000 | [diff] [blame] | 8653 | s->condlabel = gen_new_label(); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8654 | gen_test_cc(cond ^ 1, s->condlabel); |
bellard | e50e6a2 | 2005-04-26 20:36:11 +0000 | [diff] [blame] | 8655 | s->condjmp = 1; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8656 | gen_movl_T1_reg(s, 15); |
| 8657 | |
| 8658 | /* jump to the offset */ |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8659 | val = (uint32_t)s->pc + 2; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8660 | offset = ((int32_t)insn << 24) >> 24; |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8661 | val += offset << 1; |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 8662 | gen_jmp(s, val); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8663 | break; |
| 8664 | |
| 8665 | case 14: |
pbrook | 358bf29 | 2006-04-09 14:38:57 +0000 | [diff] [blame] | 8666 | if (insn & (1 << 11)) { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8667 | if (disas_thumb2_insn(env, s, insn)) |
| 8668 | goto undef32; |
pbrook | 358bf29 | 2006-04-09 14:38:57 +0000 | [diff] [blame] | 8669 | break; |
| 8670 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8671 | /* unconditional branch */ |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8672 | val = (uint32_t)s->pc; |
| 8673 | offset = ((int32_t)insn << 21) >> 21; |
| 8674 | val += (offset << 1) + 2; |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 8675 | gen_jmp(s, val); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8676 | break; |
| 8677 | |
| 8678 | case 15: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8679 | if (disas_thumb2_insn(env, s, insn)) |
balrog | 6a0d8a1 | 2008-04-13 13:25:31 +0000 | [diff] [blame] | 8680 | goto undef32; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8681 | break; |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8682 | } |
| 8683 | return; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8684 | undef32: |
| 8685 | gen_set_condexec(s); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 8686 | gen_set_pc_im(s->pc - 4); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8687 | gen_exception(EXCP_UDEF); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8688 | s->is_jmp = DISAS_JUMP; |
| 8689 | return; |
| 8690 | illegal_op: |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8691 | undef: |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8692 | gen_set_condexec(s); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 8693 | gen_set_pc_im(s->pc - 2); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8694 | gen_exception(EXCP_UDEF); |
bellard | 99c475a | 2005-01-31 20:45:13 +0000 | [diff] [blame] | 8695 | s->is_jmp = DISAS_JUMP; |
| 8696 | } |
| 8697 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8698 | /* generate intermediate code in gen_opc_buf and gen_opparam_buf for |
| 8699 | basic block 'tb'. If search_pc is TRUE, also generate PC |
| 8700 | information for each intermediate instruction. */ |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 8701 | static inline void gen_intermediate_code_internal(CPUState *env, |
| 8702 | TranslationBlock *tb, |
| 8703 | int search_pc) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8704 | { |
| 8705 | DisasContext dc1, *dc = &dc1; |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 8706 | CPUBreakpoint *bp; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8707 | uint16_t *gen_opc_end; |
| 8708 | int j, lj; |
bellard | 0fa85d4 | 2005-01-03 23:43:32 +0000 | [diff] [blame] | 8709 | target_ulong pc_start; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8710 | uint32_t next_page_start; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 8711 | int num_insns; |
| 8712 | int max_insns; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 8713 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8714 | /* generate intermediate code */ |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 8715 | num_temps = 0; |
| 8716 | memset(temps, 0, sizeof(temps)); |
| 8717 | |
bellard | 0fa85d4 | 2005-01-03 23:43:32 +0000 | [diff] [blame] | 8718 | pc_start = tb->pc; |
ths | 3b46e62 | 2007-09-17 08:09:54 +0000 | [diff] [blame] | 8719 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8720 | dc->tb = tb; |
| 8721 | |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8722 | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8723 | |
| 8724 | dc->is_jmp = DISAS_NEXT; |
| 8725 | dc->pc = pc_start; |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 8726 | dc->singlestep_enabled = env->singlestep_enabled; |
bellard | e50e6a2 | 2005-04-26 20:36:11 +0000 | [diff] [blame] | 8727 | dc->condjmp = 0; |
bellard | 5899f38 | 2005-04-27 20:25:20 +0000 | [diff] [blame] | 8728 | dc->thumb = env->thumb; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8729 | dc->condexec_mask = (env->condexec_bits & 0xf) << 1; |
| 8730 | dc->condexec_cond = env->condexec_bits >> 4; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8731 | #if !defined(CONFIG_USER_ONLY) |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8732 | if (IS_M(env)) { |
| 8733 | dc->user = ((env->v7m.exception == 0) && (env->v7m.control & 1)); |
| 8734 | } else { |
| 8735 | dc->user = (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR; |
| 8736 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8737 | #endif |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 8738 | cpu_F0s = tcg_temp_new_i32(); |
| 8739 | cpu_F1s = tcg_temp_new_i32(); |
| 8740 | cpu_F0d = tcg_temp_new_i64(); |
| 8741 | cpu_F1d = tcg_temp_new_i64(); |
pbrook | ad69471 | 2008-03-31 03:48:30 +0000 | [diff] [blame] | 8742 | cpu_V0 = cpu_F0d; |
| 8743 | cpu_V1 = cpu_F1d; |
pbrook | e677137 | 2008-03-31 03:49:05 +0000 | [diff] [blame] | 8744 | /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 8745 | cpu_M0 = tcg_temp_new_i64(); |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8746 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8747 | lj = -1; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 8748 | num_insns = 0; |
| 8749 | max_insns = tb->cflags & CF_COUNT_MASK; |
| 8750 | if (max_insns == 0) |
| 8751 | max_insns = CF_COUNT_MASK; |
| 8752 | |
| 8753 | gen_icount_start(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8754 | /* Reset the conditional execution bits immediately. This avoids |
| 8755 | complications trying to do it at the end of the block. */ |
| 8756 | if (env->condexec_bits) |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 8757 | { |
| 8758 | TCGv tmp = new_tmp(); |
| 8759 | tcg_gen_movi_i32(tmp, 0); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8760 | store_cpu_field(tmp, condexec_bits); |
pbrook | 8f01245 | 2008-03-31 03:46:03 +0000 | [diff] [blame] | 8761 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8762 | do { |
pbrook | fbb4a2e | 2008-05-29 00:20:44 +0000 | [diff] [blame] | 8763 | #ifdef CONFIG_USER_ONLY |
| 8764 | /* Intercept jump to the magic kernel page. */ |
| 8765 | if (dc->pc >= 0xffff0000) { |
| 8766 | /* We always get here via a jump, so know we are not in a |
| 8767 | conditional execution block. */ |
| 8768 | gen_exception(EXCP_KERNEL_TRAP); |
| 8769 | dc->is_jmp = DISAS_UPDATE; |
| 8770 | break; |
| 8771 | } |
| 8772 | #else |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8773 | if (dc->pc >= 0xfffffff0 && IS_M(env)) { |
| 8774 | /* We always get here via a jump, so know we are not in a |
| 8775 | conditional execution block. */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8776 | gen_exception(EXCP_EXCEPTION_EXIT); |
pbrook | d60bb01 | 2008-07-11 00:27:19 +0000 | [diff] [blame] | 8777 | dc->is_jmp = DISAS_UPDATE; |
| 8778 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8779 | } |
| 8780 | #endif |
| 8781 | |
aliguori | c0ce998 | 2008-11-25 22:13:57 +0000 | [diff] [blame] | 8782 | if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) { |
| 8783 | TAILQ_FOREACH(bp, &env->breakpoints, entry) { |
aliguori | a1d1bb3 | 2008-11-18 20:07:32 +0000 | [diff] [blame] | 8784 | if (bp->pc == dc->pc) { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8785 | gen_set_condexec(dc); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 8786 | gen_set_pc_im(dc->pc); |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8787 | gen_exception(EXCP_DEBUG); |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 8788 | dc->is_jmp = DISAS_JUMP; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8789 | /* Advance PC so that clearing the breakpoint will |
| 8790 | invalidate this TB. */ |
| 8791 | dc->pc += 2; |
| 8792 | goto done_generating; |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 8793 | break; |
| 8794 | } |
| 8795 | } |
| 8796 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8797 | if (search_pc) { |
| 8798 | j = gen_opc_ptr - gen_opc_buf; |
| 8799 | if (lj < j) { |
| 8800 | lj++; |
| 8801 | while (lj < j) |
| 8802 | gen_opc_instr_start[lj++] = 0; |
| 8803 | } |
bellard | 0fa85d4 | 2005-01-03 23:43:32 +0000 | [diff] [blame] | 8804 | gen_opc_pc[lj] = dc->pc; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8805 | gen_opc_instr_start[lj] = 1; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 8806 | gen_opc_icount[lj] = num_insns; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8807 | } |
bellard | e50e6a2 | 2005-04-26 20:36:11 +0000 | [diff] [blame] | 8808 | |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 8809 | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
| 8810 | gen_io_start(); |
| 8811 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8812 | if (env->thumb) { |
| 8813 | disas_thumb_insn(env, dc); |
| 8814 | if (dc->condexec_mask) { |
| 8815 | dc->condexec_cond = (dc->condexec_cond & 0xe) |
| 8816 | | ((dc->condexec_mask >> 4) & 1); |
| 8817 | dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; |
| 8818 | if (dc->condexec_mask == 0) { |
| 8819 | dc->condexec_cond = 0; |
| 8820 | } |
| 8821 | } |
| 8822 | } else { |
| 8823 | disas_arm_insn(env, dc); |
| 8824 | } |
pbrook | b26eefb | 2008-03-31 03:44:26 +0000 | [diff] [blame] | 8825 | if (num_temps) { |
| 8826 | fprintf(stderr, "Internal resource leak before %08x\n", dc->pc); |
| 8827 | num_temps = 0; |
| 8828 | } |
bellard | e50e6a2 | 2005-04-26 20:36:11 +0000 | [diff] [blame] | 8829 | |
| 8830 | if (dc->condjmp && !dc->is_jmp) { |
| 8831 | gen_set_label(dc->condlabel); |
| 8832 | dc->condjmp = 0; |
| 8833 | } |
balrog | aaf2d97 | 2008-12-07 13:20:16 +0000 | [diff] [blame] | 8834 | /* Translation stops when a conditional branch is encountered. |
bellard | e50e6a2 | 2005-04-26 20:36:11 +0000 | [diff] [blame] | 8835 | * Otherwise the subsequent code could get translated several times. |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8836 | * Also stop translation when a page boundary is reached. This |
ths | bf20dc0 | 2008-06-30 17:22:19 +0000 | [diff] [blame] | 8837 | * ensures prefetch aborts occur at the right place. */ |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 8838 | num_insns ++; |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 8839 | } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end && |
| 8840 | !env->singlestep_enabled && |
aurel32 | 1b530a6 | 2009-04-05 20:08:59 +0000 | [diff] [blame] | 8841 | !singlestep && |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 8842 | dc->pc < next_page_start && |
| 8843 | num_insns < max_insns); |
| 8844 | |
| 8845 | if (tb->cflags & CF_LAST_IO) { |
| 8846 | if (dc->condjmp) { |
| 8847 | /* FIXME: This can theoretically happen with self-modifying |
| 8848 | code. */ |
| 8849 | cpu_abort(env, "IO on conditional branch instruction"); |
| 8850 | } |
| 8851 | gen_io_end(); |
| 8852 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8853 | |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8854 | /* At this stage dc->condjmp will only be set when the skipped |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8855 | instruction was a conditional branch or trap, and the PC has |
| 8856 | already been written. */ |
ths | 551bd27 | 2008-07-03 17:57:36 +0000 | [diff] [blame] | 8857 | if (unlikely(env->singlestep_enabled)) { |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 8858 | /* Make sure the pc is updated, and raise a debug exception. */ |
bellard | e50e6a2 | 2005-04-26 20:36:11 +0000 | [diff] [blame] | 8859 | if (dc->condjmp) { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8860 | gen_set_condexec(dc); |
| 8861 | if (dc->is_jmp == DISAS_SWI) { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8862 | gen_exception(EXCP_SWI); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8863 | } else { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8864 | gen_exception(EXCP_DEBUG); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8865 | } |
bellard | e50e6a2 | 2005-04-26 20:36:11 +0000 | [diff] [blame] | 8866 | gen_set_label(dc->condlabel); |
| 8867 | } |
| 8868 | if (dc->condjmp || !dc->is_jmp) { |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 8869 | gen_set_pc_im(dc->pc); |
bellard | e50e6a2 | 2005-04-26 20:36:11 +0000 | [diff] [blame] | 8870 | dc->condjmp = 0; |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 8871 | } |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8872 | gen_set_condexec(dc); |
| 8873 | if (dc->is_jmp == DISAS_SWI && !dc->condjmp) { |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8874 | gen_exception(EXCP_SWI); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8875 | } else { |
| 8876 | /* FIXME: Single stepping a WFI insn will not halt |
| 8877 | the CPU. */ |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8878 | gen_exception(EXCP_DEBUG); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8879 | } |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 8880 | } else { |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8881 | /* While branches must always occur at the end of an IT block, |
| 8882 | there are a few other things that can cause us to terminate |
| 8883 | the TB in the middel of an IT block: |
| 8884 | - Exception generating instructions (bkpt, swi, undefined). |
| 8885 | - Page boundaries. |
| 8886 | - Hardware watchpoints. |
| 8887 | Hardware breakpoints have already been handled and skip this code. |
| 8888 | */ |
| 8889 | gen_set_condexec(dc); |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 8890 | switch(dc->is_jmp) { |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 8891 | case DISAS_NEXT: |
bellard | 6e256c9 | 2005-11-20 10:32:05 +0000 | [diff] [blame] | 8892 | gen_goto_tb(dc, 1, dc->pc); |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 8893 | break; |
| 8894 | default: |
| 8895 | case DISAS_JUMP: |
| 8896 | case DISAS_UPDATE: |
| 8897 | /* indicate that the hash table must be used to find the next TB */ |
bellard | 57fec1f | 2008-02-01 10:50:11 +0000 | [diff] [blame] | 8898 | tcg_gen_exit_tb(0); |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 8899 | break; |
| 8900 | case DISAS_TB_JUMP: |
| 8901 | /* nothing more to generate */ |
| 8902 | break; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8903 | case DISAS_WFI: |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8904 | gen_helper_wfi(); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8905 | break; |
| 8906 | case DISAS_SWI: |
pbrook | d9ba483 | 2008-03-31 03:46:50 +0000 | [diff] [blame] | 8907 | gen_exception(EXCP_SWI); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8908 | break; |
bellard | 8aaca4c | 2005-04-23 18:27:52 +0000 | [diff] [blame] | 8909 | } |
bellard | e50e6a2 | 2005-04-26 20:36:11 +0000 | [diff] [blame] | 8910 | if (dc->condjmp) { |
| 8911 | gen_set_label(dc->condlabel); |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8912 | gen_set_condexec(dc); |
bellard | 6e256c9 | 2005-11-20 10:32:05 +0000 | [diff] [blame] | 8913 | gen_goto_tb(dc, 1, dc->pc); |
bellard | e50e6a2 | 2005-04-26 20:36:11 +0000 | [diff] [blame] | 8914 | dc->condjmp = 0; |
| 8915 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8916 | } |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 8917 | |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8918 | done_generating: |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 8919 | gen_icount_end(tb, num_insns); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8920 | *gen_opc_ptr = INDEX_op_end; |
| 8921 | |
| 8922 | #ifdef DEBUG_DISAS |
aliguori | 8fec2b8 | 2009-01-15 22:36:53 +0000 | [diff] [blame] | 8923 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 8924 | qemu_log("----------------\n"); |
| 8925 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); |
| 8926 | log_target_disas(pc_start, dc->pc - pc_start, env->thumb); |
| 8927 | qemu_log("\n"); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8928 | } |
| 8929 | #endif |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8930 | if (search_pc) { |
| 8931 | j = gen_opc_ptr - gen_opc_buf; |
| 8932 | lj++; |
| 8933 | while (lj <= j) |
| 8934 | gen_opc_instr_start[lj++] = 0; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8935 | } else { |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8936 | tb->size = dc->pc - pc_start; |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 8937 | tb->icount = num_insns; |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8938 | } |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8939 | } |
| 8940 | |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 8941 | void gen_intermediate_code(CPUState *env, TranslationBlock *tb) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8942 | { |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 8943 | gen_intermediate_code_internal(env, tb, 0); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8944 | } |
| 8945 | |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 8946 | void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8947 | { |
ths | 2cfc5f1 | 2008-07-18 18:01:29 +0000 | [diff] [blame] | 8948 | gen_intermediate_code_internal(env, tb, 1); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8949 | } |
| 8950 | |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8951 | static const char *cpu_mode_names[16] = { |
| 8952 | "usr", "fiq", "irq", "svc", "???", "???", "???", "abt", |
| 8953 | "???", "???", "???", "und", "???", "???", "???", "sys" |
| 8954 | }; |
pbrook | 9ee6e8b | 2007-11-11 00:04:49 +0000 | [diff] [blame] | 8955 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 8956 | void cpu_dump_state(CPUState *env, FILE *f, |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 8957 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
| 8958 | int flags) |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8959 | { |
| 8960 | int i; |
ths | 06e80fc | 2008-07-03 16:40:06 +0000 | [diff] [blame] | 8961 | #if 0 |
bellard | bc380d1 | 2005-05-13 22:50:47 +0000 | [diff] [blame] | 8962 | union { |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 8963 | uint32_t i; |
| 8964 | float s; |
| 8965 | } s0, s1; |
| 8966 | CPU_DoubleU d; |
pbrook | a94a6ab | 2006-10-25 17:43:33 +0000 | [diff] [blame] | 8967 | /* ??? This assumes float64 and double have the same layout. |
| 8968 | Oh well, it's only debug dumps. */ |
| 8969 | union { |
| 8970 | float64 f64; |
| 8971 | double d; |
| 8972 | } d0; |
ths | 06e80fc | 2008-07-03 16:40:06 +0000 | [diff] [blame] | 8973 | #endif |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8974 | uint32_t psr; |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8975 | |
| 8976 | for(i=0;i<16;i++) { |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 8977 | cpu_fprintf(f, "R%02d=%08x", i, env->regs[i]); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8978 | if ((i % 4) == 3) |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 8979 | cpu_fprintf(f, "\n"); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8980 | else |
bellard | 7fe4848 | 2004-10-09 18:08:01 +0000 | [diff] [blame] | 8981 | cpu_fprintf(f, " "); |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 8982 | } |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8983 | psr = cpsr_read(env); |
ths | 687fa64 | 2007-04-02 08:18:36 +0000 | [diff] [blame] | 8984 | cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n", |
| 8985 | psr, |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8986 | psr & (1 << 31) ? 'N' : '-', |
| 8987 | psr & (1 << 30) ? 'Z' : '-', |
| 8988 | psr & (1 << 29) ? 'C' : '-', |
| 8989 | psr & (1 << 28) ? 'V' : '-', |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 8990 | psr & CPSR_T ? 'T' : 'A', |
bellard | b5ff1b3 | 2005-11-26 10:38:39 +0000 | [diff] [blame] | 8991 | cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 8992 | |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 8993 | #if 0 |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 8994 | for (i = 0; i < 16; i++) { |
bellard | 8e96005 | 2005-04-07 19:42:46 +0000 | [diff] [blame] | 8995 | d.d = env->vfp.regs[i]; |
| 8996 | s0.i = d.l.lower; |
| 8997 | s1.i = d.l.upper; |
pbrook | a94a6ab | 2006-10-25 17:43:33 +0000 | [diff] [blame] | 8998 | d0.f64 = d.d; |
| 8999 | cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n", |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 9000 | i * 2, (int)s0.i, s0.s, |
pbrook | a94a6ab | 2006-10-25 17:43:33 +0000 | [diff] [blame] | 9001 | i * 2 + 1, (int)s1.i, s1.s, |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 9002 | i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower, |
pbrook | a94a6ab | 2006-10-25 17:43:33 +0000 | [diff] [blame] | 9003 | d0.d); |
bellard | b7bcbe9 | 2005-02-22 19:27:29 +0000 | [diff] [blame] | 9004 | } |
pbrook | 40f137e | 2006-02-20 00:33:36 +0000 | [diff] [blame] | 9005 | cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]); |
pbrook | 5e3f878 | 2008-03-31 03:47:34 +0000 | [diff] [blame] | 9006 | #endif |
bellard | 2c0262a | 2003-09-30 20:34:21 +0000 | [diff] [blame] | 9007 | } |
bellard | a6b025d | 2004-01-24 15:18:16 +0000 | [diff] [blame] | 9008 | |
aurel32 | d2856f1 | 2008-04-28 00:32:32 +0000 | [diff] [blame] | 9009 | void gen_pc_load(CPUState *env, TranslationBlock *tb, |
| 9010 | unsigned long searched_pc, int pc_pos, void *puc) |
| 9011 | { |
| 9012 | env->regs[15] = gen_opc_pc[pc_pos]; |
| 9013 | } |