commit e160c51ccd14a9df2628a3b31d06fd26333d6f99
author pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> Sun Nov 11 14:36:36 2007 +0000
committer pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162> Sun Nov 11 14:36:36 2007 +0000
tree 98ab78c1c7f65e3993bb2a43977902d29d4d1d68
parent 579a97f7ff4c0f958a5d8adcba717a205bb58567

Fix msr_mask.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3584 c046a42c-6fe2-441c-8c8c-71466251a162

target-arm/translate.c

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 9366bf1..513b179 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2478,7 +2478,6 @@
 /* Return the mask of PSR bits set by a MSR instruction.  */
 static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
     uint32_t mask;
-    uint32_t reserved;
 
     mask = 0;
     if (flags & (1 << 0))
@@ -2493,12 +2492,12 @@
     /* Mask out undefined bits.  */
     mask &= ~CPSR_RESERVED;
     if (!arm_feature(env, ARM_FEATURE_V6))
-        reserved &= ~(CPSR_E | CPSR_GE);
+        mask &= ~(CPSR_E | CPSR_GE);
     if (!arm_feature(env, ARM_FEATURE_THUMB2))
-        reserved &= ~CPSR_IT;
+        mask &= ~CPSR_IT;
     /* Mask out execution state bits.  */
     if (!spsr)
-        reserved &= ~CPSR_EXEC;
+        mask &= ~CPSR_EXEC;
     /* Mask out privileged bits.  */
     if (IS_USER(s))
         mask &= CPSR_USER;