commit | 7997d92f2c75cf56e8142be8e4c1fb5b8dbcc2a4 | [log] [tgz] |
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author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | Sat Jul 19 10:34:35 2008 +0000 |
committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | Sat Jul 19 10:34:35 2008 +0000 |
tree | 9b07fba4334e3de4d464ce5760febadd9e0697b2 | |
parent | 22478e79f2793aa1bc7a5019ae2e48303573e0d5 [diff] |
ARM: fix CPS masks (Vincent Palatin). According to ARM Reference Manual (DDI0100 A4.1.16), bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask should be 0x0ff10020 not 0x0ff10010. Besides, mmod flag is bit 17 (b14 is SBZ) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4899 c046a42c-6fe2-441c-8c8c-71466251a162