ARM: fix CPS masks (Vincent Palatin).

According to ARM Reference Manual (DDI0100 A4.1.16),
bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask
should be  0x0ff10020 not 0x0ff10010.
Besides, mmod flag is bit 17 (b14 is SBZ)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4899 c046a42c-6fe2-441c-8c8c-71466251a162
1 file changed