bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * MIPS emulation helpers for qemu. |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 18 | */ |
ths | 2d0e944 | 2007-04-02 15:54:05 +0000 | [diff] [blame] | 19 | #include <stdlib.h> |
Blue Swirl | 3e45717 | 2011-07-13 12:44:15 +0000 | [diff] [blame] | 20 | #include "cpu.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 21 | #include "qemu/host-utils.h" |
Richard Henderson | 2ef6175 | 2014-04-07 22:31:41 -0700 | [diff] [blame] | 22 | #include "exec/helper-proto.h" |
Paolo Bonzini | f08b617 | 2014-03-28 19:42:10 +0100 | [diff] [blame] | 23 | #include "exec/cpu_ldst.h" |
James Hogan | eddedd5 | 2014-07-28 12:37:50 +0100 | [diff] [blame] | 24 | #include "sysemu/kvm.h" |
Blue Swirl | 3e45717 | 2011-07-13 12:44:15 +0000 | [diff] [blame] | 25 | |
Paolo Bonzini | 83dae09 | 2010-06-29 09:58:49 +0200 | [diff] [blame] | 26 | #ifndef CONFIG_USER_ONLY |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 27 | static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global); |
Paolo Bonzini | 83dae09 | 2010-06-29 09:58:49 +0200 | [diff] [blame] | 28 | #endif |
| 29 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 30 | /*****************************************************************************/ |
| 31 | /* Exceptions processing helpers */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 32 | |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 33 | static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, |
| 34 | uint32_t exception, |
| 35 | int error_code, |
| 36 | uintptr_t pc) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 37 | { |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 38 | CPUState *cs = CPU(mips_env_get_cpu(env)); |
| 39 | |
陳韋任 (Wei-Ren Chen) | 0f0b939 | 2012-12-11 00:15:55 +0800 | [diff] [blame] | 40 | if (exception < EXCP_SC) { |
Richard Henderson | c855701 | 2015-08-03 11:49:12 -0700 | [diff] [blame] | 41 | qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", |
| 42 | __func__, exception, error_code); |
陳韋任 (Wei-Ren Chen) | 0f0b939 | 2012-12-11 00:15:55 +0800 | [diff] [blame] | 43 | } |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 44 | cs->exception_index = exception; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 45 | env->error_code = error_code; |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 46 | |
| 47 | if (pc) { |
| 48 | /* now we have a real cpu fault */ |
Andreas Färber | 3f38f30 | 2013-09-01 16:51:34 +0200 | [diff] [blame] | 49 | cpu_restore_state(cs, pc); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 50 | } |
| 51 | |
Andreas Färber | 5638d18 | 2013-08-27 17:52:12 +0200 | [diff] [blame] | 52 | cpu_loop_exit(cs); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 53 | } |
| 54 | |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 55 | static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, |
| 56 | uint32_t exception, |
| 57 | uintptr_t pc) |
| 58 | { |
| 59 | do_raise_exception_err(env, exception, 0, pc); |
| 60 | } |
| 61 | |
| 62 | void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, |
| 63 | int error_code) |
| 64 | { |
| 65 | do_raise_exception_err(env, exception, error_code, 0); |
| 66 | } |
| 67 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 68 | void helper_raise_exception(CPUMIPSState *env, uint32_t exception) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 69 | { |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 70 | do_raise_exception(env, exception, 0); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 71 | } |
| 72 | |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 73 | #if defined(CONFIG_USER_ONLY) |
| 74 | #define HELPER_LD(name, insn, type) \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 75 | static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ |
| 76 | int mem_idx) \ |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 77 | { \ |
Peter Maydell | 1535300 | 2015-01-20 15:19:33 +0000 | [diff] [blame] | 78 | return (type) cpu_##insn##_data(env, addr); \ |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 79 | } |
| 80 | #else |
| 81 | #define HELPER_LD(name, insn, type) \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 82 | static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ |
| 83 | int mem_idx) \ |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 84 | { \ |
| 85 | switch (mem_idx) \ |
| 86 | { \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 87 | case 0: return (type) cpu_##insn##_kernel(env, addr); break; \ |
| 88 | case 1: return (type) cpu_##insn##_super(env, addr); break; \ |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 89 | default: \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 90 | case 2: return (type) cpu_##insn##_user(env, addr); break; \ |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 91 | } \ |
| 92 | } |
| 93 | #endif |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 94 | HELPER_LD(lw, ldl, int32_t) |
Yongbok Kim | adc370a | 2015-06-01 12:13:24 +0100 | [diff] [blame] | 95 | #if defined(TARGET_MIPS64) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 96 | HELPER_LD(ld, ldq, int64_t) |
Yongbok Kim | adc370a | 2015-06-01 12:13:24 +0100 | [diff] [blame] | 97 | #endif |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 98 | #undef HELPER_LD |
| 99 | |
| 100 | #if defined(CONFIG_USER_ONLY) |
| 101 | #define HELPER_ST(name, insn, type) \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 102 | static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ |
| 103 | type val, int mem_idx) \ |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 104 | { \ |
Peter Maydell | 1535300 | 2015-01-20 15:19:33 +0000 | [diff] [blame] | 105 | cpu_##insn##_data(env, addr, val); \ |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 106 | } |
| 107 | #else |
| 108 | #define HELPER_ST(name, insn, type) \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 109 | static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ |
| 110 | type val, int mem_idx) \ |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 111 | { \ |
| 112 | switch (mem_idx) \ |
| 113 | { \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 114 | case 0: cpu_##insn##_kernel(env, addr, val); break; \ |
| 115 | case 1: cpu_##insn##_super(env, addr, val); break; \ |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 116 | default: \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 117 | case 2: cpu_##insn##_user(env, addr, val); break; \ |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 118 | } \ |
| 119 | } |
| 120 | #endif |
| 121 | HELPER_ST(sb, stb, uint8_t) |
| 122 | HELPER_ST(sw, stl, uint32_t) |
Yongbok Kim | adc370a | 2015-06-01 12:13:24 +0100 | [diff] [blame] | 123 | #if defined(TARGET_MIPS64) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 124 | HELPER_ST(sd, stq, uint64_t) |
Yongbok Kim | adc370a | 2015-06-01 12:13:24 +0100 | [diff] [blame] | 125 | #endif |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 126 | #undef HELPER_ST |
| 127 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 128 | target_ulong helper_clo (target_ulong arg1) |
ths | 3089880 | 2008-05-21 02:04:15 +0000 | [diff] [blame] | 129 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 130 | return clo32(arg1); |
ths | 3089880 | 2008-05-21 02:04:15 +0000 | [diff] [blame] | 131 | } |
| 132 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 133 | target_ulong helper_clz (target_ulong arg1) |
ths | 3089880 | 2008-05-21 02:04:15 +0000 | [diff] [blame] | 134 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 135 | return clz32(arg1); |
ths | 3089880 | 2008-05-21 02:04:15 +0000 | [diff] [blame] | 136 | } |
| 137 | |
ths | d26bc21 | 2007-11-08 18:05:37 +0000 | [diff] [blame] | 138 | #if defined(TARGET_MIPS64) |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 139 | target_ulong helper_dclo (target_ulong arg1) |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 140 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 141 | return clo64(arg1); |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 142 | } |
| 143 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 144 | target_ulong helper_dclz (target_ulong arg1) |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 145 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 146 | return clz64(arg1); |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 147 | } |
ths | d26bc21 | 2007-11-08 18:05:37 +0000 | [diff] [blame] | 148 | #endif /* TARGET_MIPS64 */ |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 149 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 150 | /* 64 bits arithmetic for 32 bits hosts */ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 151 | static inline uint64_t get_HILO(CPUMIPSState *env) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 152 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 153 | return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0]; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 154 | } |
| 155 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 156 | static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 157 | { |
Stefan Weil | 6fc97fa | 2012-03-04 08:21:39 +0100 | [diff] [blame] | 158 | target_ulong tmp; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 159 | env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
Stefan Weil | 6fc97fa | 2012-03-04 08:21:39 +0100 | [diff] [blame] | 160 | tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
| 161 | return tmp; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 162 | } |
| 163 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 164 | static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 165 | { |
Stefan Weil | 6fc97fa | 2012-03-04 08:21:39 +0100 | [diff] [blame] | 166 | target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 167 | env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
Stefan Weil | 6fc97fa | 2012-03-04 08:21:39 +0100 | [diff] [blame] | 168 | return tmp; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 169 | } |
| 170 | |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 171 | /* Multiplication variants of the vr54xx. */ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 172 | target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, |
| 173 | target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 174 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 175 | return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * |
| 176 | (int64_t)(int32_t)arg2)); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 177 | } |
| 178 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 179 | target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, |
| 180 | target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 181 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 182 | return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * |
| 183 | (uint64_t)(uint32_t)arg2); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 184 | } |
| 185 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 186 | target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, |
| 187 | target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 188 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 189 | return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * |
| 190 | (int64_t)(int32_t)arg2); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 191 | } |
| 192 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 193 | target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, |
| 194 | target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 195 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 196 | return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * |
| 197 | (int64_t)(int32_t)arg2); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 198 | } |
| 199 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 200 | target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, |
| 201 | target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 202 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 203 | return set_HI_LOT0(env, (uint64_t)get_HILO(env) + |
| 204 | (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 205 | } |
| 206 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 207 | target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, |
| 208 | target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 209 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 210 | return set_HIT0_LO(env, (uint64_t)get_HILO(env) + |
| 211 | (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 212 | } |
| 213 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 214 | target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, |
| 215 | target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 216 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 217 | return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * |
| 218 | (int64_t)(int32_t)arg2); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 219 | } |
| 220 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 221 | target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, |
| 222 | target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 223 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 224 | return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * |
| 225 | (int64_t)(int32_t)arg2); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 226 | } |
| 227 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 228 | target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, |
| 229 | target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 230 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 231 | return set_HI_LOT0(env, (uint64_t)get_HILO(env) - |
| 232 | (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 233 | } |
| 234 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 235 | target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, |
| 236 | target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 237 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 238 | return set_HIT0_LO(env, (uint64_t)get_HILO(env) - |
| 239 | (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 240 | } |
| 241 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 242 | target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, |
| 243 | target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 244 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 245 | return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 246 | } |
| 247 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 248 | target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, |
| 249 | target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 250 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 251 | return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 * |
| 252 | (uint64_t)(uint32_t)arg2); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 253 | } |
| 254 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 255 | target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, |
| 256 | target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 257 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 258 | return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * |
| 259 | (int64_t)(int32_t)arg2); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 260 | } |
| 261 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 262 | target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, |
| 263 | target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 264 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 265 | return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * |
| 266 | (uint64_t)(uint32_t)arg2); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 267 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 268 | |
Yongbok Kim | 15eacb9 | 2014-06-27 08:49:05 +0100 | [diff] [blame] | 269 | static inline target_ulong bitswap(target_ulong v) |
| 270 | { |
Leon Alrae | 74dda987 | 2014-10-22 14:00:29 +0100 | [diff] [blame] | 271 | v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) | |
| 272 | ((v & (target_ulong)0x5555555555555555ULL) << 1); |
| 273 | v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) | |
| 274 | ((v & (target_ulong)0x3333333333333333ULL) << 2); |
| 275 | v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) | |
| 276 | ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4); |
Yongbok Kim | 15eacb9 | 2014-06-27 08:49:05 +0100 | [diff] [blame] | 277 | return v; |
| 278 | } |
| 279 | |
| 280 | #ifdef TARGET_MIPS64 |
| 281 | target_ulong helper_dbitswap(target_ulong rt) |
| 282 | { |
| 283 | return bitswap(rt); |
| 284 | } |
| 285 | #endif |
| 286 | |
| 287 | target_ulong helper_bitswap(target_ulong rt) |
| 288 | { |
| 289 | return (int32_t)bitswap(rt); |
| 290 | } |
| 291 | |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 292 | #ifndef CONFIG_USER_ONLY |
Aurelien Jarno | c36bbb2 | 2010-02-06 17:02:45 +0100 | [diff] [blame] | 293 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 294 | static inline hwaddr do_translate_address(CPUMIPSState *env, |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 295 | target_ulong address, |
| 296 | int rw) |
Aurelien Jarno | c36bbb2 | 2010-02-06 17:02:45 +0100 | [diff] [blame] | 297 | { |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 298 | hwaddr lladdr; |
Aurelien Jarno | c36bbb2 | 2010-02-06 17:02:45 +0100 | [diff] [blame] | 299 | |
| 300 | lladdr = cpu_mips_translate_address(env, address, rw); |
| 301 | |
| 302 | if (lladdr == -1LL) { |
Andreas Färber | 5638d18 | 2013-08-27 17:52:12 +0200 | [diff] [blame] | 303 | cpu_loop_exit(CPU(mips_env_get_cpu(env))); |
Aurelien Jarno | c36bbb2 | 2010-02-06 17:02:45 +0100 | [diff] [blame] | 304 | } else { |
| 305 | return lladdr; |
| 306 | } |
| 307 | } |
| 308 | |
Leon Alrae | 6489dd2 | 2015-01-26 16:06:43 +0000 | [diff] [blame] | 309 | #define HELPER_LD_ATOMIC(name, insn, almask) \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 310 | target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \ |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 311 | { \ |
Leon Alrae | 6489dd2 | 2015-01-26 16:06:43 +0000 | [diff] [blame] | 312 | if (arg & almask) { \ |
| 313 | env->CP0_BadVAddr = arg; \ |
| 314 | helper_raise_exception(env, EXCP_AdEL); \ |
| 315 | } \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 316 | env->lladdr = do_translate_address(env, arg, 0); \ |
| 317 | env->llval = do_##insn(env, arg, mem_idx); \ |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 318 | return env->llval; \ |
| 319 | } |
Leon Alrae | 6489dd2 | 2015-01-26 16:06:43 +0000 | [diff] [blame] | 320 | HELPER_LD_ATOMIC(ll, lw, 0x3) |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 321 | #ifdef TARGET_MIPS64 |
Leon Alrae | 6489dd2 | 2015-01-26 16:06:43 +0000 | [diff] [blame] | 322 | HELPER_LD_ATOMIC(lld, ld, 0x7) |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 323 | #endif |
| 324 | #undef HELPER_LD_ATOMIC |
| 325 | |
| 326 | #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 327 | target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \ |
| 328 | target_ulong arg2, int mem_idx) \ |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 329 | { \ |
| 330 | target_long tmp; \ |
| 331 | \ |
| 332 | if (arg2 & almask) { \ |
| 333 | env->CP0_BadVAddr = arg2; \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 334 | helper_raise_exception(env, EXCP_AdES); \ |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 335 | } \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 336 | if (do_translate_address(env, arg2, 1) == env->lladdr) { \ |
| 337 | tmp = do_##ld_insn(env, arg2, mem_idx); \ |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 338 | if (tmp == env->llval) { \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 339 | do_##st_insn(env, arg2, arg1, mem_idx); \ |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 340 | return 1; \ |
| 341 | } \ |
| 342 | } \ |
| 343 | return 0; \ |
| 344 | } |
| 345 | HELPER_ST_ATOMIC(sc, lw, sw, 0x3) |
| 346 | #ifdef TARGET_MIPS64 |
| 347 | HELPER_ST_ATOMIC(scd, ld, sd, 0x7) |
| 348 | #endif |
| 349 | #undef HELPER_ST_ATOMIC |
| 350 | #endif |
| 351 | |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 352 | #ifdef TARGET_WORDS_BIGENDIAN |
| 353 | #define GET_LMASK(v) ((v) & 3) |
| 354 | #define GET_OFFSET(addr, offset) (addr + (offset)) |
| 355 | #else |
| 356 | #define GET_LMASK(v) (((v) & 3) ^ 3) |
| 357 | #define GET_OFFSET(addr, offset) (addr - (offset)) |
| 358 | #endif |
| 359 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 360 | void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, |
| 361 | int mem_idx) |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 362 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 363 | do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 364 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 365 | if (GET_LMASK(arg2) <= 2) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 366 | do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 367 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 368 | if (GET_LMASK(arg2) <= 1) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 369 | do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 370 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 371 | if (GET_LMASK(arg2) == 0) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 372 | do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 373 | } |
| 374 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 375 | void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, |
| 376 | int mem_idx) |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 377 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 378 | do_sb(env, arg2, (uint8_t)arg1, mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 379 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 380 | if (GET_LMASK(arg2) >= 1) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 381 | do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 382 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 383 | if (GET_LMASK(arg2) >= 2) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 384 | do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 385 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 386 | if (GET_LMASK(arg2) == 3) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 387 | do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | #if defined(TARGET_MIPS64) |
| 391 | /* "half" load and stores. We must do the memory access inline, |
| 392 | or fault handling won't work. */ |
| 393 | |
| 394 | #ifdef TARGET_WORDS_BIGENDIAN |
| 395 | #define GET_LMASK64(v) ((v) & 7) |
| 396 | #else |
| 397 | #define GET_LMASK64(v) (((v) & 7) ^ 7) |
| 398 | #endif |
| 399 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 400 | void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, |
| 401 | int mem_idx) |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 402 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 403 | do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 404 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 405 | if (GET_LMASK64(arg2) <= 6) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 406 | do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 407 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 408 | if (GET_LMASK64(arg2) <= 5) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 409 | do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 410 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 411 | if (GET_LMASK64(arg2) <= 4) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 412 | do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 413 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 414 | if (GET_LMASK64(arg2) <= 3) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 415 | do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 416 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 417 | if (GET_LMASK64(arg2) <= 2) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 418 | do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 419 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 420 | if (GET_LMASK64(arg2) <= 1) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 421 | do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 422 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 423 | if (GET_LMASK64(arg2) <= 0) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 424 | do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 425 | } |
| 426 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 427 | void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, |
| 428 | int mem_idx) |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 429 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 430 | do_sb(env, arg2, (uint8_t)arg1, mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 431 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 432 | if (GET_LMASK64(arg2) >= 1) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 433 | do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 434 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 435 | if (GET_LMASK64(arg2) >= 2) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 436 | do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 437 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 438 | if (GET_LMASK64(arg2) >= 3) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 439 | do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 440 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 441 | if (GET_LMASK64(arg2) >= 4) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 442 | do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 443 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 444 | if (GET_LMASK64(arg2) >= 5) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 445 | do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 446 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 447 | if (GET_LMASK64(arg2) >= 6) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 448 | do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 449 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 450 | if (GET_LMASK64(arg2) == 7) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 451 | do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 452 | } |
| 453 | #endif /* TARGET_MIPS64 */ |
| 454 | |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 455 | static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 }; |
| 456 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 457 | void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, |
| 458 | uint32_t mem_idx) |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 459 | { |
| 460 | target_ulong base_reglist = reglist & 0xf; |
| 461 | target_ulong do_r31 = reglist & 0x10; |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 462 | |
| 463 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
| 464 | target_ulong i; |
| 465 | |
| 466 | for (i = 0; i < base_reglist; i++) { |
Aurelien Jarno | 18bba4d | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 467 | env->active_tc.gpr[multiple_regs[i]] = |
| 468 | (target_long)do_lw(env, addr, mem_idx); |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 469 | addr += 4; |
| 470 | } |
| 471 | } |
| 472 | |
| 473 | if (do_r31) { |
Aurelien Jarno | 18bba4d | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 474 | env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx); |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 475 | } |
| 476 | } |
| 477 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 478 | void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, |
| 479 | uint32_t mem_idx) |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 480 | { |
| 481 | target_ulong base_reglist = reglist & 0xf; |
| 482 | target_ulong do_r31 = reglist & 0x10; |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 483 | |
| 484 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
| 485 | target_ulong i; |
| 486 | |
| 487 | for (i = 0; i < base_reglist; i++) { |
Aurelien Jarno | 18bba4d | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 488 | do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx); |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 489 | addr += 4; |
| 490 | } |
| 491 | } |
| 492 | |
| 493 | if (do_r31) { |
Aurelien Jarno | 18bba4d | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 494 | do_sw(env, addr, env->active_tc.gpr[31], mem_idx); |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 495 | } |
| 496 | } |
| 497 | |
| 498 | #if defined(TARGET_MIPS64) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 499 | void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, |
| 500 | uint32_t mem_idx) |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 501 | { |
| 502 | target_ulong base_reglist = reglist & 0xf; |
| 503 | target_ulong do_r31 = reglist & 0x10; |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 504 | |
| 505 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
| 506 | target_ulong i; |
| 507 | |
| 508 | for (i = 0; i < base_reglist; i++) { |
Aurelien Jarno | 18bba4d | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 509 | env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx); |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 510 | addr += 8; |
| 511 | } |
| 512 | } |
| 513 | |
| 514 | if (do_r31) { |
Aurelien Jarno | 18bba4d | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 515 | env->active_tc.gpr[31] = do_ld(env, addr, mem_idx); |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 516 | } |
| 517 | } |
| 518 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 519 | void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, |
| 520 | uint32_t mem_idx) |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 521 | { |
| 522 | target_ulong base_reglist = reglist & 0xf; |
| 523 | target_ulong do_r31 = reglist & 0x10; |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 524 | |
| 525 | if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { |
| 526 | target_ulong i; |
| 527 | |
| 528 | for (i = 0; i < base_reglist; i++) { |
Aurelien Jarno | 18bba4d | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 529 | do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx); |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 530 | addr += 8; |
| 531 | } |
| 532 | } |
| 533 | |
| 534 | if (do_r31) { |
Aurelien Jarno | 18bba4d | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 535 | do_sd(env, addr, env->active_tc.gpr[31], mem_idx); |
Nathan Froyd | 3c82410 | 2010-06-08 13:29:59 -0700 | [diff] [blame] | 536 | } |
| 537 | } |
| 538 | #endif |
| 539 | |
ths | 0eaef5a | 2008-07-23 16:14:22 +0000 | [diff] [blame] | 540 | #ifndef CONFIG_USER_ONLY |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 541 | /* SMP helpers. */ |
Andreas Färber | b35d77d | 2012-10-12 00:56:35 +0200 | [diff] [blame] | 542 | static bool mips_vpe_is_wfi(MIPSCPU *c) |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 543 | { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 544 | CPUState *cpu = CPU(c); |
Andreas Färber | b35d77d | 2012-10-12 00:56:35 +0200 | [diff] [blame] | 545 | CPUMIPSState *env = &c->env; |
| 546 | |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 547 | /* If the VPE is halted but otherwise active, it means it's waiting for |
| 548 | an interrupt. */ |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 549 | return cpu->halted && mips_vpe_active(env); |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 550 | } |
| 551 | |
Andreas Färber | c3affe5 | 2013-01-18 15:03:43 +0100 | [diff] [blame] | 552 | static inline void mips_vpe_wake(MIPSCPU *c) |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 553 | { |
| 554 | /* Dont set ->halted = 0 directly, let it be done via cpu_has_work |
| 555 | because there might be other conditions that state that c should |
| 556 | be sleeping. */ |
Andreas Färber | c3affe5 | 2013-01-18 15:03:43 +0100 | [diff] [blame] | 557 | cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE); |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 558 | } |
| 559 | |
Andreas Färber | 6f4d6b0 | 2012-10-12 00:56:37 +0200 | [diff] [blame] | 560 | static inline void mips_vpe_sleep(MIPSCPU *cpu) |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 561 | { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 562 | CPUState *cs = CPU(cpu); |
Andreas Färber | 6f4d6b0 | 2012-10-12 00:56:37 +0200 | [diff] [blame] | 563 | |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 564 | /* The VPE was shut off, really go to bed. |
| 565 | Reset any old _WAKE requests. */ |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 566 | cs->halted = 1; |
Andreas Färber | d8ed887 | 2013-01-17 22:30:20 +0100 | [diff] [blame] | 567 | cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 568 | } |
| 569 | |
Andreas Färber | 135dd63 | 2012-10-12 00:56:34 +0200 | [diff] [blame] | 570 | static inline void mips_tc_wake(MIPSCPU *cpu, int tc) |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 571 | { |
Andreas Färber | 135dd63 | 2012-10-12 00:56:34 +0200 | [diff] [blame] | 572 | CPUMIPSState *c = &cpu->env; |
| 573 | |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 574 | /* FIXME: TC reschedule. */ |
Andreas Färber | b35d77d | 2012-10-12 00:56:35 +0200 | [diff] [blame] | 575 | if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) { |
Andreas Färber | c3affe5 | 2013-01-18 15:03:43 +0100 | [diff] [blame] | 576 | mips_vpe_wake(cpu); |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 577 | } |
| 578 | } |
| 579 | |
Andreas Färber | c6679e9 | 2012-10-12 00:56:36 +0200 | [diff] [blame] | 580 | static inline void mips_tc_sleep(MIPSCPU *cpu, int tc) |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 581 | { |
Andreas Färber | c6679e9 | 2012-10-12 00:56:36 +0200 | [diff] [blame] | 582 | CPUMIPSState *c = &cpu->env; |
| 583 | |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 584 | /* FIXME: TC reschedule. */ |
| 585 | if (!mips_vpe_active(c)) { |
Andreas Färber | 6f4d6b0 | 2012-10-12 00:56:37 +0200 | [diff] [blame] | 586 | mips_vpe_sleep(cpu); |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 587 | } |
| 588 | } |
| 589 | |
Andreas Färber | 66afd1a | 2012-12-17 20:36:30 +0100 | [diff] [blame] | 590 | /** |
| 591 | * mips_cpu_map_tc: |
| 592 | * @env: CPU from which mapping is performed. |
| 593 | * @tc: Should point to an int with the value of the global TC index. |
| 594 | * |
| 595 | * This function will transform @tc into a local index within the |
| 596 | * returned #CPUMIPSState. |
| 597 | */ |
| 598 | /* FIXME: This code assumes that all VPEs have the same number of TCs, |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 599 | which depends on runtime setup. Can probably be fixed by |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 600 | walking the list of CPUMIPSStates. */ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 601 | static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 602 | { |
Andreas Färber | 38d8f5c | 2012-12-17 19:47:15 +0100 | [diff] [blame] | 603 | MIPSCPU *cpu; |
Andreas Färber | ce3960e | 2012-12-17 03:27:07 +0100 | [diff] [blame] | 604 | CPUState *cs; |
Andreas Färber | 38d8f5c | 2012-12-17 19:47:15 +0100 | [diff] [blame] | 605 | CPUState *other_cs; |
Andreas Färber | ce3960e | 2012-12-17 03:27:07 +0100 | [diff] [blame] | 606 | int vpe_idx; |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 607 | int tc_idx = *tc; |
| 608 | |
| 609 | if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { |
| 610 | /* Not allowed to address other CPUs. */ |
| 611 | *tc = env->current_tc; |
| 612 | return env; |
| 613 | } |
| 614 | |
Andreas Färber | ce3960e | 2012-12-17 03:27:07 +0100 | [diff] [blame] | 615 | cs = CPU(mips_env_get_cpu(env)); |
| 616 | vpe_idx = tc_idx / cs->nr_threads; |
| 617 | *tc = tc_idx % cs->nr_threads; |
Andreas Färber | 38d8f5c | 2012-12-17 19:47:15 +0100 | [diff] [blame] | 618 | other_cs = qemu_get_cpu(vpe_idx); |
| 619 | if (other_cs == NULL) { |
| 620 | return env; |
| 621 | } |
| 622 | cpu = MIPS_CPU(other_cs); |
| 623 | return &cpu->env; |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 624 | } |
| 625 | |
Edgar E. Iglesias | fe8dca8 | 2011-08-29 23:07:33 +0200 | [diff] [blame] | 626 | /* The per VPE CP0_Status register shares some fields with the per TC |
| 627 | CP0_TCStatus registers. These fields are wired to the same registers, |
| 628 | so changes to either of them should be reflected on both registers. |
| 629 | |
| 630 | Also, EntryHi shares the bottom 8 bit ASID with TCStauts. |
| 631 | |
| 632 | These helper call synchronizes the regs for a given cpu. */ |
| 633 | |
Maciej W. Rozycki | 81a423e | 2014-11-10 13:46:35 +0000 | [diff] [blame] | 634 | /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */ |
| 635 | /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, |
| 636 | int tc); */ |
Edgar E. Iglesias | fe8dca8 | 2011-08-29 23:07:33 +0200 | [diff] [blame] | 637 | |
| 638 | /* Called for updates to CP0_TCStatus. */ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 639 | static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, |
| 640 | target_ulong v) |
Edgar E. Iglesias | fe8dca8 | 2011-08-29 23:07:33 +0200 | [diff] [blame] | 641 | { |
| 642 | uint32_t status; |
| 643 | uint32_t tcu, tmx, tasid, tksu; |
Peter Maydell | f45cb2f | 2014-03-17 16:00:34 +0000 | [diff] [blame] | 644 | uint32_t mask = ((1U << CP0St_CU3) |
Edgar E. Iglesias | fe8dca8 | 2011-08-29 23:07:33 +0200 | [diff] [blame] | 645 | | (1 << CP0St_CU2) |
| 646 | | (1 << CP0St_CU1) |
| 647 | | (1 << CP0St_CU0) |
| 648 | | (1 << CP0St_MX) |
| 649 | | (3 << CP0St_KSU)); |
| 650 | |
| 651 | tcu = (v >> CP0TCSt_TCU0) & 0xf; |
| 652 | tmx = (v >> CP0TCSt_TMX) & 0x1; |
| 653 | tasid = v & 0xff; |
| 654 | tksu = (v >> CP0TCSt_TKSU) & 0x3; |
| 655 | |
| 656 | status = tcu << CP0St_CU0; |
| 657 | status |= tmx << CP0St_MX; |
| 658 | status |= tksu << CP0St_KSU; |
| 659 | |
| 660 | cpu->CP0_Status &= ~mask; |
| 661 | cpu->CP0_Status |= status; |
| 662 | |
| 663 | /* Sync the TASID with EntryHi. */ |
| 664 | cpu->CP0_EntryHi &= ~0xff; |
Aurelien Jarno | 6a973e6 | 2015-07-01 15:59:13 +0200 | [diff] [blame] | 665 | cpu->CP0_EntryHi |= tasid; |
Edgar E. Iglesias | fe8dca8 | 2011-08-29 23:07:33 +0200 | [diff] [blame] | 666 | |
| 667 | compute_hflags(cpu); |
| 668 | } |
| 669 | |
| 670 | /* Called for updates to CP0_EntryHi. */ |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 671 | static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) |
Edgar E. Iglesias | fe8dca8 | 2011-08-29 23:07:33 +0200 | [diff] [blame] | 672 | { |
| 673 | int32_t *tcst; |
| 674 | uint32_t asid, v = cpu->CP0_EntryHi; |
| 675 | |
| 676 | asid = v & 0xff; |
| 677 | |
| 678 | if (tc == cpu->current_tc) { |
| 679 | tcst = &cpu->active_tc.CP0_TCStatus; |
| 680 | } else { |
| 681 | tcst = &cpu->tcs[tc].CP0_TCStatus; |
| 682 | } |
| 683 | |
| 684 | *tcst &= ~0xff; |
| 685 | *tcst |= asid; |
| 686 | } |
| 687 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 688 | /* CP0 helpers */ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 689 | target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 690 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 691 | return env->mvp->CP0_MVPControl; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 692 | } |
| 693 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 694 | target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 695 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 696 | return env->mvp->CP0_MVPConf0; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 697 | } |
| 698 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 699 | target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 700 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 701 | return env->mvp->CP0_MVPConf1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 702 | } |
| 703 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 704 | target_ulong helper_mfc0_random(CPUMIPSState *env) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 705 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 706 | return (int32_t)cpu_mips_get_random(env); |
ths | 873eb01 | 2006-12-06 17:59:07 +0000 | [diff] [blame] | 707 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 708 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 709 | target_ulong helper_mfc0_tcstatus(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 710 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 711 | return env->active_tc.CP0_TCStatus; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 712 | } |
| 713 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 714 | target_ulong helper_mftc0_tcstatus(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 715 | { |
| 716 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 717 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 718 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 719 | if (other_tc == other->current_tc) |
| 720 | return other->active_tc.CP0_TCStatus; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 721 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 722 | return other->tcs[other_tc].CP0_TCStatus; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 723 | } |
| 724 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 725 | target_ulong helper_mfc0_tcbind(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 726 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 727 | return env->active_tc.CP0_TCBind; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 728 | } |
| 729 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 730 | target_ulong helper_mftc0_tcbind(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 731 | { |
| 732 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 733 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 734 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 735 | if (other_tc == other->current_tc) |
| 736 | return other->active_tc.CP0_TCBind; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 737 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 738 | return other->tcs[other_tc].CP0_TCBind; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 739 | } |
| 740 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 741 | target_ulong helper_mfc0_tcrestart(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 742 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 743 | return env->active_tc.PC; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 744 | } |
| 745 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 746 | target_ulong helper_mftc0_tcrestart(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 747 | { |
| 748 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 749 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 750 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 751 | if (other_tc == other->current_tc) |
| 752 | return other->active_tc.PC; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 753 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 754 | return other->tcs[other_tc].PC; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 755 | } |
| 756 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 757 | target_ulong helper_mfc0_tchalt(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 758 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 759 | return env->active_tc.CP0_TCHalt; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 760 | } |
| 761 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 762 | target_ulong helper_mftc0_tchalt(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 763 | { |
| 764 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 765 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 766 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 767 | if (other_tc == other->current_tc) |
| 768 | return other->active_tc.CP0_TCHalt; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 769 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 770 | return other->tcs[other_tc].CP0_TCHalt; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 771 | } |
| 772 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 773 | target_ulong helper_mfc0_tccontext(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 774 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 775 | return env->active_tc.CP0_TCContext; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 776 | } |
| 777 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 778 | target_ulong helper_mftc0_tccontext(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 779 | { |
| 780 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 781 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 782 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 783 | if (other_tc == other->current_tc) |
| 784 | return other->active_tc.CP0_TCContext; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 785 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 786 | return other->tcs[other_tc].CP0_TCContext; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 787 | } |
| 788 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 789 | target_ulong helper_mfc0_tcschedule(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 790 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 791 | return env->active_tc.CP0_TCSchedule; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 792 | } |
| 793 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 794 | target_ulong helper_mftc0_tcschedule(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 795 | { |
| 796 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 797 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 798 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 799 | if (other_tc == other->current_tc) |
| 800 | return other->active_tc.CP0_TCSchedule; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 801 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 802 | return other->tcs[other_tc].CP0_TCSchedule; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 803 | } |
| 804 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 805 | target_ulong helper_mfc0_tcschefback(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 806 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 807 | return env->active_tc.CP0_TCScheFBack; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 808 | } |
| 809 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 810 | target_ulong helper_mftc0_tcschefback(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 811 | { |
| 812 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 813 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 814 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 815 | if (other_tc == other->current_tc) |
| 816 | return other->active_tc.CP0_TCScheFBack; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 817 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 818 | return other->tcs[other_tc].CP0_TCScheFBack; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 819 | } |
| 820 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 821 | target_ulong helper_mfc0_count(CPUMIPSState *env) |
ths | 873eb01 | 2006-12-06 17:59:07 +0000 | [diff] [blame] | 822 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 823 | return (int32_t)cpu_mips_get_count(env); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 824 | } |
| 825 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 826 | target_ulong helper_mftc0_entryhi(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 827 | { |
| 828 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 829 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 830 | |
Edgar E. Iglesias | fe8dca8 | 2011-08-29 23:07:33 +0200 | [diff] [blame] | 831 | return other->CP0_EntryHi; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 832 | } |
| 833 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 834 | target_ulong helper_mftc0_cause(CPUMIPSState *env) |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 835 | { |
| 836 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 837 | int32_t tccause; |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 838 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 839 | |
| 840 | if (other_tc == other->current_tc) { |
| 841 | tccause = other->CP0_Cause; |
| 842 | } else { |
| 843 | tccause = other->CP0_Cause; |
| 844 | } |
| 845 | |
| 846 | return tccause; |
| 847 | } |
| 848 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 849 | target_ulong helper_mftc0_status(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 850 | { |
| 851 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 852 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 853 | |
Edgar E. Iglesias | fe8dca8 | 2011-08-29 23:07:33 +0200 | [diff] [blame] | 854 | return other->CP0_Status; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 855 | } |
| 856 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 857 | target_ulong helper_mfc0_lladdr(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 858 | { |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 859 | return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 860 | } |
| 861 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 862 | target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 863 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 864 | return (int32_t)env->CP0_WatchLo[sel]; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 865 | } |
| 866 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 867 | target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 868 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 869 | return env->CP0_WatchHi[sel]; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 870 | } |
| 871 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 872 | target_ulong helper_mfc0_debug(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 873 | { |
ths | 1a3fd9c | 2008-06-24 21:58:35 +0000 | [diff] [blame] | 874 | target_ulong t0 = env->CP0_Debug; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 875 | if (env->hflags & MIPS_HFLAG_DM) |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 876 | t0 |= 1 << CP0DB_DM; |
| 877 | |
| 878 | return t0; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 879 | } |
| 880 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 881 | target_ulong helper_mftc0_debug(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 882 | { |
| 883 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 884 | int32_t tcstatus; |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 885 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 886 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 887 | if (other_tc == other->current_tc) |
| 888 | tcstatus = other->active_tc.CP0_Debug_tcstatus; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 889 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 890 | tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 891 | |
| 892 | /* XXX: Might be wrong, check with EJTAG spec. */ |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 893 | return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 894 | (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 895 | } |
| 896 | |
| 897 | #if defined(TARGET_MIPS64) |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 898 | target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 899 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 900 | return env->active_tc.PC; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 901 | } |
| 902 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 903 | target_ulong helper_dmfc0_tchalt(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 904 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 905 | return env->active_tc.CP0_TCHalt; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 906 | } |
| 907 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 908 | target_ulong helper_dmfc0_tccontext(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 909 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 910 | return env->active_tc.CP0_TCContext; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 911 | } |
| 912 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 913 | target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 914 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 915 | return env->active_tc.CP0_TCSchedule; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 916 | } |
| 917 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 918 | target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 919 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 920 | return env->active_tc.CP0_TCScheFBack; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 921 | } |
| 922 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 923 | target_ulong helper_dmfc0_lladdr(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 924 | { |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 925 | return env->lladdr >> env->CP0_LLAddr_shift; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 926 | } |
| 927 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 928 | target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 929 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 930 | return env->CP0_WatchLo[sel]; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 931 | } |
| 932 | #endif /* TARGET_MIPS64 */ |
| 933 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 934 | void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 935 | { |
Leon Alrae | ba801af | 2014-07-11 16:11:34 +0100 | [diff] [blame] | 936 | uint32_t index_p = env->CP0_Index & 0x80000000; |
| 937 | uint32_t tlb_index = arg1 & 0x7fffffff; |
| 938 | if (tlb_index < env->tlb->nb_tlb) { |
| 939 | if (env->insn_flags & ISA_MIPS32R6) { |
| 940 | index_p |= arg1 & 0x80000000; |
| 941 | } |
| 942 | env->CP0_Index = index_p | tlb_index; |
| 943 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 944 | } |
| 945 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 946 | void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 947 | { |
| 948 | uint32_t mask = 0; |
| 949 | uint32_t newval; |
| 950 | |
| 951 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) |
| 952 | mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | |
| 953 | (1 << CP0MVPCo_EVP); |
| 954 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 955 | mask |= (1 << CP0MVPCo_STLB); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 956 | newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 957 | |
| 958 | // TODO: Enable/disable shared TLB, enable/disable VPEs. |
| 959 | |
| 960 | env->mvp->CP0_MVPControl = newval; |
| 961 | } |
| 962 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 963 | void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 964 | { |
| 965 | uint32_t mask; |
| 966 | uint32_t newval; |
| 967 | |
| 968 | mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | |
| 969 | (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 970 | newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 971 | |
| 972 | /* Yield scheduler intercept not implemented. */ |
| 973 | /* Gating storage scheduler intercept not implemented. */ |
| 974 | |
| 975 | // TODO: Enable/disable TCs. |
| 976 | |
| 977 | env->CP0_VPEControl = newval; |
| 978 | } |
| 979 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 980 | void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 981 | { |
| 982 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 983 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 984 | uint32_t mask; |
| 985 | uint32_t newval; |
| 986 | |
| 987 | mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | |
| 988 | (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); |
| 989 | newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask); |
| 990 | |
| 991 | /* TODO: Enable/disable TCs. */ |
| 992 | |
| 993 | other->CP0_VPEControl = newval; |
| 994 | } |
| 995 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 996 | target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env) |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 997 | { |
| 998 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 999 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1000 | /* FIXME: Mask away return zero on read bits. */ |
| 1001 | return other->CP0_VPEControl; |
| 1002 | } |
| 1003 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1004 | target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env) |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1005 | { |
| 1006 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1007 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1008 | |
| 1009 | return other->CP0_VPEConf0; |
| 1010 | } |
| 1011 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1012 | void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1013 | { |
| 1014 | uint32_t mask = 0; |
| 1015 | uint32_t newval; |
| 1016 | |
| 1017 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { |
| 1018 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) |
| 1019 | mask |= (0xff << CP0VPEC0_XTC); |
| 1020 | mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); |
| 1021 | } |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1022 | newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1023 | |
| 1024 | // TODO: TC exclusive handling due to ERL/EXL. |
| 1025 | |
| 1026 | env->CP0_VPEConf0 = newval; |
| 1027 | } |
| 1028 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1029 | void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1030 | { |
| 1031 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1032 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1033 | uint32_t mask = 0; |
| 1034 | uint32_t newval; |
| 1035 | |
| 1036 | mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); |
| 1037 | newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask); |
| 1038 | |
| 1039 | /* TODO: TC exclusive handling due to ERL/EXL. */ |
| 1040 | other->CP0_VPEConf0 = newval; |
| 1041 | } |
| 1042 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1043 | void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1044 | { |
| 1045 | uint32_t mask = 0; |
| 1046 | uint32_t newval; |
| 1047 | |
| 1048 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 1049 | mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | |
| 1050 | (0xff << CP0VPEC1_NCP1); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1051 | newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1052 | |
| 1053 | /* UDI not implemented. */ |
| 1054 | /* CP2 not implemented. */ |
| 1055 | |
| 1056 | // TODO: Handle FPU (CP1) binding. |
| 1057 | |
| 1058 | env->CP0_VPEConf1 = newval; |
| 1059 | } |
| 1060 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1061 | void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1062 | { |
| 1063 | /* Yield qualifier inputs not implemented. */ |
| 1064 | env->CP0_YQMask = 0x00000000; |
| 1065 | } |
| 1066 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1067 | void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1068 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1069 | env->CP0_VPEOpt = arg1 & 0x0000ffff; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1070 | } |
| 1071 | |
Leon Alrae | e117f52 | 2015-04-14 10:09:38 +0100 | [diff] [blame] | 1072 | #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF) |
| 1073 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1074 | void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1075 | { |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1076 | /* 1k pages not implemented */ |
Leon Alrae | 7207c7f | 2014-07-07 11:23:59 +0100 | [diff] [blame] | 1077 | target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE)); |
Leon Alrae | e117f52 | 2015-04-14 10:09:38 +0100 | [diff] [blame] | 1078 | env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env)) |
| 1079 | | (rxi << (CP0EnLo_XI - 30)); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1080 | } |
| 1081 | |
Leon Alrae | 7207c7f | 2014-07-07 11:23:59 +0100 | [diff] [blame] | 1082 | #if defined(TARGET_MIPS64) |
Leon Alrae | e117f52 | 2015-04-14 10:09:38 +0100 | [diff] [blame] | 1083 | #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6) |
| 1084 | |
Leon Alrae | 7207c7f | 2014-07-07 11:23:59 +0100 | [diff] [blame] | 1085 | void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1) |
| 1086 | { |
| 1087 | uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32); |
Leon Alrae | e117f52 | 2015-04-14 10:09:38 +0100 | [diff] [blame] | 1088 | env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi; |
Leon Alrae | 7207c7f | 2014-07-07 11:23:59 +0100 | [diff] [blame] | 1089 | } |
| 1090 | #endif |
| 1091 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1092 | void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1093 | { |
| 1094 | uint32_t mask = env->CP0_TCStatus_rw_bitmask; |
| 1095 | uint32_t newval; |
| 1096 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1097 | newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1098 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1099 | env->active_tc.CP0_TCStatus = newval; |
Edgar E. Iglesias | fe8dca8 | 2011-08-29 23:07:33 +0200 | [diff] [blame] | 1100 | sync_c0_tcstatus(env, env->current_tc, newval); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1101 | } |
| 1102 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1103 | void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1104 | { |
| 1105 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1106 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1107 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1108 | if (other_tc == other->current_tc) |
| 1109 | other->active_tc.CP0_TCStatus = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1110 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1111 | other->tcs[other_tc].CP0_TCStatus = arg1; |
Edgar E. Iglesias | fe8dca8 | 2011-08-29 23:07:33 +0200 | [diff] [blame] | 1112 | sync_c0_tcstatus(other, other_tc, arg1); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1113 | } |
| 1114 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1115 | void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1116 | { |
| 1117 | uint32_t mask = (1 << CP0TCBd_TBE); |
| 1118 | uint32_t newval; |
| 1119 | |
| 1120 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 1121 | mask |= (1 << CP0TCBd_CurVPE); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1122 | newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1123 | env->active_tc.CP0_TCBind = newval; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1124 | } |
| 1125 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1126 | void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1127 | { |
| 1128 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1129 | uint32_t mask = (1 << CP0TCBd_TBE); |
| 1130 | uint32_t newval; |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1131 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1132 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1133 | if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1134 | mask |= (1 << CP0TCBd_CurVPE); |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1135 | if (other_tc == other->current_tc) { |
| 1136 | newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); |
| 1137 | other->active_tc.CP0_TCBind = newval; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1138 | } else { |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1139 | newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask); |
| 1140 | other->tcs[other_tc].CP0_TCBind = newval; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1141 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1142 | } |
| 1143 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1144 | void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1145 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1146 | env->active_tc.PC = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1147 | env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); |
Aurelien Jarno | 5499b6f | 2009-11-22 13:08:14 +0100 | [diff] [blame] | 1148 | env->lladdr = 0ULL; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1149 | /* MIPS16 not implemented. */ |
| 1150 | } |
| 1151 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1152 | void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1153 | { |
| 1154 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1155 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1156 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1157 | if (other_tc == other->current_tc) { |
| 1158 | other->active_tc.PC = arg1; |
| 1159 | other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); |
| 1160 | other->lladdr = 0ULL; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1161 | /* MIPS16 not implemented. */ |
| 1162 | } else { |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1163 | other->tcs[other_tc].PC = arg1; |
| 1164 | other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS); |
| 1165 | other->lladdr = 0ULL; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1166 | /* MIPS16 not implemented. */ |
| 1167 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1168 | } |
| 1169 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1170 | void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1171 | { |
Andreas Färber | 135dd63 | 2012-10-12 00:56:34 +0200 | [diff] [blame] | 1172 | MIPSCPU *cpu = mips_env_get_cpu(env); |
| 1173 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1174 | env->active_tc.CP0_TCHalt = arg1 & 0x1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1175 | |
| 1176 | // TODO: Halt TC / Restart (if allocated+active) TC. |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 1177 | if (env->active_tc.CP0_TCHalt & 1) { |
Andreas Färber | c6679e9 | 2012-10-12 00:56:36 +0200 | [diff] [blame] | 1178 | mips_tc_sleep(cpu, env->current_tc); |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 1179 | } else { |
Andreas Färber | 135dd63 | 2012-10-12 00:56:34 +0200 | [diff] [blame] | 1180 | mips_tc_wake(cpu, env->current_tc); |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 1181 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1182 | } |
| 1183 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1184 | void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1185 | { |
| 1186 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1187 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
Andreas Färber | 135dd63 | 2012-10-12 00:56:34 +0200 | [diff] [blame] | 1188 | MIPSCPU *other_cpu = mips_env_get_cpu(other); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1189 | |
| 1190 | // TODO: Halt TC / Restart (if allocated+active) TC. |
| 1191 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1192 | if (other_tc == other->current_tc) |
| 1193 | other->active_tc.CP0_TCHalt = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1194 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1195 | other->tcs[other_tc].CP0_TCHalt = arg1; |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 1196 | |
| 1197 | if (arg1 & 1) { |
Andreas Färber | c6679e9 | 2012-10-12 00:56:36 +0200 | [diff] [blame] | 1198 | mips_tc_sleep(other_cpu, other_tc); |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 1199 | } else { |
Andreas Färber | 135dd63 | 2012-10-12 00:56:34 +0200 | [diff] [blame] | 1200 | mips_tc_wake(other_cpu, other_tc); |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 1201 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1202 | } |
| 1203 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1204 | void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1205 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1206 | env->active_tc.CP0_TCContext = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1207 | } |
| 1208 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1209 | void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1210 | { |
| 1211 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1212 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1213 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1214 | if (other_tc == other->current_tc) |
| 1215 | other->active_tc.CP0_TCContext = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1216 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1217 | other->tcs[other_tc].CP0_TCContext = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1218 | } |
| 1219 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1220 | void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1221 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1222 | env->active_tc.CP0_TCSchedule = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1223 | } |
| 1224 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1225 | void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1226 | { |
| 1227 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1228 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1229 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1230 | if (other_tc == other->current_tc) |
| 1231 | other->active_tc.CP0_TCSchedule = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1232 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1233 | other->tcs[other_tc].CP0_TCSchedule = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1234 | } |
| 1235 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1236 | void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1237 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1238 | env->active_tc.CP0_TCScheFBack = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1239 | } |
| 1240 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1241 | void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1242 | { |
| 1243 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1244 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1245 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1246 | if (other_tc == other->current_tc) |
| 1247 | other->active_tc.CP0_TCScheFBack = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1248 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1249 | other->tcs[other_tc].CP0_TCScheFBack = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1250 | } |
| 1251 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1252 | void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1253 | { |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1254 | /* 1k pages not implemented */ |
Leon Alrae | 7207c7f | 2014-07-07 11:23:59 +0100 | [diff] [blame] | 1255 | target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE)); |
Leon Alrae | e117f52 | 2015-04-14 10:09:38 +0100 | [diff] [blame] | 1256 | env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env)) |
| 1257 | | (rxi << (CP0EnLo_XI - 30)); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1258 | } |
| 1259 | |
Leon Alrae | 7207c7f | 2014-07-07 11:23:59 +0100 | [diff] [blame] | 1260 | #if defined(TARGET_MIPS64) |
| 1261 | void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1) |
| 1262 | { |
| 1263 | uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32); |
Leon Alrae | e117f52 | 2015-04-14 10:09:38 +0100 | [diff] [blame] | 1264 | env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi; |
Leon Alrae | 7207c7f | 2014-07-07 11:23:59 +0100 | [diff] [blame] | 1265 | } |
| 1266 | #endif |
| 1267 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1268 | void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1269 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1270 | env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1271 | } |
| 1272 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1273 | void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1274 | { |
Leon Alrae | ba801af | 2014-07-11 16:11:34 +0100 | [diff] [blame] | 1275 | uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1); |
| 1276 | if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) || |
| 1277 | (mask == 0x0000 || mask == 0x0003 || mask == 0x000F || |
| 1278 | mask == 0x003F || mask == 0x00FF || mask == 0x03FF || |
| 1279 | mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) { |
| 1280 | env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); |
| 1281 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1282 | } |
| 1283 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1284 | void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1285 | { |
| 1286 | /* SmartMIPS not implemented */ |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1287 | /* 1k pages not implemented */ |
Leon Alrae | 7207c7f | 2014-07-07 11:23:59 +0100 | [diff] [blame] | 1288 | env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) | |
| 1289 | (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask); |
Leon Alrae | e117f52 | 2015-04-14 10:09:38 +0100 | [diff] [blame] | 1290 | compute_hflags(env); |
| 1291 | restore_pamask(env); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1292 | } |
| 1293 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1294 | void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1295 | { |
Leon Alrae | ba801af | 2014-07-11 16:11:34 +0100 | [diff] [blame] | 1296 | if (env->insn_flags & ISA_MIPS32R6) { |
| 1297 | if (arg1 < env->tlb->nb_tlb) { |
| 1298 | env->CP0_Wired = arg1; |
| 1299 | } |
| 1300 | } else { |
| 1301 | env->CP0_Wired = arg1 % env->tlb->nb_tlb; |
| 1302 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1303 | } |
| 1304 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1305 | void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1306 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1307 | env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1308 | } |
| 1309 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1310 | void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1311 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1312 | env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1313 | } |
| 1314 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1315 | void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1316 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1317 | env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1318 | } |
| 1319 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1320 | void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1321 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1322 | env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1323 | } |
| 1324 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1325 | void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1326 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1327 | env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1328 | } |
| 1329 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1330 | void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1331 | { |
Petar Jovanovic | d279279 | 2014-06-18 17:48:20 +0200 | [diff] [blame] | 1332 | uint32_t mask = 0x0000000F; |
| 1333 | |
| 1334 | if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { |
| 1335 | mask |= (1 << 29); |
| 1336 | |
| 1337 | if (arg1 & (1 << 29)) { |
| 1338 | env->hflags |= MIPS_HFLAG_HWRENA_ULR; |
| 1339 | } else { |
| 1340 | env->hflags &= ~MIPS_HFLAG_HWRENA_ULR; |
| 1341 | } |
| 1342 | } |
| 1343 | |
| 1344 | env->CP0_HWREna = arg1 & mask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1345 | } |
| 1346 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1347 | void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1348 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1349 | cpu_mips_store_count(env, arg1); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1350 | } |
| 1351 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1352 | void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1353 | { |
Leon Alrae | 9456c2f | 2014-07-07 11:24:00 +0100 | [diff] [blame] | 1354 | target_ulong old, val, mask; |
| 1355 | mask = (TARGET_PAGE_MASK << 1) | 0xFF; |
| 1356 | if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) { |
| 1357 | mask |= 1 << CP0EnHi_EHINV; |
| 1358 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1359 | |
| 1360 | /* 1k pages not implemented */ |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1361 | #if defined(TARGET_MIPS64) |
Leon Alrae | ba801af | 2014-07-11 16:11:34 +0100 | [diff] [blame] | 1362 | if (env->insn_flags & ISA_MIPS32R6) { |
| 1363 | int entryhi_r = extract64(arg1, 62, 2); |
| 1364 | int config0_at = extract32(env->CP0_Config0, 13, 2); |
| 1365 | bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0; |
| 1366 | if ((entryhi_r == 2) || |
| 1367 | (entryhi_r == 1 && (no_supervisor || config0_at == 1))) { |
| 1368 | /* skip EntryHi.R field if new value is reserved */ |
| 1369 | mask &= ~(0x3ull << 62); |
| 1370 | } |
| 1371 | } |
| 1372 | mask &= env->SEGMask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1373 | #endif |
| 1374 | old = env->CP0_EntryHi; |
Leon Alrae | ba801af | 2014-07-11 16:11:34 +0100 | [diff] [blame] | 1375 | val = (arg1 & mask) | (old & ~mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1376 | env->CP0_EntryHi = val; |
| 1377 | if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
Edgar E. Iglesias | fe8dca8 | 2011-08-29 23:07:33 +0200 | [diff] [blame] | 1378 | sync_c0_entryhi(env, env->current_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1379 | } |
| 1380 | /* If the ASID changes, flush qemu's TLB. */ |
| 1381 | if ((old & 0xFF) != (val & 0xFF)) |
| 1382 | cpu_mips_tlb_flush(env, 1); |
| 1383 | } |
| 1384 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1385 | void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1386 | { |
| 1387 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1388 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1389 | |
Edgar E. Iglesias | fe8dca8 | 2011-08-29 23:07:33 +0200 | [diff] [blame] | 1390 | other->CP0_EntryHi = arg1; |
| 1391 | sync_c0_entryhi(other, other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1392 | } |
| 1393 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1394 | void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1395 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1396 | cpu_mips_store_compare(env, arg1); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1397 | } |
| 1398 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1399 | void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1400 | { |
Andreas Färber | a47dddd | 2013-09-03 17:38:47 +0200 | [diff] [blame] | 1401 | MIPSCPU *cpu = mips_env_get_cpu(env); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1402 | uint32_t val, old; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1403 | |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1404 | old = env->CP0_Status; |
Maciej W. Rozycki | 81a423e | 2014-11-10 13:46:35 +0000 | [diff] [blame] | 1405 | cpu_mips_store_status(env, arg1); |
| 1406 | val = env->CP0_Status; |
Edgar E. Iglesias | fe8dca8 | 2011-08-29 23:07:33 +0200 | [diff] [blame] | 1407 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1408 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
| 1409 | qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x", |
| 1410 | old, old & env->CP0_Cause & CP0Ca_IP_mask, |
| 1411 | val, val & env->CP0_Cause & CP0Ca_IP_mask, |
| 1412 | env->CP0_Cause); |
| 1413 | switch (env->hflags & MIPS_HFLAG_KSU) { |
| 1414 | case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; |
| 1415 | case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; |
| 1416 | case MIPS_HFLAG_KM: qemu_log("\n"); break; |
Andreas Färber | a47dddd | 2013-09-03 17:38:47 +0200 | [diff] [blame] | 1417 | default: |
| 1418 | cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); |
| 1419 | break; |
Aurelien Jarno | 31e3104 | 2009-11-14 13:10:00 +0100 | [diff] [blame] | 1420 | } |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1421 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1422 | } |
| 1423 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1424 | void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1425 | { |
| 1426 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Maciej W. Rozycki | 1d725ae | 2014-11-20 11:15:34 +0000 | [diff] [blame] | 1427 | uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018; |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1428 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1429 | |
Maciej W. Rozycki | 1d725ae | 2014-11-20 11:15:34 +0000 | [diff] [blame] | 1430 | other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1431 | sync_c0_status(env, other, other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1432 | } |
| 1433 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1434 | void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1435 | { |
Edgar E. Iglesias | bc45a67 | 2011-08-29 23:07:35 +0200 | [diff] [blame] | 1436 | env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1437 | } |
| 1438 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1439 | void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1440 | { |
| 1441 | uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1442 | env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1443 | } |
| 1444 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1445 | void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1) |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1446 | { |
Maciej W. Rozycki | 81a423e | 2014-11-10 13:46:35 +0000 | [diff] [blame] | 1447 | cpu_mips_store_cause(env, arg1); |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1448 | } |
| 1449 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1450 | void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1) |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1451 | { |
| 1452 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1453 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1454 | |
Maciej W. Rozycki | 81a423e | 2014-11-10 13:46:35 +0000 | [diff] [blame] | 1455 | cpu_mips_store_cause(other, arg1); |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1456 | } |
| 1457 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1458 | target_ulong helper_mftc0_epc(CPUMIPSState *env) |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1459 | { |
| 1460 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1461 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1462 | |
| 1463 | return other->CP0_EPC; |
| 1464 | } |
| 1465 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1466 | target_ulong helper_mftc0_ebase(CPUMIPSState *env) |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1467 | { |
| 1468 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1469 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1470 | |
| 1471 | return other->CP0_EBase; |
| 1472 | } |
| 1473 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1474 | void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1475 | { |
Hervé Poussineau | 671b0f3 | 2010-07-31 12:29:03 +0200 | [diff] [blame] | 1476 | env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1477 | } |
| 1478 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1479 | void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1) |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1480 | { |
| 1481 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1482 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1483 | other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); |
| 1484 | } |
| 1485 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1486 | target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx) |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1487 | { |
| 1488 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1489 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
Edgar E. Iglesias | 5a25ce9 | 2011-08-29 23:07:34 +0200 | [diff] [blame] | 1490 | |
| 1491 | switch (idx) { |
| 1492 | case 0: return other->CP0_Config0; |
| 1493 | case 1: return other->CP0_Config1; |
| 1494 | case 2: return other->CP0_Config2; |
| 1495 | case 3: return other->CP0_Config3; |
| 1496 | /* 4 and 5 are reserved. */ |
| 1497 | case 6: return other->CP0_Config6; |
| 1498 | case 7: return other->CP0_Config7; |
| 1499 | default: |
| 1500 | break; |
| 1501 | } |
| 1502 | return 0; |
| 1503 | } |
| 1504 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1505 | void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1506 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1507 | env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1508 | } |
| 1509 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1510 | void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1511 | { |
| 1512 | /* tertiary/secondary caches not implemented */ |
| 1513 | env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); |
| 1514 | } |
| 1515 | |
Maciej W. Rozycki | 90f12d7 | 2014-11-18 03:59:07 +0000 | [diff] [blame] | 1516 | void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1) |
| 1517 | { |
| 1518 | if (env->insn_flags & ASE_MICROMIPS) { |
| 1519 | env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) | |
| 1520 | (arg1 & (1 << CP0C3_ISA_ON_EXC)); |
| 1521 | } |
| 1522 | } |
| 1523 | |
Petar Jovanovic | b4160af | 2014-01-24 13:45:05 +0100 | [diff] [blame] | 1524 | void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1) |
| 1525 | { |
| 1526 | env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) | |
| 1527 | (arg1 & env->CP0_Config4_rw_bitmask); |
| 1528 | } |
| 1529 | |
Petar Jovanovic | b4dd99a | 2014-01-17 19:25:57 +0100 | [diff] [blame] | 1530 | void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1) |
| 1531 | { |
| 1532 | env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) | |
| 1533 | (arg1 & env->CP0_Config5_rw_bitmask); |
Yongbok Kim | e97a391 | 2014-11-01 05:28:35 +0000 | [diff] [blame] | 1534 | compute_hflags(env); |
Petar Jovanovic | b4dd99a | 2014-01-17 19:25:57 +0100 | [diff] [blame] | 1535 | } |
| 1536 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1537 | void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1) |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 1538 | { |
| 1539 | target_long mask = env->CP0_LLAddr_rw_bitmask; |
| 1540 | arg1 = arg1 << env->CP0_LLAddr_shift; |
| 1541 | env->lladdr = (env->lladdr & ~mask) | (arg1 & mask); |
| 1542 | } |
| 1543 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1544 | void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1545 | { |
| 1546 | /* Watch exceptions for instructions, data loads, data stores |
| 1547 | not implemented. */ |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1548 | env->CP0_WatchLo[sel] = (arg1 & ~0x7); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1549 | } |
| 1550 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1551 | void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1552 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1553 | env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8); |
| 1554 | env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1555 | } |
| 1556 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1557 | void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1558 | { |
| 1559 | target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1560 | env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1561 | } |
| 1562 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1563 | void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1564 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1565 | env->CP0_Framemask = arg1; /* XXX */ |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1566 | } |
| 1567 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1568 | void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1569 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1570 | env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); |
| 1571 | if (arg1 & (1 << CP0DB_DM)) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1572 | env->hflags |= MIPS_HFLAG_DM; |
| 1573 | else |
| 1574 | env->hflags &= ~MIPS_HFLAG_DM; |
| 1575 | } |
| 1576 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1577 | void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1578 | { |
| 1579 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1580 | uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1581 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1582 | |
| 1583 | /* XXX: Might be wrong, check with EJTAG spec. */ |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1584 | if (other_tc == other->current_tc) |
| 1585 | other->active_tc.CP0_Debug_tcstatus = val; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1586 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1587 | other->tcs[other_tc].CP0_Debug_tcstatus = val; |
| 1588 | other->CP0_Debug = (other->CP0_Debug & |
| 1589 | ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1590 | (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1591 | } |
| 1592 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1593 | void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1594 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1595 | env->CP0_Performance0 = arg1 & 0x000007ff; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1596 | } |
| 1597 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1598 | void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1599 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1600 | env->CP0_TagLo = arg1 & 0xFFFFFCF6; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1601 | } |
| 1602 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1603 | void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1604 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1605 | env->CP0_DataLo = arg1; /* XXX */ |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1606 | } |
| 1607 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1608 | void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1609 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1610 | env->CP0_TagHi = arg1; /* XXX */ |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1611 | } |
| 1612 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1613 | void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1614 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1615 | env->CP0_DataHi = arg1; /* XXX */ |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1616 | } |
| 1617 | |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1618 | /* MIPS MT functions */ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1619 | target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1620 | { |
| 1621 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1622 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1623 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1624 | if (other_tc == other->current_tc) |
| 1625 | return other->active_tc.gpr[sel]; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1626 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1627 | return other->tcs[other_tc].gpr[sel]; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1628 | } |
| 1629 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1630 | target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1631 | { |
| 1632 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1633 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1634 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1635 | if (other_tc == other->current_tc) |
| 1636 | return other->active_tc.LO[sel]; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1637 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1638 | return other->tcs[other_tc].LO[sel]; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1639 | } |
| 1640 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1641 | target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1642 | { |
| 1643 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1644 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1645 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1646 | if (other_tc == other->current_tc) |
| 1647 | return other->active_tc.HI[sel]; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1648 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1649 | return other->tcs[other_tc].HI[sel]; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1650 | } |
| 1651 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1652 | target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1653 | { |
| 1654 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1655 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1656 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1657 | if (other_tc == other->current_tc) |
| 1658 | return other->active_tc.ACX[sel]; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1659 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1660 | return other->tcs[other_tc].ACX[sel]; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1661 | } |
| 1662 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1663 | target_ulong helper_mftdsp(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1664 | { |
| 1665 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1666 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1667 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1668 | if (other_tc == other->current_tc) |
| 1669 | return other->active_tc.DSPControl; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1670 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1671 | return other->tcs[other_tc].DSPControl; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1672 | } |
| 1673 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1674 | void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1675 | { |
| 1676 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1677 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1678 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1679 | if (other_tc == other->current_tc) |
| 1680 | other->active_tc.gpr[sel] = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1681 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1682 | other->tcs[other_tc].gpr[sel] = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1683 | } |
| 1684 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1685 | void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1686 | { |
| 1687 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1688 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1689 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1690 | if (other_tc == other->current_tc) |
| 1691 | other->active_tc.LO[sel] = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1692 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1693 | other->tcs[other_tc].LO[sel] = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1694 | } |
| 1695 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1696 | void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1697 | { |
| 1698 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1699 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1700 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1701 | if (other_tc == other->current_tc) |
| 1702 | other->active_tc.HI[sel] = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1703 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1704 | other->tcs[other_tc].HI[sel] = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1705 | } |
| 1706 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1707 | void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1708 | { |
| 1709 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1710 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1711 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1712 | if (other_tc == other->current_tc) |
| 1713 | other->active_tc.ACX[sel] = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1714 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1715 | other->tcs[other_tc].ACX[sel] = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1716 | } |
| 1717 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1718 | void helper_mttdsp(CPUMIPSState *env, target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1719 | { |
| 1720 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1721 | CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1722 | |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1723 | if (other_tc == other->current_tc) |
| 1724 | other->active_tc.DSPControl = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1725 | else |
Edgar E. Iglesias | b93bbdc | 2011-08-29 23:07:32 +0200 | [diff] [blame] | 1726 | other->tcs[other_tc].DSPControl = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1727 | } |
| 1728 | |
| 1729 | /* MIPS MT functions */ |
Nathan Froyd | 9ed5726 | 2010-10-29 07:48:46 -0700 | [diff] [blame] | 1730 | target_ulong helper_dmt(void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1731 | { |
| 1732 | // TODO |
Nathan Froyd | 9ed5726 | 2010-10-29 07:48:46 -0700 | [diff] [blame] | 1733 | return 0; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1734 | } |
| 1735 | |
Nathan Froyd | 9ed5726 | 2010-10-29 07:48:46 -0700 | [diff] [blame] | 1736 | target_ulong helper_emt(void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1737 | { |
| 1738 | // TODO |
Nathan Froyd | 9ed5726 | 2010-10-29 07:48:46 -0700 | [diff] [blame] | 1739 | return 0; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1740 | } |
| 1741 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1742 | target_ulong helper_dvpe(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1743 | { |
Andreas Färber | 182735e | 2013-05-29 22:29:20 +0200 | [diff] [blame] | 1744 | CPUState *other_cs = first_cpu; |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 1745 | target_ulong prev = env->mvp->CP0_MVPControl; |
| 1746 | |
Andreas Färber | bdc4464 | 2013-06-24 23:50:24 +0200 | [diff] [blame] | 1747 | CPU_FOREACH(other_cs) { |
Andreas Färber | 182735e | 2013-05-29 22:29:20 +0200 | [diff] [blame] | 1748 | MIPSCPU *other_cpu = MIPS_CPU(other_cs); |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 1749 | /* Turn off all VPEs except the one executing the dvpe. */ |
Andreas Färber | 182735e | 2013-05-29 22:29:20 +0200 | [diff] [blame] | 1750 | if (&other_cpu->env != env) { |
| 1751 | other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP); |
Andreas Färber | 6f4d6b0 | 2012-10-12 00:56:37 +0200 | [diff] [blame] | 1752 | mips_vpe_sleep(other_cpu); |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 1753 | } |
Andreas Färber | bdc4464 | 2013-06-24 23:50:24 +0200 | [diff] [blame] | 1754 | } |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 1755 | return prev; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1756 | } |
| 1757 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1758 | target_ulong helper_evpe(CPUMIPSState *env) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1759 | { |
Andreas Färber | 182735e | 2013-05-29 22:29:20 +0200 | [diff] [blame] | 1760 | CPUState *other_cs = first_cpu; |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 1761 | target_ulong prev = env->mvp->CP0_MVPControl; |
| 1762 | |
Andreas Färber | bdc4464 | 2013-06-24 23:50:24 +0200 | [diff] [blame] | 1763 | CPU_FOREACH(other_cs) { |
Andreas Färber | 182735e | 2013-05-29 22:29:20 +0200 | [diff] [blame] | 1764 | MIPSCPU *other_cpu = MIPS_CPU(other_cs); |
Andreas Färber | b35d77d | 2012-10-12 00:56:35 +0200 | [diff] [blame] | 1765 | |
Andreas Färber | 182735e | 2013-05-29 22:29:20 +0200 | [diff] [blame] | 1766 | if (&other_cpu->env != env |
Andreas Färber | 81bad50 | 2012-10-12 00:56:33 +0200 | [diff] [blame] | 1767 | /* If the VPE is WFI, don't disturb its sleep. */ |
Andreas Färber | b35d77d | 2012-10-12 00:56:35 +0200 | [diff] [blame] | 1768 | && !mips_vpe_is_wfi(other_cpu)) { |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 1769 | /* Enable the VPE. */ |
Andreas Färber | 182735e | 2013-05-29 22:29:20 +0200 | [diff] [blame] | 1770 | other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); |
Andreas Färber | c3affe5 | 2013-01-18 15:03:43 +0100 | [diff] [blame] | 1771 | mips_vpe_wake(other_cpu); /* And wake it up. */ |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 1772 | } |
Andreas Färber | bdc4464 | 2013-06-24 23:50:24 +0200 | [diff] [blame] | 1773 | } |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 1774 | return prev; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1775 | } |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 1776 | #endif /* !CONFIG_USER_ONLY */ |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1777 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1778 | void helper_fork(target_ulong arg1, target_ulong arg2) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1779 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1780 | // arg1 = rt, arg2 = rs |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1781 | // TODO: store to TC register |
| 1782 | } |
| 1783 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1784 | target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1785 | { |
Blue Swirl | 1c7242d | 2010-09-18 05:53:15 +0000 | [diff] [blame] | 1786 | target_long arg1 = arg; |
| 1787 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1788 | if (arg1 < 0) { |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1789 | /* No scheduling policy implemented. */ |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1790 | if (arg1 != -2) { |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1791 | if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1792 | env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1793 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
| 1794 | env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1795 | helper_raise_exception(env, EXCP_THREAD); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1796 | } |
| 1797 | } |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1798 | } else if (arg1 == 0) { |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 1799 | if (0 /* TODO: TC underflow */) { |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1800 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1801 | helper_raise_exception(env, EXCP_THREAD); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1802 | } else { |
| 1803 | // TODO: Deallocate TC |
| 1804 | } |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1805 | } else if (arg1 > 0) { |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1806 | /* Yield qualifier inputs not implemented. */ |
| 1807 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
| 1808 | env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1809 | helper_raise_exception(env, EXCP_THREAD); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1810 | } |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1811 | return env->CP0_YQMask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1812 | } |
| 1813 | |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1814 | #ifndef CONFIG_USER_ONLY |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1815 | /* TLB management */ |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 1816 | static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global) |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1817 | { |
Andreas Färber | 00c8cb0 | 2013-09-04 02:19:44 +0200 | [diff] [blame] | 1818 | MIPSCPU *cpu = mips_env_get_cpu(env); |
| 1819 | |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1820 | /* Flush qemu's TLB and discard all shadowed entries. */ |
Andreas Färber | 00c8cb0 | 2013-09-04 02:19:44 +0200 | [diff] [blame] | 1821 | tlb_flush(CPU(cpu), flush_global); |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1822 | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1823 | } |
| 1824 | |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 1825 | static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first) |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1826 | { |
| 1827 | /* Discard entries from env->tlb[first] onwards. */ |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1828 | while (env->tlb->tlb_in_use > first) { |
| 1829 | r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1830 | } |
| 1831 | } |
| 1832 | |
Leon Alrae | cd0d45c | 2014-09-11 16:28:16 +0100 | [diff] [blame] | 1833 | static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) |
| 1834 | { |
| 1835 | #if defined(TARGET_MIPS64) |
| 1836 | return extract64(entrylo, 6, 54); |
| 1837 | #else |
| 1838 | return extract64(entrylo, 6, 24) | /* PFN */ |
| 1839 | (extract64(entrylo, 32, 32) << 24); /* PFNX */ |
| 1840 | #endif |
| 1841 | } |
| 1842 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1843 | static void r4k_fill_tlb(CPUMIPSState *env, int idx) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1844 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1845 | r4k_tlb_t *tlb; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1846 | |
| 1847 | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1848 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
Leon Alrae | 9456c2f | 2014-07-07 11:24:00 +0100 | [diff] [blame] | 1849 | if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { |
| 1850 | tlb->EHINV = 1; |
| 1851 | return; |
| 1852 | } |
| 1853 | tlb->EHINV = 0; |
ths | f2e9ebe | 2007-05-13 14:07:26 +0000 | [diff] [blame] | 1854 | tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); |
ths | d26bc21 | 2007-11-08 18:05:37 +0000 | [diff] [blame] | 1855 | #if defined(TARGET_MIPS64) |
ths | e034e2c | 2007-06-23 18:04:12 +0000 | [diff] [blame] | 1856 | tlb->VPN &= env->SEGMask; |
ths | 100ce98 | 2007-05-13 19:22:13 +0000 | [diff] [blame] | 1857 | #endif |
pbrook | 98c1b82 | 2006-03-11 16:20:36 +0000 | [diff] [blame] | 1858 | tlb->ASID = env->CP0_EntryHi & 0xFF; |
ths | 3b1c8be | 2007-01-22 20:50:42 +0000 | [diff] [blame] | 1859 | tlb->PageMask = env->CP0_PageMask; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1860 | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; |
pbrook | 98c1b82 | 2006-03-11 16:20:36 +0000 | [diff] [blame] | 1861 | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
| 1862 | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
| 1863 | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
Leon Alrae | 2fb58b7 | 2014-07-07 11:23:58 +0100 | [diff] [blame] | 1864 | tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; |
| 1865 | tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; |
Leon Alrae | cd0d45c | 2014-09-11 16:28:16 +0100 | [diff] [blame] | 1866 | tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12; |
pbrook | 98c1b82 | 2006-03-11 16:20:36 +0000 | [diff] [blame] | 1867 | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
| 1868 | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
| 1869 | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
Leon Alrae | 2fb58b7 | 2014-07-07 11:23:58 +0100 | [diff] [blame] | 1870 | tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; |
| 1871 | tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; |
Leon Alrae | cd0d45c | 2014-09-11 16:28:16 +0100 | [diff] [blame] | 1872 | tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1873 | } |
| 1874 | |
Leon Alrae | 9456c2f | 2014-07-07 11:24:00 +0100 | [diff] [blame] | 1875 | void r4k_helper_tlbinv(CPUMIPSState *env) |
| 1876 | { |
| 1877 | int idx; |
| 1878 | r4k_tlb_t *tlb; |
| 1879 | uint8_t ASID = env->CP0_EntryHi & 0xFF; |
| 1880 | |
| 1881 | for (idx = 0; idx < env->tlb->nb_tlb; idx++) { |
| 1882 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
| 1883 | if (!tlb->G && tlb->ASID == ASID) { |
| 1884 | tlb->EHINV = 1; |
| 1885 | } |
| 1886 | } |
| 1887 | cpu_mips_tlb_flush(env, 1); |
| 1888 | } |
| 1889 | |
| 1890 | void r4k_helper_tlbinvf(CPUMIPSState *env) |
| 1891 | { |
| 1892 | int idx; |
| 1893 | |
| 1894 | for (idx = 0; idx < env->tlb->nb_tlb; idx++) { |
| 1895 | env->tlb->mmu.r4k.tlb[idx].EHINV = 1; |
| 1896 | } |
| 1897 | cpu_mips_tlb_flush(env, 1); |
| 1898 | } |
| 1899 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1900 | void r4k_helper_tlbwi(CPUMIPSState *env) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1901 | { |
Aurelien Jarno | 286d52e | 2012-10-09 21:53:21 +0200 | [diff] [blame] | 1902 | r4k_tlb_t *tlb; |
aurel32 | bbc0d79 | 2008-09-14 17:09:56 +0000 | [diff] [blame] | 1903 | int idx; |
Aurelien Jarno | 286d52e | 2012-10-09 21:53:21 +0200 | [diff] [blame] | 1904 | target_ulong VPN; |
| 1905 | uint8_t ASID; |
| 1906 | bool G, V0, D0, V1, D1; |
aurel32 | bbc0d79 | 2008-09-14 17:09:56 +0000 | [diff] [blame] | 1907 | |
| 1908 | idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; |
Aurelien Jarno | 286d52e | 2012-10-09 21:53:21 +0200 | [diff] [blame] | 1909 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
| 1910 | VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); |
| 1911 | #if defined(TARGET_MIPS64) |
| 1912 | VPN &= env->SEGMask; |
| 1913 | #endif |
| 1914 | ASID = env->CP0_EntryHi & 0xff; |
| 1915 | G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; |
| 1916 | V0 = (env->CP0_EntryLo0 & 2) != 0; |
| 1917 | D0 = (env->CP0_EntryLo0 & 4) != 0; |
| 1918 | V1 = (env->CP0_EntryLo1 & 2) != 0; |
| 1919 | D1 = (env->CP0_EntryLo1 & 4) != 0; |
aurel32 | bbc0d79 | 2008-09-14 17:09:56 +0000 | [diff] [blame] | 1920 | |
Aurelien Jarno | 286d52e | 2012-10-09 21:53:21 +0200 | [diff] [blame] | 1921 | /* Discard cached TLB entries, unless tlbwi is just upgrading access |
| 1922 | permissions on the current entry. */ |
| 1923 | if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G || |
| 1924 | (tlb->V0 && !V0) || (tlb->D0 && !D0) || |
| 1925 | (tlb->V1 && !V1) || (tlb->D1 && !D1)) { |
| 1926 | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
| 1927 | } |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1928 | |
aurel32 | bbc0d79 | 2008-09-14 17:09:56 +0000 | [diff] [blame] | 1929 | r4k_invalidate_tlb(env, idx, 0); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1930 | r4k_fill_tlb(env, idx); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1931 | } |
| 1932 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1933 | void r4k_helper_tlbwr(CPUMIPSState *env) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1934 | { |
| 1935 | int r = cpu_mips_get_random(env); |
| 1936 | |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 1937 | r4k_invalidate_tlb(env, r, 1); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1938 | r4k_fill_tlb(env, r); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1939 | } |
| 1940 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1941 | void r4k_helper_tlbp(CPUMIPSState *env) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1942 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1943 | r4k_tlb_t *tlb; |
ths | f2e9ebe | 2007-05-13 14:07:26 +0000 | [diff] [blame] | 1944 | target_ulong mask; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1945 | target_ulong tag; |
ths | f2e9ebe | 2007-05-13 14:07:26 +0000 | [diff] [blame] | 1946 | target_ulong VPN; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1947 | uint8_t ASID; |
| 1948 | int i; |
| 1949 | |
bellard | 3d9fb9fe | 2006-05-22 22:13:29 +0000 | [diff] [blame] | 1950 | ASID = env->CP0_EntryHi & 0xFF; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1951 | for (i = 0; i < env->tlb->nb_tlb; i++) { |
| 1952 | tlb = &env->tlb->mmu.r4k.tlb[i]; |
ths | f2e9ebe | 2007-05-13 14:07:26 +0000 | [diff] [blame] | 1953 | /* 1k pages are not supported. */ |
| 1954 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
| 1955 | tag = env->CP0_EntryHi & ~mask; |
| 1956 | VPN = tlb->VPN & ~mask; |
Aurelien Jarno | bc3e45e | 2012-10-09 21:53:21 +0200 | [diff] [blame] | 1957 | #if defined(TARGET_MIPS64) |
| 1958 | tag &= env->SEGMask; |
| 1959 | #endif |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1960 | /* Check ASID, virtual page number & size */ |
Leon Alrae | 9456c2f | 2014-07-07 11:24:00 +0100 | [diff] [blame] | 1961 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) { |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1962 | /* TLB match */ |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 1963 | env->CP0_Index = i; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1964 | break; |
| 1965 | } |
| 1966 | } |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1967 | if (i == env->tlb->nb_tlb) { |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1968 | /* No match. Discard any shadow entries, if any of them match. */ |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1969 | for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 1970 | tlb = &env->tlb->mmu.r4k.tlb[i]; |
| 1971 | /* 1k pages are not supported. */ |
| 1972 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
| 1973 | tag = env->CP0_EntryHi & ~mask; |
| 1974 | VPN = tlb->VPN & ~mask; |
Aurelien Jarno | bc3e45e | 2012-10-09 21:53:21 +0200 | [diff] [blame] | 1975 | #if defined(TARGET_MIPS64) |
| 1976 | tag &= env->SEGMask; |
| 1977 | #endif |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 1978 | /* Check ASID, virtual page number & size */ |
| 1979 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 1980 | r4k_mips_tlb_flush_extra (env, i); |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 1981 | break; |
| 1982 | } |
| 1983 | } |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1984 | |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 1985 | env->CP0_Index |= 0x80000000; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1986 | } |
| 1987 | } |
| 1988 | |
Leon Alrae | cd0d45c | 2014-09-11 16:28:16 +0100 | [diff] [blame] | 1989 | static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) |
| 1990 | { |
| 1991 | #if defined(TARGET_MIPS64) |
| 1992 | return tlb_pfn << 6; |
| 1993 | #else |
| 1994 | return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */ |
| 1995 | (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */ |
| 1996 | #endif |
| 1997 | } |
| 1998 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 1999 | void r4k_helper_tlbr(CPUMIPSState *env) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 2000 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 2001 | r4k_tlb_t *tlb; |
pbrook | 09c56b8 | 2006-03-11 16:39:23 +0000 | [diff] [blame] | 2002 | uint8_t ASID; |
aurel32 | bbc0d79 | 2008-09-14 17:09:56 +0000 | [diff] [blame] | 2003 | int idx; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 2004 | |
pbrook | 09c56b8 | 2006-03-11 16:39:23 +0000 | [diff] [blame] | 2005 | ASID = env->CP0_EntryHi & 0xFF; |
aurel32 | bbc0d79 | 2008-09-14 17:09:56 +0000 | [diff] [blame] | 2006 | idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; |
| 2007 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 2008 | |
| 2009 | /* If this will change the current ASID, flush qemu's TLB. */ |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 2010 | if (ASID != tlb->ASID) |
| 2011 | cpu_mips_tlb_flush (env, 1); |
| 2012 | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 2013 | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 2014 | |
Leon Alrae | 9456c2f | 2014-07-07 11:24:00 +0100 | [diff] [blame] | 2015 | if (tlb->EHINV) { |
| 2016 | env->CP0_EntryHi = 1 << CP0EnHi_EHINV; |
| 2017 | env->CP0_PageMask = 0; |
| 2018 | env->CP0_EntryLo0 = 0; |
| 2019 | env->CP0_EntryLo1 = 0; |
| 2020 | } else { |
| 2021 | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
| 2022 | env->CP0_PageMask = tlb->PageMask; |
| 2023 | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
Leon Alrae | 284b731 | 2015-06-09 17:14:13 +0100 | [diff] [blame] | 2024 | ((uint64_t)tlb->RI0 << CP0EnLo_RI) | |
Leon Alrae | cd0d45c | 2014-09-11 16:28:16 +0100 | [diff] [blame] | 2025 | ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) | |
| 2026 | get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12); |
Leon Alrae | 9456c2f | 2014-07-07 11:24:00 +0100 | [diff] [blame] | 2027 | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
Leon Alrae | 284b731 | 2015-06-09 17:14:13 +0100 | [diff] [blame] | 2028 | ((uint64_t)tlb->RI1 << CP0EnLo_RI) | |
Leon Alrae | cd0d45c | 2014-09-11 16:28:16 +0100 | [diff] [blame] | 2029 | ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) | |
| 2030 | get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12); |
Leon Alrae | 9456c2f | 2014-07-07 11:24:00 +0100 | [diff] [blame] | 2031 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 2032 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 2033 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2034 | void helper_tlbwi(CPUMIPSState *env) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2035 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2036 | env->tlb->helper_tlbwi(env); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2037 | } |
| 2038 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2039 | void helper_tlbwr(CPUMIPSState *env) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2040 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2041 | env->tlb->helper_tlbwr(env); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2042 | } |
| 2043 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2044 | void helper_tlbp(CPUMIPSState *env) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2045 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2046 | env->tlb->helper_tlbp(env); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2047 | } |
| 2048 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2049 | void helper_tlbr(CPUMIPSState *env) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2050 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2051 | env->tlb->helper_tlbr(env); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 2052 | } |
| 2053 | |
Leon Alrae | 9456c2f | 2014-07-07 11:24:00 +0100 | [diff] [blame] | 2054 | void helper_tlbinv(CPUMIPSState *env) |
| 2055 | { |
| 2056 | env->tlb->helper_tlbinv(env); |
| 2057 | } |
| 2058 | |
| 2059 | void helper_tlbinvf(CPUMIPSState *env) |
| 2060 | { |
| 2061 | env->tlb->helper_tlbinvf(env); |
| 2062 | } |
| 2063 | |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2064 | /* Specials */ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2065 | target_ulong helper_di(CPUMIPSState *env) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2066 | { |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 2067 | target_ulong t0 = env->CP0_Status; |
| 2068 | |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 2069 | env->CP0_Status = t0 & ~(1 << CP0St_IE); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 2070 | return t0; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2071 | } |
| 2072 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2073 | target_ulong helper_ei(CPUMIPSState *env) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2074 | { |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 2075 | target_ulong t0 = env->CP0_Status; |
| 2076 | |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 2077 | env->CP0_Status = t0 | (1 << CP0St_IE); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 2078 | return t0; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2079 | } |
| 2080 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2081 | static void debug_pre_eret(CPUMIPSState *env) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 2082 | { |
aliguori | 8fec2b8 | 2009-01-15 22:36:53 +0000 | [diff] [blame] | 2083 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 2084 | qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
| 2085 | env->active_tc.PC, env->CP0_EPC); |
| 2086 | if (env->CP0_Status & (1 << CP0St_ERL)) |
| 2087 | qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); |
| 2088 | if (env->hflags & MIPS_HFLAG_DM) |
| 2089 | qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); |
| 2090 | qemu_log("\n"); |
| 2091 | } |
ths | f41c52f | 2007-04-06 18:46:01 +0000 | [diff] [blame] | 2092 | } |
| 2093 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2094 | static void debug_post_eret(CPUMIPSState *env) |
ths | f41c52f | 2007-04-06 18:46:01 +0000 | [diff] [blame] | 2095 | { |
Andreas Färber | a47dddd | 2013-09-03 17:38:47 +0200 | [diff] [blame] | 2096 | MIPSCPU *cpu = mips_env_get_cpu(env); |
| 2097 | |
aliguori | 8fec2b8 | 2009-01-15 22:36:53 +0000 | [diff] [blame] | 2098 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 2099 | qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
| 2100 | env->active_tc.PC, env->CP0_EPC); |
| 2101 | if (env->CP0_Status & (1 << CP0St_ERL)) |
| 2102 | qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); |
| 2103 | if (env->hflags & MIPS_HFLAG_DM) |
| 2104 | qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); |
| 2105 | switch (env->hflags & MIPS_HFLAG_KSU) { |
| 2106 | case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; |
| 2107 | case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; |
| 2108 | case MIPS_HFLAG_KM: qemu_log("\n"); break; |
Andreas Färber | a47dddd | 2013-09-03 17:38:47 +0200 | [diff] [blame] | 2109 | default: |
| 2110 | cpu_abort(CPU(cpu), "Invalid MMU mode!\n"); |
| 2111 | break; |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 2112 | } |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 2113 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 2114 | } |
| 2115 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2116 | static void set_pc(CPUMIPSState *env, target_ulong error_pc) |
Nathan Froyd | 32188a0 | 2009-12-08 08:06:23 -0800 | [diff] [blame] | 2117 | { |
| 2118 | env->active_tc.PC = error_pc & ~(target_ulong)1; |
| 2119 | if (error_pc & 1) { |
| 2120 | env->hflags |= MIPS_HFLAG_M16; |
| 2121 | } else { |
| 2122 | env->hflags &= ~(MIPS_HFLAG_M16); |
| 2123 | } |
| 2124 | } |
| 2125 | |
Leon Alrae | ce9782f | 2015-06-04 17:00:31 +0100 | [diff] [blame] | 2126 | static inline void exception_return(CPUMIPSState *env) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2127 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2128 | debug_pre_eret(env); |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2129 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2130 | set_pc(env, env->CP0_ErrorEPC); |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2131 | env->CP0_Status &= ~(1 << CP0St_ERL); |
| 2132 | } else { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2133 | set_pc(env, env->CP0_EPC); |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2134 | env->CP0_Status &= ~(1 << CP0St_EXL); |
| 2135 | } |
| 2136 | compute_hflags(env); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2137 | debug_post_eret(env); |
Leon Alrae | ce9782f | 2015-06-04 17:00:31 +0100 | [diff] [blame] | 2138 | } |
| 2139 | |
| 2140 | void helper_eret(CPUMIPSState *env) |
| 2141 | { |
| 2142 | exception_return(env); |
Aurelien Jarno | 5499b6f | 2009-11-22 13:08:14 +0100 | [diff] [blame] | 2143 | env->lladdr = 1; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2144 | } |
| 2145 | |
Leon Alrae | ce9782f | 2015-06-04 17:00:31 +0100 | [diff] [blame] | 2146 | void helper_eretnc(CPUMIPSState *env) |
| 2147 | { |
| 2148 | exception_return(env); |
| 2149 | } |
| 2150 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2151 | void helper_deret(CPUMIPSState *env) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2152 | { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2153 | debug_pre_eret(env); |
| 2154 | set_pc(env, env->CP0_DEPC); |
Nathan Froyd | 32188a0 | 2009-12-08 08:06:23 -0800 | [diff] [blame] | 2155 | |
Leon Alrae | fe87c2b | 2015-07-14 11:08:13 +0100 | [diff] [blame] | 2156 | env->hflags &= ~MIPS_HFLAG_DM; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2157 | compute_hflags(env); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2158 | debug_post_eret(env); |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2159 | } |
ths | 0eaef5a | 2008-07-23 16:14:22 +0000 | [diff] [blame] | 2160 | #endif /* !CONFIG_USER_ONLY */ |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2161 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2162 | target_ulong helper_rdhwr_cpunum(CPUMIPSState *env) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2163 | { |
| 2164 | if ((env->hflags & MIPS_HFLAG_CP0) || |
| 2165 | (env->CP0_HWREna & (1 << 0))) |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 2166 | return env->CP0_EBase & 0x3ff; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2167 | else |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2168 | helper_raise_exception(env, EXCP_RI); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 2169 | |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 2170 | return 0; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2171 | } |
| 2172 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2173 | target_ulong helper_rdhwr_synci_step(CPUMIPSState *env) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2174 | { |
| 2175 | if ((env->hflags & MIPS_HFLAG_CP0) || |
| 2176 | (env->CP0_HWREna & (1 << 1))) |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 2177 | return env->SYNCI_Step; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2178 | else |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2179 | helper_raise_exception(env, EXCP_RI); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 2180 | |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 2181 | return 0; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2182 | } |
| 2183 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2184 | target_ulong helper_rdhwr_cc(CPUMIPSState *env) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2185 | { |
| 2186 | if ((env->hflags & MIPS_HFLAG_CP0) || |
| 2187 | (env->CP0_HWREna & (1 << 2))) |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 2188 | return env->CP0_Count; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2189 | else |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2190 | helper_raise_exception(env, EXCP_RI); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 2191 | |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 2192 | return 0; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2193 | } |
| 2194 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2195 | target_ulong helper_rdhwr_ccres(CPUMIPSState *env) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2196 | { |
| 2197 | if ((env->hflags & MIPS_HFLAG_CP0) || |
| 2198 | (env->CP0_HWREna & (1 << 3))) |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 2199 | return env->CCRes; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2200 | else |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2201 | helper_raise_exception(env, EXCP_RI); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 2202 | |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 2203 | return 0; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 2204 | } |
| 2205 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2206 | void helper_pmon(CPUMIPSState *env, int function) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 2207 | { |
| 2208 | function /= 2; |
| 2209 | switch (function) { |
| 2210 | case 2: /* TODO: char inbyte(int waitflag); */ |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 2211 | if (env->active_tc.gpr[4] == 0) |
| 2212 | env->active_tc.gpr[2] = -1; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 2213 | /* Fall through */ |
| 2214 | case 11: /* TODO: char inbyte (void); */ |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 2215 | env->active_tc.gpr[2] = -1; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 2216 | break; |
| 2217 | case 3: |
| 2218 | case 12: |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 2219 | printf("%c", (char)(env->active_tc.gpr[4] & 0xFF)); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 2220 | break; |
| 2221 | case 17: |
| 2222 | break; |
| 2223 | case 158: |
| 2224 | { |
Stefan Weil | b69e48a | 2012-04-12 15:43:09 +0200 | [diff] [blame] | 2225 | unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4]; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 2226 | printf("%s", fmt); |
| 2227 | } |
| 2228 | break; |
| 2229 | } |
| 2230 | } |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 2231 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2232 | void helper_wait(CPUMIPSState *env) |
ths | 08ba796 | 2008-06-12 03:15:13 +0000 | [diff] [blame] | 2233 | { |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 2234 | CPUState *cs = CPU(mips_env_get_cpu(env)); |
| 2235 | |
| 2236 | cs->halted = 1; |
Andreas Färber | d8ed887 | 2013-01-17 22:30:20 +0100 | [diff] [blame] | 2237 | cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2238 | helper_raise_exception(env, EXCP_HLT); |
ths | 08ba796 | 2008-06-12 03:15:13 +0000 | [diff] [blame] | 2239 | } |
| 2240 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 2241 | #if !defined(CONFIG_USER_ONLY) |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 2242 | |
Paolo Bonzini | 93e2232 | 2014-03-28 18:14:58 +0100 | [diff] [blame] | 2243 | void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
Leon Alrae | aea1409 | 2014-07-07 11:24:01 +0100 | [diff] [blame] | 2244 | int access_type, int is_user, |
| 2245 | uintptr_t retaddr) |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 2246 | { |
Paolo Bonzini | 93e2232 | 2014-03-28 18:14:58 +0100 | [diff] [blame] | 2247 | MIPSCPU *cpu = MIPS_CPU(cs); |
| 2248 | CPUMIPSState *env = &cpu->env; |
Leon Alrae | aea1409 | 2014-07-07 11:24:01 +0100 | [diff] [blame] | 2249 | int error_code = 0; |
| 2250 | int excp; |
Paolo Bonzini | 93e2232 | 2014-03-28 18:14:58 +0100 | [diff] [blame] | 2251 | |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 2252 | env->CP0_BadVAddr = addr; |
Leon Alrae | aea1409 | 2014-07-07 11:24:01 +0100 | [diff] [blame] | 2253 | |
| 2254 | if (access_type == MMU_DATA_STORE) { |
| 2255 | excp = EXCP_AdES; |
| 2256 | } else { |
| 2257 | excp = EXCP_AdEL; |
| 2258 | if (access_type == MMU_INST_FETCH) { |
| 2259 | error_code |= EXCP_INST_NOTAVAIL; |
| 2260 | } |
| 2261 | } |
| 2262 | |
| 2263 | do_raise_exception_err(env, excp, error_code, retaddr); |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 2264 | } |
| 2265 | |
Andreas Färber | d5a11fe | 2013-08-27 00:28:06 +0200 | [diff] [blame] | 2266 | void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx, |
Blue Swirl | 2050396 | 2012-04-09 14:20:20 +0000 | [diff] [blame] | 2267 | uintptr_t retaddr) |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 2268 | { |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 2269 | int ret; |
| 2270 | |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 2271 | ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx); |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 2272 | if (ret) { |
Andreas Färber | d5a11fe | 2013-08-27 00:28:06 +0200 | [diff] [blame] | 2273 | MIPSCPU *cpu = MIPS_CPU(cs); |
| 2274 | CPUMIPSState *env = &cpu->env; |
| 2275 | |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 2276 | do_raise_exception_err(env, cs->exception_index, |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2277 | env->error_code, retaddr); |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 2278 | } |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 2279 | } |
| 2280 | |
Andreas Färber | c658b94 | 2013-05-27 06:49:53 +0200 | [diff] [blame] | 2281 | void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr, |
| 2282 | bool is_write, bool is_exec, int unused, |
| 2283 | unsigned size) |
ths | 647de6c | 2007-10-20 19:45:44 +0000 | [diff] [blame] | 2284 | { |
Andreas Färber | c658b94 | 2013-05-27 06:49:53 +0200 | [diff] [blame] | 2285 | MIPSCPU *cpu = MIPS_CPU(cs); |
| 2286 | CPUMIPSState *env = &cpu->env; |
| 2287 | |
James Hogan | eddedd5 | 2014-07-28 12:37:50 +0100 | [diff] [blame] | 2288 | /* |
| 2289 | * Raising an exception with KVM enabled will crash because it won't be from |
| 2290 | * the main execution loop so the longjmp won't have a matching setjmp. |
| 2291 | * Until we can trigger a bus error exception through KVM lets just ignore |
| 2292 | * the access. |
| 2293 | */ |
| 2294 | if (kvm_enabled()) { |
| 2295 | return; |
| 2296 | } |
| 2297 | |
Andreas Färber | c658b94 | 2013-05-27 06:49:53 +0200 | [diff] [blame] | 2298 | if (is_exec) { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2299 | helper_raise_exception(env, EXCP_IBE); |
Andreas Färber | c658b94 | 2013-05-27 06:49:53 +0200 | [diff] [blame] | 2300 | } else { |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2301 | helper_raise_exception(env, EXCP_DBE); |
Andreas Färber | c658b94 | 2013-05-27 06:49:53 +0200 | [diff] [blame] | 2302 | } |
ths | 647de6c | 2007-10-20 19:45:44 +0000 | [diff] [blame] | 2303 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 2304 | #endif /* !CONFIG_USER_ONLY */ |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2305 | |
| 2306 | /* Complex FPU operations which may need stack space. */ |
| 2307 | |
pbrook | f090c9d | 2007-11-18 14:33:24 +0000 | [diff] [blame] | 2308 | #define FLOAT_TWO32 make_float32(1 << 30) |
| 2309 | #define FLOAT_TWO64 make_float64(1ULL << 62) |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2310 | #define FP_TO_INT32_OVERFLOW 0x7fffffff |
| 2311 | #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2312 | |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2313 | /* convert MIPS rounding mode in FCR31 to IEEE library */ |
Yongbok Kim | b7651e9 | 2014-11-01 05:28:37 +0000 | [diff] [blame] | 2314 | unsigned int ieee_rm[] = { |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2315 | float_round_nearest_even, |
| 2316 | float_round_to_zero, |
| 2317 | float_round_up, |
| 2318 | float_round_down |
| 2319 | }; |
| 2320 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2321 | target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2322 | { |
Petar Jovanovic | 736d120 | 2014-01-22 18:35:32 +0100 | [diff] [blame] | 2323 | target_ulong arg1 = 0; |
ths | 6c5c1e2 | 2008-06-24 15:12:27 +0000 | [diff] [blame] | 2324 | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 2325 | switch (reg) { |
| 2326 | case 0: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 2327 | arg1 = (int32_t)env->active_fpu.fcr0; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 2328 | break; |
Petar Jovanovic | 736d120 | 2014-01-22 18:35:32 +0100 | [diff] [blame] | 2329 | case 1: |
| 2330 | /* UFR Support - Read Status FR */ |
| 2331 | if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) { |
| 2332 | if (env->CP0_Config5 & (1 << CP0C5_UFR)) { |
| 2333 | arg1 = (int32_t) |
| 2334 | ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR); |
| 2335 | } else { |
| 2336 | helper_raise_exception(env, EXCP_RI); |
| 2337 | } |
| 2338 | } |
| 2339 | break; |
Leon Alrae | 7c979af | 2015-04-21 16:06:28 +0100 | [diff] [blame] | 2340 | case 5: |
| 2341 | /* FRE Support - read Config5.FRE bit */ |
| 2342 | if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { |
| 2343 | if (env->CP0_Config5 & (1 << CP0C5_UFE)) { |
| 2344 | arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1; |
| 2345 | } else { |
| 2346 | helper_raise_exception(env, EXCP_RI); |
| 2347 | } |
| 2348 | } |
| 2349 | break; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 2350 | case 25: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 2351 | arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1); |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 2352 | break; |
| 2353 | case 26: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 2354 | arg1 = env->active_fpu.fcr31 & 0x0003f07c; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 2355 | break; |
| 2356 | case 28: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 2357 | arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4); |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 2358 | break; |
| 2359 | default: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 2360 | arg1 = (int32_t)env->active_fpu.fcr31; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 2361 | break; |
| 2362 | } |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 2363 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 2364 | return arg1; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 2365 | } |
| 2366 | |
Petar Jovanovic | 736d120 | 2014-01-22 18:35:32 +0100 | [diff] [blame] | 2367 | void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt) |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 2368 | { |
Petar Jovanovic | 736d120 | 2014-01-22 18:35:32 +0100 | [diff] [blame] | 2369 | switch (fs) { |
| 2370 | case 1: |
| 2371 | /* UFR Alias - Reset Status FR */ |
| 2372 | if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) { |
| 2373 | return; |
| 2374 | } |
| 2375 | if (env->CP0_Config5 & (1 << CP0C5_UFR)) { |
| 2376 | env->CP0_Status &= ~(1 << CP0St_FR); |
| 2377 | compute_hflags(env); |
| 2378 | } else { |
| 2379 | helper_raise_exception(env, EXCP_RI); |
| 2380 | } |
| 2381 | break; |
| 2382 | case 4: |
| 2383 | /* UNFR Alias - Set Status FR */ |
| 2384 | if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) { |
| 2385 | return; |
| 2386 | } |
| 2387 | if (env->CP0_Config5 & (1 << CP0C5_UFR)) { |
| 2388 | env->CP0_Status |= (1 << CP0St_FR); |
| 2389 | compute_hflags(env); |
| 2390 | } else { |
| 2391 | helper_raise_exception(env, EXCP_RI); |
| 2392 | } |
| 2393 | break; |
Leon Alrae | 7c979af | 2015-04-21 16:06:28 +0100 | [diff] [blame] | 2394 | case 5: |
| 2395 | /* FRE Support - clear Config5.FRE bit */ |
| 2396 | if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) { |
| 2397 | return; |
| 2398 | } |
| 2399 | if (env->CP0_Config5 & (1 << CP0C5_UFE)) { |
| 2400 | env->CP0_Config5 &= ~(1 << CP0C5_FRE); |
| 2401 | compute_hflags(env); |
| 2402 | } else { |
| 2403 | helper_raise_exception(env, EXCP_RI); |
| 2404 | } |
| 2405 | break; |
| 2406 | case 6: |
| 2407 | /* FRE Support - set Config5.FRE bit */ |
| 2408 | if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) { |
| 2409 | return; |
| 2410 | } |
| 2411 | if (env->CP0_Config5 & (1 << CP0C5_UFE)) { |
| 2412 | env->CP0_Config5 |= (1 << CP0C5_FRE); |
| 2413 | compute_hflags(env); |
| 2414 | } else { |
| 2415 | helper_raise_exception(env, EXCP_RI); |
| 2416 | } |
| 2417 | break; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2418 | case 25: |
Leon Alrae | ba801af | 2014-07-11 16:11:34 +0100 | [diff] [blame] | 2419 | if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) { |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2420 | return; |
Leon Alrae | ba801af | 2014-07-11 16:11:34 +0100 | [diff] [blame] | 2421 | } |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 2422 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) | |
| 2423 | ((arg1 & 0x1) << 23); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2424 | break; |
| 2425 | case 26: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 2426 | if (arg1 & 0x007c0000) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2427 | return; |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 2428 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2429 | break; |
| 2430 | case 28: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 2431 | if (arg1 & 0x007c0000) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2432 | return; |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 2433 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) | |
| 2434 | ((arg1 & 0x4) << 22); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2435 | break; |
| 2436 | case 31: |
Leon Alrae | ba801af | 2014-07-11 16:11:34 +0100 | [diff] [blame] | 2437 | if (env->insn_flags & ISA_MIPS32R6) { |
| 2438 | uint32_t mask = 0xfefc0000; |
| 2439 | env->active_fpu.fcr31 = (arg1 & ~mask) | |
| 2440 | (env->active_fpu.fcr31 & mask); |
| 2441 | } else if (!(arg1 & 0x007c0000)) { |
| 2442 | env->active_fpu.fcr31 = arg1; |
| 2443 | } |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2444 | break; |
| 2445 | default: |
| 2446 | return; |
| 2447 | } |
| 2448 | /* set rounding mode */ |
Stefan Weil | e320d05 | 2013-01-01 19:44:31 +0100 | [diff] [blame] | 2449 | restore_rounding_mode(env); |
aurel32 | 41e0c70 | 2009-03-28 22:22:40 +0000 | [diff] [blame] | 2450 | /* set flush-to-zero mode */ |
Stefan Weil | e320d05 | 2013-01-01 19:44:31 +0100 | [diff] [blame] | 2451 | restore_flush_mode(env); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2452 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2453 | if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2454 | do_raise_exception(env, EXCP_FPE, GETPC()); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2455 | } |
| 2456 | |
Yongbok Kim | b7651e9 | 2014-11-01 05:28:37 +0000 | [diff] [blame] | 2457 | int ieee_ex_to_mips(int xcpt) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2458 | { |
Aurelien Jarno | 353ebb7 | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 2459 | int ret = 0; |
| 2460 | if (xcpt) { |
| 2461 | if (xcpt & float_flag_invalid) { |
| 2462 | ret |= FP_INVALID; |
| 2463 | } |
| 2464 | if (xcpt & float_flag_overflow) { |
| 2465 | ret |= FP_OVERFLOW; |
| 2466 | } |
| 2467 | if (xcpt & float_flag_underflow) { |
| 2468 | ret |= FP_UNDERFLOW; |
| 2469 | } |
| 2470 | if (xcpt & float_flag_divbyzero) { |
| 2471 | ret |= FP_DIV0; |
| 2472 | } |
| 2473 | if (xcpt & float_flag_inexact) { |
| 2474 | ret |= FP_INEXACT; |
| 2475 | } |
| 2476 | } |
| 2477 | return ret; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2478 | } |
| 2479 | |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2480 | static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2481 | { |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2482 | int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status)); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2483 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2484 | SET_FP_CAUSE(env->active_fpu.fcr31, tmp); |
Aurelien Jarno | 4a587b2 | 2012-10-28 18:08:27 +0100 | [diff] [blame] | 2485 | |
| 2486 | if (tmp) { |
| 2487 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2488 | |
| 2489 | if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) { |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2490 | do_raise_exception(env, EXCP_FPE, pc); |
Aurelien Jarno | 4a587b2 | 2012-10-28 18:08:27 +0100 | [diff] [blame] | 2491 | } else { |
| 2492 | UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); |
| 2493 | } |
| 2494 | } |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2495 | } |
| 2496 | |
ths | a16336e | 2008-06-19 18:35:02 +0000 | [diff] [blame] | 2497 | /* Float support. |
| 2498 | Single precition routines have a "s" suffix, double precision a |
| 2499 | "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", |
| 2500 | paired single lower "pl", paired single upper "pu". */ |
| 2501 | |
ths | a16336e | 2008-06-19 18:35:02 +0000 | [diff] [blame] | 2502 | /* unary operations, modifying fp status */ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2503 | uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2504 | { |
Aurelien Jarno | 5dbe90b | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 2505 | fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2506 | update_fcr31(env, GETPC()); |
Aurelien Jarno | 5dbe90b | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 2507 | return fdt0; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2508 | } |
| 2509 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2510 | uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2511 | { |
Aurelien Jarno | 5dbe90b | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 2512 | fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2513 | update_fcr31(env, GETPC()); |
Aurelien Jarno | 5dbe90b | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 2514 | return fst0; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2515 | } |
| 2516 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2517 | uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2518 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2519 | uint64_t fdt2; |
| 2520 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2521 | fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2522 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2523 | return fdt2; |
| 2524 | } |
| 2525 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2526 | uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2527 | { |
| 2528 | uint64_t fdt2; |
| 2529 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2530 | fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2531 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2532 | return fdt2; |
| 2533 | } |
| 2534 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2535 | uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2536 | { |
| 2537 | uint64_t fdt2; |
| 2538 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2539 | fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2540 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2541 | return fdt2; |
| 2542 | } |
| 2543 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2544 | uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2545 | { |
| 2546 | uint64_t dt2; |
| 2547 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2548 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2549 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2550 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2551 | dt2 = FP_TO_INT64_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2552 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2553 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2554 | return dt2; |
| 2555 | } |
| 2556 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2557 | uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2558 | { |
| 2559 | uint64_t dt2; |
| 2560 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2561 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2562 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2563 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2564 | dt2 = FP_TO_INT64_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2565 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2566 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2567 | return dt2; |
| 2568 | } |
| 2569 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2570 | uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2571 | { |
| 2572 | uint32_t fst2; |
| 2573 | uint32_t fsth2; |
| 2574 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2575 | fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
| 2576 | fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2577 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2578 | return ((uint64_t)fsth2 << 32) | fst2; |
| 2579 | } |
| 2580 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2581 | uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2582 | { |
| 2583 | uint32_t wt2; |
| 2584 | uint32_t wth2; |
Aurelien Jarno | 5dbe90b | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 2585 | int excp, excph; |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2586 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2587 | wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
Aurelien Jarno | 5dbe90b | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 2588 | excp = get_float_exception_flags(&env->active_fpu.fp_status); |
| 2589 | if (excp & (float_flag_overflow | float_flag_invalid)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2590 | wt2 = FP_TO_INT32_OVERFLOW; |
Aurelien Jarno | 5dbe90b | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 2591 | } |
| 2592 | |
| 2593 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2594 | wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); |
| 2595 | excph = get_float_exception_flags(&env->active_fpu.fp_status); |
| 2596 | if (excph & (float_flag_overflow | float_flag_invalid)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2597 | wth2 = FP_TO_INT32_OVERFLOW; |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2598 | } |
Aurelien Jarno | 5dbe90b | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 2599 | |
| 2600 | set_float_exception_flags(excp | excph, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2601 | update_fcr31(env, GETPC()); |
Aurelien Jarno | 5dbe90b | 2012-10-09 21:53:20 +0200 | [diff] [blame] | 2602 | |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2603 | return ((uint64_t)wth2 << 32) | wt2; |
| 2604 | } |
| 2605 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2606 | uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2607 | { |
| 2608 | uint32_t fst2; |
| 2609 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2610 | fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2611 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2612 | return fst2; |
| 2613 | } |
| 2614 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2615 | uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2616 | { |
| 2617 | uint32_t fst2; |
| 2618 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2619 | fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2620 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2621 | return fst2; |
| 2622 | } |
| 2623 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2624 | uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2625 | { |
| 2626 | uint32_t fst2; |
| 2627 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2628 | fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2629 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2630 | return fst2; |
| 2631 | } |
| 2632 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2633 | uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2634 | { |
| 2635 | uint32_t wt2; |
| 2636 | |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2637 | wt2 = wt0; |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2638 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2639 | return wt2; |
| 2640 | } |
| 2641 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2642 | uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2643 | { |
| 2644 | uint32_t wt2; |
| 2645 | |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2646 | wt2 = wth0; |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2647 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2648 | return wt2; |
| 2649 | } |
| 2650 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2651 | uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2652 | { |
| 2653 | uint32_t wt2; |
| 2654 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2655 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2656 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2657 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2658 | wt2 = FP_TO_INT32_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2659 | } |
Maciej W. Rozycki | 2b09f94 | 2014-11-05 15:35:59 +0000 | [diff] [blame] | 2660 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2661 | return wt2; |
| 2662 | } |
| 2663 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2664 | uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2665 | { |
| 2666 | uint32_t wt2; |
| 2667 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2668 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2669 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2670 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2671 | wt2 = FP_TO_INT32_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2672 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2673 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2674 | return wt2; |
| 2675 | } |
| 2676 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2677 | uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2678 | { |
| 2679 | uint64_t dt2; |
| 2680 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2681 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
| 2682 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
Stefan Weil | e320d05 | 2013-01-01 19:44:31 +0100 | [diff] [blame] | 2683 | restore_rounding_mode(env); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2684 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2685 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2686 | dt2 = FP_TO_INT64_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2687 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2688 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2689 | return dt2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2690 | } |
| 2691 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2692 | uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2693 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2694 | uint64_t dt2; |
| 2695 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2696 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
| 2697 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
Stefan Weil | e320d05 | 2013-01-01 19:44:31 +0100 | [diff] [blame] | 2698 | restore_rounding_mode(env); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2699 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2700 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2701 | dt2 = FP_TO_INT64_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2702 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2703 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2704 | return dt2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2705 | } |
| 2706 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2707 | uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2708 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2709 | uint32_t wt2; |
| 2710 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2711 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
| 2712 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
Stefan Weil | e320d05 | 2013-01-01 19:44:31 +0100 | [diff] [blame] | 2713 | restore_rounding_mode(env); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2714 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2715 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2716 | wt2 = FP_TO_INT32_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2717 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2718 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2719 | return wt2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2720 | } |
| 2721 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2722 | uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2723 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2724 | uint32_t wt2; |
| 2725 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2726 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
| 2727 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
Stefan Weil | e320d05 | 2013-01-01 19:44:31 +0100 | [diff] [blame] | 2728 | restore_rounding_mode(env); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2729 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2730 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2731 | wt2 = FP_TO_INT32_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2732 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2733 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2734 | return wt2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2735 | } |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2736 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2737 | uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2738 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2739 | uint64_t dt2; |
| 2740 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2741 | dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2742 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2743 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2744 | dt2 = FP_TO_INT64_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2745 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2746 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2747 | return dt2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2748 | } |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2749 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2750 | uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2751 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2752 | uint64_t dt2; |
| 2753 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2754 | dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2755 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2756 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2757 | dt2 = FP_TO_INT64_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2758 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2759 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2760 | return dt2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2761 | } |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2762 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2763 | uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2764 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2765 | uint32_t wt2; |
| 2766 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2767 | wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2768 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2769 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2770 | wt2 = FP_TO_INT32_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2771 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2772 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2773 | return wt2; |
| 2774 | } |
| 2775 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2776 | uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2777 | { |
| 2778 | uint32_t wt2; |
| 2779 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2780 | wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2781 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2782 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2783 | wt2 = FP_TO_INT32_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2784 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2785 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2786 | return wt2; |
| 2787 | } |
| 2788 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2789 | uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2790 | { |
| 2791 | uint64_t dt2; |
| 2792 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2793 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
| 2794 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
Stefan Weil | e320d05 | 2013-01-01 19:44:31 +0100 | [diff] [blame] | 2795 | restore_rounding_mode(env); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2796 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2797 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2798 | dt2 = FP_TO_INT64_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2799 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2800 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2801 | return dt2; |
| 2802 | } |
| 2803 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2804 | uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2805 | { |
| 2806 | uint64_t dt2; |
| 2807 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2808 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
| 2809 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
Stefan Weil | e320d05 | 2013-01-01 19:44:31 +0100 | [diff] [blame] | 2810 | restore_rounding_mode(env); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2811 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2812 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2813 | dt2 = FP_TO_INT64_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2814 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2815 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2816 | return dt2; |
| 2817 | } |
| 2818 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2819 | uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2820 | { |
| 2821 | uint32_t wt2; |
| 2822 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2823 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
| 2824 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
Stefan Weil | e320d05 | 2013-01-01 19:44:31 +0100 | [diff] [blame] | 2825 | restore_rounding_mode(env); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2826 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2827 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2828 | wt2 = FP_TO_INT32_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2829 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2830 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2831 | return wt2; |
| 2832 | } |
| 2833 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2834 | uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2835 | { |
| 2836 | uint32_t wt2; |
| 2837 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2838 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
| 2839 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
Stefan Weil | e320d05 | 2013-01-01 19:44:31 +0100 | [diff] [blame] | 2840 | restore_rounding_mode(env); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2841 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2842 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2843 | wt2 = FP_TO_INT32_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2844 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2845 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2846 | return wt2; |
| 2847 | } |
| 2848 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2849 | uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2850 | { |
| 2851 | uint64_t dt2; |
| 2852 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2853 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
| 2854 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
Stefan Weil | e320d05 | 2013-01-01 19:44:31 +0100 | [diff] [blame] | 2855 | restore_rounding_mode(env); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2856 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2857 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2858 | dt2 = FP_TO_INT64_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2859 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2860 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2861 | return dt2; |
| 2862 | } |
| 2863 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2864 | uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2865 | { |
| 2866 | uint64_t dt2; |
| 2867 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2868 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
| 2869 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
Stefan Weil | e320d05 | 2013-01-01 19:44:31 +0100 | [diff] [blame] | 2870 | restore_rounding_mode(env); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2871 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2872 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2873 | dt2 = FP_TO_INT64_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2874 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2875 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2876 | return dt2; |
| 2877 | } |
| 2878 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2879 | uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2880 | { |
| 2881 | uint32_t wt2; |
| 2882 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2883 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
| 2884 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
Stefan Weil | e320d05 | 2013-01-01 19:44:31 +0100 | [diff] [blame] | 2885 | restore_rounding_mode(env); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2886 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2887 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2888 | wt2 = FP_TO_INT32_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2889 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2890 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2891 | return wt2; |
| 2892 | } |
| 2893 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2894 | uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2895 | { |
| 2896 | uint32_t wt2; |
| 2897 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2898 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
| 2899 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
Stefan Weil | e320d05 | 2013-01-01 19:44:31 +0100 | [diff] [blame] | 2900 | restore_rounding_mode(env); |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2901 | if (get_float_exception_flags(&env->active_fpu.fp_status) |
| 2902 | & (float_flag_invalid | float_flag_overflow)) { |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2903 | wt2 = FP_TO_INT32_OVERFLOW; |
Aurelien Jarno | 4cc2e5f | 2012-10-23 09:53:50 +0200 | [diff] [blame] | 2904 | } |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2905 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2906 | return wt2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2907 | } |
| 2908 | |
ths | a16336e | 2008-06-19 18:35:02 +0000 | [diff] [blame] | 2909 | /* unary operations, not modifying fp status */ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2910 | #define FLOAT_UNOP(name) \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2911 | uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2912 | { \ |
| 2913 | return float64_ ## name(fdt0); \ |
| 2914 | } \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2915 | uint32_t helper_float_ ## name ## _s(uint32_t fst0) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2916 | { \ |
| 2917 | return float32_ ## name(fst0); \ |
| 2918 | } \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2919 | uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2920 | { \ |
| 2921 | uint32_t wt0; \ |
| 2922 | uint32_t wth0; \ |
| 2923 | \ |
| 2924 | wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \ |
| 2925 | wth0 = float32_ ## name(fdt0 >> 32); \ |
| 2926 | return ((uint64_t)wth0 << 32) | wt0; \ |
ths | a16336e | 2008-06-19 18:35:02 +0000 | [diff] [blame] | 2927 | } |
| 2928 | FLOAT_UNOP(abs) |
| 2929 | FLOAT_UNOP(chs) |
| 2930 | #undef FLOAT_UNOP |
| 2931 | |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2932 | /* MIPS specific unary operations */ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2933 | uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2934 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2935 | uint64_t fdt2; |
| 2936 | |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2937 | fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2938 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2939 | return fdt2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2940 | } |
ths | 57fa1fb | 2007-05-19 20:29:41 +0000 | [diff] [blame] | 2941 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2942 | uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2943 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2944 | uint32_t fst2; |
| 2945 | |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2946 | fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2947 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2948 | return fst2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2949 | } |
| 2950 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2951 | uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2952 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2953 | uint64_t fdt2; |
| 2954 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2955 | fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2956 | fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2957 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2958 | return fdt2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2959 | } |
| 2960 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2961 | uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2962 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2963 | uint32_t fst2; |
| 2964 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2965 | fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2966 | fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2967 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2968 | return fst2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2969 | } |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2970 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2971 | uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2972 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2973 | uint64_t fdt2; |
| 2974 | |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2975 | fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2976 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2977 | return fdt2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2978 | } |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2979 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2980 | uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2981 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2982 | uint32_t fst2; |
| 2983 | |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2984 | fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2985 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2986 | return fst2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2987 | } |
ths | 57fa1fb | 2007-05-19 20:29:41 +0000 | [diff] [blame] | 2988 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 2989 | uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2990 | { |
| 2991 | uint32_t fst2; |
| 2992 | uint32_t fsth2; |
| 2993 | |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 2994 | fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
| 2995 | fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 2996 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2997 | return ((uint64_t)fsth2 << 32) | fst2; |
| 2998 | } |
| 2999 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3000 | uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3001 | { |
| 3002 | uint64_t fdt2; |
| 3003 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3004 | fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 3005 | fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3006 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3007 | return fdt2; |
| 3008 | } |
| 3009 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3010 | uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3011 | { |
| 3012 | uint32_t fst2; |
| 3013 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3014 | fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 3015 | fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3016 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3017 | return fst2; |
| 3018 | } |
| 3019 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3020 | uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3021 | { |
| 3022 | uint32_t fst2; |
| 3023 | uint32_t fsth2; |
| 3024 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3025 | fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
| 3026 | fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 3027 | fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); |
| 3028 | fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3029 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3030 | return ((uint64_t)fsth2 << 32) | fst2; |
| 3031 | } |
| 3032 | |
Maciej W. Rozycki | 8fc605b | 2014-11-05 15:38:01 +0000 | [diff] [blame] | 3033 | #define FLOAT_RINT(name, bits) \ |
| 3034 | uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \ |
| 3035 | uint ## bits ## _t fs) \ |
| 3036 | { \ |
| 3037 | uint ## bits ## _t fdret; \ |
| 3038 | \ |
| 3039 | fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \ |
| 3040 | update_fcr31(env, GETPC()); \ |
| 3041 | return fdret; \ |
| 3042 | } |
| 3043 | |
| 3044 | FLOAT_RINT(rint_s, 32) |
| 3045 | FLOAT_RINT(rint_d, 64) |
| 3046 | #undef FLOAT_RINT |
| 3047 | |
| 3048 | #define FLOAT_CLASS_SIGNALING_NAN 0x001 |
| 3049 | #define FLOAT_CLASS_QUIET_NAN 0x002 |
| 3050 | #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004 |
| 3051 | #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008 |
| 3052 | #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010 |
| 3053 | #define FLOAT_CLASS_NEGATIVE_ZERO 0x020 |
| 3054 | #define FLOAT_CLASS_POSITIVE_INFINITY 0x040 |
| 3055 | #define FLOAT_CLASS_POSITIVE_NORMAL 0x080 |
| 3056 | #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100 |
| 3057 | #define FLOAT_CLASS_POSITIVE_ZERO 0x200 |
| 3058 | |
| 3059 | #define FLOAT_CLASS(name, bits) \ |
| 3060 | uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \ |
| 3061 | { \ |
| 3062 | if (float ## bits ## _is_signaling_nan(arg)) { \ |
| 3063 | return FLOAT_CLASS_SIGNALING_NAN; \ |
| 3064 | } else if (float ## bits ## _is_quiet_nan(arg)) { \ |
| 3065 | return FLOAT_CLASS_QUIET_NAN; \ |
| 3066 | } else if (float ## bits ## _is_neg(arg)) { \ |
| 3067 | if (float ## bits ## _is_infinity(arg)) { \ |
| 3068 | return FLOAT_CLASS_NEGATIVE_INFINITY; \ |
| 3069 | } else if (float ## bits ## _is_zero(arg)) { \ |
| 3070 | return FLOAT_CLASS_NEGATIVE_ZERO; \ |
| 3071 | } else if (float ## bits ## _is_zero_or_denormal(arg)) { \ |
| 3072 | return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \ |
| 3073 | } else { \ |
| 3074 | return FLOAT_CLASS_NEGATIVE_NORMAL; \ |
| 3075 | } \ |
| 3076 | } else { \ |
| 3077 | if (float ## bits ## _is_infinity(arg)) { \ |
| 3078 | return FLOAT_CLASS_POSITIVE_INFINITY; \ |
| 3079 | } else if (float ## bits ## _is_zero(arg)) { \ |
| 3080 | return FLOAT_CLASS_POSITIVE_ZERO; \ |
| 3081 | } else if (float ## bits ## _is_zero_or_denormal(arg)) { \ |
| 3082 | return FLOAT_CLASS_POSITIVE_SUBNORMAL; \ |
| 3083 | } else { \ |
| 3084 | return FLOAT_CLASS_POSITIVE_NORMAL; \ |
| 3085 | } \ |
| 3086 | } \ |
| 3087 | } |
| 3088 | |
| 3089 | FLOAT_CLASS(class_s, 32) |
| 3090 | FLOAT_CLASS(class_d, 64) |
| 3091 | #undef FLOAT_CLASS |
| 3092 | |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3093 | /* binary operations */ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3094 | #define FLOAT_BINOP(name) \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3095 | uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ |
| 3096 | uint64_t fdt0, uint64_t fdt1) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3097 | { \ |
| 3098 | uint64_t dt2; \ |
| 3099 | \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3100 | dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3101 | update_fcr31(env, GETPC()); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3102 | return dt2; \ |
| 3103 | } \ |
| 3104 | \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3105 | uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ |
| 3106 | uint32_t fst0, uint32_t fst1) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3107 | { \ |
| 3108 | uint32_t wt2; \ |
| 3109 | \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3110 | wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3111 | update_fcr31(env, GETPC()); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3112 | return wt2; \ |
| 3113 | } \ |
| 3114 | \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3115 | uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ |
| 3116 | uint64_t fdt0, \ |
| 3117 | uint64_t fdt1) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3118 | { \ |
| 3119 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ |
| 3120 | uint32_t fsth0 = fdt0 >> 32; \ |
| 3121 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ |
| 3122 | uint32_t fsth1 = fdt1 >> 32; \ |
| 3123 | uint32_t wt2; \ |
| 3124 | uint32_t wth2; \ |
| 3125 | \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3126 | wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ |
| 3127 | wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3128 | update_fcr31(env, GETPC()); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3129 | return ((uint64_t)wth2 << 32) | wt2; \ |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3130 | } |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3131 | |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3132 | FLOAT_BINOP(add) |
| 3133 | FLOAT_BINOP(sub) |
| 3134 | FLOAT_BINOP(mul) |
| 3135 | FLOAT_BINOP(div) |
| 3136 | #undef FLOAT_BINOP |
| 3137 | |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 3138 | /* MIPS specific binary operations */ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3139 | uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 3140 | { |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3141 | fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 3142 | fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status)); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3143 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3144 | return fdt2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 3145 | } |
| 3146 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3147 | uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 3148 | { |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3149 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 3150 | fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status)); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3151 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3152 | return fst2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 3153 | } |
ths | 57fa1fb | 2007-05-19 20:29:41 +0000 | [diff] [blame] | 3154 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3155 | uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3156 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3157 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
| 3158 | uint32_t fsth0 = fdt0 >> 32; |
| 3159 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; |
| 3160 | uint32_t fsth2 = fdt2 >> 32; |
| 3161 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3162 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
| 3163 | fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 3164 | fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status)); |
| 3165 | fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status)); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3166 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3167 | return ((uint64_t)fsth2 << 32) | fst2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3168 | } |
| 3169 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3170 | uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
ths | 57fa1fb | 2007-05-19 20:29:41 +0000 | [diff] [blame] | 3171 | { |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3172 | fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 3173 | fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3174 | fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3175 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3176 | return fdt2; |
| 3177 | } |
| 3178 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3179 | uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3180 | { |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3181 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 3182 | fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3183 | fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3184 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3185 | return fst2; |
| 3186 | } |
| 3187 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3188 | uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3189 | { |
| 3190 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
| 3191 | uint32_t fsth0 = fdt0 >> 32; |
| 3192 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; |
| 3193 | uint32_t fsth2 = fdt2 >> 32; |
| 3194 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3195 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
| 3196 | fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); |
Aurelien Jarno | 05993cd | 2012-10-23 10:12:00 +0200 | [diff] [blame] | 3197 | fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); |
| 3198 | fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3199 | fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
| 3200 | fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3201 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3202 | return ((uint64_t)fsth2 << 32) | fst2; |
| 3203 | } |
| 3204 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3205 | uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3206 | { |
| 3207 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
| 3208 | uint32_t fsth0 = fdt0 >> 32; |
| 3209 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; |
| 3210 | uint32_t fsth1 = fdt1 >> 32; |
| 3211 | uint32_t fst2; |
| 3212 | uint32_t fsth2; |
| 3213 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3214 | fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); |
| 3215 | fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3216 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3217 | return ((uint64_t)fsth2 << 32) | fst2; |
| 3218 | } |
| 3219 | |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3220 | uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3221 | { |
| 3222 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
| 3223 | uint32_t fsth0 = fdt0 >> 32; |
| 3224 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; |
| 3225 | uint32_t fsth1 = fdt1 >> 32; |
| 3226 | uint32_t fst2; |
| 3227 | uint32_t fsth2; |
| 3228 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3229 | fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); |
| 3230 | fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3231 | update_fcr31(env, GETPC()); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3232 | return ((uint64_t)fsth2 << 32) | fst2; |
ths | 57fa1fb | 2007-05-19 20:29:41 +0000 | [diff] [blame] | 3233 | } |
| 3234 | |
Maciej W. Rozycki | 8fc605b | 2014-11-05 15:38:01 +0000 | [diff] [blame] | 3235 | #define FLOAT_MINMAX(name, bits, minmaxfunc) \ |
| 3236 | uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \ |
| 3237 | uint ## bits ## _t fs, \ |
| 3238 | uint ## bits ## _t ft) \ |
| 3239 | { \ |
| 3240 | uint ## bits ## _t fdret; \ |
| 3241 | \ |
| 3242 | fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \ |
| 3243 | &env->active_fpu.fp_status); \ |
| 3244 | update_fcr31(env, GETPC()); \ |
| 3245 | return fdret; \ |
| 3246 | } |
| 3247 | |
| 3248 | FLOAT_MINMAX(max_s, 32, maxnum) |
| 3249 | FLOAT_MINMAX(max_d, 64, maxnum) |
| 3250 | FLOAT_MINMAX(maxa_s, 32, maxnummag) |
| 3251 | FLOAT_MINMAX(maxa_d, 64, maxnummag) |
| 3252 | |
| 3253 | FLOAT_MINMAX(min_s, 32, minnum) |
| 3254 | FLOAT_MINMAX(min_d, 64, minnum) |
| 3255 | FLOAT_MINMAX(mina_s, 32, minnummag) |
| 3256 | FLOAT_MINMAX(mina_d, 64, minnummag) |
| 3257 | #undef FLOAT_MINMAX |
| 3258 | |
| 3259 | /* ternary operations */ |
| 3260 | #define UNFUSED_FMA(prefix, a, b, c, flags) \ |
| 3261 | { \ |
| 3262 | a = prefix##_mul(a, b, &env->active_fpu.fp_status); \ |
| 3263 | if ((flags) & float_muladd_negate_c) { \ |
| 3264 | a = prefix##_sub(a, c, &env->active_fpu.fp_status); \ |
| 3265 | } else { \ |
| 3266 | a = prefix##_add(a, c, &env->active_fpu.fp_status); \ |
| 3267 | } \ |
| 3268 | if ((flags) & float_muladd_negate_result) { \ |
| 3269 | a = prefix##_chs(a); \ |
| 3270 | } \ |
| 3271 | } |
| 3272 | |
| 3273 | /* FMA based operations */ |
| 3274 | #define FLOAT_FMA(name, type) \ |
| 3275 | uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ |
| 3276 | uint64_t fdt0, uint64_t fdt1, \ |
| 3277 | uint64_t fdt2) \ |
| 3278 | { \ |
| 3279 | UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \ |
| 3280 | update_fcr31(env, GETPC()); \ |
| 3281 | return fdt0; \ |
| 3282 | } \ |
| 3283 | \ |
| 3284 | uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ |
| 3285 | uint32_t fst0, uint32_t fst1, \ |
| 3286 | uint32_t fst2) \ |
| 3287 | { \ |
| 3288 | UNFUSED_FMA(float32, fst0, fst1, fst2, type); \ |
| 3289 | update_fcr31(env, GETPC()); \ |
| 3290 | return fst0; \ |
| 3291 | } \ |
| 3292 | \ |
| 3293 | uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ |
| 3294 | uint64_t fdt0, uint64_t fdt1, \ |
| 3295 | uint64_t fdt2) \ |
| 3296 | { \ |
| 3297 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ |
| 3298 | uint32_t fsth0 = fdt0 >> 32; \ |
| 3299 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ |
| 3300 | uint32_t fsth1 = fdt1 >> 32; \ |
| 3301 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ |
| 3302 | uint32_t fsth2 = fdt2 >> 32; \ |
| 3303 | \ |
| 3304 | UNFUSED_FMA(float32, fst0, fst1, fst2, type); \ |
| 3305 | UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \ |
| 3306 | update_fcr31(env, GETPC()); \ |
| 3307 | return ((uint64_t)fsth0 << 32) | fst0; \ |
| 3308 | } |
| 3309 | FLOAT_FMA(madd, 0) |
| 3310 | FLOAT_FMA(msub, float_muladd_negate_c) |
| 3311 | FLOAT_FMA(nmadd, float_muladd_negate_result) |
| 3312 | FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c) |
| 3313 | #undef FLOAT_FMA |
| 3314 | |
| 3315 | #define FLOAT_FMADDSUB(name, bits, muladd_arg) \ |
| 3316 | uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \ |
| 3317 | uint ## bits ## _t fs, \ |
| 3318 | uint ## bits ## _t ft, \ |
| 3319 | uint ## bits ## _t fd) \ |
| 3320 | { \ |
| 3321 | uint ## bits ## _t fdret; \ |
| 3322 | \ |
| 3323 | fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \ |
| 3324 | &env->active_fpu.fp_status); \ |
| 3325 | update_fcr31(env, GETPC()); \ |
| 3326 | return fdret; \ |
| 3327 | } |
| 3328 | |
| 3329 | FLOAT_FMADDSUB(maddf_s, 32, 0) |
| 3330 | FLOAT_FMADDSUB(maddf_d, 64, 0) |
| 3331 | FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product) |
| 3332 | FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product) |
| 3333 | #undef FLOAT_FMADDSUB |
| 3334 | |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 3335 | /* compare operations */ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3336 | #define FOP_COND_D(op, cond) \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3337 | void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
| 3338 | uint64_t fdt1, int cc) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3339 | { \ |
Aurelien Jarno | 6a38534 | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3340 | int c; \ |
Aurelien Jarno | 6a38534 | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3341 | c = cond; \ |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3342 | update_fcr31(env, GETPC()); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3343 | if (c) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3344 | SET_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3345 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3346 | CLEAR_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3347 | } \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3348 | void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
| 3349 | uint64_t fdt1, int cc) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3350 | { \ |
| 3351 | int c; \ |
| 3352 | fdt0 = float64_abs(fdt0); \ |
| 3353 | fdt1 = float64_abs(fdt1); \ |
| 3354 | c = cond; \ |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3355 | update_fcr31(env, GETPC()); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3356 | if (c) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3357 | SET_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3358 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3359 | CLEAR_FP_COND(cc, env->active_fpu); \ |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3360 | } |
| 3361 | |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3362 | /* NOTE: the comma operator will make "cond" to eval to false, |
Aurelien Jarno | 3a59938 | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3363 | * but float64_unordered_quiet() is still called. */ |
| 3364 | FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0)) |
| 3365 | FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)) |
Aurelien Jarno | 06a0e6b | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3366 | FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 211315f | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3367 | FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 06a0e6b | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3368 | FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3369 | FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3370 | FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3371 | FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3372 | /* NOTE: the comma operator will make "cond" to eval to false, |
Aurelien Jarno | 3a59938 | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3373 | * but float64_unordered() is still called. */ |
| 3374 | FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0)) |
| 3375 | FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)) |
Aurelien Jarno | 06a0e6b | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3376 | FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3377 | FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 3378 | FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 3a59938 | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3379 | FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 06a0e6b | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3380 | FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 3a59938 | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3381 | FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3382 | |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3383 | #define FOP_COND_S(op, cond) \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3384 | void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ |
| 3385 | uint32_t fst1, int cc) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3386 | { \ |
Aurelien Jarno | 6a38534 | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3387 | int c; \ |
Aurelien Jarno | 6a38534 | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3388 | c = cond; \ |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3389 | update_fcr31(env, GETPC()); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3390 | if (c) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3391 | SET_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3392 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3393 | CLEAR_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3394 | } \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3395 | void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ |
| 3396 | uint32_t fst1, int cc) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3397 | { \ |
| 3398 | int c; \ |
| 3399 | fst0 = float32_abs(fst0); \ |
| 3400 | fst1 = float32_abs(fst1); \ |
| 3401 | c = cond; \ |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3402 | update_fcr31(env, GETPC()); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3403 | if (c) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3404 | SET_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3405 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3406 | CLEAR_FP_COND(cc, env->active_fpu); \ |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3407 | } |
| 3408 | |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3409 | /* NOTE: the comma operator will make "cond" to eval to false, |
Aurelien Jarno | 3a59938 | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3410 | * but float32_unordered_quiet() is still called. */ |
| 3411 | FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0)) |
| 3412 | FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)) |
Aurelien Jarno | 06a0e6b | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3413 | FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 211315f | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3414 | FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 06a0e6b | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3415 | FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
| 3416 | FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
| 3417 | FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
| 3418 | FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3419 | /* NOTE: the comma operator will make "cond" to eval to false, |
Aurelien Jarno | 3a59938 | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3420 | * but float32_unordered() is still called. */ |
| 3421 | FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0)) |
| 3422 | FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status)) |
Aurelien Jarno | 06a0e6b | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3423 | FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status)) |
| 3424 | FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) |
| 3425 | FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 3a59938 | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3426 | FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 06a0e6b | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3427 | FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 3a59938 | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3428 | FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3429 | |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3430 | #define FOP_COND_PS(op, condl, condh) \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3431 | void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
| 3432 | uint64_t fdt1, int cc) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3433 | { \ |
Aurelien Jarno | 6a38534 | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3434 | uint32_t fst0, fsth0, fst1, fsth1; \ |
| 3435 | int ch, cl; \ |
Aurelien Jarno | 6a38534 | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3436 | fst0 = fdt0 & 0XFFFFFFFF; \ |
| 3437 | fsth0 = fdt0 >> 32; \ |
| 3438 | fst1 = fdt1 & 0XFFFFFFFF; \ |
| 3439 | fsth1 = fdt1 >> 32; \ |
| 3440 | cl = condl; \ |
| 3441 | ch = condh; \ |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3442 | update_fcr31(env, GETPC()); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3443 | if (cl) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3444 | SET_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3445 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3446 | CLEAR_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3447 | if (ch) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3448 | SET_FP_COND(cc + 1, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3449 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3450 | CLEAR_FP_COND(cc + 1, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3451 | } \ |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 3452 | void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ |
| 3453 | uint64_t fdt1, int cc) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3454 | { \ |
Aurelien Jarno | 6a38534 | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3455 | uint32_t fst0, fsth0, fst1, fsth1; \ |
| 3456 | int ch, cl; \ |
| 3457 | fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \ |
| 3458 | fsth0 = float32_abs(fdt0 >> 32); \ |
| 3459 | fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \ |
| 3460 | fsth1 = float32_abs(fdt1 >> 32); \ |
| 3461 | cl = condl; \ |
| 3462 | ch = condh; \ |
Aurelien Jarno | 5f7319c | 2012-10-28 19:34:03 +0100 | [diff] [blame] | 3463 | update_fcr31(env, GETPC()); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3464 | if (cl) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3465 | SET_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3466 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3467 | CLEAR_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3468 | if (ch) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3469 | SET_FP_COND(cc + 1, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 3470 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 3471 | CLEAR_FP_COND(cc + 1, env->active_fpu); \ |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3472 | } |
| 3473 | |
| 3474 | /* NOTE: the comma operator will make "cond" to eval to false, |
Aurelien Jarno | 3a59938 | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3475 | * but float32_unordered_quiet() is still called. */ |
| 3476 | FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0), |
| 3477 | (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0)) |
| 3478 | FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), |
| 3479 | float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)) |
Aurelien Jarno | 06a0e6b | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3480 | FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), |
| 3481 | float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 211315f | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3482 | FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status), |
| 3483 | float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 06a0e6b | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3484 | FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), |
| 3485 | float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3486 | FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status), |
| 3487 | float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3488 | FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), |
| 3489 | float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3490 | FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status), |
| 3491 | float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status)) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 3492 | /* NOTE: the comma operator will make "cond" to eval to false, |
Aurelien Jarno | 3a59938 | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3493 | * but float32_unordered() is still called. */ |
| 3494 | FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0), |
| 3495 | (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0)) |
| 3496 | FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status), |
| 3497 | float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)) |
Aurelien Jarno | 06a0e6b | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3498 | FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status), |
| 3499 | float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3500 | FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), |
| 3501 | float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 3502 | FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status), |
| 3503 | float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 3a59938 | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3504 | FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), |
| 3505 | float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 06a0e6b | 2011-04-14 00:49:30 +0200 | [diff] [blame] | 3506 | FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status), |
| 3507 | float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |
Aurelien Jarno | 3a59938 | 2011-04-14 00:49:29 +0200 | [diff] [blame] | 3508 | FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), |
| 3509 | float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |
Yongbok Kim | 3f49388 | 2014-06-27 08:49:07 +0100 | [diff] [blame] | 3510 | |
| 3511 | /* R6 compare operations */ |
| 3512 | #define FOP_CONDN_D(op, cond) \ |
| 3513 | uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \ |
| 3514 | uint64_t fdt1) \ |
| 3515 | { \ |
| 3516 | uint64_t c; \ |
| 3517 | c = cond; \ |
| 3518 | update_fcr31(env, GETPC()); \ |
| 3519 | if (c) { \ |
| 3520 | return -1; \ |
| 3521 | } else { \ |
| 3522 | return 0; \ |
| 3523 | } \ |
| 3524 | } |
| 3525 | |
| 3526 | /* NOTE: the comma operator will make "cond" to eval to false, |
| 3527 | * but float64_unordered_quiet() is still called. */ |
| 3528 | FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0)) |
| 3529 | FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))) |
| 3530 | FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3531 | FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) |
| 3532 | || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3533 | FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3534 | FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) |
| 3535 | || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3536 | FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3537 | FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) |
| 3538 | || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3539 | /* NOTE: the comma operator will make "cond" to eval to false, |
| 3540 | * but float64_unordered() is still called. */ |
| 3541 | FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0)) |
| 3542 | FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))) |
| 3543 | FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3544 | FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) |
| 3545 | || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3546 | FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3547 | FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) |
| 3548 | || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3549 | FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3550 | FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) |
| 3551 | || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3552 | FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status) |
| 3553 | || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3554 | FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) |
| 3555 | || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status) |
| 3556 | || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3557 | FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status) |
| 3558 | || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3559 | FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status) |
| 3560 | || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3561 | FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) |
| 3562 | || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status) |
| 3563 | || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3564 | FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status) |
| 3565 | || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))) |
| 3566 | |
| 3567 | #define FOP_CONDN_S(op, cond) \ |
| 3568 | uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \ |
| 3569 | uint32_t fst1) \ |
| 3570 | { \ |
| 3571 | uint64_t c; \ |
| 3572 | c = cond; \ |
| 3573 | update_fcr31(env, GETPC()); \ |
| 3574 | if (c) { \ |
| 3575 | return -1; \ |
| 3576 | } else { \ |
| 3577 | return 0; \ |
| 3578 | } \ |
| 3579 | } |
| 3580 | |
| 3581 | /* NOTE: the comma operator will make "cond" to eval to false, |
| 3582 | * but float32_unordered_quiet() is still called. */ |
| 3583 | FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0)) |
| 3584 | FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))) |
| 3585 | FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))) |
| 3586 | FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) |
| 3587 | || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))) |
| 3588 | FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))) |
| 3589 | FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) |
| 3590 | || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))) |
| 3591 | FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))) |
| 3592 | FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) |
| 3593 | || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))) |
| 3594 | /* NOTE: the comma operator will make "cond" to eval to false, |
| 3595 | * but float32_unordered() is still called. */ |
| 3596 | FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0)) |
| 3597 | FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status))) |
| 3598 | FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status))) |
| 3599 | FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status) |
| 3600 | || float32_eq(fst0, fst1, &env->active_fpu.fp_status))) |
| 3601 | FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status))) |
| 3602 | FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status) |
| 3603 | || float32_lt(fst0, fst1, &env->active_fpu.fp_status))) |
| 3604 | FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status))) |
| 3605 | FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status) |
| 3606 | || float32_le(fst0, fst1, &env->active_fpu.fp_status))) |
| 3607 | FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status) |
| 3608 | || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))) |
| 3609 | FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) |
| 3610 | || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status) |
| 3611 | || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))) |
| 3612 | FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status) |
| 3613 | || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))) |
| 3614 | FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status) |
| 3615 | || float32_le(fst0, fst1, &env->active_fpu.fp_status))) |
| 3616 | FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status) |
| 3617 | || float32_lt(fst1, fst0, &env->active_fpu.fp_status) |
| 3618 | || float32_lt(fst0, fst1, &env->active_fpu.fp_status))) |
| 3619 | FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status) |
| 3620 | || float32_lt(fst0, fst1, &env->active_fpu.fp_status))) |
Yongbok Kim | f768587 | 2014-11-01 05:28:51 +0000 | [diff] [blame] | 3621 | |
| 3622 | /* MSA */ |
| 3623 | /* Data format min and max values */ |
| 3624 | #define DF_BITS(df) (1 << ((df) + 3)) |
| 3625 | |
| 3626 | /* Element-by-element access macros */ |
| 3627 | #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df)) |
| 3628 | |
Yongbok Kim | adc370a | 2015-06-01 12:13:24 +0100 | [diff] [blame] | 3629 | #if !defined(CONFIG_USER_ONLY) |
| 3630 | #define MEMOP_IDX(DF) \ |
| 3631 | TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \ |
| 3632 | cpu_mmu_index(env)); |
| 3633 | #else |
| 3634 | #define MEMOP_IDX(DF) |
| 3635 | #endif |
Yongbok Kim | f768587 | 2014-11-01 05:28:51 +0000 | [diff] [blame] | 3636 | |
Yongbok Kim | adc370a | 2015-06-01 12:13:24 +0100 | [diff] [blame] | 3637 | #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \ |
| 3638 | void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \ |
| 3639 | target_ulong addr) \ |
| 3640 | { \ |
| 3641 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ |
| 3642 | wr_t wx; \ |
| 3643 | int i; \ |
| 3644 | MEMOP_IDX(DF) \ |
| 3645 | for (i = 0; i < DF_ELEMENTS(DF); i++) { \ |
| 3646 | wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \ |
| 3647 | } \ |
| 3648 | memcpy(pwd, &wx, sizeof(wr_t)); \ |
Yongbok Kim | f768587 | 2014-11-01 05:28:51 +0000 | [diff] [blame] | 3649 | } |
| 3650 | |
Yongbok Kim | adc370a | 2015-06-01 12:13:24 +0100 | [diff] [blame] | 3651 | #if !defined(CONFIG_USER_ONLY) |
| 3652 | MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETRA()) |
| 3653 | MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETRA()) |
| 3654 | MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETRA()) |
| 3655 | MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETRA()) |
| 3656 | #else |
| 3657 | MSA_LD_DF(DF_BYTE, b, cpu_ldub_data) |
| 3658 | MSA_LD_DF(DF_HALF, h, cpu_lduw_data) |
| 3659 | MSA_LD_DF(DF_WORD, w, cpu_ldl_data) |
| 3660 | MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data) |
| 3661 | #endif |
Yongbok Kim | f768587 | 2014-11-01 05:28:51 +0000 | [diff] [blame] | 3662 | |
Yongbok Kim | adc370a | 2015-06-01 12:13:24 +0100 | [diff] [blame] | 3663 | #define MSA_PAGESPAN(x) \ |
| 3664 | ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE) |
| 3665 | |
| 3666 | static inline void ensure_writable_pages(CPUMIPSState *env, |
| 3667 | target_ulong addr, |
| 3668 | int mmu_idx, |
| 3669 | uintptr_t retaddr) |
| 3670 | { |
| 3671 | #if !defined(CONFIG_USER_ONLY) |
| 3672 | target_ulong page_addr; |
| 3673 | if (unlikely(MSA_PAGESPAN(addr))) { |
| 3674 | /* first page */ |
| 3675 | probe_write(env, addr, mmu_idx, retaddr); |
| 3676 | /* second page */ |
| 3677 | page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |
| 3678 | probe_write(env, page_addr, mmu_idx, retaddr); |
Yongbok Kim | f768587 | 2014-11-01 05:28:51 +0000 | [diff] [blame] | 3679 | } |
Yongbok Kim | adc370a | 2015-06-01 12:13:24 +0100 | [diff] [blame] | 3680 | #endif |
Yongbok Kim | f768587 | 2014-11-01 05:28:51 +0000 | [diff] [blame] | 3681 | } |
Yongbok Kim | adc370a | 2015-06-01 12:13:24 +0100 | [diff] [blame] | 3682 | |
| 3683 | #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \ |
| 3684 | void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \ |
| 3685 | target_ulong addr) \ |
| 3686 | { \ |
| 3687 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ |
| 3688 | int mmu_idx = cpu_mmu_index(env); \ |
| 3689 | int i; \ |
| 3690 | MEMOP_IDX(DF) \ |
| 3691 | ensure_writable_pages(env, addr, mmu_idx, GETRA()); \ |
| 3692 | for (i = 0; i < DF_ELEMENTS(DF); i++) { \ |
| 3693 | ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \ |
| 3694 | } \ |
| 3695 | } |
| 3696 | |
| 3697 | #if !defined(CONFIG_USER_ONLY) |
| 3698 | MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETRA()) |
| 3699 | MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETRA()) |
| 3700 | MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETRA()) |
| 3701 | MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETRA()) |
| 3702 | #else |
| 3703 | MSA_ST_DF(DF_BYTE, b, cpu_stb_data) |
| 3704 | MSA_ST_DF(DF_HALF, h, cpu_stw_data) |
| 3705 | MSA_ST_DF(DF_WORD, w, cpu_stl_data) |
| 3706 | MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data) |
| 3707 | #endif |