MIPS TLB style selection at runtime, by Herve Poussineau.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2809 c046a42c-6fe2-441c-8c8c-71466251a162
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 2ebcede..9d7a560 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -298,26 +298,6 @@
cpu_abort(env, "mtc0 status irqraise debug\n");
}
-void do_tlbwi (void)
-{
- cpu_abort(env, "tlbwi\n");
-}
-
-void do_tlbwr (void)
-{
- cpu_abort(env, "tlbwr\n");
-}
-
-void do_tlbp (void)
-{
- cpu_abort(env, "tlbp\n");
-}
-
-void do_tlbr (void)
-{
- cpu_abort(env, "tlbr\n");
-}
-
void cpu_mips_tlb_flush (CPUState *env, int flush_global)
{
cpu_abort(env, "mips_tlb_flush\n");
@@ -389,7 +369,6 @@
}
/* TLB management */
-#if defined(MIPS_USES_R4K_TLB)
void cpu_mips_tlb_flush (CPUState *env, int flush_global)
{
/* Flush qemu's TLB and discard all shadowed entries. */
@@ -397,20 +376,20 @@
env->tlb_in_use = env->nb_tlb;
}
-static void mips_tlb_flush_extra (CPUState *env, int first)
+static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
{
/* Discard entries from env->tlb[first] onwards. */
while (env->tlb_in_use > first) {
- invalidate_tlb(env, --env->tlb_in_use, 0);
+ r4k_invalidate_tlb(env, --env->tlb_in_use, 0);
}
}
-static void fill_tlb (int idx)
+static void r4k_fill_tlb (int idx)
{
- tlb_t *tlb;
+ r4k_tlb_t *tlb;
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
- tlb = &env->tlb[idx];
+ tlb = &env->mmu.r4k.tlb[idx];
tlb->VPN = env->CP0_EntryHi & ~(target_ulong)0x1FFF;
tlb->ASID = env->CP0_EntryHi & 0xFF;
tlb->PageMask = env->CP0_PageMask;
@@ -425,28 +404,28 @@
tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
}
-void do_tlbwi (void)
+void r4k_do_tlbwi (void)
{
/* Discard cached TLB entries. We could avoid doing this if the
tlbwi is just upgrading access permissions on the current entry;
that might be a further win. */
- mips_tlb_flush_extra (env, env->nb_tlb);
+ r4k_mips_tlb_flush_extra (env, env->nb_tlb);
- invalidate_tlb(env, env->CP0_Index % env->nb_tlb, 0);
- fill_tlb(env->CP0_Index % env->nb_tlb);
+ r4k_invalidate_tlb(env, env->CP0_Index % env->nb_tlb, 0);
+ r4k_fill_tlb(env->CP0_Index % env->nb_tlb);
}
-void do_tlbwr (void)
+void r4k_do_tlbwr (void)
{
int r = cpu_mips_get_random(env);
- invalidate_tlb(env, r, 1);
- fill_tlb(r);
+ r4k_invalidate_tlb(env, r, 1);
+ r4k_fill_tlb(r);
}
-void do_tlbp (void)
+void r4k_do_tlbp (void)
{
- tlb_t *tlb;
+ r4k_tlb_t *tlb;
target_ulong tag;
uint8_t ASID;
int i;
@@ -454,7 +433,7 @@
tag = env->CP0_EntryHi & (int32_t)0xFFFFE000;
ASID = env->CP0_EntryHi & 0xFF;
for (i = 0; i < env->nb_tlb; i++) {
- tlb = &env->tlb[i];
+ tlb = &env->mmu.r4k.tlb[i];
/* Check ASID, virtual page number & size */
if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
/* TLB match */
@@ -465,11 +444,11 @@
if (i == env->nb_tlb) {
/* No match. Discard any shadow entries, if any of them match. */
for (i = env->nb_tlb; i < env->tlb_in_use; i++) {
- tlb = &env->tlb[i];
+ tlb = &env->mmu.r4k.tlb[i];
/* Check ASID, virtual page number & size */
if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
- mips_tlb_flush_extra (env, i);
+ r4k_mips_tlb_flush_extra (env, i);
break;
}
}
@@ -478,19 +457,19 @@
}
}
-void do_tlbr (void)
+void r4k_do_tlbr (void)
{
- tlb_t *tlb;
+ r4k_tlb_t *tlb;
uint8_t ASID;
ASID = env->CP0_EntryHi & 0xFF;
- tlb = &env->tlb[env->CP0_Index % env->nb_tlb];
+ tlb = &env->mmu.r4k.tlb[env->CP0_Index % env->nb_tlb];
/* If this will change the current ASID, flush qemu's TLB. */
if (ASID != tlb->ASID)
cpu_mips_tlb_flush (env, 1);
- mips_tlb_flush_extra(env, env->nb_tlb);
+ r4k_mips_tlb_flush_extra(env, env->nb_tlb);
env->CP0_EntryHi = tlb->VPN | tlb->ASID;
env->CP0_PageMask = tlb->PageMask;
@@ -499,7 +478,6 @@
env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
(tlb->C1 << 3) | (tlb->PFN[1] >> 6);
}
-#endif
#endif /* !CONFIG_USER_ONLY */
