commit 2a6e32dd46967124f12c29eece7aa7fc3f0ee063
author Aurelien Jarno <aurelien@aurel32.net> Sun Nov 22 13:22:54 2009 +0100
committer Aurelien Jarno <aurelien@aurel32.net> Sun Nov 22 14:12:19 2009 +0100
tree fa0760fd31f33d71b3a52c3c90d056ce31adc5c6
parent 5499b6ffac490a3a44dcb97e9cebb99f0151d696

target-mips: make CP0_LLAddr register CPU dependent

Depending on the CPU, CP0_LLAddr is either read-only or read-write,
and the returned value can be shifted by a variable amount of bits.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>

target-mips/op_helper.c

diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index d2a81f0..52d687d 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -730,7 +730,7 @@
 
 target_ulong helper_mfc0_lladdr (void)
 {
-    return (int32_t)env->lladdr >> 4;
+    return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 }
 
 target_ulong helper_mfc0_watchlo (uint32_t sel)
@@ -795,7 +795,7 @@
 
 target_ulong helper_dmfc0_lladdr (void)
 {
-    return env->lladdr >> 4;
+    return env->lladdr >> env->CP0_LLAddr_shift;
 }
 
 target_ulong helper_dmfc0_watchlo (uint32_t sel)
@@ -1243,6 +1243,13 @@
     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
 }
 
+void helper_mtc0_lladdr (target_ulong arg1)
+{
+    target_long mask = env->CP0_LLAddr_rw_bitmask;
+    arg1 = arg1 << env->CP0_LLAddr_shift;
+    env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
+}
+
 void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
 {
     /* Watch exceptions for instructions, data loads, data stores