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bellard6af0bf92005-07-02 14:58:51 +00001#if !defined (__MIPS_CPU_H__)
2#define __MIPS_CPU_H__
3
Blue Swirl3e457172011-07-13 12:44:15 +00004//#define DEBUG_OP
5
Paolo Bonzinid94f0a82014-03-28 17:48:12 +01006#define ALIGNED_ONLY
bellard4ad40f32005-12-05 19:59:36 +00007
Andreas Färber9349b4f2012-03-14 01:38:32 +01008#define CPUArchState struct CPUMIPSState
pbrookc2764712009-03-07 15:24:59 +00009
Stefan Weil9a78eea2010-10-22 23:03:33 +020010#include "qemu-common.h"
Paolo Bonzini416bf932016-03-15 13:49:25 +010011#include "cpu-qom.h"
bellard6af0bf92005-07-02 14:58:51 +000012#include "mips-defs.h"
Paolo Bonzini022c62c2012-12-17 18:19:49 +010013#include "exec/cpu-defs.h"
Paolo Bonzini6b4c3052012-10-24 13:12:00 +020014#include "fpu/softfloat.h"
bellard6af0bf92005-07-02 14:58:51 +000015
thsead93602007-09-06 00:18:15 +000016struct CPUMIPSState;
bellard6af0bf92005-07-02 14:58:51 +000017
Anthony Liguoric227f092009-10-01 16:12:16 -050018typedef struct r4k_tlb_t r4k_tlb_t;
19struct r4k_tlb_t {
bellard6af0bf92005-07-02 14:58:51 +000020 target_ulong VPN;
ths9c2149c2007-01-23 22:45:22 +000021 uint32_t PageMask;
Peter Maydelld783f782016-01-25 17:40:49 +000022 uint8_t ASID;
23 unsigned int G:1;
24 unsigned int C0:3;
25 unsigned int C1:3;
26 unsigned int V0:1;
27 unsigned int V1:1;
28 unsigned int D0:1;
29 unsigned int D1:1;
30 unsigned int XI0:1;
31 unsigned int XI1:1;
32 unsigned int RI0:1;
33 unsigned int RI1:1;
34 unsigned int EHINV:1;
Leon Alrae284b7312015-06-09 17:14:13 +010035 uint64_t PFN[2];
bellard6af0bf92005-07-02 14:58:51 +000036};
bellard6af0bf92005-07-02 14:58:51 +000037
Paul Brook3c7b48b2010-03-01 04:11:28 +000038#if !defined(CONFIG_USER_ONLY)
thsead93602007-09-06 00:18:15 +000039typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
40struct CPUMIPSTLBContext {
41 uint32_t nb_tlb;
42 uint32_t tlb_in_use;
Avi Kivitya8170e52012-10-23 12:30:10 +020043 int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
Blue Swirl895c2d02012-09-02 14:52:59 +000044 void (*helper_tlbwi)(struct CPUMIPSState *env);
45 void (*helper_tlbwr)(struct CPUMIPSState *env);
46 void (*helper_tlbp)(struct CPUMIPSState *env);
47 void (*helper_tlbr)(struct CPUMIPSState *env);
Leon Alrae9456c2f2014-07-07 11:24:00 +010048 void (*helper_tlbinv)(struct CPUMIPSState *env);
49 void (*helper_tlbinvf)(struct CPUMIPSState *env);
thsead93602007-09-06 00:18:15 +000050 union {
51 struct {
Anthony Liguoric227f092009-10-01 16:12:16 -050052 r4k_tlb_t tlb[MIPS_TLB_MAX];
thsead93602007-09-06 00:18:15 +000053 } r4k;
54 } mmu;
55};
Paul Brook3c7b48b2010-03-01 04:11:28 +000056#endif
ths51b27722007-05-30 20:46:02 +000057
Yongbok Kime97a3912014-11-01 05:28:35 +000058/* MSA Context */
59#define MSA_WRLEN (128)
60
61enum CPUMIPSMSADataFormat {
62 DF_BYTE = 0,
63 DF_HALF,
64 DF_WORD,
65 DF_DOUBLE
66};
67
68typedef union wr_t wr_t;
69union wr_t {
70 int8_t b[MSA_WRLEN/8];
71 int16_t h[MSA_WRLEN/16];
72 int32_t w[MSA_WRLEN/32];
73 int64_t d[MSA_WRLEN/64];
74};
75
Anthony Liguoric227f092009-10-01 16:12:16 -050076typedef union fpr_t fpr_t;
77union fpr_t {
thsead93602007-09-06 00:18:15 +000078 float64 fd; /* ieee double precision */
79 float32 fs[2];/* ieee single precision */
80 uint64_t d; /* binary double fixed-point */
81 uint32_t w[2]; /* binary single fixed-point */
Yongbok Kime97a3912014-11-01 05:28:35 +000082/* FPU/MSA register mapping is not tested on big-endian hosts. */
83 wr_t wr; /* vector data */
thsead93602007-09-06 00:18:15 +000084};
85/* define FP_ENDIAN_IDX to access the same location
Stefan Weil4ff97862011-03-13 15:44:02 +010086 * in the fpr_t union regardless of the host endianness
thsead93602007-09-06 00:18:15 +000087 */
Juan Quintelae2542fe2009-07-27 16:13:06 +020088#if defined(HOST_WORDS_BIGENDIAN)
thsead93602007-09-06 00:18:15 +000089# define FP_ENDIAN_IDX 1
90#else
91# define FP_ENDIAN_IDX 0
thsc570fd12006-12-21 01:19:56 +000092#endif
thsead93602007-09-06 00:18:15 +000093
94typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
95struct CPUMIPSFPUContext {
bellard6af0bf92005-07-02 14:58:51 +000096 /* Floating point registers */
Anthony Liguoric227f092009-10-01 16:12:16 -050097 fpr_t fpr[32];
bellard6ea83fe2006-06-14 12:56:19 +000098 float_status fp_status;
ths5a5012e2007-05-07 13:55:33 +000099 /* fpu implementation/revision register (fir) */
bellard6af0bf92005-07-02 14:58:51 +0000100 uint32_t fcr0;
Leon Alrae7c979af2015-04-21 16:06:28 +0100101#define FCR0_FREP 29
Petar Jovanovicb4dd99a2014-01-17 19:25:57 +0100102#define FCR0_UFRP 28
Leon Alraeba5c79f2016-02-24 10:47:10 +0000103#define FCR0_HAS2008 23
ths5a5012e2007-05-07 13:55:33 +0000104#define FCR0_F64 22
105#define FCR0_L 21
106#define FCR0_W 20
107#define FCR0_3D 19
108#define FCR0_PS 18
109#define FCR0_D 17
110#define FCR0_S 16
111#define FCR0_PRID 8
112#define FCR0_REV 0
bellard6ea83fe2006-06-14 12:56:19 +0000113 /* fcsr */
114 uint32_t fcr31;
Leon Alraeba5c79f2016-02-24 10:47:10 +0000115#define FCR31_ABS2008 19
116#define FCR31_NAN2008 18
thsf01be152008-09-18 11:57:27 +0000117#define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
118#define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
119#define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
ths5a5012e2007-05-07 13:55:33 +0000120#define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
121#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
122#define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
123#define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
124#define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
125#define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
126#define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
bellard6ea83fe2006-06-14 12:56:19 +0000127#define FP_INEXACT 1
128#define FP_UNDERFLOW 2
129#define FP_OVERFLOW 4
130#define FP_DIV0 8
131#define FP_INVALID 16
132#define FP_UNIMPLEMENTED 32
thsead93602007-09-06 00:18:15 +0000133};
ths36d23952007-02-28 22:37:42 +0000134
ths623a9302007-10-28 19:45:05 +0000135#define NB_MMU_MODES 3
Richard Hendersonc20d5942015-08-30 09:25:36 -0700136#define TARGET_INSN_START_EXTRA_WORDS 2
j_mayer6ebbf392007-10-14 07:07:08 +0000137
thsead93602007-09-06 00:18:15 +0000138typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
139struct CPUMIPSMVPContext {
140 int32_t CP0_MVPControl;
141#define CP0MVPCo_CPA 3
142#define CP0MVPCo_STLB 2
143#define CP0MVPCo_VPC 1
144#define CP0MVPCo_EVP 0
145 int32_t CP0_MVPConf0;
146#define CP0MVPC0_M 31
147#define CP0MVPC0_TLBS 29
148#define CP0MVPC0_GS 28
149#define CP0MVPC0_PCP 27
150#define CP0MVPC0_PTLBE 16
151#define CP0MVPC0_TCA 15
152#define CP0MVPC0_PVPE 10
153#define CP0MVPC0_PTC 0
154 int32_t CP0_MVPConf1;
155#define CP0MVPC1_CIM 31
156#define CP0MVPC1_CIF 30
157#define CP0MVPC1_PCX 20
158#define CP0MVPC1_PCP2 10
159#define CP0MVPC1_PCP1 0
160};
161
Anthony Liguoric227f092009-10-01 16:12:16 -0500162typedef struct mips_def_t mips_def_t;
thsead93602007-09-06 00:18:15 +0000163
164#define MIPS_SHADOW_SET_MAX 16
165#define MIPS_TC_MAX 5
thsf01be152008-09-18 11:57:27 +0000166#define MIPS_FPU_MAX 1
thsead93602007-09-06 00:18:15 +0000167#define MIPS_DSP_ACC 4
Leon Alraee98c0d12014-07-07 11:23:55 +0100168#define MIPS_KSCRATCH_NUM 6
Yongbok Kimf6d4dd82016-03-24 15:49:58 +0000169#define MIPS_MAAR_MAX 16 /* Must be an even number. */
thsead93602007-09-06 00:18:15 +0000170
thsb5dc7732008-06-27 10:02:35 +0000171typedef struct TCState TCState;
172struct TCState {
173 target_ulong gpr[32];
174 target_ulong PC;
175 target_ulong HI[MIPS_DSP_ACC];
176 target_ulong LO[MIPS_DSP_ACC];
177 target_ulong ACX[MIPS_DSP_ACC];
178 target_ulong DSPControl;
179 int32_t CP0_TCStatus;
180#define CP0TCSt_TCU3 31
181#define CP0TCSt_TCU2 30
182#define CP0TCSt_TCU1 29
183#define CP0TCSt_TCU0 28
184#define CP0TCSt_TMX 27
185#define CP0TCSt_RNST 23
186#define CP0TCSt_TDS 21
187#define CP0TCSt_DT 20
188#define CP0TCSt_DA 15
189#define CP0TCSt_A 13
190#define CP0TCSt_TKSU 11
191#define CP0TCSt_IXMT 10
192#define CP0TCSt_TASID 0
193 int32_t CP0_TCBind;
194#define CP0TCBd_CurTC 21
195#define CP0TCBd_TBE 17
196#define CP0TCBd_CurVPE 0
197 target_ulong CP0_TCHalt;
198 target_ulong CP0_TCContext;
199 target_ulong CP0_TCSchedule;
200 target_ulong CP0_TCScheFBack;
201 int32_t CP0_Debug_tcstatus;
Petar Jovanovicd2792792014-06-18 17:48:20 +0200202 target_ulong CP0_UserLocal;
Yongbok Kime97a3912014-11-01 05:28:35 +0000203
204 int32_t msacsr;
205
206#define MSACSR_FS 24
207#define MSACSR_FS_MASK (1 << MSACSR_FS)
208#define MSACSR_NX 18
209#define MSACSR_NX_MASK (1 << MSACSR_NX)
210#define MSACSR_CEF 2
211#define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
212#define MSACSR_RM 0
213#define MSACSR_RM_MASK (0x3 << MSACSR_RM)
214#define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
215 MSACSR_FS_MASK)
216
217 float_status msa_fp_status;
thsb5dc7732008-06-27 10:02:35 +0000218};
219
thsead93602007-09-06 00:18:15 +0000220typedef struct CPUMIPSState CPUMIPSState;
221struct CPUMIPSState {
thsb5dc7732008-06-27 10:02:35 +0000222 TCState active_tc;
thsf01be152008-09-18 11:57:27 +0000223 CPUMIPSFPUContext active_fpu;
thsb5dc7732008-06-27 10:02:35 +0000224
thsead93602007-09-06 00:18:15 +0000225 uint32_t current_tc;
thsf01be152008-09-18 11:57:27 +0000226 uint32_t current_fpu;
thsead93602007-09-06 00:18:15 +0000227
thse034e2c2007-06-23 18:04:12 +0000228 uint32_t SEGBITS;
ths6d355242007-12-25 03:13:56 +0000229 uint32_t PABITS;
Leon Alraee117f522015-04-14 10:09:38 +0100230#if defined(TARGET_MIPS64)
231# define PABITS_BASE 36
232#else
233# define PABITS_BASE 32
234#endif
thsb6d96be2008-07-09 11:05:10 +0000235 target_ulong SEGMask;
Leon Alrae284b7312015-06-09 17:14:13 +0100236 uint64_t PAMask;
Leon Alraee117f522015-04-14 10:09:38 +0100237#define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
ths29929e32007-05-13 13:49:44 +0000238
Yongbok Kime97a3912014-11-01 05:28:35 +0000239 int32_t msair;
240#define MSAIR_ProcID 8
241#define MSAIR_Rev 0
242
ths9c2149c2007-01-23 22:45:22 +0000243 int32_t CP0_Index;
thsead93602007-09-06 00:18:15 +0000244 /* CP0_MVP* are per MVP registers. */
Yongbok Kim01bc4352016-02-03 12:31:07 +0000245 int32_t CP0_VPControl;
246#define CP0VPCtl_DIS 0
ths9c2149c2007-01-23 22:45:22 +0000247 int32_t CP0_Random;
thsead93602007-09-06 00:18:15 +0000248 int32_t CP0_VPEControl;
249#define CP0VPECo_YSI 21
250#define CP0VPECo_GSI 20
251#define CP0VPECo_EXCPT 16
252#define CP0VPECo_TE 15
253#define CP0VPECo_TargTC 0
254 int32_t CP0_VPEConf0;
255#define CP0VPEC0_M 31
256#define CP0VPEC0_XTC 21
257#define CP0VPEC0_TCS 19
258#define CP0VPEC0_SCS 18
259#define CP0VPEC0_DSC 17
260#define CP0VPEC0_ICS 16
261#define CP0VPEC0_MVP 1
262#define CP0VPEC0_VPA 0
263 int32_t CP0_VPEConf1;
264#define CP0VPEC1_NCX 20
265#define CP0VPEC1_NCP2 10
266#define CP0VPEC1_NCP1 0
267 target_ulong CP0_YQMask;
268 target_ulong CP0_VPESchedule;
269 target_ulong CP0_VPEScheFBack;
270 int32_t CP0_VPEOpt;
271#define CP0VPEOpt_IWX7 15
272#define CP0VPEOpt_IWX6 14
273#define CP0VPEOpt_IWX5 13
274#define CP0VPEOpt_IWX4 12
275#define CP0VPEOpt_IWX3 11
276#define CP0VPEOpt_IWX2 10
277#define CP0VPEOpt_IWX1 9
278#define CP0VPEOpt_IWX0 8
279#define CP0VPEOpt_DWX7 7
280#define CP0VPEOpt_DWX6 6
281#define CP0VPEOpt_DWX5 5
282#define CP0VPEOpt_DWX4 4
283#define CP0VPEOpt_DWX3 3
284#define CP0VPEOpt_DWX2 2
285#define CP0VPEOpt_DWX1 1
286#define CP0VPEOpt_DWX0 0
Leon Alrae284b7312015-06-09 17:14:13 +0100287 uint64_t CP0_EntryLo0;
288 uint64_t CP0_EntryLo1;
Leon Alrae2fb58b72014-07-07 11:23:58 +0100289#if defined(TARGET_MIPS64)
290# define CP0EnLo_RI 63
291# define CP0EnLo_XI 62
292#else
293# define CP0EnLo_RI 31
294# define CP0EnLo_XI 30
295#endif
Yongbok Kim01bc4352016-02-03 12:31:07 +0000296 int32_t CP0_GlobalNumber;
297#define CP0GN_VPId 0
ths9c2149c2007-01-23 22:45:22 +0000298 target_ulong CP0_Context;
Leon Alraee98c0d12014-07-07 11:23:55 +0100299 target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
ths9c2149c2007-01-23 22:45:22 +0000300 int32_t CP0_PageMask;
Leon Alrae7207c7f2014-07-07 11:23:59 +0100301 int32_t CP0_PageGrain_rw_bitmask;
ths9c2149c2007-01-23 22:45:22 +0000302 int32_t CP0_PageGrain;
Leon Alrae7207c7f2014-07-07 11:23:59 +0100303#define CP0PG_RIE 31
304#define CP0PG_XIE 30
Leon Alraee117f522015-04-14 10:09:38 +0100305#define CP0PG_ELPA 29
Leon Alrae92ceb442014-07-07 11:23:59 +0100306#define CP0PG_IEC 27
ths9c2149c2007-01-23 22:45:22 +0000307 int32_t CP0_Wired;
thsead93602007-09-06 00:18:15 +0000308 int32_t CP0_SRSConf0_rw_bitmask;
309 int32_t CP0_SRSConf0;
310#define CP0SRSC0_M 31
311#define CP0SRSC0_SRS3 20
312#define CP0SRSC0_SRS2 10
313#define CP0SRSC0_SRS1 0
314 int32_t CP0_SRSConf1_rw_bitmask;
315 int32_t CP0_SRSConf1;
316#define CP0SRSC1_M 31
317#define CP0SRSC1_SRS6 20
318#define CP0SRSC1_SRS5 10
319#define CP0SRSC1_SRS4 0
320 int32_t CP0_SRSConf2_rw_bitmask;
321 int32_t CP0_SRSConf2;
322#define CP0SRSC2_M 31
323#define CP0SRSC2_SRS9 20
324#define CP0SRSC2_SRS8 10
325#define CP0SRSC2_SRS7 0
326 int32_t CP0_SRSConf3_rw_bitmask;
327 int32_t CP0_SRSConf3;
328#define CP0SRSC3_M 31
329#define CP0SRSC3_SRS12 20
330#define CP0SRSC3_SRS11 10
331#define CP0SRSC3_SRS10 0
332 int32_t CP0_SRSConf4_rw_bitmask;
333 int32_t CP0_SRSConf4;
334#define CP0SRSC4_SRS15 20
335#define CP0SRSC4_SRS14 10
336#define CP0SRSC4_SRS13 0
ths9c2149c2007-01-23 22:45:22 +0000337 int32_t CP0_HWREna;
thsc570fd12006-12-21 01:19:56 +0000338 target_ulong CP0_BadVAddr;
Leon Alraeaea14092014-07-07 11:24:01 +0100339 uint32_t CP0_BadInstr;
340 uint32_t CP0_BadInstrP;
ths9c2149c2007-01-23 22:45:22 +0000341 int32_t CP0_Count;
342 target_ulong CP0_EntryHi;
Leon Alrae9456c2f2014-07-07 11:24:00 +0100343#define CP0EnHi_EHINV 10
ths9c2149c2007-01-23 22:45:22 +0000344 int32_t CP0_Compare;
345 int32_t CP0_Status;
bellard6af0bf92005-07-02 14:58:51 +0000346#define CP0St_CU3 31
347#define CP0St_CU2 30
348#define CP0St_CU1 29
349#define CP0St_CU0 28
350#define CP0St_RP 27
bellard6ea83fe2006-06-14 12:56:19 +0000351#define CP0St_FR 26
bellard6af0bf92005-07-02 14:58:51 +0000352#define CP0St_RE 25
ths7a387ff2006-12-06 20:17:30 +0000353#define CP0St_MX 24
354#define CP0St_PX 23
bellard6af0bf92005-07-02 14:58:51 +0000355#define CP0St_BEV 22
356#define CP0St_TS 21
357#define CP0St_SR 20
358#define CP0St_NMI 19
359#define CP0St_IM 8
ths7a387ff2006-12-06 20:17:30 +0000360#define CP0St_KX 7
361#define CP0St_SX 6
362#define CP0St_UX 5
ths623a9302007-10-28 19:45:05 +0000363#define CP0St_KSU 3
bellard6af0bf92005-07-02 14:58:51 +0000364#define CP0St_ERL 2
365#define CP0St_EXL 1
366#define CP0St_IE 0
ths9c2149c2007-01-23 22:45:22 +0000367 int32_t CP0_IntCtl;
thsead93602007-09-06 00:18:15 +0000368#define CP0IntCtl_IPTI 29
Dongxue Zhang88991292015-11-25 20:57:12 +0800369#define CP0IntCtl_IPPCI 26
thsead93602007-09-06 00:18:15 +0000370#define CP0IntCtl_VS 5
ths9c2149c2007-01-23 22:45:22 +0000371 int32_t CP0_SRSCtl;
thsead93602007-09-06 00:18:15 +0000372#define CP0SRSCtl_HSS 26
373#define CP0SRSCtl_EICSS 18
374#define CP0SRSCtl_ESS 12
375#define CP0SRSCtl_PSS 6
376#define CP0SRSCtl_CSS 0
ths9c2149c2007-01-23 22:45:22 +0000377 int32_t CP0_SRSMap;
thsead93602007-09-06 00:18:15 +0000378#define CP0SRSMap_SSV7 28
379#define CP0SRSMap_SSV6 24
380#define CP0SRSMap_SSV5 20
381#define CP0SRSMap_SSV4 16
382#define CP0SRSMap_SSV3 12
383#define CP0SRSMap_SSV2 8
384#define CP0SRSMap_SSV1 4
385#define CP0SRSMap_SSV0 0
ths9c2149c2007-01-23 22:45:22 +0000386 int32_t CP0_Cause;
ths7a387ff2006-12-06 20:17:30 +0000387#define CP0Ca_BD 31
388#define CP0Ca_TI 30
389#define CP0Ca_CE 28
390#define CP0Ca_DC 27
391#define CP0Ca_PCI 26
bellard6af0bf92005-07-02 14:58:51 +0000392#define CP0Ca_IV 23
ths7a387ff2006-12-06 20:17:30 +0000393#define CP0Ca_WP 22
394#define CP0Ca_IP 8
ths4de9b242007-01-24 01:47:51 +0000395#define CP0Ca_IP_mask 0x0000FF00
ths7a387ff2006-12-06 20:17:30 +0000396#define CP0Ca_EC 2
thsc570fd12006-12-21 01:19:56 +0000397 target_ulong CP0_EPC;
ths9c2149c2007-01-23 22:45:22 +0000398 int32_t CP0_PRid;
thsb29a0342007-01-24 18:01:23 +0000399 int32_t CP0_EBase;
Yongbok Kimc870e3f2016-03-15 09:59:27 +0000400 target_ulong CP0_CMGCRBase;
ths9c2149c2007-01-23 22:45:22 +0000401 int32_t CP0_Config0;
bellard6af0bf92005-07-02 14:58:51 +0000402#define CP0C0_M 31
403#define CP0C0_K23 28
404#define CP0C0_KU 25
405#define CP0C0_MDU 20
Yongbok Kimaff2bc62015-07-10 12:10:52 +0100406#define CP0C0_MM 18
bellard6af0bf92005-07-02 14:58:51 +0000407#define CP0C0_BM 16
408#define CP0C0_BE 15
409#define CP0C0_AT 13
410#define CP0C0_AR 10
411#define CP0C0_MT 7
ths7a387ff2006-12-06 20:17:30 +0000412#define CP0C0_VI 3
bellard6af0bf92005-07-02 14:58:51 +0000413#define CP0C0_K0 0
ths9c2149c2007-01-23 22:45:22 +0000414 int32_t CP0_Config1;
ths7a387ff2006-12-06 20:17:30 +0000415#define CP0C1_M 31
bellard6af0bf92005-07-02 14:58:51 +0000416#define CP0C1_MMU 25
417#define CP0C1_IS 22
418#define CP0C1_IL 19
419#define CP0C1_IA 16
420#define CP0C1_DS 13
421#define CP0C1_DL 10
422#define CP0C1_DA 7
ths7a387ff2006-12-06 20:17:30 +0000423#define CP0C1_C2 6
424#define CP0C1_MD 5
bellard6af0bf92005-07-02 14:58:51 +0000425#define CP0C1_PC 4
426#define CP0C1_WR 3
427#define CP0C1_CA 2
428#define CP0C1_EP 1
429#define CP0C1_FP 0
ths9c2149c2007-01-23 22:45:22 +0000430 int32_t CP0_Config2;
ths7a387ff2006-12-06 20:17:30 +0000431#define CP0C2_M 31
432#define CP0C2_TU 28
433#define CP0C2_TS 24
434#define CP0C2_TL 20
435#define CP0C2_TA 16
436#define CP0C2_SU 12
437#define CP0C2_SS 8
438#define CP0C2_SL 4
439#define CP0C2_SA 0
ths9c2149c2007-01-23 22:45:22 +0000440 int32_t CP0_Config3;
ths7a387ff2006-12-06 20:17:30 +0000441#define CP0C3_M 31
Maciej W. Rozycki70409e62014-11-04 15:38:05 +0000442#define CP0C3_BPG 30
Yongbok Kimc870e3f2016-03-15 09:59:27 +0000443#define CP0C3_CMGCR 29
Yongbok Kime97a3912014-11-01 05:28:35 +0000444#define CP0C3_MSAP 28
Leon Alraeaea14092014-07-07 11:24:01 +0100445#define CP0C3_BP 27
446#define CP0C3_BI 26
Maciej W. Rozycki70409e62014-11-04 15:38:05 +0000447#define CP0C3_IPLW 21
448#define CP0C3_MMAR 18
449#define CP0C3_MCU 17
Nathan Froydbbfa8f72010-06-08 13:30:01 -0700450#define CP0C3_ISA_ON_EXC 16
Maciej W. Rozycki70409e62014-11-04 15:38:05 +0000451#define CP0C3_ISA 14
Petar Jovanovicd2792792014-06-18 17:48:20 +0200452#define CP0C3_ULRI 13
Leon Alrae7207c7f2014-07-07 11:23:59 +0100453#define CP0C3_RXI 12
Maciej W. Rozycki70409e62014-11-04 15:38:05 +0000454#define CP0C3_DSP2P 11
ths7a387ff2006-12-06 20:17:30 +0000455#define CP0C3_DSPP 10
456#define CP0C3_LPA 7
457#define CP0C3_VEIC 6
458#define CP0C3_VInt 5
459#define CP0C3_SP 4
Maciej W. Rozycki70409e62014-11-04 15:38:05 +0000460#define CP0C3_CDMM 3
ths7a387ff2006-12-06 20:17:30 +0000461#define CP0C3_MT 2
462#define CP0C3_SM 1
463#define CP0C3_TL 0
Maciej W. Rozycki8280b122014-11-04 15:37:17 +0000464 int32_t CP0_Config4;
465 int32_t CP0_Config4_rw_bitmask;
Petar Jovanovicb4160af2014-01-24 13:45:05 +0100466#define CP0C4_M 31
Leon Alrae9456c2f2014-07-07 11:24:00 +0100467#define CP0C4_IE 29
Leon Alraee98c0d12014-07-07 11:23:55 +0100468#define CP0C4_KScrExist 16
Maciej W. Rozycki70409e62014-11-04 15:38:05 +0000469#define CP0C4_MMUExtDef 14
470#define CP0C4_FTLBPageSize 8
471#define CP0C4_FTLBWays 4
472#define CP0C4_FTLBSets 0
473#define CP0C4_MMUSizeExt 0
Maciej W. Rozycki8280b122014-11-04 15:37:17 +0000474 int32_t CP0_Config5;
475 int32_t CP0_Config5_rw_bitmask;
Petar Jovanovicb4dd99a2014-01-17 19:25:57 +0100476#define CP0C5_M 31
477#define CP0C5_K 30
478#define CP0C5_CV 29
479#define CP0C5_EVA 28
480#define CP0C5_MSAEn 27
Yongbok Kimb00c7212015-10-29 15:18:39 +0000481#define CP0C5_XNP 13
Leon Alrae7c979af2015-04-21 16:06:28 +0100482#define CP0C5_UFE 9
483#define CP0C5_FRE 8
Yongbok Kim01bc4352016-02-03 12:31:07 +0000484#define CP0C5_VP 7
Leon Alraefaf1f682014-07-11 16:11:33 +0100485#define CP0C5_SBRI 6
Leon Alrae5204ea72014-09-11 16:28:17 +0100486#define CP0C5_MVH 5
Leon Alraece9782f2015-06-04 17:00:31 +0100487#define CP0C5_LLB 4
Yongbok Kimf6d4dd82016-03-24 15:49:58 +0000488#define CP0C5_MRP 3
Petar Jovanovicb4dd99a2014-01-17 19:25:57 +0100489#define CP0C5_UFR 2
490#define CP0C5_NFExists 0
thse397ee32007-03-23 00:43:28 +0000491 int32_t CP0_Config6;
492 int32_t CP0_Config7;
Yongbok Kimf6d4dd82016-03-24 15:49:58 +0000493 uint64_t CP0_MAAR[MIPS_MAAR_MAX];
494 int32_t CP0_MAARI;
thsead93602007-09-06 00:18:15 +0000495 /* XXX: Maybe make LLAddr per-TC? */
Leon Alrae284b7312015-06-09 17:14:13 +0100496 uint64_t lladdr;
Paul Brook590bc602009-07-09 17:45:17 +0100497 target_ulong llval;
498 target_ulong llnewval;
499 target_ulong llreg;
Leon Alrae284b7312015-06-09 17:14:13 +0100500 uint64_t CP0_LLAddr_rw_bitmask;
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100501 int CP0_LLAddr_shift;
thsfd88b6a2007-05-23 08:24:25 +0000502 target_ulong CP0_WatchLo[8];
503 int32_t CP0_WatchHi[8];
ths9c2149c2007-01-23 22:45:22 +0000504 target_ulong CP0_XContext;
505 int32_t CP0_Framemask;
506 int32_t CP0_Debug;
thsead93602007-09-06 00:18:15 +0000507#define CP0DB_DBD 31
bellard6af0bf92005-07-02 14:58:51 +0000508#define CP0DB_DM 30
509#define CP0DB_LSNM 28
510#define CP0DB_Doze 27
511#define CP0DB_Halt 26
512#define CP0DB_CNT 25
513#define CP0DB_IBEP 24
514#define CP0DB_DBEP 21
515#define CP0DB_IEXI 20
516#define CP0DB_VER 15
517#define CP0DB_DEC 10
518#define CP0DB_SSt 8
519#define CP0DB_DINT 5
520#define CP0DB_DIB 4
521#define CP0DB_DDBS 3
522#define CP0DB_DDBL 2
523#define CP0DB_DBp 1
524#define CP0DB_DSS 0
thsc570fd12006-12-21 01:19:56 +0000525 target_ulong CP0_DEPC;
ths9c2149c2007-01-23 22:45:22 +0000526 int32_t CP0_Performance0;
Leon Alrae0d74a222016-03-25 13:49:36 +0000527 int32_t CP0_ErrCtl;
528#define CP0EC_WST 29
529#define CP0EC_SPR 28
530#define CP0EC_ITC 26
Leon Alrae284b7312015-06-09 17:14:13 +0100531 uint64_t CP0_TagLo;
ths9c2149c2007-01-23 22:45:22 +0000532 int32_t CP0_DataLo;
533 int32_t CP0_TagHi;
534 int32_t CP0_DataHi;
thsc570fd12006-12-21 01:19:56 +0000535 target_ulong CP0_ErrorEPC;
ths9c2149c2007-01-23 22:45:22 +0000536 int32_t CP0_DESAVE;
thsb5dc7732008-06-27 10:02:35 +0000537 /* We waste some space so we can handle shadow registers like TCs. */
538 TCState tcs[MIPS_SHADOW_SET_MAX];
thsf01be152008-09-18 11:57:27 +0000539 CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
Stefan Weil5cbdb3a2012-04-07 09:23:39 +0200540 /* QEMU */
bellard6af0bf92005-07-02 14:58:51 +0000541 int error_code;
Leon Alraeaea14092014-07-07 11:24:01 +0100542#define EXCP_TLB_NOMATCH 0x1
543#define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
bellard6af0bf92005-07-02 14:58:51 +0000544 uint32_t hflags; /* CPU State */
545 /* TMASK defines different execution modes */
Leon Alrae0d74a222016-03-25 13:49:36 +0000546#define MIPS_HFLAG_TMASK 0xF5807FF
Nathan Froyd79ef2c42009-12-08 08:06:22 -0800547#define MIPS_HFLAG_MODE 0x00007 /* execution modes */
ths623a9302007-10-28 19:45:05 +0000548 /* The KSU flags must be the lowest bits in hflags. The flag order
549 must be the same as defined for CP0 Status. This allows to use
550 the bits as the value of mmu_idx. */
Nathan Froyd79ef2c42009-12-08 08:06:22 -0800551#define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
552#define MIPS_HFLAG_UM 0x00002 /* user mode flag */
553#define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
554#define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
555#define MIPS_HFLAG_DM 0x00004 /* Debug mode */
556#define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
557#define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
558#define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
559#define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
thsb8aa4592007-12-30 15:36:58 +0000560 /* True if the MIPS IV COP1X instructions can be used. This also
561 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
562 and RSQRT.D. */
Nathan Froyd79ef2c42009-12-08 08:06:22 -0800563#define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
564#define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
Leon Alrae01f72882014-06-27 08:49:04 +0100565#define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */
Nathan Froyd79ef2c42009-12-08 08:06:22 -0800566#define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
567#define MIPS_HFLAG_M16_SHIFT 10
bellard4ad40f32005-12-05 19:59:36 +0000568 /* If translation is interrupted between the branch instruction and
569 * the delay slot, record what type of branch it is so that we can
570 * resume translation properly. It might be possible to reduce
571 * this from three bits to two. */
Leon Alrae339cd2a2014-07-11 16:11:33 +0100572#define MIPS_HFLAG_BMASK_BASE 0x803800
Nathan Froyd79ef2c42009-12-08 08:06:22 -0800573#define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
574#define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
575#define MIPS_HFLAG_BL 0x01800 /* Likely branch */
576#define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
577 /* Extra flags about the current pending branch. */
Yongbok Kimb231c102014-07-01 17:43:05 +0100578#define MIPS_HFLAG_BMASK_EXT 0x7C000
Nathan Froyd79ef2c42009-12-08 08:06:22 -0800579#define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
580#define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
581#define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
Yongbok Kimb231c102014-07-01 17:43:05 +0100582#define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */
583#define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */
Nathan Froyd79ef2c42009-12-08 08:06:22 -0800584#define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
Jia Liu853c3242012-10-24 22:17:02 +0800585 /* MIPS DSP resources access. */
Yongbok Kimb231c102014-07-01 17:43:05 +0100586#define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */
587#define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */
Petar Jovanovicd2792792014-06-18 17:48:20 +0200588 /* Extra flag about HWREna register. */
Yongbok Kimb231c102014-07-01 17:43:05 +0100589#define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
Leon Alraefaf1f682014-07-11 16:11:33 +0100590#define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
Leon Alrae339cd2a2014-07-11 16:11:33 +0100591#define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */
Yongbok Kime97a3912014-11-01 05:28:35 +0000592#define MIPS_HFLAG_MSA 0x1000000
Leon Alrae7c979af2015-04-21 16:06:28 +0100593#define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */
Leon Alraee117f522015-04-14 10:09:38 +0100594#define MIPS_HFLAG_ELPA 0x4000000
Leon Alrae0d74a222016-03-25 13:49:36 +0000595#define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */
bellard6af0bf92005-07-02 14:58:51 +0000596 target_ulong btarget; /* Jump / branch target */
aurel321ba74fb2009-03-29 01:18:52 +0000597 target_ulong bcond; /* Branch condition (if needed) */
bellarda316d332005-11-20 10:32:34 +0000598
ths7a387ff2006-12-06 20:17:30 +0000599 int SYNCI_Step; /* Address step size for SYNCI */
600 int CCRes; /* Cycle count resolution/divisor */
thsead93602007-09-06 00:18:15 +0000601 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
602 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
thse189e742007-09-24 12:48:00 +0000603 int insn_flags; /* Supported instruction set */
ths7a387ff2006-12-06 20:17:30 +0000604
bellarda316d332005-11-20 10:32:34 +0000605 CPU_COMMON
ths6ae81772006-12-06 17:48:52 +0000606
Andreas Färberf0c3c502013-08-26 21:22:53 +0200607 /* Fields from here on are preserved across CPU reset. */
Blue Swirl51cc2e72009-11-08 12:50:21 +0200608 CPUMIPSMVPContext *mvp;
Paul Brook3c7b48b2010-03-01 04:11:28 +0000609#if !defined(CONFIG_USER_ONLY)
Blue Swirl51cc2e72009-11-08 12:50:21 +0200610 CPUMIPSTLBContext *tlb;
Paul Brook3c7b48b2010-03-01 04:11:28 +0000611#endif
Blue Swirl51cc2e72009-11-08 12:50:21 +0200612
Anthony Liguoric227f092009-10-01 16:12:16 -0500613 const mips_def_t *cpu_model;
ths33ac7f12007-05-31 16:18:58 +0000614 void *irq[8];
Stefan Weil1246b252013-12-01 08:49:47 +0100615 QEMUTimer *timer; /* Internal timer */
Leon Alrae34fa7e82016-03-25 13:49:30 +0000616 MemoryRegion *itc_tag; /* ITC Configuration Tags */
bellard6af0bf92005-07-02 14:58:51 +0000617};
618
Paolo Bonzini416bf932016-03-15 13:49:25 +0100619/**
620 * MIPSCPU:
621 * @env: #CPUMIPSState
622 *
623 * A MIPS CPU.
624 */
625struct MIPSCPU {
626 /*< private >*/
627 CPUState parent_obj;
628 /*< public >*/
629
630 CPUMIPSState env;
631};
632
633static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
634{
635 return container_of(env, MIPSCPU, env);
636}
637
638#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))
639
640#define ENV_OFFSET offsetof(MIPSCPU, env)
641
642#ifndef CONFIG_USER_ONLY
643extern const struct VMStateDescription vmstate_mips_cpu;
644#endif
645
646void mips_cpu_do_interrupt(CPUState *cpu);
647bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
648void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
649 int flags);
650hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
651int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
652int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
653void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
654 int is_write, int is_user, uintptr_t retaddr);
Andreas Färber0f71a702012-04-15 23:29:19 +0200655
Paul Brook3c7b48b2010-03-01 04:11:28 +0000656#if !defined(CONFIG_USER_ONLY)
Avi Kivitya8170e52012-10-23 12:30:10 +0200657int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
ths29929e32007-05-13 13:49:44 +0000658 target_ulong address, int rw, int access_type);
Avi Kivitya8170e52012-10-23 12:30:10 +0200659int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
ths29929e32007-05-13 13:49:44 +0000660 target_ulong address, int rw, int access_type);
Avi Kivitya8170e52012-10-23 12:30:10 +0200661int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
ths29929e32007-05-13 13:49:44 +0000662 target_ulong address, int rw, int access_type);
Blue Swirl895c2d02012-09-02 14:52:59 +0000663void r4k_helper_tlbwi(CPUMIPSState *env);
664void r4k_helper_tlbwr(CPUMIPSState *env);
665void r4k_helper_tlbp(CPUMIPSState *env);
666void r4k_helper_tlbr(CPUMIPSState *env);
Leon Alrae9456c2f2014-07-07 11:24:00 +0100667void r4k_helper_tlbinv(CPUMIPSState *env);
668void r4k_helper_tlbinvf(CPUMIPSState *env);
ths33d68b52007-03-18 00:30:29 +0000669
Andreas Färberc658b942013-05-27 06:49:53 +0200670void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
671 bool is_write, bool is_exec, int unused,
672 unsigned size);
Paul Brook3c7b48b2010-03-01 04:11:28 +0000673#endif
674
Stefan Weil9a78eea2010-10-22 23:03:33 +0200675void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
ths647de6c2007-10-20 19:45:44 +0000676
ths9467d442007-06-03 21:02:38 +0000677#define cpu_exec cpu_mips_exec
ths9467d442007-06-03 21:02:38 +0000678#define cpu_signal_handler cpu_mips_signal_handler
j_mayerc732abe2007-10-12 06:47:46 +0000679#define cpu_list mips_cpu_list
ths9467d442007-06-03 21:02:38 +0000680
Richard Henderson084d0492013-02-10 10:30:44 -0800681extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
682extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
683
ths623a9302007-10-28 19:45:05 +0000684/* MMU modes definitions. We carefully match the indices with our
685 hflags layout. */
j_mayer6ebbf392007-10-14 07:07:08 +0000686#define MMU_MODE0_SUFFIX _kernel
ths623a9302007-10-28 19:45:05 +0000687#define MMU_MODE1_SUFFIX _super
688#define MMU_MODE2_SUFFIX _user
689#define MMU_USER_IDX 2
Benjamin Herrenschmidt97ed5cc2015-08-17 17:34:10 +1000690static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
j_mayer6ebbf392007-10-14 07:07:08 +0000691{
ths623a9302007-10-28 19:45:05 +0000692 return env->hflags & MIPS_HFLAG_KSU;
j_mayer6ebbf392007-10-14 07:07:08 +0000693}
694
Leon Alrae71ca0342015-09-14 13:58:23 +0100695static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
Edgar E. Iglesias138afb02010-08-06 12:21:16 +0200696{
Leon Alrae71ca0342015-09-14 13:58:23 +0100697 return (env->CP0_Status & (1 << CP0St_IE)) &&
698 !(env->CP0_Status & (1 << CP0St_EXL)) &&
699 !(env->CP0_Status & (1 << CP0St_ERL)) &&
700 !(env->hflags & MIPS_HFLAG_DM) &&
Edgar E. Iglesias344eecf2011-08-30 00:44:28 +0200701 /* Note that the TCStatus IXMT field is initialized to zero,
702 and only MT capable cores can set it to one. So we don't
703 need to check for MT capabilities here. */
Leon Alrae71ca0342015-09-14 13:58:23 +0100704 !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
705}
706
707/* Check if there is pending and not masked out interrupt */
708static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
709{
710 int32_t pending;
711 int32_t status;
712 bool r;
Aurelien Jarno4cdc1cd2010-12-25 22:56:32 +0100713
Edgar E. Iglesias138afb02010-08-06 12:21:16 +0200714 pending = env->CP0_Cause & CP0Ca_IP_mask;
715 status = env->CP0_Status & CP0Ca_IP_mask;
716
717 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
718 /* A MIPS configured with a vectorizing external interrupt controller
719 will feed a vector into the Cause pending lines. The core treats
720 the status lines as a vector level, not as indiviual masks. */
721 r = pending > status;
722 } else {
723 /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
724 treats the pending lines as individual interrupt lines, the status
725 lines are individual masks. */
Leon Alrae71ca0342015-09-14 13:58:23 +0100726 r = (pending & status) != 0;
Edgar E. Iglesias138afb02010-08-06 12:21:16 +0200727 }
728 return r;
729}
730
Paolo Bonzini022c62c2012-12-17 18:19:49 +0100731#include "exec/cpu-all.h"
bellard6af0bf92005-07-02 14:58:51 +0000732
733/* Memory access type :
734 * may be needed for precise access rights control and precise exceptions.
735 */
736enum {
737 /* 1 bit to define user level / supervisor access */
738 ACCESS_USER = 0x00,
739 ACCESS_SUPER = 0x01,
740 /* 1 bit to indicate direction */
741 ACCESS_STORE = 0x02,
742 /* Type of instruction that generated the access */
743 ACCESS_CODE = 0x10, /* Code fetch access */
744 ACCESS_INT = 0x20, /* Integer load/store access */
745 ACCESS_FLOAT = 0x30, /* floating point load/store access */
746};
747
748/* Exceptions */
749enum {
750 EXCP_NONE = -1,
751 EXCP_RESET = 0,
752 EXCP_SRESET,
753 EXCP_DSS,
754 EXCP_DINT,
ths14e51cc2007-12-26 19:34:03 +0000755 EXCP_DDBL,
756 EXCP_DDBS,
bellard6af0bf92005-07-02 14:58:51 +0000757 EXCP_NMI,
758 EXCP_MCHECK,
ths14e51cc2007-12-26 19:34:03 +0000759 EXCP_EXT_INTERRUPT, /* 8 */
bellard6af0bf92005-07-02 14:58:51 +0000760 EXCP_DFWATCH,
ths14e51cc2007-12-26 19:34:03 +0000761 EXCP_DIB,
bellard6af0bf92005-07-02 14:58:51 +0000762 EXCP_IWATCH,
763 EXCP_AdEL,
764 EXCP_AdES,
765 EXCP_TLBF,
766 EXCP_IBE,
ths14e51cc2007-12-26 19:34:03 +0000767 EXCP_DBp, /* 16 */
bellard6af0bf92005-07-02 14:58:51 +0000768 EXCP_SYSCALL,
ths14e51cc2007-12-26 19:34:03 +0000769 EXCP_BREAK,
bellard4ad40f32005-12-05 19:59:36 +0000770 EXCP_CpU,
bellard6af0bf92005-07-02 14:58:51 +0000771 EXCP_RI,
772 EXCP_OVERFLOW,
773 EXCP_TRAP,
ths5a5012e2007-05-07 13:55:33 +0000774 EXCP_FPE,
ths14e51cc2007-12-26 19:34:03 +0000775 EXCP_DWATCH, /* 24 */
bellard6af0bf92005-07-02 14:58:51 +0000776 EXCP_LTLBL,
777 EXCP_TLBL,
778 EXCP_TLBS,
779 EXCP_DBE,
thsead93602007-09-06 00:18:15 +0000780 EXCP_THREAD,
ths14e51cc2007-12-26 19:34:03 +0000781 EXCP_MDMX,
782 EXCP_C2E,
783 EXCP_CACHE, /* 32 */
Jia Liu853c3242012-10-24 22:17:02 +0800784 EXCP_DSPDIS,
Yongbok Kime97a3912014-11-01 05:28:35 +0000785 EXCP_MSADIS,
786 EXCP_MSAFPE,
Leon Alrae92ceb442014-07-07 11:23:59 +0100787 EXCP_TLBXI,
788 EXCP_TLBRI,
ths14e51cc2007-12-26 19:34:03 +0000789
Leon Alrae92ceb442014-07-07 11:23:59 +0100790 EXCP_LAST = EXCP_TLBRI,
bellard6af0bf92005-07-02 14:58:51 +0000791};
Paul Brook590bc602009-07-09 17:45:17 +0100792/* Dummy exception for conditional stores. */
793#define EXCP_SC 0x100
bellard6af0bf92005-07-02 14:58:51 +0000794
Edgar E. Iglesiasf2494122011-08-29 23:07:40 +0200795/*
796 * This is an interrnally generated WAKE request line.
797 * It is driven by the CPU itself. Raised when the MT
798 * block wants to wake a VPE from an inactive state and
799 * cleared when VPE goes from active to inactive.
800 */
801#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
802
Peter Crosthwaiteea3e9842015-06-18 10:24:55 -0700803int cpu_mips_exec(CPUState *cpu);
Andreas Färber78ce64f2013-01-20 01:22:25 +0100804void mips_tcg_init(void);
Andreas Färber30bf9422012-05-05 13:33:04 +0200805MIPSCPU *cpu_mips_init(const char *cpu_model);
ths388bb212007-05-13 13:58:00 +0000806int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
bellard6af0bf92005-07-02 14:58:51 +0000807
Eduardo Habkost2994fd92015-02-26 17:37:49 -0300808#define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
Leon Alraebff384a2016-03-15 09:59:35 +0000809bool cpu_supports_cps_smp(const char *cpu_model);
Andreas Färber30bf9422012-05-05 13:33:04 +0200810
Andreas Färberb7e516c2012-05-05 15:43:31 +0200811/* TODO QOM'ify CPU reset and remove */
812void cpu_state_reset(CPUMIPSState *s);
813
thsf9480ff2008-12-20 19:42:14 +0000814/* mips_timer.c */
Andreas Färber7db13fa2012-03-14 01:38:22 +0100815uint32_t cpu_mips_get_random (CPUMIPSState *env);
816uint32_t cpu_mips_get_count (CPUMIPSState *env);
817void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
818void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
819void cpu_mips_start_count(CPUMIPSState *env);
820void cpu_mips_stop_count(CPUMIPSState *env);
thsf9480ff2008-12-20 19:42:14 +0000821
Aurelien Jarno5dc5d9f2010-07-25 16:51:29 +0200822/* mips_int.c */
Andreas Färber7db13fa2012-03-14 01:38:22 +0100823void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
Aurelien Jarno5dc5d9f2010-07-25 16:51:29 +0200824
thsf9480ff2008-12-20 19:42:14 +0000825/* helper.c */
Andreas Färber75104542013-08-26 03:01:33 +0200826int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
827 int mmu_idx);
Paul Brook3c7b48b2010-03-01 04:11:28 +0000828#if !defined(CONFIG_USER_ONLY)
Andreas Färber7db13fa2012-03-14 01:38:22 +0100829void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
Avi Kivitya8170e52012-10-23 12:30:10 +0200830hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
Aurelien Jarnoc36bbb22010-02-06 17:02:45 +0100831 int rw);
Paul Brook3c7b48b2010-03-01 04:11:28 +0000832#endif
Kwok Cheung Yeung1239b472013-05-17 14:51:21 -0700833target_ulong exception_resume_pc (CPUMIPSState *env);
thsf9480ff2008-12-20 19:42:14 +0000834
Yongbok Kimb7651e92014-11-01 05:28:37 +0000835/* op_helper.c */
836extern unsigned int ieee_rm[];
837int ieee_ex_to_mips(int xcpt);
838
Maciej W. Rozyckibb962382014-12-02 17:02:38 +0000839static inline void restore_rounding_mode(CPUMIPSState *env)
840{
841 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
842 &env->active_fpu.fp_status);
843}
844
845static inline void restore_flush_mode(CPUMIPSState *env)
846{
847 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
848 &env->active_fpu.fp_status);
849}
850
Leon Alrae64451112015-02-20 13:07:45 +0000851static inline void restore_fp_status(CPUMIPSState *env)
852{
853 restore_rounding_mode(env);
854 restore_flush_mode(env);
855}
856
857static inline void restore_msa_fp_status(CPUMIPSState *env)
858{
859 float_status *status = &env->active_tc.msa_fp_status;
860 int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
861 bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
862
863 set_float_rounding_mode(ieee_rm[rounding_mode], status);
864 set_flush_to_zero(flush_to_zero, status);
865 set_flush_inputs_to_zero(flush_to_zero, status);
866}
867
Leon Alraee117f522015-04-14 10:09:38 +0100868static inline void restore_pamask(CPUMIPSState *env)
869{
870 if (env->hflags & MIPS_HFLAG_ELPA) {
871 env->PAMask = (1ULL << env->PABITS) - 1;
872 } else {
873 env->PAMask = PAMASK_BASE;
874 }
875}
876
Andreas Färber7db13fa2012-03-14 01:38:22 +0100877static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
Emilio G. Cota89fee742016-04-07 13:19:22 -0400878 target_ulong *cs_base, uint32_t *flags)
aliguori6b917542008-11-18 19:46:41 +0000879{
880 *pc = env->active_tc.PC;
881 *cs_base = 0;
Petar Jovanovicd2792792014-06-18 17:48:20 +0200882 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
883 MIPS_HFLAG_HWRENA_ULR);
aliguori6b917542008-11-18 19:46:41 +0000884}
885
Andreas Färber7db13fa2012-03-14 01:38:22 +0100886static inline int mips_vpe_active(CPUMIPSState *env)
Edgar E. Iglesiasf2494122011-08-29 23:07:40 +0200887{
888 int active = 1;
889
890 /* Check that the VPE is enabled. */
891 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
892 active = 0;
893 }
Dong Xu Wang4abf79a2011-11-22 18:06:21 +0800894 /* Check that the VPE is activated. */
Edgar E. Iglesiasf2494122011-08-29 23:07:40 +0200895 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
896 active = 0;
897 }
898
899 /* Now verify that there are active thread contexts in the VPE.
900
901 This assumes the CPU model will internally reschedule threads
902 if the active one goes to sleep. If there are no threads available
903 the active one will be in a sleeping state, and we can turn off
904 the entire VPE. */
905 if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
906 /* TC is not activated. */
907 active = 0;
908 }
909 if (env->active_tc.CP0_TCHalt & 1) {
910 /* TC is in halt state. */
911 active = 0;
912 }
913
914 return active;
915}
916
Yongbok Kim01bc4352016-02-03 12:31:07 +0000917static inline int mips_vp_active(CPUMIPSState *env)
918{
919 CPUState *other_cs = first_cpu;
920
921 /* Check if the VP disabled other VPs (which means the VP is enabled) */
922 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
923 return 1;
924 }
925
926 /* Check if the virtual processor is disabled due to a DVP */
927 CPU_FOREACH(other_cs) {
928 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
929 if ((&other_cpu->env != env) &&
930 ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
931 return 0;
932 }
933 }
934 return 1;
935}
936
Maciej W. Rozycki03e6e502012-06-08 02:04:40 +0100937static inline void compute_hflags(CPUMIPSState *env)
938{
939 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
940 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
Leon Alraefaf1f682014-07-11 16:11:33 +0100941 MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
Leon Alraee117f522015-04-14 10:09:38 +0100942 MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
943 MIPS_HFLAG_ELPA);
Maciej W. Rozycki03e6e502012-06-08 02:04:40 +0100944 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
945 !(env->CP0_Status & (1 << CP0St_ERL)) &&
946 !(env->hflags & MIPS_HFLAG_DM)) {
947 env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
948 }
949#if defined(TARGET_MIPS64)
Maciej W. Rozyckid9224452014-12-05 18:47:58 +0000950 if ((env->insn_flags & ISA_MIPS3) &&
951 (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
952 (env->CP0_Status & (1 << CP0St_PX)) ||
953 (env->CP0_Status & (1 << CP0St_UX)))) {
Maciej W. Rozycki03e6e502012-06-08 02:04:40 +0100954 env->hflags |= MIPS_HFLAG_64;
955 }
Leon Alrae01f72882014-06-27 08:49:04 +0100956
Maciej W. Rozyckic48245f2014-11-19 17:29:00 +0000957 if (!(env->insn_flags & ISA_MIPS3)) {
Leon Alrae01f72882014-06-27 08:49:04 +0100958 env->hflags |= MIPS_HFLAG_AWRAP;
Maciej W. Rozyckic48245f2014-11-19 17:29:00 +0000959 } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
960 !(env->CP0_Status & (1 << CP0St_UX))) {
961 env->hflags |= MIPS_HFLAG_AWRAP;
962 } else if (env->insn_flags & ISA_MIPS64R6) {
Leon Alrae01f72882014-06-27 08:49:04 +0100963 /* Address wrapping for Supervisor and Kernel is specified in R6 */
964 if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
965 !(env->CP0_Status & (1 << CP0St_SX))) ||
966 (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
967 !(env->CP0_Status & (1 << CP0St_KX)))) {
968 env->hflags |= MIPS_HFLAG_AWRAP;
969 }
Maciej W. Rozycki03e6e502012-06-08 02:04:40 +0100970 }
971#endif
Leon Alraea63eb0c2014-07-11 16:11:34 +0100972 if (((env->CP0_Status & (1 << CP0St_CU0)) &&
973 !(env->insn_flags & ISA_MIPS32R6)) ||
Maciej W. Rozycki03e6e502012-06-08 02:04:40 +0100974 !(env->hflags & MIPS_HFLAG_KSU)) {
975 env->hflags |= MIPS_HFLAG_CP0;
976 }
977 if (env->CP0_Status & (1 << CP0St_CU1)) {
978 env->hflags |= MIPS_HFLAG_FPU;
979 }
980 if (env->CP0_Status & (1 << CP0St_FR)) {
981 env->hflags |= MIPS_HFLAG_F64;
982 }
Leon Alraefaf1f682014-07-11 16:11:33 +0100983 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
984 (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
985 env->hflags |= MIPS_HFLAG_SBRI;
986 }
Jia Liu853c3242012-10-24 22:17:02 +0800987 if (env->insn_flags & ASE_DSPR2) {
988 /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
989 so enable to access DSPR2 resources. */
990 if (env->CP0_Status & (1 << CP0St_MX)) {
991 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
992 }
993
994 } else if (env->insn_flags & ASE_DSP) {
995 /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
996 so enable to access DSP resources. */
997 if (env->CP0_Status & (1 << CP0St_MX)) {
998 env->hflags |= MIPS_HFLAG_DSP;
999 }
1000
1001 }
Maciej W. Rozycki03e6e502012-06-08 02:04:40 +01001002 if (env->insn_flags & ISA_MIPS32R2) {
1003 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
1004 env->hflags |= MIPS_HFLAG_COP1X;
1005 }
1006 } else if (env->insn_flags & ISA_MIPS32) {
1007 if (env->hflags & MIPS_HFLAG_64) {
1008 env->hflags |= MIPS_HFLAG_COP1X;
1009 }
1010 } else if (env->insn_flags & ISA_MIPS4) {
1011 /* All supported MIPS IV CPUs use the XX (CU3) to enable
1012 and disable the MIPS IV extensions to the MIPS III ISA.
1013 Some other MIPS IV CPUs ignore the bit, so the check here
1014 would be too restrictive for them. */
Peter Maydellf45cb2f2014-03-17 16:00:34 +00001015 if (env->CP0_Status & (1U << CP0St_CU3)) {
Maciej W. Rozycki03e6e502012-06-08 02:04:40 +01001016 env->hflags |= MIPS_HFLAG_COP1X;
1017 }
1018 }
Yongbok Kime97a3912014-11-01 05:28:35 +00001019 if (env->insn_flags & ASE_MSA) {
1020 if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
1021 env->hflags |= MIPS_HFLAG_MSA;
1022 }
1023 }
Leon Alrae7c979af2015-04-21 16:06:28 +01001024 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
1025 if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
1026 env->hflags |= MIPS_HFLAG_FRE;
1027 }
1028 }
Leon Alraee117f522015-04-14 10:09:38 +01001029 if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
1030 if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
1031 env->hflags |= MIPS_HFLAG_ELPA;
1032 }
1033 }
Maciej W. Rozycki03e6e502012-06-08 02:04:40 +01001034}
1035
Paolo Bonzinie6623d82015-12-15 13:49:17 +01001036void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global);
1037void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
1038void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
1039void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
Maciej W. Rozycki81a423e2014-11-10 13:46:35 +00001040
Paolo Bonzini33c11872016-03-15 16:58:45 +01001041void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
1042 int error_code, uintptr_t pc);
Pavel Dovgaluk9c708c72015-07-10 12:57:08 +03001043
1044static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
1045 uint32_t exception,
1046 uintptr_t pc)
1047{
1048 do_raise_exception_err(env, exception, 0, pc);
1049}
1050
bellard6af0bf92005-07-02 14:58:51 +00001051#endif /* !defined (__MIPS_CPU_H__) */