commit b00c72180c36510bf9b124e190bd520e3b7e1358
author Yongbok Kim <yongbok.kim@imgtec.com> Thu Oct 29 15:18:39 2015 +0000
committer Leon Alrae <leon.alrae@imgtec.com> Fri Oct 30 14:35:52 2015 +0000
tree f5a64bd037c0b5577e406da3a7d17f1fc1f5080d
parent ca2f6bbbce32b7e1ba4fdaf54165ab0dee47a3a5

target-mips: add PC, XNP reg numbers to RDHWR

Add Performance Counter (4) and XNP (5) register numbers to RDHWR.
Add check_hwrena() to simplify access control checkings.
Add RDHWR support to microMIPS R6.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>

target-mips/cpu.h

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index c68681d..fa919c1 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -469,6 +469,7 @@
 #define CP0C5_CV         29
 #define CP0C5_EVA        28
 #define CP0C5_MSAEn      27
+#define CP0C5_XNP        13
 #define CP0C5_UFE        9
 #define CP0C5_FRE        8
 #define CP0C5_SBRI       6