commit e189e7486867e36c35f99cbac27d503ce4e7c71d
author ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Mon Sep 24 12:48:00 2007 +0000
committer ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Mon Sep 24 12:48:00 2007 +0000
tree ac7f7d77ee235b50b3db039b78d6965f807daca7
parent 92a34c10b595ae01ff55c385b9867363ac91e0eb

Per-CPU instruction decoding implementation, by Aurelien Jarno.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3228 c046a42c-6fe2-441c-8c8c-71466251a162

target-mips/cpu.h

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index f8b4b18..f8299ad 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -441,6 +441,7 @@
     int CCRes; /* Cycle count resolution/divisor */
     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
+    int insn_flags; /* Supported instruction set */
 
 #ifdef CONFIG_USER_ONLY
     target_ulong tls_value;