- 954886e hw/riscv: virt: Add optional ACLINT support to virt machine by Anup Patel · 3 years, 6 months ago
- ea6eaa0 sifive_u: Connect the SiFive PWM device by Alistair Francis · 3 years, 5 months ago
- bb7e0cd hw/riscv: opentitan: Add the flash alias by Alistair Francis · 3 years, 7 months ago
- 5ee2576 hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri by Alistair Francis · 3 years, 7 months ago
- 3ef6434 hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer by Alistair Francis · 3 years, 8 months ago
- a0acd0a hw/riscv: Use macros for BIOS image names by Bin Meng · 3 years, 10 months ago
- d4cad54 hw/opentitan: Update the interrupt layout by Alistair Francis · 3 years, 11 months ago
- 8a2aca3 hw/riscv: Connect Shakti UART to Shakti platform by Vijai Kumar K · 3 years, 11 months ago
- 7a261ba riscv: Add initial support for Shakti C machine by Vijai Kumar K · 3 years, 11 months ago
- d6150ac hw/riscv: microchip_pfsoc: Map EMMC/SD mux register by Bin Meng · 4 years ago
- 0489348 hw/riscv: Add fw_cfg support to virt by Asherah Connor · 4 years ago
- c65d708 hw/riscv: migrate fdt field to generic MachineState by Alex Bennée · 4 years ago
- 8e3c886 hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value by Bin Meng · 4 years, 1 month ago
- 722f135 hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card by Bin Meng · 4 years, 1 month ago
- 145b299 hw/riscv: sifive_u: Add QSPI0 controller and connect a flash by Bin Meng · 4 years, 1 month ago
- a8259b5 riscv: Pass RISCVHartArrayState by pointer by Alistair Francis · 4 years, 1 month ago
- d31e970 riscv/opentitan: Update the OpenTitan memory layout by Alistair Francis · 4 years, 2 months ago
- 3ed2b8a hw/riscv: Use the CPU to determine if 32-bit by Alistair Francis · 4 years, 2 months ago
- 7893677 hw/riscv: boot: Remove compile time XLEN checks by Alistair Francis · 4 years, 2 months ago
- 09fe171 riscv: virt: Remove target macro conditionals by Alistair Francis · 4 years, 2 months ago
- dc4d4aa riscv: spike: Remove target macro conditionals by Alistair Francis · 4 years, 2 months ago
- dfc973e hw/riscv: microchip_pfsoc: add QSPI NOR flash by Vitaly Wool · 4 years, 3 months ago
- 90742c5 hw/riscv: microchip_pfsoc: Hook the I2C1 controller by Bin Meng · 4 years, 4 months ago
- f03100d hw/riscv: microchip_pfsoc: Correct DDR memory map by Bin Meng · 4 years, 4 months ago
- 27c22b2 hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 by Bin Meng · 4 years, 4 months ago
- cdd58c7 hw/riscv: microchip_pfsoc: Connect the SYSREG module by Bin Meng · 4 years, 4 months ago
- e35d617 hw/riscv: microchip_pfsoc: Connect the IOSCB module by Bin Meng · 4 years, 4 months ago
- 933f73f hw/riscv: microchip_pfsoc: Connect DDR memory controller modules by Bin Meng · 4 years, 4 months ago
- 38bc4e3 hw/riscv: Load the kernel after the firmware by Alistair Francis · 4 years, 4 months ago
- c407784 hw/riscv: Add a riscv_is_32_bit() function by Alistair Francis · 4 years, 4 months ago
- e66c531 hw/riscv: Return the end address of the loaded firmware by Alistair Francis · 4 years, 4 months ago
- 099be03 hw/riscv: sifive_u: Allow specifying the CPU by Alistair Francis · 4 years, 4 months ago
- 8063396 Use OBJECT_DECLARE_SIMPLE_TYPE when possible by Eduardo Habkost · 4 years, 5 months ago
- 13b8c35 sifive_u: Rename memmap enum constants by Eduardo Habkost · 4 years, 5 months ago
- 5488f27 sifive_e: Rename memmap enum constants by Eduardo Habkost · 4 years, 5 months ago
- f00f57f Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging by Peter Maydell · 4 years, 5 months ago
- a4b8460 hw/riscv: Move sifive_test model to hw/misc by Bin Meng · 4 years, 6 months ago
- b609b7e hw/riscv: Move sifive_uart model to hw/char by Bin Meng · 4 years, 6 months ago
- 70eb9f9 hw/riscv: Move riscv_htif model to hw/char by Bin Meng · 4 years, 6 months ago
- 84fcf3c hw/riscv: Move sifive_plic model to hw/intc by Bin Meng · 4 years, 6 months ago
- 406fafd hw/riscv: Move sifive_clint model to hw/intc by Bin Meng · 4 years, 6 months ago
- 4921a0c hw/riscv: Move sifive_gpio model to hw/gpio by Bin Meng · 4 years, 6 months ago
- 0fa9e32 hw/riscv: Move sifive_u_otp model to hw/misc by Bin Meng · 4 years, 6 months ago
- 9fe640a hw/riscv: Move sifive_u_prci model to hw/misc by Bin Meng · 4 years, 6 months ago
- 89ece6f hw/riscv: Move sifive_e_prci model to hw/misc by Bin Meng · 4 years, 6 months ago
- 834e027 hw/riscv: sifive_u: Connect a DMA controller by Bin Meng · 4 years, 6 months ago
- a47ef6e hw/riscv: clint: Avoid using hard-coded timebase frequency by Bin Meng · 4 years, 6 months ago
- ce908a2 hw/riscv: microchip_pfsoc: Hook GPIO controllers by Bin Meng · 4 years, 6 months ago
- 47374b0 hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs by Bin Meng · 4 years, 6 months ago
- 7124e27 hw/riscv: microchip_pfsoc: Connect a DMA controller by Bin Meng · 4 years, 6 months ago
- 898dc00 hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card by Bin Meng · 4 years, 6 months ago
- 8f2ac39 hw/riscv: microchip_pfsoc: Connect 5 MMUARTs by Bin Meng · 4 years, 6 months ago
- 56f6e31 hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board by Bin Meng · 4 years, 6 months ago
- 4100d5e hw/riscv: hart: Add a new 'resetvec' property by Bin Meng · 4 years, 6 months ago
- 8110fa1 Use DECLARE_*CHECKER* macros by Eduardo Habkost · 4 years, 6 months ago
- db1015e Move QOM typedefs and add missing includes by Eduardo Habkost · 4 years, 6 months ago
- 30c717c opentitan: Rename memmap enum constants by Eduardo Habkost · 4 years, 6 months ago
- 18df0b4 hw/riscv: virt: Allow creating multiple NUMA sockets by Anup Patel · 4 years, 9 months ago
- a717279 hw/riscv: spike: Allow creating multiple NUMA sockets by Anup Patel · 4 years, 9 months ago
- 83fcaef hw/riscv: Add helpers for RISC-V multi-socket NUMA machines by Anup Patel · 4 years, 9 months ago
- c9270e1 hw/riscv: Allow creating multiple instances of PLIC by Anup Patel · 4 years, 9 months ago
- 3bf03f0 hw/riscv: Allow creating multiple instances of CLINT by Anup Patel · 4 years, 9 months ago
- 6eaf9cf hw/riscv: sifive_u: Add a dummy L2 cache controller device by Bin Meng · 4 years, 7 months ago
- dc144fe riscv: Add opensbi firmware dynamic support by Atish Patra · 4 years, 8 months ago
- 66b1205 RISC-V: Copy the fdt in dram instead of ROM by Atish Patra · 4 years, 8 months ago
- 43cf723 riscv: Unify Qemu's reset vector code path by Atish Patra · 4 years, 8 months ago
- 3eaea6e hw/riscv: sifive_u: Add a dummy DDR memory controller device by Bin Meng · 4 years, 8 months ago
- 17aad9f hw/riscv: sifive_u: Support different boot source per MSEL pin state by Bin Meng · 4 years, 8 months ago
- cfa3263 hw/riscv: sifive_u: Add a new property msel for MSEL pin state by Bin Meng · 4 years, 8 months ago
- 8a88b9f hw/riscv: sifive_u: Hook a GPIO controller by Bin Meng · 4 years, 8 months ago
- 4bb216f hw/riscv: sifive_gpio: Add a new 'ngpio' property by Bin Meng · 4 years, 8 months ago
- 2e30ccb hw/riscv: sifive_gpio: Clean up the codes by Bin Meng · 4 years, 8 months ago
- cc41126 riscv/opentitan: Connect the UART device by Alistair Francis · 4 years, 10 months ago
- b9fc513 riscv/opentitan: Connect the PLIC device by Alistair Francis · 4 years, 10 months ago
- 5a84206 sifive_e: Support the revB machine by Alistair Francis · 4 years, 9 months ago
- 589b1be riscv: Fix type of SiFive[EU]SocState, member parent_obj by Markus Armbruster · 4 years, 8 months ago
- fe0fe47 riscv: Initial commit of OpenTitan machine by Alistair Francis · 4 years, 10 months ago
- 757e99b riscv/boot: Add a missing header include by Alistair Francis · 4 years, 10 months ago
- 0869490 riscv: sifive_e: Manually define the machine by Alistair Francis · 4 years, 9 months ago
- 26cd036 hw/riscv: spike: Remove deprecated ISA specific machines by Alistair Francis · 4 years, 10 months ago
- 02777ac hw/riscv: Add optional symbol callback ptr to riscv_load_firmware() by Anup Patel · 4 years, 10 months ago
- 3ca109c riscv/sifive_u: Add a serial property to the sifive_u machine by Bin Meng · 5 years ago
- fda5b00 riscv/sifive_u: Add a serial property to the sifive_u SoC by Alistair Francis · 5 years ago
- 5f3616c hw/riscv: Provide rdtime callback for TCG in CLINT emulation by Anup Patel · 5 years ago
- 67b5ef3 riscv: virt: Use Goldfish RTC device by Anup Patel · 5 years ago
- 6478dd7 hw/riscv: Add optional symbol callback ptr to riscv_load_kernel() by Zhuang, Siwei (Data61, Kensington NSW) · 5 years ago
- 71eb522 riscv/virt: Add the PFlash CFI01 device by Alistair Francis · 5 years ago
- cdfc19e riscv/virt: Manually define the machine by Alistair Francis · 5 years ago
- fc41ae2 riscv/sifive_u: Add the start-in-flash property by Alistair Francis · 5 years ago
- 687caef riscv/sifive_u: Manually define the machine by Alistair Francis · 5 years ago
- 1b3a230 riscv/sifive_u: Add QSPI memory region by Alistair Francis · 5 years ago
- a6902ef riscv/sifive_u: Add L2-LIM cache memory by Alistair Francis · 5 years ago
- 7ae0537 riscv: hw: Drop "clock-frequency" property of cpu nodes by Bin Meng · 5 years ago
- 81e9437 riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet by Bin Meng · 5 years ago
- 7b6bb66 riscv: sifive_u: Fix broken GEM support by Bin Meng · 5 years ago
- 5461c4f riscv: sifive_u: Instantiate OTP memory with a serial number by Bin Meng · 5 years ago
- 9fb45c6 riscv: sifive: Implement a model for SiFive FU540 OTP by Bin Meng · 5 years ago
- 4b55bc2 riscv: sifive_u: Update UART base addresses and IRQs by Bin Meng · 5 years ago
- 806c64b riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes by Bin Meng · 5 years ago
- af14c84 riscv: sifive_u: Add PRCI block to the SoC by Bin Meng · 5 years ago