89ece6f76f089bc415fc4b8c78f7dbe74113380c - qemu

commit	89ece6f76f089bc415fc4b8c78f7dbe74113380c	[log] [tgz]
author	Bin Meng <bin.meng@windriver.com>	Thu Sep 03 18:40:12 2020 +0800
committer	Alistair Francis <alistair.francis@wdc.com>	Wed Sep 09 15:54:19 2020 -0700
tree	bbebaf8350b1b2ca6d9331782dd7d6b544b853c9
parent	834e027a3452e1c139c5400cae550c6c5a340b28 [diff]

hw/riscv: Move sifive_e_prci model to hw/misc

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_e_prci model to hw/misc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

hw/misc/Kconfig[diff]
hw/misc/meson.build[diff]
hw/misc/sifive_e_prci.c[Renamed from hw/riscv/sifive_e_prci.c - diff]
hw/riscv/Kconfig[diff]
hw/riscv/meson.build[diff]
hw/riscv/sifive_e.c[diff]
include/hw/misc/sifive_e_prci.h[Renamed from include/hw/riscv/sifive_e_prci.h - diff]

7 files changed

tree: bbebaf8350b1b2ca6d9331782dd7d6b544b853c9