b609b7e3199912e16ef3b0447823f21fed73597e - qemu

commit	b609b7e3199912e16ef3b0447823f21fed73597e	[log] [tgz]
author	Bin Meng <bin.meng@windriver.com>	Thu Sep 03 18:40:19 2020 +0800
committer	Alistair Francis <alistair.francis@wdc.com>	Wed Sep 09 15:54:19 2020 -0700
tree	a4996e2869a356811e641d243f53347b26117106
parent	70eb9f9cd1c0b519b31df8ab08ee2198b0e16176 [diff]

hw/riscv: Move sifive_uart model to hw/char

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

hw/char/Kconfig[diff]
hw/char/meson.build[diff]
hw/char/sifive_uart.c[Renamed from hw/riscv/sifive_uart.c - diff]
hw/riscv/Kconfig[diff]
hw/riscv/meson.build[diff]
hw/riscv/sifive_e.c[diff]
hw/riscv/sifive_u.c[diff]
include/hw/char/sifive_uart.h[Renamed from include/hw/riscv/sifive_uart.h - diff]

8 files changed

tree: a4996e2869a356811e641d243f53347b26117106