tree a4996e2869a356811e641d243f53347b26117106
parent 70eb9f9cd1c0b519b31df8ab08ee2198b0e16176
author Bin Meng <bin.meng@windriver.com> 1599129619 +0800
committer Alistair Francis <alistair.francis@wdc.com> 1599692059 -0700

hw/riscv: Move sifive_uart model to hw/char

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>