406fafd5d0f9a1c6a365ff1733c26a043b1c4877 - qemu

commit	406fafd5d0f9a1c6a365ff1733c26a043b1c4877	[log] [tgz]
author	Bin Meng <bin.meng@windriver.com>	Thu Sep 03 18:40:16 2020 +0800
committer	Alistair Francis <alistair.francis@wdc.com>	Wed Sep 09 15:54:19 2020 -0700
tree	ee4ed77217e62a3d3a8c185e8eda59ff2a138c35
parent	4921a0ce86cecd03e6918832673db79de62e6fe1 [diff]

hw/riscv: Move sifive_clint model to hw/intc

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

hw/intc/Kconfig[diff]
hw/intc/meson.build[diff]
hw/intc/sifive_clint.c[Renamed from hw/riscv/sifive_clint.c - diff]
hw/riscv/Kconfig[diff]
hw/riscv/meson.build[diff]
hw/riscv/microchip_pfsoc.c[diff]
hw/riscv/sifive_e.c[diff]
hw/riscv/sifive_u.c[diff]
hw/riscv/spike.c[diff]
hw/riscv/virt.c[diff]
include/hw/intc/sifive_clint.h[Renamed from include/hw/riscv/sifive_clint.h - diff]

11 files changed

tree: ee4ed77217e62a3d3a8c185e8eda59ff2a138c35