blob: 872456171f8e094bcfc3eddc27d8ffdd9ceb40cf [file] [log] [blame]
bellard79aceca2003-11-23 14:55:54 +00001/*
bellard3fc6c082005-07-02 20:59:34 +00002 * PowerPC emulation cpu definitions for qemu.
ths5fafdf22007-09-16 21:08:06 +00003 *
j_mayer76a66252007-03-07 08:32:30 +00004 * Copyright (c) 2003-2007 Jocelyn Mayer
bellard79aceca2003-11-23 14:55:54 +00005 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000017 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard79aceca2003-11-23 14:55:54 +000018 */
19#if !defined (__CPU_PPC_H__)
20#define __CPU_PPC_H__
21
bellard3fc6c082005-07-02 20:59:34 +000022#include "config.h"
Stefan Weil9a78eea2010-10-22 23:03:33 +020023#include "qemu-common.h"
bellard3fc6c082005-07-02 20:59:34 +000024
j_mayera4f30712007-11-17 21:14:09 +000025//#define PPC_EMULATE_32BITS_HYPV
26
j_mayer76a66252007-03-07 08:32:30 +000027#if defined (TARGET_PPC64)
j_mayer3cd7d1d2007-11-12 01:56:18 +000028/* PowerPC 64 definitions */
j_mayerd9d72102007-09-18 11:17:30 +000029#define TARGET_LONG_BITS 64
j_mayer35cdaad2007-04-24 06:50:21 +000030#define TARGET_PAGE_BITS 12
j_mayer3cd7d1d2007-11-12 01:56:18 +000031
Greg Kurz7826c2b2014-06-24 19:51:19 +020032#define TARGET_IS_BIENDIAN 1
33
Richard Henderson52705892010-03-10 14:33:23 -080034/* Note that the official physical address space bits is 62-M where M
35 is implementation dependent. I've not looked up M for the set of
36 cpus we emulate at the system level. */
37#define TARGET_PHYS_ADDR_SPACE_BITS 62
38
39/* Note that the PPC environment architecture talks about 80 bit virtual
40 addresses, with segmentation. Obviously that's not all visible to a
41 single process, which is all we're concerned with here. */
42#ifdef TARGET_ABI32
43# define TARGET_VIRT_ADDR_SPACE_BITS 32
44#else
45# define TARGET_VIRT_ADDR_SPACE_BITS 64
46#endif
47
David Gibson81762d62011-04-01 15:15:08 +110048#define TARGET_PAGE_BITS_16M 24
49
j_mayer3cd7d1d2007-11-12 01:56:18 +000050#else /* defined (TARGET_PPC64) */
51/* PowerPC 32 definitions */
j_mayerd9d72102007-09-18 11:17:30 +000052#define TARGET_LONG_BITS 32
j_mayer3cd7d1d2007-11-12 01:56:18 +000053
54#if defined(TARGET_PPCEMB)
55/* Specific definitions for PowerPC embedded */
56/* BookE have 36 bits physical address space */
j_mayer3cd7d1d2007-11-12 01:56:18 +000057#if defined(CONFIG_USER_ONLY)
58/* It looks like a lot of Linux programs assume page size
59 * is 4kB long. This is evil, but we have to deal with it...
60 */
j_mayer35cdaad2007-04-24 06:50:21 +000061#define TARGET_PAGE_BITS 12
j_mayer3cd7d1d2007-11-12 01:56:18 +000062#else /* defined(CONFIG_USER_ONLY) */
63/* Pages can be 1 kB small */
64#define TARGET_PAGE_BITS 10
65#endif /* defined(CONFIG_USER_ONLY) */
66#else /* defined(TARGET_PPCEMB) */
67/* "standard" PowerPC 32 definitions */
68#define TARGET_PAGE_BITS 12
69#endif /* defined(TARGET_PPCEMB) */
70
Alexander Graf8b242eb2011-10-18 01:46:08 +020071#define TARGET_PHYS_ADDR_SPACE_BITS 36
Richard Henderson52705892010-03-10 14:33:23 -080072#define TARGET_VIRT_ADDR_SPACE_BITS 32
73
j_mayer3cd7d1d2007-11-12 01:56:18 +000074#endif /* defined (TARGET_PPC64) */
bellard3cf1e032004-01-24 15:19:09 +000075
Andreas Färber9349b4f2012-03-14 01:38:32 +010076#define CPUArchState struct CPUPPCState
pbrookc2764712009-03-07 15:24:59 +000077
Paolo Bonzini022c62c2012-12-17 18:19:49 +010078#include "exec/cpu-defs.h"
bellard79aceca2003-11-23 14:55:54 +000079
Paolo Bonzini6b4c3052012-10-24 13:12:00 +020080#include "fpu/softfloat.h"
bellard4ecc3192005-03-13 17:01:22 +000081
bellard1fddef42005-04-17 19:16:13 +000082#define TARGET_HAS_ICE 1
83
blueswir17f70c932009-03-13 21:16:24 +000084#if defined (TARGET_PPC64)
j_mayer76a66252007-03-07 08:32:30 +000085#define ELF_MACHINE EM_PPC64
86#else
87#define ELF_MACHINE EM_PPC
88#endif
ths9042c0e2006-12-23 14:18:40 +000089
bellard3fc6c082005-07-02 20:59:34 +000090/*****************************************************************************/
j_mayera750fc02007-09-26 23:54:22 +000091/* MMU model */
Anthony Liguoric227f092009-10-01 16:12:16 -050092typedef enum powerpc_mmu_t powerpc_mmu_t;
93enum powerpc_mmu_t {
j_mayeradd78952007-11-19 11:41:10 +000094 POWERPC_MMU_UNKNOWN = 0x00000000,
j_mayera750fc02007-09-26 23:54:22 +000095 /* Standard 32 bits PowerPC MMU */
j_mayeradd78952007-11-19 11:41:10 +000096 POWERPC_MMU_32B = 0x00000001,
j_mayera750fc02007-09-26 23:54:22 +000097 /* PowerPC 6xx MMU with software TLB */
j_mayeradd78952007-11-19 11:41:10 +000098 POWERPC_MMU_SOFT_6xx = 0x00000002,
j_mayera750fc02007-09-26 23:54:22 +000099 /* PowerPC 74xx MMU with software TLB */
j_mayeradd78952007-11-19 11:41:10 +0000100 POWERPC_MMU_SOFT_74xx = 0x00000003,
j_mayera750fc02007-09-26 23:54:22 +0000101 /* PowerPC 4xx MMU with software TLB */
j_mayeradd78952007-11-19 11:41:10 +0000102 POWERPC_MMU_SOFT_4xx = 0x00000004,
j_mayera750fc02007-09-26 23:54:22 +0000103 /* PowerPC 4xx MMU with software TLB and zones protections */
j_mayeradd78952007-11-19 11:41:10 +0000104 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
j_mayerb4095fe2007-11-17 22:42:36 +0000105 /* PowerPC MMU in real mode only */
j_mayeradd78952007-11-19 11:41:10 +0000106 POWERPC_MMU_REAL = 0x00000006,
j_mayerb4095fe2007-11-17 22:42:36 +0000107 /* Freescale MPC8xx MMU model */
j_mayeradd78952007-11-19 11:41:10 +0000108 POWERPC_MMU_MPC8xx = 0x00000007,
j_mayera750fc02007-09-26 23:54:22 +0000109 /* BookE MMU model */
j_mayeradd78952007-11-19 11:41:10 +0000110 POWERPC_MMU_BOOKE = 0x00000008,
Alexander Graf01662f32011-04-30 23:34:58 +0200111 /* BookE 2.06 MMU model */
112 POWERPC_MMU_BOOKE206 = 0x00000009,
j_mayerfaadf502007-11-03 13:37:12 +0000113 /* PowerPC 601 MMU model (specific BATs format) */
j_mayeradd78952007-11-19 11:41:10 +0000114 POWERPC_MMU_601 = 0x0000000A,
j_mayer00af6852007-10-03 01:05:39 +0000115#if defined(TARGET_PPC64)
j_mayeradd78952007-11-19 11:41:10 +0000116#define POWERPC_MMU_64 0x00010000
David Gibsoncdaee002011-04-01 15:15:18 +1100117#define POWERPC_MMU_1TSEG 0x00020000
David Gibsonf80872e2013-03-12 00:31:47 +0000118#define POWERPC_MMU_AMR 0x00040000
j_mayer12de9a32007-10-05 22:06:02 +0000119 /* 64 bits PowerPC MMU */
j_mayeradd78952007-11-19 11:41:10 +0000120 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
David Gibson9d52e902011-04-01 15:15:19 +1100121 /* Architecture 2.06 variant */
David Gibsonf80872e2013-03-12 00:31:47 +0000122 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
123 | POWERPC_MMU_AMR | 0x00000003,
Alexander Graf126a7932013-05-02 00:27:51 +0200124 /* Architecture 2.06 "degraded" (no 1T segments) */
125 POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
126 | 0x00000003,
David Gibsonf80872e2013-03-12 00:31:47 +0000127 /* Architecture 2.06 "degraded" (no 1T segments or AMR) */
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000128 POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003,
j_mayer00af6852007-10-03 01:05:39 +0000129#endif /* defined(TARGET_PPC64) */
bellard3fc6c082005-07-02 20:59:34 +0000130};
bellard79aceca2003-11-23 14:55:54 +0000131
bellard3fc6c082005-07-02 20:59:34 +0000132/*****************************************************************************/
j_mayera750fc02007-09-26 23:54:22 +0000133/* Exception model */
Anthony Liguoric227f092009-10-01 16:12:16 -0500134typedef enum powerpc_excp_t powerpc_excp_t;
135enum powerpc_excp_t {
j_mayera750fc02007-09-26 23:54:22 +0000136 POWERPC_EXCP_UNKNOWN = 0,
bellard3fc6c082005-07-02 20:59:34 +0000137 /* Standard PowerPC exception model */
j_mayera750fc02007-09-26 23:54:22 +0000138 POWERPC_EXCP_STD,
j_mayer2662a052007-09-21 05:50:37 +0000139 /* PowerPC 40x exception model */
j_mayera750fc02007-09-26 23:54:22 +0000140 POWERPC_EXCP_40x,
j_mayer2662a052007-09-21 05:50:37 +0000141 /* PowerPC 601 exception model */
j_mayera750fc02007-09-26 23:54:22 +0000142 POWERPC_EXCP_601,
j_mayer2662a052007-09-21 05:50:37 +0000143 /* PowerPC 602 exception model */
j_mayera750fc02007-09-26 23:54:22 +0000144 POWERPC_EXCP_602,
j_mayer2662a052007-09-21 05:50:37 +0000145 /* PowerPC 603 exception model */
j_mayera750fc02007-09-26 23:54:22 +0000146 POWERPC_EXCP_603,
147 /* PowerPC 603e exception model */
148 POWERPC_EXCP_603E,
149 /* PowerPC G2 exception model */
150 POWERPC_EXCP_G2,
j_mayer2662a052007-09-21 05:50:37 +0000151 /* PowerPC 604 exception model */
j_mayera750fc02007-09-26 23:54:22 +0000152 POWERPC_EXCP_604,
j_mayer2662a052007-09-21 05:50:37 +0000153 /* PowerPC 7x0 exception model */
j_mayera750fc02007-09-26 23:54:22 +0000154 POWERPC_EXCP_7x0,
j_mayer2662a052007-09-21 05:50:37 +0000155 /* PowerPC 7x5 exception model */
j_mayera750fc02007-09-26 23:54:22 +0000156 POWERPC_EXCP_7x5,
j_mayer2662a052007-09-21 05:50:37 +0000157 /* PowerPC 74xx exception model */
j_mayera750fc02007-09-26 23:54:22 +0000158 POWERPC_EXCP_74xx,
j_mayer2662a052007-09-21 05:50:37 +0000159 /* BookE exception model */
j_mayera750fc02007-09-26 23:54:22 +0000160 POWERPC_EXCP_BOOKE,
j_mayer00af6852007-10-03 01:05:39 +0000161#if defined(TARGET_PPC64)
162 /* PowerPC 970 exception model */
163 POWERPC_EXCP_970,
David Gibson9d52e902011-04-01 15:15:19 +1100164 /* POWER7 exception model */
165 POWERPC_EXCP_POWER7,
j_mayer00af6852007-10-03 01:05:39 +0000166#endif /* defined(TARGET_PPC64) */
bellard3fc6c082005-07-02 20:59:34 +0000167};
168
bellard3fc6c082005-07-02 20:59:34 +0000169/*****************************************************************************/
j_mayere1833e12007-09-29 13:06:16 +0000170/* Exception vectors definitions */
171enum {
172 POWERPC_EXCP_NONE = -1,
173 /* The 64 first entries are used by the PowerPC embedded specification */
174 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
175 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
176 POWERPC_EXCP_DSI = 2, /* Data storage exception */
177 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
178 POWERPC_EXCP_EXTERNAL = 4, /* External input */
179 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
180 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
181 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
182 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
183 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
184 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
185 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
186 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
j_mayerb4095fe2007-11-17 22:42:36 +0000187 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
188 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
j_mayere1833e12007-09-29 13:06:16 +0000189 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
190 /* Vectors 16 to 31 are reserved */
j_mayere1833e12007-09-29 13:06:16 +0000191 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
192 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
193 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
194 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
195 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
196 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
Alexander Graf0ef654e2012-01-31 03:09:58 +0100197 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
198 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
199 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
200 /* Vectors 42 to 63 are reserved */
j_mayere1833e12007-09-29 13:06:16 +0000201 /* Exceptions defined in the PowerPC server specification */
202 POWERPC_EXCP_RESET = 64, /* System reset exception */
j_mayere1833e12007-09-29 13:06:16 +0000203 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
204 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
j_mayere1833e12007-09-29 13:06:16 +0000205 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
j_mayere1833e12007-09-29 13:06:16 +0000206 POWERPC_EXCP_TRACE = 68, /* Trace exception */
j_mayere1833e12007-09-29 13:06:16 +0000207 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
208 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
209 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
210 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
j_mayere1833e12007-09-29 13:06:16 +0000211 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
212 /* 40x specific exceptions */
213 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
214 /* 601 specific exceptions */
215 POWERPC_EXCP_IO = 75, /* IO error exception */
216 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
217 /* 602 specific exceptions */
218 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
219 /* 602/603 specific exceptions */
j_mayerb4095fe2007-11-17 22:42:36 +0000220 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
j_mayere1833e12007-09-29 13:06:16 +0000221 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
222 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
223 /* Exceptions available on most PowerPC */
224 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
j_mayerb4095fe2007-11-17 22:42:36 +0000225 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
226 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
227 POWERPC_EXCP_SMI = 84, /* System management interrupt */
228 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
j_mayere1833e12007-09-29 13:06:16 +0000229 /* 7xx/74xx specific exceptions */
j_mayerb4095fe2007-11-17 22:42:36 +0000230 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
j_mayere1833e12007-09-29 13:06:16 +0000231 /* 74xx specific exceptions */
j_mayerb4095fe2007-11-17 22:42:36 +0000232 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
j_mayere1833e12007-09-29 13:06:16 +0000233 /* 970FX specific exceptions */
j_mayerb4095fe2007-11-17 22:42:36 +0000234 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
235 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
Stefan Weil5b46d072011-04-28 17:20:30 +0200236 /* Freescale embedded cores specific exceptions */
j_mayerb4095fe2007-11-17 22:42:36 +0000237 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
238 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
239 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
240 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
Tom Musta1f298712013-10-22 22:06:17 +1100241 /* VSX Unavailable (Power ISA 2.06 and later) */
242 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
Alexey Kardashevskiy7019cb32014-06-04 22:50:56 +1000243 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
j_mayere1833e12007-09-29 13:06:16 +0000244 /* EOL */
245 POWERPC_EXCP_NB = 96,
Stefan Weil5cbdb3a2012-04-07 09:23:39 +0200246 /* QEMU exceptions: used internally during code translation */
j_mayere1833e12007-09-29 13:06:16 +0000247 POWERPC_EXCP_STOP = 0x200, /* stop translation */
248 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
Stefan Weil5cbdb3a2012-04-07 09:23:39 +0200249 /* QEMU exceptions: special cases we want to stop translation */
j_mayere1833e12007-09-29 13:06:16 +0000250 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
251 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
Nathan Froyd44252652009-08-03 08:43:26 -0700252 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
j_mayere1833e12007-09-29 13:06:16 +0000253};
254
j_mayere1833e12007-09-29 13:06:16 +0000255/* Exceptions error codes */
256enum {
257 /* Exception subtypes for POWERPC_EXCP_ALIGN */
258 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
259 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
260 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
261 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
262 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
263 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
264 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
265 /* FP exceptions */
266 POWERPC_EXCP_FP = 0x10,
267 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
268 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
269 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
270 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
j_mayer7c580442007-10-27 17:54:30 +0000271 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
j_mayere1833e12007-09-29 13:06:16 +0000272 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
273 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
274 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
275 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
276 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
277 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
278 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
279 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
280 /* Invalid instruction */
281 POWERPC_EXCP_INVAL = 0x20,
282 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
283 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
284 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
285 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
286 /* Privileged instruction */
287 POWERPC_EXCP_PRIV = 0x30,
288 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
289 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
290 /* Trap */
291 POWERPC_EXCP_TRAP = 0x40,
292};
293
294/*****************************************************************************/
j_mayera750fc02007-09-26 23:54:22 +0000295/* Input pins model */
Anthony Liguoric227f092009-10-01 16:12:16 -0500296typedef enum powerpc_input_t powerpc_input_t;
297enum powerpc_input_t {
j_mayera750fc02007-09-26 23:54:22 +0000298 PPC_FLAGS_INPUT_UNKNOWN = 0,
299 /* PowerPC 6xx bus */
300 PPC_FLAGS_INPUT_6xx,
301 /* BookE bus */
302 PPC_FLAGS_INPUT_BookE,
303 /* PowerPC 405 bus */
304 PPC_FLAGS_INPUT_405,
305 /* PowerPC 970 bus */
306 PPC_FLAGS_INPUT_970,
David Gibson9d52e902011-04-01 15:15:19 +1100307 /* PowerPC POWER7 bus */
308 PPC_FLAGS_INPUT_POWER7,
j_mayera750fc02007-09-26 23:54:22 +0000309 /* PowerPC 401 bus */
310 PPC_FLAGS_INPUT_401,
j_mayerb4095fe2007-11-17 22:42:36 +0000311 /* Freescale RCPU bus */
312 PPC_FLAGS_INPUT_RCPU,
j_mayera750fc02007-09-26 23:54:22 +0000313};
bellard3fc6c082005-07-02 20:59:34 +0000314
j_mayera750fc02007-09-26 23:54:22 +0000315#define PPC_INPUT(env) (env->bus_model)
bellard3fc6c082005-07-02 20:59:34 +0000316
j_mayerbe147d02007-09-30 13:03:23 +0000317/*****************************************************************************/
Anthony Liguoric227f092009-10-01 16:12:16 -0500318typedef struct opc_handler_t opc_handler_t;
bellard3fc6c082005-07-02 20:59:34 +0000319
320/*****************************************************************************/
321/* Types used to describe some PowerPC registers */
322typedef struct CPUPPCState CPUPPCState;
Anthony Liguoric227f092009-10-01 16:12:16 -0500323typedef struct ppc_tb_t ppc_tb_t;
324typedef struct ppc_spr_t ppc_spr_t;
325typedef struct ppc_dcr_t ppc_dcr_t;
326typedef union ppc_avr_t ppc_avr_t;
327typedef union ppc_tlb_t ppc_tlb_t;
j_mayer76a66252007-03-07 08:32:30 +0000328
bellard3fc6c082005-07-02 20:59:34 +0000329/* SPR access micro-ops generations callbacks */
Anthony Liguoric227f092009-10-01 16:12:16 -0500330struct ppc_spr_t {
aurel3245d827d2008-12-07 13:40:29 +0000331 void (*uea_read)(void *opaque, int gpr_num, int spr_num);
332 void (*uea_write)(void *opaque, int spr_num, int gpr_num);
j_mayer76a66252007-03-07 08:32:30 +0000333#if !defined(CONFIG_USER_ONLY)
aurel3245d827d2008-12-07 13:40:29 +0000334 void (*oea_read)(void *opaque, int gpr_num, int spr_num);
335 void (*oea_write)(void *opaque, int spr_num, int gpr_num);
336 void (*hea_read)(void *opaque, int gpr_num, int spr_num);
337 void (*hea_write)(void *opaque, int spr_num, int gpr_num);
j_mayerbe147d02007-09-30 13:03:23 +0000338#endif
blueswir1b55266b2008-09-20 08:07:15 +0000339 const char *name;
Alexey Kardashevskiyd197fdb2014-03-20 00:03:57 +1100340 target_ulong default_value;
David Gibsond67d40e2013-02-20 16:41:50 +0000341#ifdef CONFIG_KVM
342 /* We (ab)use the fact that all the SPRs will have ids for the
343 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
344 * don't sync this */
345 uint64_t one_reg_id;
346#endif
bellard3fc6c082005-07-02 20:59:34 +0000347};
348
349/* Altivec registers (128 bits) */
Anthony Liguoric227f092009-10-01 16:12:16 -0500350union ppc_avr_t {
aurel320f6fbcb2009-02-03 19:55:43 +0000351 float32 f[4];
j_mayera9d9eb82007-10-07 18:19:26 +0000352 uint8_t u8[16];
353 uint16_t u16[8];
354 uint32_t u32[4];
aurel32ab5f2652008-12-15 07:03:06 +0000355 int8_t s8[16];
356 int16_t s16[8];
357 int32_t s32[4];
j_mayera9d9eb82007-10-07 18:19:26 +0000358 uint64_t u64[2];
Tom Mustabb527532014-02-12 15:22:53 -0600359 int64_t s64[2];
360#ifdef CONFIG_INT128
361 __uint128_t u128;
362#endif
bellard3fc6c082005-07-02 20:59:34 +0000363};
364
Paul Brook3c7b48b2010-03-01 04:11:28 +0000365#if !defined(CONFIG_USER_ONLY)
bellard3fc6c082005-07-02 20:59:34 +0000366/* Software TLB cache */
Anthony Liguoric227f092009-10-01 16:12:16 -0500367typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
368struct ppc6xx_tlb_t {
j_mayer76a66252007-03-07 08:32:30 +0000369 target_ulong pte0;
370 target_ulong pte1;
371 target_ulong EPN;
j_mayer1d0a48f2007-03-31 11:10:49 +0000372};
373
Anthony Liguoric227f092009-10-01 16:12:16 -0500374typedef struct ppcemb_tlb_t ppcemb_tlb_t;
375struct ppcemb_tlb_t {
David Gibsonb162d022012-12-03 16:42:14 +0000376 uint64_t RPN;
j_mayer1d0a48f2007-03-31 11:10:49 +0000377 target_ulong EPN;
j_mayer76a66252007-03-07 08:32:30 +0000378 target_ulong PID;
j_mayerc55e9ae2007-04-16 09:21:46 +0000379 target_ulong size;
380 uint32_t prot;
381 uint32_t attr; /* Storage attributes */
j_mayer1d0a48f2007-03-31 11:10:49 +0000382};
383
Alexander Grafd1e256f2011-06-16 18:45:43 +0200384typedef struct ppcmas_tlb_t {
385 uint32_t mas8;
386 uint32_t mas1;
387 uint64_t mas2;
388 uint64_t mas7_3;
389} ppcmas_tlb_t;
390
Anthony Liguoric227f092009-10-01 16:12:16 -0500391union ppc_tlb_t {
Alexander Graf1c53acc2011-06-17 01:00:28 +0200392 ppc6xx_tlb_t *tlb6;
393 ppcemb_tlb_t *tlbe;
394 ppcmas_tlb_t *tlbm;
bellard3fc6c082005-07-02 20:59:34 +0000395};
Alexander Graf1c53acc2011-06-17 01:00:28 +0200396
397/* possible TLB variants */
398#define TLB_NONE 0
399#define TLB_6XX 1
400#define TLB_EMB 2
401#define TLB_MAS 3
Paul Brook3c7b48b2010-03-01 04:11:28 +0000402#endif
bellard3fc6c082005-07-02 20:59:34 +0000403
David Gibsonbb593902011-04-01 15:15:15 +1100404#define SDR_32_HTABORG 0xFFFF0000UL
405#define SDR_32_HTABMASK 0x000001FFUL
406
407#if defined(TARGET_PPC64)
408#define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
409#define SDR_64_HTABSIZE 0x000000000000001FULL
410#endif /* defined(TARGET_PPC64 */
411
Anthony Liguoric227f092009-10-01 16:12:16 -0500412typedef struct ppc_slb_t ppc_slb_t;
413struct ppc_slb_t {
David Gibson81762d62011-04-01 15:15:08 +1100414 uint64_t esid;
415 uint64_t vsid;
blueswir18eee0af2009-03-07 20:57:42 +0000416};
417
Aneesh Kumar K.Vd83af162013-10-01 21:49:31 +0530418#define MAX_SLB_ENTRIES 64
David Gibson81762d62011-04-01 15:15:08 +1100419#define SEGMENT_SHIFT_256M 28
420#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
421
David Gibsoncdaee002011-04-01 15:15:18 +1100422#define SEGMENT_SHIFT_1T 40
423#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
424
425
bellard3fc6c082005-07-02 20:59:34 +0000426/*****************************************************************************/
427/* Machine state register bits definition */
j_mayer76a66252007-03-07 08:32:30 +0000428#define MSR_SF 63 /* Sixty-four-bit mode hflags */
j_mayerbd928eb2007-11-21 13:08:23 +0000429#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
bellard3fc6c082005-07-02 20:59:34 +0000430#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
j_mayera4f30712007-11-17 21:14:09 +0000431#define MSR_SHV 60 /* hypervisor state hflags */
Alexey Kardashevskiycdcdda22014-06-04 22:50:59 +1000432#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
433#define MSR_TS1 33
434#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
j_mayer363be492007-03-30 10:07:33 +0000435#define MSR_CM 31 /* Computation mode for BookE hflags */
436#define MSR_ICM 30 /* Interrupt computation mode for BookE */
j_mayera4f30712007-11-17 21:14:09 +0000437#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
Alexander Graf71afeb62011-04-30 23:34:56 +0200438#define MSR_GS 28 /* guest state for BookE */
j_mayer363be492007-03-30 10:07:33 +0000439#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
j_mayerd26bfc92007-10-07 14:41:00 +0000440#define MSR_VR 25 /* altivec available x hflags */
441#define MSR_SPE 25 /* SPE enable for BookE x hflags */
j_mayer76a66252007-03-07 08:32:30 +0000442#define MSR_AP 23 /* Access privilege state on 602 hflags */
Tom Musta1f298712013-10-22 22:06:17 +1100443#define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
j_mayer76a66252007-03-07 08:32:30 +0000444#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
bellard3fc6c082005-07-02 20:59:34 +0000445#define MSR_KEY 19 /* key bit on 603e */
j_mayer25ba3a62007-10-08 02:58:07 +0000446#define MSR_POW 18 /* Power management */
j_mayerd26bfc92007-10-07 14:41:00 +0000447#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
448#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
bellard3fc6c082005-07-02 20:59:34 +0000449#define MSR_ILE 16 /* Interrupt little-endian mode */
450#define MSR_EE 15 /* External interrupt enable */
j_mayer76a66252007-03-07 08:32:30 +0000451#define MSR_PR 14 /* Problem state hflags */
452#define MSR_FP 13 /* Floating point available hflags */
bellard3fc6c082005-07-02 20:59:34 +0000453#define MSR_ME 12 /* Machine check interrupt enable */
j_mayer76a66252007-03-07 08:32:30 +0000454#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
j_mayerd26bfc92007-10-07 14:41:00 +0000455#define MSR_SE 10 /* Single-step trace enable x hflags */
456#define MSR_DWE 10 /* Debug wait enable on 405 x */
457#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
458#define MSR_BE 9 /* Branch trace enable x hflags */
459#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
j_mayer76a66252007-03-07 08:32:30 +0000460#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
bellard3fc6c082005-07-02 20:59:34 +0000461#define MSR_AL 7 /* AL bit on POWER */
j_mayer0411a972007-10-25 21:35:50 +0000462#define MSR_EP 6 /* Exception prefix on 601 */
bellard3fc6c082005-07-02 20:59:34 +0000463#define MSR_IR 5 /* Instruction relocate */
bellard3fc6c082005-07-02 20:59:34 +0000464#define MSR_DR 4 /* Data relocate */
j_mayer25ba3a62007-10-08 02:58:07 +0000465#define MSR_PE 3 /* Protection enable on 403 */
j_mayerd26bfc92007-10-07 14:41:00 +0000466#define MSR_PX 2 /* Protection exclusive on 403 x */
467#define MSR_PMM 2 /* Performance monitor mark on POWER x */
468#define MSR_RI 1 /* Recoverable interrupt 1 */
469#define MSR_LE 0 /* Little-endian mode 1 hflags */
j_mayer0411a972007-10-25 21:35:50 +0000470
Anton Blanchard1e0c7e52013-08-07 10:47:01 +1000471#define LPCR_ILE (1 << (63-38))
Alexey Kardashevskiyd5ac4f52014-06-04 22:51:05 +1000472#define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */
473#define LPCR_AIL (3 << LPCR_AIL_SHIFT)
Anton Blanchard1e0c7e52013-08-07 10:47:01 +1000474
j_mayer0411a972007-10-25 21:35:50 +0000475#define msr_sf ((env->msr >> MSR_SF) & 1)
476#define msr_isf ((env->msr >> MSR_ISF) & 1)
j_mayera4f30712007-11-17 21:14:09 +0000477#define msr_shv ((env->msr >> MSR_SHV) & 1)
j_mayer0411a972007-10-25 21:35:50 +0000478#define msr_cm ((env->msr >> MSR_CM) & 1)
479#define msr_icm ((env->msr >> MSR_ICM) & 1)
j_mayera4f30712007-11-17 21:14:09 +0000480#define msr_thv ((env->msr >> MSR_THV) & 1)
Alexander Graf71afeb62011-04-30 23:34:56 +0200481#define msr_gs ((env->msr >> MSR_GS) & 1)
j_mayer0411a972007-10-25 21:35:50 +0000482#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
483#define msr_vr ((env->msr >> MSR_VR) & 1)
aurel32f9320412008-05-06 14:58:15 +0000484#define msr_spe ((env->msr >> MSR_SPE) & 1)
j_mayer0411a972007-10-25 21:35:50 +0000485#define msr_ap ((env->msr >> MSR_AP) & 1)
Tom Musta1f298712013-10-22 22:06:17 +1100486#define msr_vsx ((env->msr >> MSR_VSX) & 1)
j_mayer0411a972007-10-25 21:35:50 +0000487#define msr_sa ((env->msr >> MSR_SA) & 1)
488#define msr_key ((env->msr >> MSR_KEY) & 1)
489#define msr_pow ((env->msr >> MSR_POW) & 1)
490#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
491#define msr_ce ((env->msr >> MSR_CE) & 1)
492#define msr_ile ((env->msr >> MSR_ILE) & 1)
493#define msr_ee ((env->msr >> MSR_EE) & 1)
494#define msr_pr ((env->msr >> MSR_PR) & 1)
495#define msr_fp ((env->msr >> MSR_FP) & 1)
496#define msr_me ((env->msr >> MSR_ME) & 1)
497#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
498#define msr_se ((env->msr >> MSR_SE) & 1)
499#define msr_dwe ((env->msr >> MSR_DWE) & 1)
500#define msr_uble ((env->msr >> MSR_UBLE) & 1)
501#define msr_be ((env->msr >> MSR_BE) & 1)
502#define msr_de ((env->msr >> MSR_DE) & 1)
503#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
504#define msr_al ((env->msr >> MSR_AL) & 1)
505#define msr_ep ((env->msr >> MSR_EP) & 1)
506#define msr_ir ((env->msr >> MSR_IR) & 1)
507#define msr_dr ((env->msr >> MSR_DR) & 1)
508#define msr_pe ((env->msr >> MSR_PE) & 1)
509#define msr_px ((env->msr >> MSR_PX) & 1)
510#define msr_pmm ((env->msr >> MSR_PMM) & 1)
511#define msr_ri ((env->msr >> MSR_RI) & 1)
512#define msr_le ((env->msr >> MSR_LE) & 1)
Alexey Kardashevskiycdcdda22014-06-04 22:50:59 +1000513#define msr_ts ((env->msr >> MSR_TS1) & 3)
514#define msr_tm ((env->msr >> MSR_TM) & 1)
515
j_mayera4f30712007-11-17 21:14:09 +0000516/* Hypervisor bit is more specific */
517#if defined(TARGET_PPC64)
518#define MSR_HVB (1ULL << MSR_SHV)
519#define msr_hv msr_shv
520#else
521#if defined(PPC_EMULATE_32BITS_HYPV)
522#define MSR_HVB (1ULL << MSR_THV)
523#define msr_hv msr_thv
j_mayera4f30712007-11-17 21:14:09 +0000524#else
525#define MSR_HVB (0ULL)
526#define msr_hv (0)
527#endif
528#endif
bellard79aceca2003-11-23 14:55:54 +0000529
Alexey Kardashevskiy7019cb32014-06-04 22:50:56 +1000530/* Facility Status and Control (FSCR) bits */
531#define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
532#define FSCR_TAR (63 - 55) /* Target Address Register */
533/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
534#define FSCR_IC_MASK (0xFFULL)
535#define FSCR_IC_POS (63 - 7)
536#define FSCR_IC_DSCR_SPR3 2
537#define FSCR_IC_PMU 3
538#define FSCR_IC_BHRB 4
539#define FSCR_IC_TM 5
540#define FSCR_IC_EBB 7
541#define FSCR_IC_TAR 8
542
Edgar E. Iglesiasa586e542010-09-20 19:06:32 +0200543/* Exception state register bits definition */
Alexander Graf542df9b2011-08-23 06:55:42 +0200544#define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
545#define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
546#define ESR_PTR (1 << (63 - 38)) /* Trap */
547#define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
548#define ESR_ST (1 << (63 - 40)) /* Store Operation */
549#define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
550#define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
551#define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
552#define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
553#define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
554#define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
555#define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
556#define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
557#define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
558#define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
559#define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
Edgar E. Iglesiasa586e542010-09-20 19:06:32 +0200560
j_mayerd26bfc92007-10-07 14:41:00 +0000561enum {
j_mayer4018bae2007-11-19 01:48:12 +0000562 POWERPC_FLAG_NONE = 0x00000000,
j_mayerd26bfc92007-10-07 14:41:00 +0000563 /* Flag for MSR bit 25 signification (VRE/SPE) */
j_mayer4018bae2007-11-19 01:48:12 +0000564 POWERPC_FLAG_SPE = 0x00000001,
565 POWERPC_FLAG_VRE = 0x00000002,
j_mayerd26bfc92007-10-07 14:41:00 +0000566 /* Flag for MSR bit 17 signification (TGPR/CE) */
j_mayer4018bae2007-11-19 01:48:12 +0000567 POWERPC_FLAG_TGPR = 0x00000004,
568 POWERPC_FLAG_CE = 0x00000008,
j_mayerd26bfc92007-10-07 14:41:00 +0000569 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
j_mayer4018bae2007-11-19 01:48:12 +0000570 POWERPC_FLAG_SE = 0x00000010,
571 POWERPC_FLAG_DWE = 0x00000020,
572 POWERPC_FLAG_UBLE = 0x00000040,
j_mayerd26bfc92007-10-07 14:41:00 +0000573 /* Flag for MSR bit 9 signification (BE/DE) */
j_mayer4018bae2007-11-19 01:48:12 +0000574 POWERPC_FLAG_BE = 0x00000080,
575 POWERPC_FLAG_DE = 0x00000100,
j_mayera4f30712007-11-17 21:14:09 +0000576 /* Flag for MSR bit 2 signification (PX/PMM) */
j_mayer4018bae2007-11-19 01:48:12 +0000577 POWERPC_FLAG_PX = 0x00000200,
578 POWERPC_FLAG_PMM = 0x00000400,
579 /* Flag for special features */
580 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
581 POWERPC_FLAG_RTC_CLK = 0x00010000,
582 POWERPC_FLAG_BUS_CLK = 0x00020000,
David Gibson697ab892011-08-31 15:45:10 +0000583 /* Has CFAR */
584 POWERPC_FLAG_CFAR = 0x00040000,
Tom Musta74f23992013-10-22 22:05:46 +1100585 /* Has VSX */
586 POWERPC_FLAG_VSX = 0x00080000,
j_mayerd26bfc92007-10-07 14:41:00 +0000587};
588
j_mayer7c580442007-10-27 17:54:30 +0000589/*****************************************************************************/
590/* Floating point status and control register */
591#define FPSCR_FX 31 /* Floating-point exception summary */
592#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
593#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
594#define FPSCR_OX 28 /* Floating-point overflow exception */
595#define FPSCR_UX 27 /* Floating-point underflow exception */
596#define FPSCR_ZX 26 /* Floating-point zero divide exception */
597#define FPSCR_XX 25 /* Floating-point inexact exception */
598#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
599#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
600#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
601#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
602#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
603#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
604#define FPSCR_FR 18 /* Floating-point fraction rounded */
605#define FPSCR_FI 17 /* Floating-point fraction inexact */
606#define FPSCR_C 16 /* Floating-point result class descriptor */
607#define FPSCR_FL 15 /* Floating-point less than or negative */
608#define FPSCR_FG 14 /* Floating-point greater than or negative */
609#define FPSCR_FE 13 /* Floating-point equal or zero */
610#define FPSCR_FU 12 /* Floating-point unordered or NaN */
611#define FPSCR_FPCC 12 /* Floating-point condition code */
612#define FPSCR_FPRF 12 /* Floating-point result flags */
613#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
614#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
615#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
616#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
617#define FPSCR_OE 6 /* Floating-point overflow exception enable */
618#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
619#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
620#define FPSCR_XE 3 /* Floating-point inexact exception enable */
621#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
622#define FPSCR_RN1 1
623#define FPSCR_RN 0 /* Floating-point rounding control */
624#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
625#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
626#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
627#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
628#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
629#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
630#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
631#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
632#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
633#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
634#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
635#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
636#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
637#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
638#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
639#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
640#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
641#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
642#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
643#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
644#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
645#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
646#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
647/* Invalid operation exception summary */
648#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
649 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
650 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
651 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
652 (1 << FPSCR_VXCVI)))
653/* exception summary */
654#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
655/* enabled exception summary */
656#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
657 0x1F)
658
659/*****************************************************************************/
aurel326fa724a2009-01-03 14:04:11 +0000660/* Vector status and control register */
661#define VSCR_NJ 16 /* Vector non-java */
662#define VSCR_SAT 0 /* Vector saturation */
663#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
664#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
665
666/*****************************************************************************/
Alexander Graf01662f32011-04-30 23:34:58 +0200667/* BookE e500 MMU registers */
668
669#define MAS0_NV_SHIFT 0
670#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
671
672#define MAS0_WQ_SHIFT 12
673#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
674/* Write TLB entry regardless of reservation */
675#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
676/* Write TLB entry only already in use */
677#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
678/* Clear TLB entry */
679#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
680
681#define MAS0_HES_SHIFT 14
682#define MAS0_HES (1 << MAS0_HES_SHIFT)
683
684#define MAS0_ESEL_SHIFT 16
685#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
686
687#define MAS0_TLBSEL_SHIFT 28
688#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
689#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
690#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
691#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
692#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
693
694#define MAS0_ATSEL_SHIFT 31
695#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
696#define MAS0_ATSEL_TLB 0
697#define MAS0_ATSEL_LRAT MAS0_ATSEL
698
Scott Wood2bd95432011-08-18 10:38:40 +0000699#define MAS1_TSIZE_SHIFT 7
700#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
Alexander Graf01662f32011-04-30 23:34:58 +0200701
702#define MAS1_TS_SHIFT 12
703#define MAS1_TS (1 << MAS1_TS_SHIFT)
704
705#define MAS1_IND_SHIFT 13
706#define MAS1_IND (1 << MAS1_IND_SHIFT)
707
708#define MAS1_TID_SHIFT 16
709#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
710
711#define MAS1_IPROT_SHIFT 30
712#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
713
714#define MAS1_VALID_SHIFT 31
715#define MAS1_VALID 0x80000000
716
717#define MAS2_EPN_SHIFT 12
Alexander Graf96091692012-06-21 13:34:20 +0200718#define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
Alexander Graf01662f32011-04-30 23:34:58 +0200719
720#define MAS2_ACM_SHIFT 6
721#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
722
723#define MAS2_VLE_SHIFT 5
724#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
725
726#define MAS2_W_SHIFT 4
727#define MAS2_W (1 << MAS2_W_SHIFT)
728
729#define MAS2_I_SHIFT 3
730#define MAS2_I (1 << MAS2_I_SHIFT)
731
732#define MAS2_M_SHIFT 2
733#define MAS2_M (1 << MAS2_M_SHIFT)
734
735#define MAS2_G_SHIFT 1
736#define MAS2_G (1 << MAS2_G_SHIFT)
737
738#define MAS2_E_SHIFT 0
739#define MAS2_E (1 << MAS2_E_SHIFT)
740
741#define MAS3_RPN_SHIFT 12
742#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
743
744#define MAS3_U0 0x00000200
745#define MAS3_U1 0x00000100
746#define MAS3_U2 0x00000080
747#define MAS3_U3 0x00000040
748#define MAS3_UX 0x00000020
749#define MAS3_SX 0x00000010
750#define MAS3_UW 0x00000008
751#define MAS3_SW 0x00000004
752#define MAS3_UR 0x00000002
753#define MAS3_SR 0x00000001
754#define MAS3_SPSIZE_SHIFT 1
755#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
756
757#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
758#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
759#define MAS4_TIDSELD_MASK 0x00030000
760#define MAS4_TIDSELD_PID0 0x00000000
761#define MAS4_TIDSELD_PID1 0x00010000
762#define MAS4_TIDSELD_PID2 0x00020000
763#define MAS4_TIDSELD_PIDZ 0x00030000
764#define MAS4_INDD 0x00008000 /* Default IND */
765#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
766#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
767#define MAS4_ACMD 0x00000040
768#define MAS4_VLED 0x00000020
769#define MAS4_WD 0x00000010
770#define MAS4_ID 0x00000008
771#define MAS4_MD 0x00000004
772#define MAS4_GD 0x00000002
773#define MAS4_ED 0x00000001
774#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
775#define MAS4_WIMGED_SHIFT 0
776
777#define MAS5_SGS 0x80000000
778#define MAS5_SLPID_MASK 0x00000fff
779
780#define MAS6_SPID0 0x3fff0000
781#define MAS6_SPID1 0x00007ffe
782#define MAS6_ISIZE(x) MAS1_TSIZE(x)
783#define MAS6_SAS 0x00000001
784#define MAS6_SPID MAS6_SPID0
785#define MAS6_SIND 0x00000002 /* Indirect page */
786#define MAS6_SIND_SHIFT 1
787#define MAS6_SPID_MASK 0x3fff0000
788#define MAS6_SPID_SHIFT 16
789#define MAS6_ISIZE_MASK 0x00000f80
790#define MAS6_ISIZE_SHIFT 7
791
792#define MAS7_RPN 0xffffffff
793
794#define MAS8_TGS 0x80000000
795#define MAS8_VF 0x40000000
796#define MAS8_TLBPID 0x00000fff
797
798/* Bit definitions for MMUCFG */
799#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
800#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
801#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
802#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
803#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
804#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
805#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
806#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
807#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
808
809/* Bit definitions for MMUCSR0 */
810#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
811#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
812#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
813#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
814#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
815 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
816#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
817#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
818#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
819#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
820
821/* TLBnCFG encoding */
822#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
823#define TLBnCFG_HES 0x00002000 /* HW select supported */
824#define TLBnCFG_AVAIL 0x00004000 /* variable page size */
825#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
826#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
827#define TLBnCFG_IND 0x00020000 /* IND entries supported */
828#define TLBnCFG_PT 0x00040000 /* Can load from page table */
829#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
830#define TLBnCFG_MINSIZE_SHIFT 20
831#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
832#define TLBnCFG_MAXSIZE_SHIFT 16
833#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
834#define TLBnCFG_ASSOC_SHIFT 24
835
836/* TLBnPS encoding */
837#define TLBnPS_4K 0x00000004
838#define TLBnPS_8K 0x00000008
839#define TLBnPS_16K 0x00000010
840#define TLBnPS_32K 0x00000020
841#define TLBnPS_64K 0x00000040
842#define TLBnPS_128K 0x00000080
843#define TLBnPS_256K 0x00000100
844#define TLBnPS_512K 0x00000200
845#define TLBnPS_1M 0x00000400
846#define TLBnPS_2M 0x00000800
847#define TLBnPS_4M 0x00001000
848#define TLBnPS_8M 0x00002000
849#define TLBnPS_16M 0x00004000
850#define TLBnPS_32M 0x00008000
851#define TLBnPS_64M 0x00010000
852#define TLBnPS_128M 0x00020000
853#define TLBnPS_256M 0x00040000
854#define TLBnPS_512M 0x00080000
855#define TLBnPS_1G 0x00100000
856#define TLBnPS_2G 0x00200000
857#define TLBnPS_4G 0x00400000
858#define TLBnPS_8G 0x00800000
859#define TLBnPS_16G 0x01000000
860#define TLBnPS_32G 0x02000000
861#define TLBnPS_64G 0x04000000
862#define TLBnPS_128G 0x08000000
863#define TLBnPS_256G 0x10000000
864
865/* tlbilx action encoding */
866#define TLBILX_T_ALL 0
867#define TLBILX_T_TID 1
868#define TLBILX_T_FULLMATCH 3
869#define TLBILX_T_CLASS0 4
870#define TLBILX_T_CLASS1 5
871#define TLBILX_T_CLASS2 6
872#define TLBILX_T_CLASS3 7
873
874/* BookE 2.06 helper defines */
875
876#define BOOKE206_FLUSH_TLB0 (1 << 0)
877#define BOOKE206_FLUSH_TLB1 (1 << 1)
878#define BOOKE206_FLUSH_TLB2 (1 << 2)
879#define BOOKE206_FLUSH_TLB3 (1 << 3)
880
881/* number of possible TLBs */
882#define BOOKE206_MAX_TLBN 4
883
884/*****************************************************************************/
Alexander Graf58e00a22012-01-31 03:11:32 +0100885/* Embedded.Processor Control */
886
887#define DBELL_TYPE_SHIFT 27
888#define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
889#define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
890#define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
891#define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
892#define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
893#define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
894
895#define DBELL_BRDCAST (1 << 26)
896#define DBELL_LPIDTAG_SHIFT 14
897#define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
898#define DBELL_PIRTAG_MASK 0x3fff
899
900/*****************************************************************************/
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +0000901/* Segment page size information, used by recent hash MMUs
902 * The format of this structure mirrors kvm_ppc_smmu_info
903 */
904
905#define PPC_PAGE_SIZES_MAX_SZ 8
906
907struct ppc_one_page_size {
908 uint32_t page_shift; /* Page shift (or 0) */
909 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
910};
911
912struct ppc_one_seg_page_size {
913 uint32_t page_shift; /* Base page shift of segment (or 0) */
914 uint32_t slb_enc; /* SLB encoding for BookS */
915 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
916};
917
918struct ppc_segment_page_sizes {
919 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
920};
921
922
923/*****************************************************************************/
j_mayer7c580442007-10-27 17:54:30 +0000924/* The whole PowerPC CPU context */
j_mayer6ebbf392007-10-14 07:07:08 +0000925#define NB_MMU_MODES 3
j_mayer6ebbf392007-10-14 07:07:08 +0000926
Andreas Färberb0489602013-06-09 22:11:49 +0200927#define PPC_CPU_OPCODES_LEN 0x40
928
bellard3fc6c082005-07-02 20:59:34 +0000929struct CPUPPCState {
930 /* First are the most commonly used resources
931 * during translated code execution
932 */
bellard79aceca2003-11-23 14:55:54 +0000933 /* general purpose registers */
aurel32bd7d9a62008-09-04 05:26:09 +0000934 target_ulong gpr[32];
j_mayer3cd7d1d2007-11-12 01:56:18 +0000935 /* Storage for GPR MSB, used by the SPE extension */
aurel32bd7d9a62008-09-04 05:26:09 +0000936 target_ulong gprh[32];
bellard3fc6c082005-07-02 20:59:34 +0000937 /* LR */
938 target_ulong lr;
939 /* CTR */
940 target_ulong ctr;
bellard79aceca2003-11-23 14:55:54 +0000941 /* condition register */
aurel3247e46612008-09-04 17:06:47 +0000942 uint32_t crf[8];
David Gibson697ab892011-08-31 15:45:10 +0000943#if defined(TARGET_PPC64)
944 /* CFAR */
945 target_ulong cfar;
946#endif
Richard Hendersonda91a002013-02-19 23:52:13 -0800947 /* XER (with SO, OV, CA split out) */
aurel323d7b4172008-10-21 11:28:46 +0000948 target_ulong xer;
Richard Hendersonda91a002013-02-19 23:52:13 -0800949 target_ulong so;
950 target_ulong ov;
951 target_ulong ca;
bellard3fc6c082005-07-02 20:59:34 +0000952 /* Reservation address */
Nathan Froyd18b21a22009-08-03 08:43:25 -0700953 target_ulong reserve_addr;
954 /* Reservation value */
955 target_ulong reserve_val;
Tom Musta9c294d52014-02-10 11:27:00 -0600956 target_ulong reserve_val2;
Nathan Froyd44252652009-08-03 08:43:26 -0700957 /* Reservation store address */
958 target_ulong reserve_ea;
959 /* Reserved store source register and size */
960 target_ulong reserve_info;
bellard3fc6c082005-07-02 20:59:34 +0000961
962 /* Those ones are used in supervisor mode only */
963 /* machine state register */
j_mayer0411a972007-10-25 21:35:50 +0000964 target_ulong msr;
bellard3fc6c082005-07-02 20:59:34 +0000965 /* temporary general purpose registers */
aurel32bd7d9a62008-09-04 05:26:09 +0000966 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
bellard3fc6c082005-07-02 20:59:34 +0000967
968 /* Floating point execution context */
bellard4ecc3192005-03-13 17:01:22 +0000969 float_status fp_status;
bellard3fc6c082005-07-02 20:59:34 +0000970 /* floating point registers */
971 float64 fpr[32];
972 /* floating point status and control register */
David Gibson30304422012-10-29 17:24:59 +0000973 target_ulong fpscr;
bellard4ecc3192005-03-13 17:01:22 +0000974
Aurelien Jarnocb2dbfc2009-10-22 14:55:37 +0200975 /* Next instruction pointer */
976 target_ulong nip;
bellarda316d332005-11-20 10:32:34 +0000977
bellardac9eb072004-01-04 23:26:24 +0000978 int access_type; /* when a memory exception occurs, the access
979 type is stored here */
bellarda541f292004-04-12 20:39:29 +0000980
Aurelien Jarnocb2dbfc2009-10-22 14:55:37 +0200981 CPU_COMMON
982
j_mayerf2e63a42007-10-07 15:43:50 +0000983 /* MMU context - only relevant for full system emulation */
984#if !defined(CONFIG_USER_ONLY)
985#if defined(TARGET_PPC64)
j_mayerf2e63a42007-10-07 15:43:50 +0000986 /* PowerPC 64 SLB area */
Aneesh Kumar K.Vd83af162013-10-01 21:49:31 +0530987 ppc_slb_t slb[MAX_SLB_ENTRIES];
Alexey Kardashevskiya90db152013-07-18 14:32:54 -0500988 int32_t slb_nr;
j_mayerf2e63a42007-10-07 15:43:50 +0000989#endif
bellard3fc6c082005-07-02 20:59:34 +0000990 /* segment registers */
Avi Kivitya8170e52012-10-23 12:30:10 +0200991 hwaddr htab_base;
Aneesh Kumar K.Vf3c75d42014-02-20 18:52:17 +0100992 /* mask used to normalize hash value to PTEG index */
Avi Kivitya8170e52012-10-23 12:30:10 +0200993 hwaddr htab_mask;
aurel3274d37792008-12-06 21:46:17 +0000994 target_ulong sr[32];
David Gibsonf43e3522011-04-01 15:15:22 +1100995 /* externally stored hash table */
996 uint8_t *external_htab;
bellard3fc6c082005-07-02 20:59:34 +0000997 /* BATs */
Alexey Kardashevskiya90db152013-07-18 14:32:54 -0500998 uint32_t nb_BATs;
bellard3fc6c082005-07-02 20:59:34 +0000999 target_ulong DBAT[2][8];
1000 target_ulong IBAT[2][8];
Alexander Graf01662f32011-04-30 23:34:58 +02001001 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
Alexey Kardashevskiya90db152013-07-18 14:32:54 -05001002 int32_t nb_tlb; /* Total number of TLB */
j_mayer76a66252007-03-07 08:32:30 +00001003 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1004 int nb_ways; /* Number of ways in the TLB set */
1005 int last_way; /* Last used way used to allocate TLB in a LRU way */
1006 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
j_mayer363be492007-03-30 10:07:33 +00001007 int nb_pids; /* Number of available PID registers */
Alexander Graf1c53acc2011-06-17 01:00:28 +02001008 int tlb_type; /* Type of TLB we're dealing with */
1009 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
bellard3fc6c082005-07-02 20:59:34 +00001010 /* 403 dedicated access protection registers */
1011 target_ulong pb[4];
Scott Wood93dd5e82011-08-31 11:26:56 +00001012 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1013 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
j_mayerf2e63a42007-10-07 15:43:50 +00001014#endif
1015
1016 /* Other registers */
1017 /* Special purpose registers */
1018 target_ulong spr[1024];
Anthony Liguoric227f092009-10-01 16:12:16 -05001019 ppc_spr_t spr_cb[1024];
j_mayerf2e63a42007-10-07 15:43:50 +00001020 /* Altivec registers */
Anthony Liguoric227f092009-10-01 16:12:16 -05001021 ppc_avr_t avr[32];
j_mayerf2e63a42007-10-07 15:43:50 +00001022 uint32_t vscr;
David Gibson30304422012-10-29 17:24:59 +00001023 /* VSX registers */
1024 uint64_t vsr[32];
j_mayerf2e63a42007-10-07 15:43:50 +00001025 /* SPE registers */
aurel322231ef12008-12-18 22:43:25 +00001026 uint64_t spe_acc;
j_mayerf2e63a42007-10-07 15:43:50 +00001027 uint32_t spe_fscr;
aurel32fbd265b2009-02-03 19:55:51 +00001028 /* SPE and Altivec can share a status since they will never be used
1029 * simultaneously */
1030 float_status vec_status;
j_mayerf2e63a42007-10-07 15:43:50 +00001031
1032 /* Internal devices resources */
1033 /* Time base and decrementer */
Anthony Liguoric227f092009-10-01 16:12:16 -05001034 ppc_tb_t *tb_env;
j_mayerf2e63a42007-10-07 15:43:50 +00001035 /* Device control registers */
Anthony Liguoric227f092009-10-01 16:12:16 -05001036 ppc_dcr_t *dcr_env;
bellard3fc6c082005-07-02 20:59:34 +00001037
j_mayerd63001d2007-10-04 00:51:58 +00001038 int dcache_line_size;
1039 int icache_line_size;
1040
bellard3fc6c082005-07-02 20:59:34 +00001041 /* Those resources are used during exception processing */
1042 /* CPU model definition */
j_mayera750fc02007-09-26 23:54:22 +00001043 target_ulong msr_mask;
Anthony Liguoric227f092009-10-01 16:12:16 -05001044 powerpc_mmu_t mmu_model;
1045 powerpc_excp_t excp_model;
1046 powerpc_input_t bus_model;
j_mayer237c0af2007-09-29 12:01:46 +00001047 int bfd_mach;
bellard3fc6c082005-07-02 20:59:34 +00001048 uint32_t flags;
Nathan Froydc29b7352009-05-12 12:26:57 -07001049 uint64_t insns_flags;
Alexander Grafa5858d72011-05-01 00:00:58 +02001050 uint64_t insns_flags2;
Benjamin Herrenschmidt4656e1f2012-06-18 19:56:25 +00001051#if defined(TARGET_PPC64)
1052 struct ppc_segment_page_sizes sps;
1053#endif
bellard3fc6c082005-07-02 20:59:34 +00001054
David Gibsoned120052011-04-01 15:15:33 +11001055#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
David Gibsonac7d12b2012-10-29 17:24:58 +00001056 uint64_t vpa_addr;
1057 uint64_t slb_shadow_addr, slb_shadow_size;
1058 uint64_t dtl_addr, dtl_size;
David Gibsoned120052011-04-01 15:15:33 +11001059#endif /* TARGET_PPC64 */
1060
bellard3fc6c082005-07-02 20:59:34 +00001061 int error_code;
j_mayer47103572007-03-30 09:38:04 +00001062 uint32_t pending_interrupts;
j_mayere9df0142007-04-09 22:45:36 +00001063#if !defined(CONFIG_USER_ONLY)
Dong Xu Wang4abf79a2011-11-22 18:06:21 +08001064 /* This is the IRQ controller, which is implementation dependent
j_mayere9df0142007-04-09 22:45:36 +00001065 * and only relevant when emulating a complete machine.
1066 */
1067 uint32_t irq_input_state;
1068 void **irq_inputs;
j_mayere1833e12007-09-29 13:06:16 +00001069 /* Exception vectors */
1070 target_ulong excp_vectors[POWERPC_EXCP_NB];
1071 target_ulong excp_prefix;
1072 target_ulong ivor_mask;
1073 target_ulong ivpr_mask;
j_mayerd63001d2007-10-04 00:51:58 +00001074 target_ulong hreset_vector;
Alexander Graf68c2dd72013-01-04 11:21:04 +01001075 hwaddr mpic_iack;
1076 /* true when the external proxy facility mode is enabled */
1077 bool mpic_proxy;
j_mayere9df0142007-04-09 22:45:36 +00001078#endif
bellard3fc6c082005-07-02 20:59:34 +00001079
1080 /* Those resources are used only during code translation */
bellard3fc6c082005-07-02 20:59:34 +00001081 /* opcode handlers */
Andreas Färberb0489602013-06-09 22:11:49 +02001082 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
bellard3fc6c082005-07-02 20:59:34 +00001083
Stefan Weil5cbdb3a2012-04-07 09:23:39 +02001084 /* Those resources are used only in QEMU core */
j_mayer056401e2007-11-04 02:55:33 +00001085 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
Dong Xu Wang4abf79a2011-11-22 18:06:21 +08001086 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
j_mayer6ebbf392007-10-14 07:07:08 +00001087 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
bellard3fc6c082005-07-02 20:59:34 +00001088
bellard9fddaa02004-05-21 12:59:32 +00001089 /* Power management */
j_mayercd346342007-10-25 23:27:04 +00001090 int (*check_pow)(CPUPPCState *env);
bellarda541f292004-04-12 20:39:29 +00001091
Edgar E. Iglesias2c50e262010-09-29 15:31:44 +02001092#if !defined(CONFIG_USER_ONLY)
1093 void *load_info; /* Holds boot loading state. */
1094#endif
Fabien Chouteauddd10552011-09-13 04:00:32 +00001095
1096 /* booke timers */
1097
1098 /* Specifies bit locations of the Time Base used to signal a fixed timer
1099 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1100 *
1101 * 0 selects the least significant bit.
1102 * 63 selects the most significant bit.
1103 */
1104 uint8_t fit_period[4];
1105 uint8_t wdt_period[4];
Alexey Kardashevskiy80b3f792014-06-04 22:51:00 +10001106
1107 /* Transactional memory state */
1108 target_ulong tm_gpr[32];
1109 ppc_avr_t tm_vsr[64];
1110 uint64_t tm_cr;
1111 uint64_t tm_lr;
1112 uint64_t tm_ctr;
1113 uint64_t tm_fpscr;
1114 uint64_t tm_amr;
1115 uint64_t tm_ppr;
1116 uint64_t tm_vrsave;
1117 uint32_t tm_vscr;
1118 uint64_t tm_dscr;
1119 uint64_t tm_tar;
bellard3fc6c082005-07-02 20:59:34 +00001120};
bellard79aceca2003-11-23 14:55:54 +00001121
Fabien Chouteauddd10552011-09-13 04:00:32 +00001122#define SET_FIT_PERIOD(a_, b_, c_, d_) \
1123do { \
1124 env->fit_period[0] = (a_); \
1125 env->fit_period[1] = (b_); \
1126 env->fit_period[2] = (c_); \
1127 env->fit_period[3] = (d_); \
1128 } while (0)
1129
1130#define SET_WDT_PERIOD(a_, b_, c_, d_) \
1131do { \
1132 env->wdt_period[0] = (a_); \
1133 env->wdt_period[1] = (b_); \
1134 env->wdt_period[2] = (c_); \
1135 env->wdt_period[3] = (d_); \
1136 } while (0)
1137
Andreas Färber1d0cb672012-04-06 14:39:03 +02001138#include "cpu-qom.h"
1139
bellard3fc6c082005-07-02 20:59:34 +00001140/*****************************************************************************/
Andreas Färber397b4572012-05-03 05:43:05 +02001141PowerPCCPU *cpu_ppc_init(const char *cpu_model);
pbrook2e70f6e2008-06-29 01:03:05 +00001142void ppc_translate_init(void);
Alexey Kardashevskiy7019cb32014-06-04 22:50:56 +10001143void gen_update_current_nip(void *opaque);
j_mayer36081602007-09-17 08:21:54 +00001144int cpu_ppc_exec (CPUPPCState *s);
bellard79aceca2003-11-23 14:55:54 +00001145/* you can call this signal handler from your SIGBUS and SIGSEGV
1146 signal handlers to inform the virtual CPU of exceptions. non zero
1147 is returned if the signal was handled by the virtual CPU. */
j_mayer36081602007-09-17 08:21:54 +00001148int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1149 void *puc);
David Gibsoncc8eae82013-03-12 00:31:48 +00001150#if defined(CONFIG_USER_ONLY)
Andreas Färber75104542013-08-26 03:01:33 +02001151int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1152 int mmu_idx);
David Gibsoncc8eae82013-03-12 00:31:48 +00001153#endif
bellarda541f292004-04-12 20:39:29 +00001154
j_mayer76a66252007-03-07 08:32:30 +00001155#if !defined(CONFIG_USER_ONLY)
aurel3245d827d2008-12-07 13:40:29 +00001156void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
j_mayer12de9a32007-10-05 22:06:02 +00001157#endif /* !defined(CONFIG_USER_ONLY) */
j_mayer0411a972007-10-25 21:35:50 +00001158void ppc_store_msr (CPUPPCState *env, target_ulong value);
bellard3fc6c082005-07-02 20:59:34 +00001159
Stefan Weil9a78eea2010-10-22 23:03:33 +02001160void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
Alexey Kardashevskiy2a48d992014-05-23 12:26:56 +10001161int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
Alexey Kardashevskiy6d9412e2014-05-23 12:26:52 +10001162int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version);
bellardaaed9092007-11-10 15:15:54 +00001163
bellard9fddaa02004-05-21 12:59:32 +00001164/* Time-base and decrementer management */
1165#ifndef NO_CPU_IO_DEFS
Alexander Grafe3ea6522009-12-21 12:24:17 +01001166uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
bellard9fddaa02004-05-21 12:59:32 +00001167uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1168void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1169void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
Aurelien Jarnob711de92009-12-21 13:52:08 +01001170uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
j_mayera062e362007-09-30 00:38:38 +00001171uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1172void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1173void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
Alexander Grafe81a9822014-04-06 01:32:06 +02001174bool ppc_decr_clear_on_delivery(CPUPPCState *env);
bellard9fddaa02004-05-21 12:59:32 +00001175uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1176void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
j_mayer58a7d322007-09-29 13:21:37 +00001177uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1178void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1179uint64_t cpu_ppc_load_purr (CPUPPCState *env);
j_mayerd9bce9d2007-03-17 14:02:15 +00001180uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1181uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1182#if !defined(CONFIG_USER_ONLY)
1183void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1184void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1185target_ulong load_40x_pit (CPUPPCState *env);
1186void store_40x_pit (CPUPPCState *env, target_ulong val);
j_mayer8ecc7912007-04-16 20:09:45 +00001187void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
j_mayerc294fc52007-04-24 06:44:14 +00001188void store_40x_sler (CPUPPCState *env, uint32_t val);
j_mayerd9bce9d2007-03-17 14:02:15 +00001189void store_booke_tcr (CPUPPCState *env, target_ulong val);
1190void store_booke_tsr (CPUPPCState *env, target_ulong val);
j_mayer0a032cb2007-04-16 08:56:52 +00001191void ppc_tlb_invalidate_all (CPUPPCState *env);
j_mayerdaf4f962007-10-01 01:51:12 +00001192void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
j_mayerd9bce9d2007-03-17 14:02:15 +00001193#endif
bellard9fddaa02004-05-21 12:59:32 +00001194#endif
bellard79aceca2003-11-23 14:55:54 +00001195
Fabien Chouteaud6478bc2013-03-19 07:41:53 +00001196void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1197
Blue Swirl636aa202009-08-16 09:06:54 +00001198static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
j_mayer6b542af2007-11-24 02:03:55 +00001199{
1200 uint64_t gprv;
1201
1202 gprv = env->gpr[gprn];
j_mayer6b542af2007-11-24 02:03:55 +00001203 if (env->flags & POWERPC_FLAG_SPE) {
1204 /* If the CPU implements the SPE extension, we have to get the
1205 * high bits of the GPR from the gprh storage area
1206 */
1207 gprv &= 0xFFFFFFFFULL;
1208 gprv |= (uint64_t)env->gprh[gprn] << 32;
1209 }
j_mayer6b542af2007-11-24 02:03:55 +00001210
1211 return gprv;
1212}
1213
j_mayer2e719ba2007-04-12 21:11:03 +00001214/* Device control registers */
Alexander Graf73b01962009-12-21 14:02:39 +01001215int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1216int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
j_mayer2e719ba2007-04-12 21:11:03 +00001217
Andreas Färber397b4572012-05-03 05:43:05 +02001218static inline CPUPPCState *cpu_init(const char *cpu_model)
1219{
1220 PowerPCCPU *cpu = cpu_ppc_init(cpu_model);
1221 if (cpu == NULL) {
1222 return NULL;
1223 }
1224 return &cpu->env;
1225}
1226
ths9467d442007-06-03 21:02:38 +00001227#define cpu_exec cpu_ppc_exec
1228#define cpu_gen_code cpu_ppc_gen_code
1229#define cpu_signal_handler cpu_ppc_signal_handler
j_mayerc732abe2007-10-12 06:47:46 +00001230#define cpu_list ppc_cpu_list
ths9467d442007-06-03 21:02:38 +00001231
j_mayer6ebbf392007-10-14 07:07:08 +00001232/* MMU modes definitions */
1233#define MMU_MODE0_SUFFIX _user
1234#define MMU_MODE1_SUFFIX _kernel
j_mayer6ebbf392007-10-14 07:07:08 +00001235#define MMU_MODE2_SUFFIX _hypv
j_mayer6ebbf392007-10-14 07:07:08 +00001236#define MMU_USER_IDX 0
Andreas Färber1328c2b2012-03-14 01:38:22 +01001237static inline int cpu_mmu_index (CPUPPCState *env)
j_mayer6ebbf392007-10-14 07:07:08 +00001238{
1239 return env->mmu_idx;
1240}
1241
Paolo Bonzini022c62c2012-12-17 18:19:49 +01001242#include "exec/cpu-all.h"
bellard79aceca2003-11-23 14:55:54 +00001243
bellard3fc6c082005-07-02 20:59:34 +00001244/*****************************************************************************/
aurel32e1571902008-10-21 11:31:14 +00001245/* CRF definitions */
aurel3257951c22008-11-10 11:10:23 +00001246#define CRF_LT 3
1247#define CRF_GT 2
1248#define CRF_EQ 1
1249#define CRF_SO 0
Nathan Froyde6bba2e2010-02-23 11:55:14 -08001250#define CRF_CH (1 << CRF_LT)
1251#define CRF_CL (1 << CRF_GT)
1252#define CRF_CH_OR_CL (1 << CRF_EQ)
1253#define CRF_CH_AND_CL (1 << CRF_SO)
aurel32e1571902008-10-21 11:31:14 +00001254
1255/* XER definitions */
aurel323d7b4172008-10-21 11:28:46 +00001256#define XER_SO 31
1257#define XER_OV 30
1258#define XER_CA 29
1259#define XER_CMP 8
1260#define XER_BC 0
Richard Hendersonda91a002013-02-19 23:52:13 -08001261#define xer_so (env->so)
1262#define xer_ov (env->ov)
1263#define xer_ca (env->ca)
aurel323d7b4172008-10-21 11:28:46 +00001264#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1265#define xer_bc ((env->xer >> XER_BC) & 0x7F)
bellard79aceca2003-11-23 14:55:54 +00001266
bellard3fc6c082005-07-02 20:59:34 +00001267/* SPR definitions */
j_mayer80d11f42007-11-17 23:02:20 +00001268#define SPR_MQ (0x000)
1269#define SPR_XER (0x001)
1270#define SPR_601_VRTCU (0x004)
1271#define SPR_601_VRTCL (0x005)
1272#define SPR_601_UDECR (0x006)
1273#define SPR_LR (0x008)
1274#define SPR_CTR (0x009)
David Gibsonf80872e2013-03-12 00:31:47 +00001275#define SPR_UAMR (0x00C)
David Gibson697ab892011-08-31 15:45:10 +00001276#define SPR_DSCR (0x011)
j_mayer80d11f42007-11-17 23:02:20 +00001277#define SPR_DSISR (0x012)
1278#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1279#define SPR_601_RTCU (0x014)
1280#define SPR_601_RTCL (0x015)
1281#define SPR_DECR (0x016)
1282#define SPR_SDR1 (0x019)
1283#define SPR_SRR0 (0x01A)
1284#define SPR_SRR1 (0x01B)
David Gibson697ab892011-08-31 15:45:10 +00001285#define SPR_CFAR (0x01C)
j_mayer80d11f42007-11-17 23:02:20 +00001286#define SPR_AMR (0x01D)
1287#define SPR_BOOKE_PID (0x030)
1288#define SPR_BOOKE_DECAR (0x036)
1289#define SPR_BOOKE_CSRR0 (0x03A)
1290#define SPR_BOOKE_CSRR1 (0x03B)
1291#define SPR_BOOKE_DEAR (0x03D)
1292#define SPR_BOOKE_ESR (0x03E)
1293#define SPR_BOOKE_IVPR (0x03F)
1294#define SPR_MPC_EIE (0x050)
1295#define SPR_MPC_EID (0x051)
1296#define SPR_MPC_NRI (0x052)
Alexey Kardashevskiycdcdda22014-06-04 22:50:59 +10001297#define SPR_TFHAR (0x080)
1298#define SPR_TFIAR (0x081)
1299#define SPR_TEXASR (0x082)
1300#define SPR_TEXASRU (0x083)
Alexey Kardashevskiy0bfe9292013-12-20 17:41:32 +11001301#define SPR_UCTRL (0x088)
j_mayer80d11f42007-11-17 23:02:20 +00001302#define SPR_MPC_CMPA (0x090)
1303#define SPR_MPC_CMPB (0x091)
1304#define SPR_MPC_CMPC (0x092)
1305#define SPR_MPC_CMPD (0x093)
1306#define SPR_MPC_ECR (0x094)
1307#define SPR_MPC_DER (0x095)
1308#define SPR_MPC_COUNTA (0x096)
1309#define SPR_MPC_COUNTB (0x097)
Alexey Kardashevskiy0bfe9292013-12-20 17:41:32 +11001310#define SPR_CTRL (0x098)
j_mayer80d11f42007-11-17 23:02:20 +00001311#define SPR_MPC_CMPE (0x098)
1312#define SPR_MPC_CMPF (0x099)
Alexey Kardashevskiy7019cb32014-06-04 22:50:56 +10001313#define SPR_FSCR (0x099)
j_mayer80d11f42007-11-17 23:02:20 +00001314#define SPR_MPC_CMPG (0x09A)
1315#define SPR_MPC_CMPH (0x09B)
1316#define SPR_MPC_LCTRL1 (0x09C)
1317#define SPR_MPC_LCTRL2 (0x09D)
David Gibsonf80872e2013-03-12 00:31:47 +00001318#define SPR_UAMOR (0x09D)
j_mayer80d11f42007-11-17 23:02:20 +00001319#define SPR_MPC_ICTRL (0x09E)
1320#define SPR_MPC_BAR (0x09F)
1321#define SPR_VRSAVE (0x100)
1322#define SPR_USPRG0 (0x100)
1323#define SPR_USPRG1 (0x101)
1324#define SPR_USPRG2 (0x102)
1325#define SPR_USPRG3 (0x103)
1326#define SPR_USPRG4 (0x104)
1327#define SPR_USPRG5 (0x105)
1328#define SPR_USPRG6 (0x106)
1329#define SPR_USPRG7 (0x107)
1330#define SPR_VTBL (0x10C)
1331#define SPR_VTBU (0x10D)
1332#define SPR_SPRG0 (0x110)
1333#define SPR_SPRG1 (0x111)
1334#define SPR_SPRG2 (0x112)
1335#define SPR_SPRG3 (0x113)
1336#define SPR_SPRG4 (0x114)
1337#define SPR_SCOMC (0x114)
1338#define SPR_SPRG5 (0x115)
1339#define SPR_SCOMD (0x115)
1340#define SPR_SPRG6 (0x116)
1341#define SPR_SPRG7 (0x117)
1342#define SPR_ASR (0x118)
1343#define SPR_EAR (0x11A)
1344#define SPR_TBL (0x11C)
1345#define SPR_TBU (0x11D)
1346#define SPR_TBU40 (0x11E)
1347#define SPR_SVR (0x11E)
1348#define SPR_BOOKE_PIR (0x11E)
1349#define SPR_PVR (0x11F)
1350#define SPR_HSPRG0 (0x130)
1351#define SPR_BOOKE_DBSR (0x130)
1352#define SPR_HSPRG1 (0x131)
1353#define SPR_HDSISR (0x132)
1354#define SPR_HDAR (0x133)
Scott Wood90dc8812011-04-29 17:10:23 -05001355#define SPR_BOOKE_EPCR (0x133)
David Gibson9d52e902011-04-01 15:15:19 +11001356#define SPR_SPURR (0x134)
j_mayer80d11f42007-11-17 23:02:20 +00001357#define SPR_BOOKE_DBCR0 (0x134)
1358#define SPR_IBCR (0x135)
1359#define SPR_PURR (0x135)
1360#define SPR_BOOKE_DBCR1 (0x135)
1361#define SPR_DBCR (0x136)
1362#define SPR_HDEC (0x136)
1363#define SPR_BOOKE_DBCR2 (0x136)
1364#define SPR_HIOR (0x137)
1365#define SPR_MBAR (0x137)
1366#define SPR_RMOR (0x138)
1367#define SPR_BOOKE_IAC1 (0x138)
1368#define SPR_HRMOR (0x139)
1369#define SPR_BOOKE_IAC2 (0x139)
1370#define SPR_HSRR0 (0x13A)
1371#define SPR_BOOKE_IAC3 (0x13A)
1372#define SPR_HSRR1 (0x13B)
1373#define SPR_BOOKE_IAC4 (0x13B)
j_mayer80d11f42007-11-17 23:02:20 +00001374#define SPR_BOOKE_DAC1 (0x13C)
1375#define SPR_LPIDR (0x13D)
1376#define SPR_DABR2 (0x13D)
1377#define SPR_BOOKE_DAC2 (0x13D)
1378#define SPR_BOOKE_DVC1 (0x13E)
Alexey Kardashevskiy6475c9f2013-12-20 17:41:30 +11001379#define SPR_LPCR (0x13E)
j_mayer80d11f42007-11-17 23:02:20 +00001380#define SPR_BOOKE_DVC2 (0x13F)
1381#define SPR_BOOKE_TSR (0x150)
Alexey Kardashevskiy6d9412e2014-05-23 12:26:52 +10001382#define SPR_PCR (0x152)
j_mayer80d11f42007-11-17 23:02:20 +00001383#define SPR_BOOKE_TCR (0x154)
Alexander Grafa1ef6182012-01-21 04:45:46 +01001384#define SPR_BOOKE_TLB0PS (0x158)
1385#define SPR_BOOKE_TLB1PS (0x159)
1386#define SPR_BOOKE_TLB2PS (0x15A)
1387#define SPR_BOOKE_TLB3PS (0x15B)
Alexander Graf84755ed2012-06-20 21:19:09 +02001388#define SPR_BOOKE_MAS7_MAS3 (0x174)
j_mayer80d11f42007-11-17 23:02:20 +00001389#define SPR_BOOKE_IVOR0 (0x190)
1390#define SPR_BOOKE_IVOR1 (0x191)
1391#define SPR_BOOKE_IVOR2 (0x192)
1392#define SPR_BOOKE_IVOR3 (0x193)
1393#define SPR_BOOKE_IVOR4 (0x194)
1394#define SPR_BOOKE_IVOR5 (0x195)
1395#define SPR_BOOKE_IVOR6 (0x196)
1396#define SPR_BOOKE_IVOR7 (0x197)
1397#define SPR_BOOKE_IVOR8 (0x198)
1398#define SPR_BOOKE_IVOR9 (0x199)
1399#define SPR_BOOKE_IVOR10 (0x19A)
1400#define SPR_BOOKE_IVOR11 (0x19B)
1401#define SPR_BOOKE_IVOR12 (0x19C)
1402#define SPR_BOOKE_IVOR13 (0x19D)
1403#define SPR_BOOKE_IVOR14 (0x19E)
1404#define SPR_BOOKE_IVOR15 (0x19F)
Alexander Grafe9205252012-01-19 19:31:51 +01001405#define SPR_BOOKE_IVOR38 (0x1B0)
1406#define SPR_BOOKE_IVOR39 (0x1B1)
1407#define SPR_BOOKE_IVOR40 (0x1B2)
1408#define SPR_BOOKE_IVOR41 (0x1B3)
1409#define SPR_BOOKE_IVOR42 (0x1B4)
Alexander Graf45eb5612014-01-19 17:41:14 +01001410#define SPR_BOOKE_GIVOR2 (0x1B8)
1411#define SPR_BOOKE_GIVOR3 (0x1B9)
1412#define SPR_BOOKE_GIVOR4 (0x1BA)
1413#define SPR_BOOKE_GIVOR8 (0x1BB)
1414#define SPR_BOOKE_GIVOR13 (0x1BC)
1415#define SPR_BOOKE_GIVOR14 (0x1BD)
Alexey Kardashevskiyd1a721a2014-06-04 22:50:55 +10001416#define SPR_TIR (0x1BE)
j_mayer80d11f42007-11-17 23:02:20 +00001417#define SPR_BOOKE_SPEFSCR (0x200)
1418#define SPR_Exxx_BBEAR (0x201)
1419#define SPR_Exxx_BBTAR (0x202)
1420#define SPR_Exxx_L1CFG0 (0x203)
Alexander Grafd2ea2bf2014-01-19 17:47:43 +01001421#define SPR_Exxx_L1CFG1 (0x204)
j_mayer80d11f42007-11-17 23:02:20 +00001422#define SPR_Exxx_NPIDR (0x205)
1423#define SPR_ATBL (0x20E)
1424#define SPR_ATBU (0x20F)
1425#define SPR_IBAT0U (0x210)
1426#define SPR_BOOKE_IVOR32 (0x210)
1427#define SPR_RCPU_MI_GRA (0x210)
1428#define SPR_IBAT0L (0x211)
1429#define SPR_BOOKE_IVOR33 (0x211)
1430#define SPR_IBAT1U (0x212)
1431#define SPR_BOOKE_IVOR34 (0x212)
1432#define SPR_IBAT1L (0x213)
1433#define SPR_BOOKE_IVOR35 (0x213)
1434#define SPR_IBAT2U (0x214)
1435#define SPR_BOOKE_IVOR36 (0x214)
1436#define SPR_IBAT2L (0x215)
1437#define SPR_BOOKE_IVOR37 (0x215)
1438#define SPR_IBAT3U (0x216)
1439#define SPR_IBAT3L (0x217)
1440#define SPR_DBAT0U (0x218)
1441#define SPR_RCPU_L2U_GRA (0x218)
1442#define SPR_DBAT0L (0x219)
1443#define SPR_DBAT1U (0x21A)
1444#define SPR_DBAT1L (0x21B)
1445#define SPR_DBAT2U (0x21C)
1446#define SPR_DBAT2L (0x21D)
1447#define SPR_DBAT3U (0x21E)
1448#define SPR_DBAT3L (0x21F)
1449#define SPR_IBAT4U (0x230)
1450#define SPR_RPCU_BBCMCR (0x230)
1451#define SPR_MPC_IC_CST (0x230)
1452#define SPR_Exxx_CTXCR (0x230)
1453#define SPR_IBAT4L (0x231)
1454#define SPR_MPC_IC_ADR (0x231)
1455#define SPR_Exxx_DBCR3 (0x231)
1456#define SPR_IBAT5U (0x232)
1457#define SPR_MPC_IC_DAT (0x232)
1458#define SPR_Exxx_DBCNT (0x232)
1459#define SPR_IBAT5L (0x233)
1460#define SPR_IBAT6U (0x234)
1461#define SPR_IBAT6L (0x235)
1462#define SPR_IBAT7U (0x236)
1463#define SPR_IBAT7L (0x237)
1464#define SPR_DBAT4U (0x238)
1465#define SPR_RCPU_L2U_MCR (0x238)
1466#define SPR_MPC_DC_CST (0x238)
1467#define SPR_Exxx_ALTCTXCR (0x238)
1468#define SPR_DBAT4L (0x239)
1469#define SPR_MPC_DC_ADR (0x239)
1470#define SPR_DBAT5U (0x23A)
1471#define SPR_BOOKE_MCSRR0 (0x23A)
1472#define SPR_MPC_DC_DAT (0x23A)
1473#define SPR_DBAT5L (0x23B)
1474#define SPR_BOOKE_MCSRR1 (0x23B)
1475#define SPR_DBAT6U (0x23C)
1476#define SPR_BOOKE_MCSR (0x23C)
1477#define SPR_DBAT6L (0x23D)
1478#define SPR_Exxx_MCAR (0x23D)
1479#define SPR_DBAT7U (0x23E)
1480#define SPR_BOOKE_DSRR0 (0x23E)
1481#define SPR_DBAT7L (0x23F)
1482#define SPR_BOOKE_DSRR1 (0x23F)
1483#define SPR_BOOKE_SPRG8 (0x25C)
1484#define SPR_BOOKE_SPRG9 (0x25D)
1485#define SPR_BOOKE_MAS0 (0x270)
1486#define SPR_BOOKE_MAS1 (0x271)
1487#define SPR_BOOKE_MAS2 (0x272)
1488#define SPR_BOOKE_MAS3 (0x273)
1489#define SPR_BOOKE_MAS4 (0x274)
1490#define SPR_BOOKE_MAS5 (0x275)
1491#define SPR_BOOKE_MAS6 (0x276)
1492#define SPR_BOOKE_PID1 (0x279)
1493#define SPR_BOOKE_PID2 (0x27A)
1494#define SPR_MPC_DPDR (0x280)
1495#define SPR_MPC_IMMR (0x288)
1496#define SPR_BOOKE_TLB0CFG (0x2B0)
1497#define SPR_BOOKE_TLB1CFG (0x2B1)
1498#define SPR_BOOKE_TLB2CFG (0x2B2)
1499#define SPR_BOOKE_TLB3CFG (0x2B3)
1500#define SPR_BOOKE_EPR (0x2BE)
1501#define SPR_PERF0 (0x300)
1502#define SPR_RCPU_MI_RBA0 (0x300)
1503#define SPR_MPC_MI_CTR (0x300)
1504#define SPR_PERF1 (0x301)
1505#define SPR_RCPU_MI_RBA1 (0x301)
Alexey Kardashevskiy70c53402014-06-04 22:50:58 +10001506#define SPR_POWER_UMMCR2 (0x301)
j_mayer80d11f42007-11-17 23:02:20 +00001507#define SPR_PERF2 (0x302)
1508#define SPR_RCPU_MI_RBA2 (0x302)
1509#define SPR_MPC_MI_AP (0x302)
Alexey Kardashevskiy75b9c322014-06-04 22:50:41 +10001510#define SPR_POWER_UMMCRA (0x302)
j_mayer80d11f42007-11-17 23:02:20 +00001511#define SPR_PERF3 (0x303)
1512#define SPR_RCPU_MI_RBA3 (0x303)
1513#define SPR_MPC_MI_EPN (0x303)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001514#define SPR_POWER_UPMC1 (0x303)
j_mayer80d11f42007-11-17 23:02:20 +00001515#define SPR_PERF4 (0x304)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001516#define SPR_POWER_UPMC2 (0x304)
j_mayer80d11f42007-11-17 23:02:20 +00001517#define SPR_PERF5 (0x305)
1518#define SPR_MPC_MI_TWC (0x305)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001519#define SPR_POWER_UPMC3 (0x305)
j_mayer80d11f42007-11-17 23:02:20 +00001520#define SPR_PERF6 (0x306)
1521#define SPR_MPC_MI_RPN (0x306)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001522#define SPR_POWER_UPMC4 (0x306)
j_mayer80d11f42007-11-17 23:02:20 +00001523#define SPR_PERF7 (0x307)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001524#define SPR_POWER_UPMC5 (0x307)
j_mayer80d11f42007-11-17 23:02:20 +00001525#define SPR_PERF8 (0x308)
1526#define SPR_RCPU_L2U_RBA0 (0x308)
1527#define SPR_MPC_MD_CTR (0x308)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001528#define SPR_POWER_UPMC6 (0x308)
j_mayer80d11f42007-11-17 23:02:20 +00001529#define SPR_PERF9 (0x309)
1530#define SPR_RCPU_L2U_RBA1 (0x309)
1531#define SPR_MPC_MD_CASID (0x309)
Alexey Kardashevskiyc36c97f2014-06-04 22:50:43 +10001532#define SPR_970_UPMC7 (0X309)
j_mayer80d11f42007-11-17 23:02:20 +00001533#define SPR_PERFA (0x30A)
1534#define SPR_RCPU_L2U_RBA2 (0x30A)
1535#define SPR_MPC_MD_AP (0x30A)
Alexey Kardashevskiyc36c97f2014-06-04 22:50:43 +10001536#define SPR_970_UPMC8 (0X30A)
j_mayer80d11f42007-11-17 23:02:20 +00001537#define SPR_PERFB (0x30B)
1538#define SPR_RCPU_L2U_RBA3 (0x30B)
1539#define SPR_MPC_MD_EPN (0x30B)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001540#define SPR_POWER_UMMCR0 (0X30B)
j_mayer80d11f42007-11-17 23:02:20 +00001541#define SPR_PERFC (0x30C)
1542#define SPR_MPC_MD_TWB (0x30C)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001543#define SPR_POWER_USIAR (0X30C)
j_mayer80d11f42007-11-17 23:02:20 +00001544#define SPR_PERFD (0x30D)
1545#define SPR_MPC_MD_TWC (0x30D)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001546#define SPR_POWER_USDAR (0X30D)
j_mayer80d11f42007-11-17 23:02:20 +00001547#define SPR_PERFE (0x30E)
1548#define SPR_MPC_MD_RPN (0x30E)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001549#define SPR_POWER_UMMCR1 (0X30E)
j_mayer80d11f42007-11-17 23:02:20 +00001550#define SPR_PERFF (0x30F)
1551#define SPR_MPC_MD_TW (0x30F)
1552#define SPR_UPERF0 (0x310)
1553#define SPR_UPERF1 (0x311)
Alexey Kardashevskiy70c53402014-06-04 22:50:58 +10001554#define SPR_POWER_MMCR2 (0x311)
j_mayer80d11f42007-11-17 23:02:20 +00001555#define SPR_UPERF2 (0x312)
Alexey Kardashevskiy75b9c322014-06-04 22:50:41 +10001556#define SPR_POWER_MMCRA (0X312)
j_mayer80d11f42007-11-17 23:02:20 +00001557#define SPR_UPERF3 (0x313)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001558#define SPR_POWER_PMC1 (0X313)
j_mayer80d11f42007-11-17 23:02:20 +00001559#define SPR_UPERF4 (0x314)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001560#define SPR_POWER_PMC2 (0X314)
j_mayer80d11f42007-11-17 23:02:20 +00001561#define SPR_UPERF5 (0x315)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001562#define SPR_POWER_PMC3 (0X315)
j_mayer80d11f42007-11-17 23:02:20 +00001563#define SPR_UPERF6 (0x316)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001564#define SPR_POWER_PMC4 (0X316)
j_mayer80d11f42007-11-17 23:02:20 +00001565#define SPR_UPERF7 (0x317)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001566#define SPR_POWER_PMC5 (0X317)
j_mayer80d11f42007-11-17 23:02:20 +00001567#define SPR_UPERF8 (0x318)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001568#define SPR_POWER_PMC6 (0X318)
j_mayer80d11f42007-11-17 23:02:20 +00001569#define SPR_UPERF9 (0x319)
Alexey Kardashevskiyc36c97f2014-06-04 22:50:43 +10001570#define SPR_970_PMC7 (0X319)
j_mayer80d11f42007-11-17 23:02:20 +00001571#define SPR_UPERFA (0x31A)
Alexey Kardashevskiyc36c97f2014-06-04 22:50:43 +10001572#define SPR_970_PMC8 (0X31A)
j_mayer80d11f42007-11-17 23:02:20 +00001573#define SPR_UPERFB (0x31B)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001574#define SPR_POWER_MMCR0 (0X31B)
j_mayer80d11f42007-11-17 23:02:20 +00001575#define SPR_UPERFC (0x31C)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001576#define SPR_POWER_SIAR (0X31C)
j_mayer80d11f42007-11-17 23:02:20 +00001577#define SPR_UPERFD (0x31D)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001578#define SPR_POWER_SDAR (0X31D)
j_mayer80d11f42007-11-17 23:02:20 +00001579#define SPR_UPERFE (0x31E)
Alexey Kardashevskiyfd51ff62014-06-04 22:50:40 +10001580#define SPR_POWER_MMCR1 (0X31E)
j_mayer80d11f42007-11-17 23:02:20 +00001581#define SPR_UPERFF (0x31F)
1582#define SPR_RCPU_MI_RA0 (0x320)
1583#define SPR_MPC_MI_DBCAM (0x320)
Alexey Kardashevskiy4ee4a032014-06-04 22:51:01 +10001584#define SPR_BESCRS (0x320)
j_mayer80d11f42007-11-17 23:02:20 +00001585#define SPR_RCPU_MI_RA1 (0x321)
1586#define SPR_MPC_MI_DBRAM0 (0x321)
Alexey Kardashevskiy4ee4a032014-06-04 22:51:01 +10001587#define SPR_BESCRSU (0x321)
j_mayer80d11f42007-11-17 23:02:20 +00001588#define SPR_RCPU_MI_RA2 (0x322)
1589#define SPR_MPC_MI_DBRAM1 (0x322)
Alexey Kardashevskiy4ee4a032014-06-04 22:51:01 +10001590#define SPR_BESCRR (0x322)
j_mayer80d11f42007-11-17 23:02:20 +00001591#define SPR_RCPU_MI_RA3 (0x323)
Alexey Kardashevskiy4ee4a032014-06-04 22:51:01 +10001592#define SPR_BESCRRU (0x323)
1593#define SPR_EBBHR (0x324)
1594#define SPR_EBBRR (0x325)
1595#define SPR_BESCR (0x326)
j_mayer80d11f42007-11-17 23:02:20 +00001596#define SPR_RCPU_L2U_RA0 (0x328)
1597#define SPR_MPC_MD_DBCAM (0x328)
1598#define SPR_RCPU_L2U_RA1 (0x329)
1599#define SPR_MPC_MD_DBRAM0 (0x329)
1600#define SPR_RCPU_L2U_RA2 (0x32A)
1601#define SPR_MPC_MD_DBRAM1 (0x32A)
1602#define SPR_RCPU_L2U_RA3 (0x32B)
Tom Musta60511042014-02-10 11:26:54 -06001603#define SPR_TAR (0x32F)
j_mayer80d11f42007-11-17 23:02:20 +00001604#define SPR_440_INV0 (0x370)
1605#define SPR_440_INV1 (0x371)
1606#define SPR_440_INV2 (0x372)
1607#define SPR_440_INV3 (0x373)
1608#define SPR_440_ITV0 (0x374)
1609#define SPR_440_ITV1 (0x375)
1610#define SPR_440_ITV2 (0x376)
1611#define SPR_440_ITV3 (0x377)
1612#define SPR_440_CCR1 (0x378)
1613#define SPR_DCRIPR (0x37B)
Alexey Kardashevskiy70c53402014-06-04 22:50:58 +10001614#define SPR_POWER_MMCRS (0x37E)
j_mayer80d11f42007-11-17 23:02:20 +00001615#define SPR_PPR (0x380)
j_mayerbd928eb2007-11-21 13:08:23 +00001616#define SPR_750_GQR0 (0x390)
j_mayer80d11f42007-11-17 23:02:20 +00001617#define SPR_440_DNV0 (0x390)
j_mayerbd928eb2007-11-21 13:08:23 +00001618#define SPR_750_GQR1 (0x391)
j_mayer80d11f42007-11-17 23:02:20 +00001619#define SPR_440_DNV1 (0x391)
j_mayerbd928eb2007-11-21 13:08:23 +00001620#define SPR_750_GQR2 (0x392)
j_mayer80d11f42007-11-17 23:02:20 +00001621#define SPR_440_DNV2 (0x392)
j_mayerbd928eb2007-11-21 13:08:23 +00001622#define SPR_750_GQR3 (0x393)
j_mayer80d11f42007-11-17 23:02:20 +00001623#define SPR_440_DNV3 (0x393)
j_mayerbd928eb2007-11-21 13:08:23 +00001624#define SPR_750_GQR4 (0x394)
j_mayer80d11f42007-11-17 23:02:20 +00001625#define SPR_440_DTV0 (0x394)
j_mayerbd928eb2007-11-21 13:08:23 +00001626#define SPR_750_GQR5 (0x395)
j_mayer80d11f42007-11-17 23:02:20 +00001627#define SPR_440_DTV1 (0x395)
j_mayerbd928eb2007-11-21 13:08:23 +00001628#define SPR_750_GQR6 (0x396)
j_mayer80d11f42007-11-17 23:02:20 +00001629#define SPR_440_DTV2 (0x396)
j_mayerbd928eb2007-11-21 13:08:23 +00001630#define SPR_750_GQR7 (0x397)
j_mayer80d11f42007-11-17 23:02:20 +00001631#define SPR_440_DTV3 (0x397)
j_mayerbd928eb2007-11-21 13:08:23 +00001632#define SPR_750_THRM4 (0x398)
1633#define SPR_750CL_HID2 (0x398)
j_mayer80d11f42007-11-17 23:02:20 +00001634#define SPR_440_DVLIM (0x398)
j_mayerbd928eb2007-11-21 13:08:23 +00001635#define SPR_750_WPAR (0x399)
j_mayer80d11f42007-11-17 23:02:20 +00001636#define SPR_440_IVLIM (0x399)
j_mayerbd928eb2007-11-21 13:08:23 +00001637#define SPR_750_DMAU (0x39A)
1638#define SPR_750_DMAL (0x39B)
j_mayer80d11f42007-11-17 23:02:20 +00001639#define SPR_440_RSTCFG (0x39B)
1640#define SPR_BOOKE_DCDBTRL (0x39C)
1641#define SPR_BOOKE_DCDBTRH (0x39D)
1642#define SPR_BOOKE_ICDBTRL (0x39E)
1643#define SPR_BOOKE_ICDBTRH (0x39F)
Alexey Kardashevskiycb8b8bf2014-06-04 22:50:36 +10001644#define SPR_74XX_UMMCR2 (0x3A0)
1645#define SPR_7XX_UPMC5 (0x3A1)
1646#define SPR_7XX_UPMC6 (0x3A2)
j_mayer80d11f42007-11-17 23:02:20 +00001647#define SPR_UBAMR (0x3A7)
Alexey Kardashevskiycb8b8bf2014-06-04 22:50:36 +10001648#define SPR_7XX_UMMCR0 (0x3A8)
1649#define SPR_7XX_UPMC1 (0x3A9)
1650#define SPR_7XX_UPMC2 (0x3AA)
1651#define SPR_7XX_USIAR (0x3AB)
1652#define SPR_7XX_UMMCR1 (0x3AC)
1653#define SPR_7XX_UPMC3 (0x3AD)
1654#define SPR_7XX_UPMC4 (0x3AE)
j_mayer80d11f42007-11-17 23:02:20 +00001655#define SPR_USDA (0x3AF)
1656#define SPR_40x_ZPR (0x3B0)
1657#define SPR_BOOKE_MAS7 (0x3B0)
Alexey Kardashevskiycb8b8bf2014-06-04 22:50:36 +10001658#define SPR_74XX_MMCR2 (0x3B0)
1659#define SPR_7XX_PMC5 (0x3B1)
j_mayer80d11f42007-11-17 23:02:20 +00001660#define SPR_40x_PID (0x3B1)
Alexey Kardashevskiycb8b8bf2014-06-04 22:50:36 +10001661#define SPR_7XX_PMC6 (0x3B2)
j_mayer80d11f42007-11-17 23:02:20 +00001662#define SPR_440_MMUCR (0x3B2)
j_mayer80d11f42007-11-17 23:02:20 +00001663#define SPR_4xx_CCR0 (0x3B3)
1664#define SPR_BOOKE_EPLC (0x3B3)
j_mayer80d11f42007-11-17 23:02:20 +00001665#define SPR_405_IAC3 (0x3B4)
1666#define SPR_BOOKE_EPSC (0x3B4)
j_mayer80d11f42007-11-17 23:02:20 +00001667#define SPR_405_IAC4 (0x3B5)
j_mayer80d11f42007-11-17 23:02:20 +00001668#define SPR_405_DVC1 (0x3B6)
j_mayer80d11f42007-11-17 23:02:20 +00001669#define SPR_405_DVC2 (0x3B7)
j_mayer80d11f42007-11-17 23:02:20 +00001670#define SPR_BAMR (0x3B7)
Alexey Kardashevskiycb8b8bf2014-06-04 22:50:36 +10001671#define SPR_7XX_MMCR0 (0x3B8)
1672#define SPR_7XX_PMC1 (0x3B9)
j_mayer80d11f42007-11-17 23:02:20 +00001673#define SPR_40x_SGR (0x3B9)
Alexey Kardashevskiycb8b8bf2014-06-04 22:50:36 +10001674#define SPR_7XX_PMC2 (0x3BA)
j_mayer80d11f42007-11-17 23:02:20 +00001675#define SPR_40x_DCWR (0x3BA)
Alexey Kardashevskiycb8b8bf2014-06-04 22:50:36 +10001676#define SPR_7XX_SIAR (0x3BB)
j_mayer80d11f42007-11-17 23:02:20 +00001677#define SPR_405_SLER (0x3BB)
Alexey Kardashevskiycb8b8bf2014-06-04 22:50:36 +10001678#define SPR_7XX_MMCR1 (0x3BC)
j_mayer80d11f42007-11-17 23:02:20 +00001679#define SPR_405_SU0R (0x3BC)
j_mayer80d11f42007-11-17 23:02:20 +00001680#define SPR_401_SKR (0x3BC)
Alexey Kardashevskiycb8b8bf2014-06-04 22:50:36 +10001681#define SPR_7XX_PMC3 (0x3BD)
j_mayer80d11f42007-11-17 23:02:20 +00001682#define SPR_405_DBCR1 (0x3BD)
Alexey Kardashevskiycb8b8bf2014-06-04 22:50:36 +10001683#define SPR_7XX_PMC4 (0x3BE)
j_mayer80d11f42007-11-17 23:02:20 +00001684#define SPR_SDA (0x3BF)
j_mayer80d11f42007-11-17 23:02:20 +00001685#define SPR_403_VTBL (0x3CC)
1686#define SPR_403_VTBU (0x3CD)
1687#define SPR_DMISS (0x3D0)
1688#define SPR_DCMP (0x3D1)
1689#define SPR_HASH1 (0x3D2)
1690#define SPR_HASH2 (0x3D3)
1691#define SPR_BOOKE_ICDBDR (0x3D3)
1692#define SPR_TLBMISS (0x3D4)
1693#define SPR_IMISS (0x3D4)
1694#define SPR_40x_ESR (0x3D4)
1695#define SPR_PTEHI (0x3D5)
1696#define SPR_ICMP (0x3D5)
1697#define SPR_40x_DEAR (0x3D5)
1698#define SPR_PTELO (0x3D6)
1699#define SPR_RPA (0x3D6)
1700#define SPR_40x_EVPR (0x3D6)
1701#define SPR_L3PM (0x3D7)
1702#define SPR_403_CDBCR (0x3D7)
j_mayer4e777442007-12-10 07:40:16 +00001703#define SPR_L3ITCR0 (0x3D8)
j_mayer80d11f42007-11-17 23:02:20 +00001704#define SPR_TCR (0x3D8)
1705#define SPR_40x_TSR (0x3D8)
1706#define SPR_IBR (0x3DA)
1707#define SPR_40x_TCR (0x3DA)
1708#define SPR_ESASRR (0x3DB)
1709#define SPR_40x_PIT (0x3DB)
1710#define SPR_403_TBL (0x3DC)
1711#define SPR_403_TBU (0x3DD)
1712#define SPR_SEBR (0x3DE)
1713#define SPR_40x_SRR2 (0x3DE)
1714#define SPR_SER (0x3DF)
1715#define SPR_40x_SRR3 (0x3DF)
j_mayer4e777442007-12-10 07:40:16 +00001716#define SPR_L3OHCR (0x3E8)
j_mayer80d11f42007-11-17 23:02:20 +00001717#define SPR_L3ITCR1 (0x3E9)
1718#define SPR_L3ITCR2 (0x3EA)
1719#define SPR_L3ITCR3 (0x3EB)
1720#define SPR_HID0 (0x3F0)
1721#define SPR_40x_DBSR (0x3F0)
1722#define SPR_HID1 (0x3F1)
1723#define SPR_IABR (0x3F2)
1724#define SPR_40x_DBCR0 (0x3F2)
1725#define SPR_601_HID2 (0x3F2)
1726#define SPR_Exxx_L1CSR0 (0x3F2)
1727#define SPR_ICTRL (0x3F3)
1728#define SPR_HID2 (0x3F3)
j_mayerbd928eb2007-11-21 13:08:23 +00001729#define SPR_750CL_HID4 (0x3F3)
j_mayer80d11f42007-11-17 23:02:20 +00001730#define SPR_Exxx_L1CSR1 (0x3F3)
1731#define SPR_440_DBDR (0x3F3)
1732#define SPR_LDSTDB (0x3F4)
j_mayerbd928eb2007-11-21 13:08:23 +00001733#define SPR_750_TDCL (0x3F4)
j_mayer80d11f42007-11-17 23:02:20 +00001734#define SPR_40x_IAC1 (0x3F4)
1735#define SPR_MMUCSR0 (0x3F4)
Alexey Kardashevskiyba881002014-06-04 22:50:44 +10001736#define SPR_970_HID4 (0x3F4)
j_mayer80d11f42007-11-17 23:02:20 +00001737#define SPR_DABR (0x3F5)
bellard3fc6c082005-07-02 20:59:34 +00001738#define DABR_MASK (~(target_ulong)0x7)
j_mayer80d11f42007-11-17 23:02:20 +00001739#define SPR_Exxx_BUCSR (0x3F5)
1740#define SPR_40x_IAC2 (0x3F5)
1741#define SPR_601_HID5 (0x3F5)
1742#define SPR_40x_DAC1 (0x3F6)
1743#define SPR_MSSCR0 (0x3F6)
1744#define SPR_970_HID5 (0x3F6)
1745#define SPR_MSSSR0 (0x3F7)
j_mayer4e777442007-12-10 07:40:16 +00001746#define SPR_MSSCR1 (0x3F7)
j_mayer80d11f42007-11-17 23:02:20 +00001747#define SPR_DABRX (0x3F7)
1748#define SPR_40x_DAC2 (0x3F7)
1749#define SPR_MMUCFG (0x3F7)
1750#define SPR_LDSTCR (0x3F8)
1751#define SPR_L2PMCR (0x3F8)
j_mayerbd928eb2007-11-21 13:08:23 +00001752#define SPR_750FX_HID2 (0x3F8)
j_mayer80d11f42007-11-17 23:02:20 +00001753#define SPR_Exxx_L1FINV0 (0x3F8)
1754#define SPR_L2CR (0x3F9)
j_mayer80d11f42007-11-17 23:02:20 +00001755#define SPR_L3CR (0x3FA)
j_mayerbd928eb2007-11-21 13:08:23 +00001756#define SPR_750_TDCH (0x3FA)
j_mayer80d11f42007-11-17 23:02:20 +00001757#define SPR_IABR2 (0x3FA)
1758#define SPR_40x_DCCR (0x3FA)
1759#define SPR_ICTC (0x3FB)
1760#define SPR_40x_ICCR (0x3FB)
1761#define SPR_THRM1 (0x3FC)
1762#define SPR_403_PBL1 (0x3FC)
1763#define SPR_SP (0x3FD)
1764#define SPR_THRM2 (0x3FD)
1765#define SPR_403_PBU1 (0x3FD)
1766#define SPR_604_HID13 (0x3FD)
1767#define SPR_LT (0x3FE)
1768#define SPR_THRM3 (0x3FE)
1769#define SPR_RCPU_FPECR (0x3FE)
1770#define SPR_403_PBL2 (0x3FE)
1771#define SPR_PIR (0x3FF)
1772#define SPR_403_PBU2 (0x3FF)
1773#define SPR_601_HID15 (0x3FF)
1774#define SPR_604_HID15 (0x3FF)
1775#define SPR_E500_SVR (0x3FF)
bellard79aceca2003-11-23 14:55:54 +00001776
Alexander Graf84755ed2012-06-20 21:19:09 +02001777/* Disable MAS Interrupt Updates for Hypervisor */
1778#define EPCR_DMIUH (1 << 22)
1779/* Disable Guest TLB Management Instructions */
1780#define EPCR_DGTMI (1 << 23)
1781/* Guest Interrupt Computation Mode */
1782#define EPCR_GICM (1 << 24)
1783/* Interrupt Computation Mode */
1784#define EPCR_ICM (1 << 25)
1785/* Disable Embedded Hypervisor Debug */
1786#define EPCR_DUVD (1 << 26)
1787/* Instruction Storage Interrupt Directed to Guest State */
1788#define EPCR_ISIGS (1 << 27)
1789/* Data Storage Interrupt Directed to Guest State */
1790#define EPCR_DSIGS (1 << 28)
1791/* Instruction TLB Error Interrupt Directed to Guest State */
1792#define EPCR_ITLBGS (1 << 29)
1793/* Data TLB Error Interrupt Directed to Guest State */
1794#define EPCR_DTLBGS (1 << 30)
1795/* External Input Interrupt Directed to Guest State */
1796#define EPCR_EXTGS (1 << 31)
1797
Alexander Grafea712582014-01-19 17:49:11 +01001798#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1799#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1800#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1801#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1802#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1803
1804#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1805#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1806#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1807#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1808#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1809
Alexey Kardashevskiybbc01ca2014-06-04 22:50:37 +10001810/* HID0 bits */
1811#define HID0_DEEPNAP (1 << 24)
1812#define HID0_DOZE (1 << 23)
1813#define HID0_NAP (1 << 22)
1814
j_mayer76a66252007-03-07 08:32:30 +00001815/*****************************************************************************/
Nathan Froydc29b7352009-05-12 12:26:57 -07001816/* PowerPC Instructions types definitions */
1817enum {
1818 PPC_NONE = 0x0000000000000000ULL,
1819 /* PowerPC base instructions set */
1820 PPC_INSNS_BASE = 0x0000000000000001ULL,
1821 /* integer operations instructions */
1822#define PPC_INTEGER PPC_INSNS_BASE
1823 /* flow control instructions */
1824#define PPC_FLOW PPC_INSNS_BASE
1825 /* virtual memory instructions */
1826#define PPC_MEM PPC_INSNS_BASE
1827 /* ld/st with reservation instructions */
1828#define PPC_RES PPC_INSNS_BASE
1829 /* spr/msr access instructions */
1830#define PPC_MISC PPC_INSNS_BASE
1831 /* Deprecated instruction sets */
1832 /* Original POWER instruction set */
1833 PPC_POWER = 0x0000000000000002ULL,
1834 /* POWER2 instruction set extension */
1835 PPC_POWER2 = 0x0000000000000004ULL,
1836 /* Power RTC support */
1837 PPC_POWER_RTC = 0x0000000000000008ULL,
1838 /* Power-to-PowerPC bridge (601) */
1839 PPC_POWER_BR = 0x0000000000000010ULL,
1840 /* 64 bits PowerPC instruction set */
1841 PPC_64B = 0x0000000000000020ULL,
1842 /* New 64 bits extensions (PowerPC 2.0x) */
1843 PPC_64BX = 0x0000000000000040ULL,
1844 /* 64 bits hypervisor extensions */
1845 PPC_64H = 0x0000000000000080ULL,
1846 /* New wait instruction (PowerPC 2.0x) */
1847 PPC_WAIT = 0x0000000000000100ULL,
1848 /* Time base mftb instruction */
1849 PPC_MFTB = 0x0000000000000200ULL,
1850
1851 /* Fixed-point unit extensions */
1852 /* PowerPC 602 specific */
1853 PPC_602_SPEC = 0x0000000000000400ULL,
1854 /* isel instruction */
1855 PPC_ISEL = 0x0000000000000800ULL,
1856 /* popcntb instruction */
1857 PPC_POPCNTB = 0x0000000000001000ULL,
1858 /* string load / store */
1859 PPC_STRING = 0x0000000000002000ULL,
1860
1861 /* Floating-point unit extensions */
1862 /* Optional floating point instructions */
1863 PPC_FLOAT = 0x0000000000010000ULL,
1864 /* New floating-point extensions (PowerPC 2.0x) */
1865 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1866 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1867 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1868 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1869 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1870 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1871 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1872
1873 /* Vector/SIMD extensions */
1874 /* Altivec support */
1875 PPC_ALTIVEC = 0x0000000001000000ULL,
1876 /* PowerPC 2.03 SPE extension */
1877 PPC_SPE = 0x0000000002000000ULL,
1878 /* PowerPC 2.03 SPE single-precision floating-point extension */
1879 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1880 /* PowerPC 2.03 SPE double-precision floating-point extension */
1881 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1882
1883 /* Optional memory control instructions */
1884 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1885 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1886 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1887 /* sync instruction */
1888 PPC_MEM_SYNC = 0x0000000080000000ULL,
1889 /* eieio instruction */
1890 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1891
1892 /* Cache control instructions */
1893 PPC_CACHE = 0x0000000200000000ULL,
1894 /* icbi instruction */
1895 PPC_CACHE_ICBI = 0x0000000400000000ULL,
Alexander Graf8e339442013-01-29 13:36:02 +01001896 /* dcbz instruction */
Nathan Froydc29b7352009-05-12 12:26:57 -07001897 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
Nathan Froydc29b7352009-05-12 12:26:57 -07001898 /* dcba instruction */
1899 PPC_CACHE_DCBA = 0x0000002000000000ULL,
1900 /* Freescale cache locking instructions */
1901 PPC_CACHE_LOCK = 0x0000004000000000ULL,
1902
1903 /* MMU related extensions */
1904 /* external control instructions */
1905 PPC_EXTERN = 0x0000010000000000ULL,
1906 /* segment register access instructions */
1907 PPC_SEGMENT = 0x0000020000000000ULL,
1908 /* PowerPC 6xx TLB management instructions */
1909 PPC_6xx_TLB = 0x0000040000000000ULL,
1910 /* PowerPC 74xx TLB management instructions */
1911 PPC_74xx_TLB = 0x0000080000000000ULL,
1912 /* PowerPC 40x TLB management instructions */
1913 PPC_40x_TLB = 0x0000100000000000ULL,
1914 /* segment register access instructions for PowerPC 64 "bridge" */
1915 PPC_SEGMENT_64B = 0x0000200000000000ULL,
1916 /* SLB management */
1917 PPC_SLBI = 0x0000400000000000ULL,
1918
1919 /* Embedded PowerPC dedicated instructions */
1920 PPC_WRTEE = 0x0001000000000000ULL,
1921 /* PowerPC 40x exception model */
1922 PPC_40x_EXCP = 0x0002000000000000ULL,
1923 /* PowerPC 405 Mac instructions */
1924 PPC_405_MAC = 0x0004000000000000ULL,
1925 /* PowerPC 440 specific instructions */
1926 PPC_440_SPEC = 0x0008000000000000ULL,
1927 /* BookE (embedded) PowerPC specification */
1928 PPC_BOOKE = 0x0010000000000000ULL,
1929 /* mfapidi instruction */
1930 PPC_MFAPIDI = 0x0020000000000000ULL,
1931 /* tlbiva instruction */
1932 PPC_TLBIVA = 0x0040000000000000ULL,
1933 /* tlbivax instruction */
1934 PPC_TLBIVAX = 0x0080000000000000ULL,
1935 /* PowerPC 4xx dedicated instructions */
1936 PPC_4xx_COMMON = 0x0100000000000000ULL,
1937 /* PowerPC 40x ibct instructions */
1938 PPC_40x_ICBT = 0x0200000000000000ULL,
1939 /* rfmci is not implemented in all BookE PowerPC */
1940 PPC_RFMCI = 0x0400000000000000ULL,
1941 /* rfdi instruction */
1942 PPC_RFDI = 0x0800000000000000ULL,
1943 /* DCR accesses */
1944 PPC_DCR = 0x1000000000000000ULL,
1945 /* DCR extended accesse */
1946 PPC_DCRX = 0x2000000000000000ULL,
1947 /* user-mode DCR access, implemented in PowerPC 460 */
1948 PPC_DCRUX = 0x4000000000000000ULL,
David Gibsoneaabeef2011-04-01 15:15:13 +11001949 /* popcntw and popcntd instructions */
1950 PPC_POPCNTWD = 0x8000000000000000ULL,
Alexander Graf01662f32011-04-30 23:34:58 +02001951
David Gibson02d4eae2011-10-30 15:51:24 +00001952#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
1953 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
1954 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
1955 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
1956 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
1957 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
1958 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
1959 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
1960 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
1961 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
1962 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
1963 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
1964 | PPC_CACHE | PPC_CACHE_ICBI \
Alexander Graf8e339442013-01-29 13:36:02 +01001965 | PPC_CACHE_DCBZ \
David Gibson02d4eae2011-10-30 15:51:24 +00001966 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
1967 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
1968 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
1969 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
1970 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
1971 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
1972 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
1973 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
1974 | PPC_POPCNTWD)
1975
Alexander Graf01662f32011-04-30 23:34:58 +02001976 /* extended type values */
1977
1978 /* BookE 2.06 PowerPC specification */
1979 PPC2_BOOKE206 = 0x0000000000000001ULL,
David Gibsona7342582011-10-17 18:15:41 +00001980 /* VSX (extensions to Altivec / VMX) */
1981 PPC2_VSX = 0x0000000000000002ULL,
1982 /* Decimal Floating Point (DFP) */
1983 PPC2_DFP = 0x0000000000000004ULL,
Alexander Graf3f9f6a52012-01-31 03:13:30 +01001984 /* Embedded.Processor Control */
1985 PPC2_PRCNTL = 0x0000000000000008ULL,
Thomas Huthcd6e9322012-02-27 17:18:08 +00001986 /* Byte-reversed, indexed, double-word load and store */
1987 PPC2_DBRX = 0x0000000000000010ULL,
Aurelien Jarno9c2627b2013-04-20 08:56:15 +00001988 /* Book I 2.05 PowerPC specification */
1989 PPC2_ISA205 = 0x0000000000000020ULL,
Tom Mustadbcc48f2014-01-15 08:10:28 -06001990 /* VSX additions in ISA 2.07 */
1991 PPC2_VSX207 = 0x0000000000000040ULL,
Tom Musta86ba37e2014-01-07 10:05:49 -06001992 /* ISA 2.06B bpermd */
1993 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
Tom Mustaa824bc12014-01-07 10:05:50 -06001994 /* ISA 2.06B divide extended variants */
1995 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
Tom Musta1fa6c532014-01-07 10:05:55 -06001996 /* ISA 2.06B larx/stcx. instructions */
1997 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
Tom Musta1b0bd002014-01-07 10:05:58 -06001998 /* ISA 2.06B floating point integer conversion */
1999 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
Tom Musta29a0e4e2014-01-07 10:06:06 -06002000 /* ISA 2.06B floating point test instructions */
2001 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
Tom Musta94840e02014-02-10 11:26:53 -06002002 /* ISA 2.07 bctar instruction */
2003 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
Tom Musta38a85332014-02-10 11:26:56 -06002004 /* ISA 2.07 load/store quadword */
2005 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
Tom Musta32ea54a2014-02-12 15:22:52 -06002006 /* ISA 2.07 Altivec */
2007 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
Alexey Kardashevskiydf99d302014-03-07 15:37:39 +11002008 /* PowerISA 2.07 Book3s specification */
2009 PPC2_ISA207S = 0x0000000000008000ULL,
David Gibson02d4eae2011-10-30 15:51:24 +00002010
Tom Musta74f23992013-10-22 22:05:46 +11002011#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
Tom Mustaa824bc12014-01-07 10:05:50 -06002012 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
Tom Musta1b0bd002014-01-07 10:05:58 -06002013 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
Tom Musta94840e02014-02-10 11:26:53 -06002014 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
Tom Musta32ea54a2014-02-12 15:22:52 -06002015 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
Tom Mustab2f13552014-06-16 11:03:20 -05002016 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP)
Nathan Froydc29b7352009-05-12 12:26:57 -07002017};
2018
2019/*****************************************************************************/
bellard9a64fbe2004-01-04 22:58:38 +00002020/* Memory access type :
2021 * may be needed for precise access rights control and precise exceptions.
2022 */
bellard79aceca2003-11-23 14:55:54 +00002023enum {
bellard9a64fbe2004-01-04 22:58:38 +00002024 /* 1 bit to define user level / supervisor access */
2025 ACCESS_USER = 0x00,
2026 ACCESS_SUPER = 0x01,
2027 /* Type of instruction that generated the access */
2028 ACCESS_CODE = 0x10, /* Code fetch access */
2029 ACCESS_INT = 0x20, /* Integer load/store access */
2030 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2031 ACCESS_RES = 0x40, /* load/store with reservation */
2032 ACCESS_EXT = 0x50, /* external access */
2033 ACCESS_CACHE = 0x60, /* Cache manipulation */
2034};
2035
j_mayer47103572007-03-30 09:38:04 +00002036/* Hardware interruption sources:
2037 * all those exception can be raised simulteaneously
2038 */
j_mayere9df0142007-04-09 22:45:36 +00002039/* Input pins definitions */
j_mayer47103572007-03-30 09:38:04 +00002040enum {
j_mayere9df0142007-04-09 22:45:36 +00002041 /* 6xx bus input pins */
j_mayer24be5ae2007-04-12 21:24:29 +00002042 PPC6xx_INPUT_HRESET = 0,
2043 PPC6xx_INPUT_SRESET = 1,
2044 PPC6xx_INPUT_CKSTP_IN = 2,
2045 PPC6xx_INPUT_MCP = 3,
2046 PPC6xx_INPUT_SMI = 4,
2047 PPC6xx_INPUT_INT = 5,
j_mayerd68f1302007-10-14 09:27:16 +00002048 PPC6xx_INPUT_TBEN = 6,
2049 PPC6xx_INPUT_WAKEUP = 7,
2050 PPC6xx_INPUT_NB,
j_mayer24be5ae2007-04-12 21:24:29 +00002051};
2052
2053enum {
j_mayere9df0142007-04-09 22:45:36 +00002054 /* Embedded PowerPC input pins */
j_mayer24be5ae2007-04-12 21:24:29 +00002055 PPCBookE_INPUT_HRESET = 0,
2056 PPCBookE_INPUT_SRESET = 1,
2057 PPCBookE_INPUT_CKSTP_IN = 2,
2058 PPCBookE_INPUT_MCP = 3,
2059 PPCBookE_INPUT_SMI = 4,
2060 PPCBookE_INPUT_INT = 5,
2061 PPCBookE_INPUT_CINT = 6,
j_mayerd68f1302007-10-14 09:27:16 +00002062 PPCBookE_INPUT_NB,
j_mayer24be5ae2007-04-12 21:24:29 +00002063};
2064
2065enum {
aurel329fdc60b2009-03-02 16:42:32 +00002066 /* PowerPC E500 input pins */
2067 PPCE500_INPUT_RESET_CORE = 0,
2068 PPCE500_INPUT_MCK = 1,
2069 PPCE500_INPUT_CINT = 3,
2070 PPCE500_INPUT_INT = 4,
2071 PPCE500_INPUT_DEBUG = 6,
2072 PPCE500_INPUT_NB,
2073};
2074
2075enum {
j_mayer4e290a02007-10-01 01:27:10 +00002076 /* PowerPC 40x input pins */
2077 PPC40x_INPUT_RESET_CORE = 0,
2078 PPC40x_INPUT_RESET_CHIP = 1,
2079 PPC40x_INPUT_RESET_SYS = 2,
2080 PPC40x_INPUT_CINT = 3,
2081 PPC40x_INPUT_INT = 4,
2082 PPC40x_INPUT_HALT = 5,
2083 PPC40x_INPUT_DEBUG = 6,
2084 PPC40x_INPUT_NB,
j_mayere9df0142007-04-09 22:45:36 +00002085};
2086
j_mayerb4095fe2007-11-17 22:42:36 +00002087enum {
2088 /* RCPU input pins */
2089 PPCRCPU_INPUT_PORESET = 0,
2090 PPCRCPU_INPUT_HRESET = 1,
2091 PPCRCPU_INPUT_SRESET = 2,
2092 PPCRCPU_INPUT_IRQ0 = 3,
2093 PPCRCPU_INPUT_IRQ1 = 4,
2094 PPCRCPU_INPUT_IRQ2 = 5,
2095 PPCRCPU_INPUT_IRQ3 = 6,
2096 PPCRCPU_INPUT_IRQ4 = 7,
2097 PPCRCPU_INPUT_IRQ5 = 8,
2098 PPCRCPU_INPUT_IRQ6 = 9,
2099 PPCRCPU_INPUT_IRQ7 = 10,
2100 PPCRCPU_INPUT_NB,
2101};
2102
j_mayer00af6852007-10-03 01:05:39 +00002103#if defined(TARGET_PPC64)
j_mayerd0dfae62007-04-16 07:34:39 +00002104enum {
2105 /* PowerPC 970 input pins */
2106 PPC970_INPUT_HRESET = 0,
2107 PPC970_INPUT_SRESET = 1,
2108 PPC970_INPUT_CKSTP = 2,
2109 PPC970_INPUT_TBEN = 3,
2110 PPC970_INPUT_MCP = 4,
2111 PPC970_INPUT_INT = 5,
2112 PPC970_INPUT_THINT = 6,
j_mayer7b62a952007-11-17 02:04:00 +00002113 PPC970_INPUT_NB,
j_mayerd0dfae62007-04-16 07:34:39 +00002114};
David Gibson9d52e902011-04-01 15:15:19 +11002115
2116enum {
2117 /* POWER7 input pins */
2118 POWER7_INPUT_INT = 0,
2119 /* POWER7 probably has other inputs, but we don't care about them
2120 * for any existing machine. We can wire these up when we need
2121 * them */
2122 POWER7_INPUT_NB,
2123};
j_mayer00af6852007-10-03 01:05:39 +00002124#endif
j_mayerd0dfae62007-04-16 07:34:39 +00002125
j_mayere9df0142007-04-09 22:45:36 +00002126/* Hardware exceptions definitions */
2127enum {
2128 /* External hardware exception sources */
j_mayere1833e12007-09-29 13:06:16 +00002129 PPC_INTERRUPT_RESET = 0, /* Reset exception */
j_mayerd68f1302007-10-14 09:27:16 +00002130 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2131 PPC_INTERRUPT_MCK, /* Machine check exception */
2132 PPC_INTERRUPT_EXT, /* External interrupt */
2133 PPC_INTERRUPT_SMI, /* System management interrupt */
2134 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2135 PPC_INTERRUPT_DEBUG, /* External debug exception */
2136 PPC_INTERRUPT_THERM, /* Thermal exception */
j_mayere9df0142007-04-09 22:45:36 +00002137 /* Internal hardware exception sources */
j_mayerd68f1302007-10-14 09:27:16 +00002138 PPC_INTERRUPT_DECR, /* Decrementer exception */
2139 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2140 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2141 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2142 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2143 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2144 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2145 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
j_mayer47103572007-03-30 09:38:04 +00002146};
2147
Alexey Kardashevskiy6d9412e2014-05-23 12:26:52 +10002148/* Processor Compatibility mask (PCR) */
2149enum {
2150 PCR_COMPAT_2_05 = 1ull << (63-62),
2151 PCR_COMPAT_2_06 = 1ull << (63-61),
2152 PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2153 PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2154 PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2155};
2156
bellard9a64fbe2004-01-04 22:58:38 +00002157/*****************************************************************************/
bellard79aceca2003-11-23 14:55:54 +00002158
Richard Hendersonda91a002013-02-19 23:52:13 -08002159static inline target_ulong cpu_read_xer(CPUPPCState *env)
2160{
2161 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2162}
2163
2164static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2165{
2166 env->so = (xer >> XER_SO) & 1;
2167 env->ov = (xer >> XER_OV) & 1;
2168 env->ca = (xer >> XER_CA) & 1;
2169 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2170}
2171
Andreas Färber1328c2b2012-03-14 01:38:22 +01002172static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
aliguori6b917542008-11-18 19:46:41 +00002173 target_ulong *cs_base, int *flags)
2174{
2175 *pc = env->nip;
2176 *cs_base = 0;
2177 *flags = env->hflags;
2178}
2179
Alexander Graf01662f32011-04-30 23:34:58 +02002180#if !defined(CONFIG_USER_ONLY)
Andreas Färber1328c2b2012-03-14 01:38:22 +01002181static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
Alexander Graf01662f32011-04-30 23:34:58 +02002182{
Alexander Grafd1e256f2011-06-16 18:45:43 +02002183 uintptr_t tlbml = (uintptr_t)tlbm;
Alexander Graf1c53acc2011-06-17 01:00:28 +02002184 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
Alexander Graf01662f32011-04-30 23:34:58 +02002185
Alexander Graf1c53acc2011-06-17 01:00:28 +02002186 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
Alexander Graf01662f32011-04-30 23:34:58 +02002187}
2188
Andreas Färber1328c2b2012-03-14 01:38:22 +01002189static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
Alexander Graf01662f32011-04-30 23:34:58 +02002190{
2191 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2192 int r = tlbncfg & TLBnCFG_N_ENTRY;
2193 return r;
2194}
2195
Andreas Färber1328c2b2012-03-14 01:38:22 +01002196static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
Alexander Graf01662f32011-04-30 23:34:58 +02002197{
2198 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2199 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2200 return r;
2201}
2202
Andreas Färber1328c2b2012-03-14 01:38:22 +01002203static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
Alexander Graf01662f32011-04-30 23:34:58 +02002204{
Alexander Grafd1e256f2011-06-16 18:45:43 +02002205 int id = booke206_tlbm_id(env, tlbm);
Alexander Graf01662f32011-04-30 23:34:58 +02002206 int end = 0;
2207 int i;
2208
2209 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2210 end += booke206_tlb_size(env, i);
2211 if (id < end) {
2212 return i;
2213 }
2214 }
2215
Andreas Färbera47dddd2013-09-03 17:38:47 +02002216 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
Alexander Graf01662f32011-04-30 23:34:58 +02002217 return 0;
2218}
2219
Andreas Färber1328c2b2012-03-14 01:38:22 +01002220static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
Alexander Graf01662f32011-04-30 23:34:58 +02002221{
Alexander Grafd1e256f2011-06-16 18:45:43 +02002222 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2223 int tlbid = booke206_tlbm_id(env, tlb);
Alexander Graf01662f32011-04-30 23:34:58 +02002224 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2225}
2226
Andreas Färber1328c2b2012-03-14 01:38:22 +01002227static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
Alexander Graf01662f32011-04-30 23:34:58 +02002228 target_ulong ea, int way)
2229{
2230 int r;
2231 uint32_t ways = booke206_tlb_ways(env, tlbn);
2232 int ways_bits = ffs(ways) - 1;
2233 int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1;
2234 int i;
2235
2236 way &= ways - 1;
2237 ea >>= MAS2_EPN_SHIFT;
2238 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2239 r = (ea << ways_bits) | way;
2240
Alexander Graf3f162d12012-01-25 16:27:26 +01002241 if (r >= booke206_tlb_size(env, tlbn)) {
2242 return NULL;
2243 }
2244
Alexander Graf01662f32011-04-30 23:34:58 +02002245 /* bump up to tlbn index */
2246 for (i = 0; i < tlbn; i++) {
2247 r += booke206_tlb_size(env, i);
2248 }
2249
Alexander Graf1c53acc2011-06-17 01:00:28 +02002250 return &env->tlb.tlbm[r];
Alexander Graf01662f32011-04-30 23:34:58 +02002251}
2252
Alexander Grafa1ef6182012-01-21 04:45:46 +01002253/* returns bitmap of supported page sizes for a given TLB */
Andreas Färber1328c2b2012-03-14 01:38:22 +01002254static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
Alexander Grafa1ef6182012-01-21 04:45:46 +01002255{
2256 bool mav2 = false;
2257 uint32_t ret = 0;
2258
2259 if (mav2) {
2260 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2261 } else {
2262 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2263 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2264 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2265 int i;
2266 for (i = min; i <= max; i++) {
2267 ret |= (1 << (i << 1));
2268 }
2269 }
2270
2271 return ret;
2272}
2273
Alexander Graf01662f32011-04-30 23:34:58 +02002274#endif
2275
Alexander Grafe42a61f2012-06-20 21:20:29 +02002276static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2277{
2278 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2279 return msr & (1ULL << MSR_CM);
2280 }
2281
2282 return msr & (1ULL << MSR_SF);
2283}
2284
Andreas Färber1b146702012-05-03 06:03:45 +02002285extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
David Gibsond5699562011-04-01 15:15:10 +11002286
Paolo Bonzini022c62c2012-12-17 18:19:49 +01002287#include "exec/exec-all.h"
Blue Swirlf081c762011-05-21 07:10:23 +00002288
Andreas Färber1328c2b2012-03-14 01:38:22 +01002289void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
Scott Woodbebabbc2011-08-18 10:38:42 +00002290
Alexey Kardashevskiy0ce470c2014-02-02 01:45:51 +11002291/**
2292 * ppc_get_vcpu_dt_id:
2293 * @cs: a PowerPCCPU struct.
2294 *
2295 * Returns a device-tree ID for a CPU.
2296 */
2297int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2298
2299/**
2300 * ppc_get_vcpu_by_dt_id:
2301 * @cpu_dt_id: a device tree id
2302 *
2303 * Searches for a CPU by @cpu_dt_id.
2304 *
2305 * Returns: a PowerPCCPU struct
2306 */
2307PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2308
bellard79aceca2003-11-23 14:55:54 +00002309#endif /* !defined (__CPU_PPC_H__) */