commit 4ee4a03b38685be863803e52d9b00ffbc7ce9a22
author Alexey Kardashevskiy <aik@ozlabs.ru> Wed Jun 04 22:51:01 2014 +1000
committer Alexander Graf <agraf@suse.de> Mon Jun 16 13:24:45 2014 +0200
tree 2297a43ae990bc832cc7c1fec7f03a7a68ffae8d
parent 80b3f79b999a334b277137f698c43e7730da4224

target-ppc: Add POWER8's Event Based Branch (EBB) control SPRs

POWER8 supports Event-Based Branch Facility (EBB). It is controlled via
set of SPRs access to which should generate an "Facility Unavailable"
interrupt if the facilities are not enabled in FSCR for problem state.

This adds EBB SPRs.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>

target-ppc/cpu.h

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index c5837dd..32ee652 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1578,11 +1578,18 @@
 #define SPR_UPERFF            (0x31F)
 #define SPR_RCPU_MI_RA0       (0x320)
 #define SPR_MPC_MI_DBCAM      (0x320)
+#define SPR_BESCRS            (0x320)
 #define SPR_RCPU_MI_RA1       (0x321)
 #define SPR_MPC_MI_DBRAM0     (0x321)
+#define SPR_BESCRSU           (0x321)
 #define SPR_RCPU_MI_RA2       (0x322)
 #define SPR_MPC_MI_DBRAM1     (0x322)
+#define SPR_BESCRR            (0x322)
 #define SPR_RCPU_MI_RA3       (0x323)
+#define SPR_BESCRRU           (0x323)
+#define SPR_EBBHR             (0x324)
+#define SPR_EBBRR             (0x325)
+#define SPR_BESCR             (0x326)
 #define SPR_RCPU_L2U_RA0      (0x328)
 #define SPR_MPC_MD_DBCAM      (0x328)
 #define SPR_RCPU_L2U_RA1      (0x329)