bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1 | /* |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 2 | * PowerPC emulation cpu definitions for qemu. |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 18 | */ |
| 19 | #if !defined (__CPU_PPC_H__) |
| 20 | #define __CPU_PPC_H__ |
| 21 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 22 | #include "config.h" |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 23 | #include "qemu-common.h" |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 24 | |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 25 | //#define PPC_EMULATE_32BITS_HYPV |
| 26 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 27 | #if defined (TARGET_PPC64) |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 28 | /* PowerPC 64 definitions */ |
j_mayer | d9d7210 | 2007-09-18 11:17:30 +0000 | [diff] [blame] | 29 | #define TARGET_LONG_BITS 64 |
j_mayer | 35cdaad | 2007-04-24 06:50:21 +0000 | [diff] [blame] | 30 | #define TARGET_PAGE_BITS 12 |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 31 | |
Richard Henderson | 5270589 | 2010-03-10 14:33:23 -0800 | [diff] [blame] | 32 | /* Note that the official physical address space bits is 62-M where M |
| 33 | is implementation dependent. I've not looked up M for the set of |
| 34 | cpus we emulate at the system level. */ |
| 35 | #define TARGET_PHYS_ADDR_SPACE_BITS 62 |
| 36 | |
| 37 | /* Note that the PPC environment architecture talks about 80 bit virtual |
| 38 | addresses, with segmentation. Obviously that's not all visible to a |
| 39 | single process, which is all we're concerned with here. */ |
| 40 | #ifdef TARGET_ABI32 |
| 41 | # define TARGET_VIRT_ADDR_SPACE_BITS 32 |
| 42 | #else |
| 43 | # define TARGET_VIRT_ADDR_SPACE_BITS 64 |
| 44 | #endif |
| 45 | |
David Gibson | 81762d6 | 2011-04-01 15:15:08 +1100 | [diff] [blame] | 46 | #define TARGET_PAGE_BITS_16M 24 |
| 47 | |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 48 | #else /* defined (TARGET_PPC64) */ |
| 49 | /* PowerPC 32 definitions */ |
j_mayer | d9d7210 | 2007-09-18 11:17:30 +0000 | [diff] [blame] | 50 | #define TARGET_LONG_BITS 32 |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 51 | |
| 52 | #if defined(TARGET_PPCEMB) |
| 53 | /* Specific definitions for PowerPC embedded */ |
| 54 | /* BookE have 36 bits physical address space */ |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 55 | #if defined(CONFIG_USER_ONLY) |
| 56 | /* It looks like a lot of Linux programs assume page size |
| 57 | * is 4kB long. This is evil, but we have to deal with it... |
| 58 | */ |
j_mayer | 35cdaad | 2007-04-24 06:50:21 +0000 | [diff] [blame] | 59 | #define TARGET_PAGE_BITS 12 |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 60 | #else /* defined(CONFIG_USER_ONLY) */ |
| 61 | /* Pages can be 1 kB small */ |
| 62 | #define TARGET_PAGE_BITS 10 |
| 63 | #endif /* defined(CONFIG_USER_ONLY) */ |
| 64 | #else /* defined(TARGET_PPCEMB) */ |
| 65 | /* "standard" PowerPC 32 definitions */ |
| 66 | #define TARGET_PAGE_BITS 12 |
| 67 | #endif /* defined(TARGET_PPCEMB) */ |
| 68 | |
Alexander Graf | 8b242eb | 2011-10-18 01:46:08 +0200 | [diff] [blame] | 69 | #define TARGET_PHYS_ADDR_SPACE_BITS 36 |
Richard Henderson | 5270589 | 2010-03-10 14:33:23 -0800 | [diff] [blame] | 70 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
| 71 | |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 72 | #endif /* defined (TARGET_PPC64) */ |
bellard | 3cf1e03 | 2004-01-24 15:19:09 +0000 | [diff] [blame] | 73 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 74 | #define CPUArchState struct CPUPPCState |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 75 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 76 | #include "exec/cpu-defs.h" |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 77 | |
Paolo Bonzini | 6b4c305 | 2012-10-24 13:12:00 +0200 | [diff] [blame] | 78 | #include "fpu/softfloat.h" |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 79 | |
bellard | 1fddef4 | 2005-04-17 19:16:13 +0000 | [diff] [blame] | 80 | #define TARGET_HAS_ICE 1 |
| 81 | |
blueswir1 | 7f70c93 | 2009-03-13 21:16:24 +0000 | [diff] [blame] | 82 | #if defined (TARGET_PPC64) |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 83 | #define ELF_MACHINE EM_PPC64 |
| 84 | #else |
| 85 | #define ELF_MACHINE EM_PPC |
| 86 | #endif |
ths | 9042c0e | 2006-12-23 14:18:40 +0000 | [diff] [blame] | 87 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 88 | /*****************************************************************************/ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 89 | /* MMU model */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 90 | typedef enum powerpc_mmu_t powerpc_mmu_t; |
| 91 | enum powerpc_mmu_t { |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 92 | POWERPC_MMU_UNKNOWN = 0x00000000, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 93 | /* Standard 32 bits PowerPC MMU */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 94 | POWERPC_MMU_32B = 0x00000001, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 95 | /* PowerPC 6xx MMU with software TLB */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 96 | POWERPC_MMU_SOFT_6xx = 0x00000002, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 97 | /* PowerPC 74xx MMU with software TLB */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 98 | POWERPC_MMU_SOFT_74xx = 0x00000003, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 99 | /* PowerPC 4xx MMU with software TLB */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 100 | POWERPC_MMU_SOFT_4xx = 0x00000004, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 101 | /* PowerPC 4xx MMU with software TLB and zones protections */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 102 | POWERPC_MMU_SOFT_4xx_Z = 0x00000005, |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 103 | /* PowerPC MMU in real mode only */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 104 | POWERPC_MMU_REAL = 0x00000006, |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 105 | /* Freescale MPC8xx MMU model */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 106 | POWERPC_MMU_MPC8xx = 0x00000007, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 107 | /* BookE MMU model */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 108 | POWERPC_MMU_BOOKE = 0x00000008, |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 109 | /* BookE 2.06 MMU model */ |
| 110 | POWERPC_MMU_BOOKE206 = 0x00000009, |
j_mayer | faadf50 | 2007-11-03 13:37:12 +0000 | [diff] [blame] | 111 | /* PowerPC 601 MMU model (specific BATs format) */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 112 | POWERPC_MMU_601 = 0x0000000A, |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 113 | #if defined(TARGET_PPC64) |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 114 | #define POWERPC_MMU_64 0x00010000 |
David Gibson | cdaee00 | 2011-04-01 15:15:18 +1100 | [diff] [blame] | 115 | #define POWERPC_MMU_1TSEG 0x00020000 |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 116 | #define POWERPC_MMU_AMR 0x00040000 |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 117 | /* 64 bits PowerPC MMU */ |
j_mayer | add7895 | 2007-11-19 11:41:10 +0000 | [diff] [blame] | 118 | POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 119 | /* Architecture 2.06 variant */ |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 120 | POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG |
| 121 | | POWERPC_MMU_AMR | 0x00000003, |
Alexander Graf | 126a793 | 2013-05-02 00:27:51 +0200 | [diff] [blame] | 122 | /* Architecture 2.06 "degraded" (no 1T segments) */ |
| 123 | POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR |
| 124 | | 0x00000003, |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 125 | /* Architecture 2.06 "degraded" (no 1T segments or AMR) */ |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 126 | POWERPC_MMU_2_06d = POWERPC_MMU_64 | 0x00000003, |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 127 | #endif /* defined(TARGET_PPC64) */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 128 | }; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 129 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 130 | /*****************************************************************************/ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 131 | /* Exception model */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 132 | typedef enum powerpc_excp_t powerpc_excp_t; |
| 133 | enum powerpc_excp_t { |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 134 | POWERPC_EXCP_UNKNOWN = 0, |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 135 | /* Standard PowerPC exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 136 | POWERPC_EXCP_STD, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 137 | /* PowerPC 40x exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 138 | POWERPC_EXCP_40x, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 139 | /* PowerPC 601 exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 140 | POWERPC_EXCP_601, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 141 | /* PowerPC 602 exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 142 | POWERPC_EXCP_602, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 143 | /* PowerPC 603 exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 144 | POWERPC_EXCP_603, |
| 145 | /* PowerPC 603e exception model */ |
| 146 | POWERPC_EXCP_603E, |
| 147 | /* PowerPC G2 exception model */ |
| 148 | POWERPC_EXCP_G2, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 149 | /* PowerPC 604 exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 150 | POWERPC_EXCP_604, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 151 | /* PowerPC 7x0 exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 152 | POWERPC_EXCP_7x0, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 153 | /* PowerPC 7x5 exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 154 | POWERPC_EXCP_7x5, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 155 | /* PowerPC 74xx exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 156 | POWERPC_EXCP_74xx, |
j_mayer | 2662a05 | 2007-09-21 05:50:37 +0000 | [diff] [blame] | 157 | /* BookE exception model */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 158 | POWERPC_EXCP_BOOKE, |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 159 | #if defined(TARGET_PPC64) |
| 160 | /* PowerPC 970 exception model */ |
| 161 | POWERPC_EXCP_970, |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 162 | /* POWER7 exception model */ |
| 163 | POWERPC_EXCP_POWER7, |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 164 | #endif /* defined(TARGET_PPC64) */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 165 | }; |
| 166 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 167 | /*****************************************************************************/ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 168 | /* Exception vectors definitions */ |
| 169 | enum { |
| 170 | POWERPC_EXCP_NONE = -1, |
| 171 | /* The 64 first entries are used by the PowerPC embedded specification */ |
| 172 | POWERPC_EXCP_CRITICAL = 0, /* Critical input */ |
| 173 | POWERPC_EXCP_MCHECK = 1, /* Machine check exception */ |
| 174 | POWERPC_EXCP_DSI = 2, /* Data storage exception */ |
| 175 | POWERPC_EXCP_ISI = 3, /* Instruction storage exception */ |
| 176 | POWERPC_EXCP_EXTERNAL = 4, /* External input */ |
| 177 | POWERPC_EXCP_ALIGN = 5, /* Alignment exception */ |
| 178 | POWERPC_EXCP_PROGRAM = 6, /* Program exception */ |
| 179 | POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */ |
| 180 | POWERPC_EXCP_SYSCALL = 8, /* System call exception */ |
| 181 | POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */ |
| 182 | POWERPC_EXCP_DECR = 10, /* Decrementer exception */ |
| 183 | POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */ |
| 184 | POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */ |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 185 | POWERPC_EXCP_DTLB = 13, /* Data TLB miss */ |
| 186 | POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 187 | POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */ |
| 188 | /* Vectors 16 to 31 are reserved */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 189 | POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */ |
| 190 | POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */ |
| 191 | POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */ |
| 192 | POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */ |
| 193 | POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */ |
| 194 | POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */ |
Alexander Graf | 0ef654e | 2012-01-31 03:09:58 +0100 | [diff] [blame] | 195 | POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */ |
| 196 | POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/ |
| 197 | POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */ |
| 198 | /* Vectors 42 to 63 are reserved */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 199 | /* Exceptions defined in the PowerPC server specification */ |
| 200 | POWERPC_EXCP_RESET = 64, /* System reset exception */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 201 | POWERPC_EXCP_DSEG = 65, /* Data segment exception */ |
| 202 | POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 203 | POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 204 | POWERPC_EXCP_TRACE = 68, /* Trace exception */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 205 | POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */ |
| 206 | POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */ |
| 207 | POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */ |
| 208 | POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 209 | POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */ |
| 210 | /* 40x specific exceptions */ |
| 211 | POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */ |
| 212 | /* 601 specific exceptions */ |
| 213 | POWERPC_EXCP_IO = 75, /* IO error exception */ |
| 214 | POWERPC_EXCP_RUNM = 76, /* Run mode exception */ |
| 215 | /* 602 specific exceptions */ |
| 216 | POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */ |
| 217 | /* 602/603 specific exceptions */ |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 218 | POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 219 | POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */ |
| 220 | POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */ |
| 221 | /* Exceptions available on most PowerPC */ |
| 222 | POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */ |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 223 | POWERPC_EXCP_DABR = 82, /* Data address breakpoint */ |
| 224 | POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */ |
| 225 | POWERPC_EXCP_SMI = 84, /* System management interrupt */ |
| 226 | POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 227 | /* 7xx/74xx specific exceptions */ |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 228 | POWERPC_EXCP_THERM = 86, /* Thermal interrupt */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 229 | /* 74xx specific exceptions */ |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 230 | POWERPC_EXCP_VPUA = 87, /* Vector assist exception */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 231 | /* 970FX specific exceptions */ |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 232 | POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */ |
| 233 | POWERPC_EXCP_MAINT = 89, /* Maintenance exception */ |
Stefan Weil | 5b46d07 | 2011-04-28 17:20:30 +0200 | [diff] [blame] | 234 | /* Freescale embedded cores specific exceptions */ |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 235 | POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */ |
| 236 | POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */ |
| 237 | POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */ |
| 238 | POWERPC_EXCP_DTLBE = 93, /* Data TLB error */ |
Tom Musta | 1f29871 | 2013-10-22 22:06:17 +1100 | [diff] [blame] | 239 | /* VSX Unavailable (Power ISA 2.06 and later) */ |
| 240 | POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 241 | /* EOL */ |
| 242 | POWERPC_EXCP_NB = 96, |
Stefan Weil | 5cbdb3a | 2012-04-07 09:23:39 +0200 | [diff] [blame] | 243 | /* QEMU exceptions: used internally during code translation */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 244 | POWERPC_EXCP_STOP = 0x200, /* stop translation */ |
| 245 | POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ |
Stefan Weil | 5cbdb3a | 2012-04-07 09:23:39 +0200 | [diff] [blame] | 246 | /* QEMU exceptions: special cases we want to stop translation */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 247 | POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ |
| 248 | POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ |
Nathan Froyd | 4425265 | 2009-08-03 08:43:26 -0700 | [diff] [blame] | 249 | POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 250 | }; |
| 251 | |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 252 | /* Exceptions error codes */ |
| 253 | enum { |
| 254 | /* Exception subtypes for POWERPC_EXCP_ALIGN */ |
| 255 | POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
| 256 | POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
| 257 | POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
| 258 | POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
| 259 | POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
| 260 | POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
| 261 | /* Exception subtypes for POWERPC_EXCP_PROGRAM */ |
| 262 | /* FP exceptions */ |
| 263 | POWERPC_EXCP_FP = 0x10, |
| 264 | POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */ |
| 265 | POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */ |
| 266 | POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
| 267 | POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 268 | POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 269 | POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ |
| 270 | POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
| 271 | POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
| 272 | POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
| 273 | POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
| 274 | POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
| 275 | POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
| 276 | POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
| 277 | /* Invalid instruction */ |
| 278 | POWERPC_EXCP_INVAL = 0x20, |
| 279 | POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
| 280 | POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
| 281 | POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
| 282 | POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
| 283 | /* Privileged instruction */ |
| 284 | POWERPC_EXCP_PRIV = 0x30, |
| 285 | POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ |
| 286 | POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */ |
| 287 | /* Trap */ |
| 288 | POWERPC_EXCP_TRAP = 0x40, |
| 289 | }; |
| 290 | |
| 291 | /*****************************************************************************/ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 292 | /* Input pins model */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 293 | typedef enum powerpc_input_t powerpc_input_t; |
| 294 | enum powerpc_input_t { |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 295 | PPC_FLAGS_INPUT_UNKNOWN = 0, |
| 296 | /* PowerPC 6xx bus */ |
| 297 | PPC_FLAGS_INPUT_6xx, |
| 298 | /* BookE bus */ |
| 299 | PPC_FLAGS_INPUT_BookE, |
| 300 | /* PowerPC 405 bus */ |
| 301 | PPC_FLAGS_INPUT_405, |
| 302 | /* PowerPC 970 bus */ |
| 303 | PPC_FLAGS_INPUT_970, |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 304 | /* PowerPC POWER7 bus */ |
| 305 | PPC_FLAGS_INPUT_POWER7, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 306 | /* PowerPC 401 bus */ |
| 307 | PPC_FLAGS_INPUT_401, |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 308 | /* Freescale RCPU bus */ |
| 309 | PPC_FLAGS_INPUT_RCPU, |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 310 | }; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 311 | |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 312 | #define PPC_INPUT(env) (env->bus_model) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 313 | |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 314 | /*****************************************************************************/ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 315 | typedef struct opc_handler_t opc_handler_t; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 316 | |
| 317 | /*****************************************************************************/ |
| 318 | /* Types used to describe some PowerPC registers */ |
| 319 | typedef struct CPUPPCState CPUPPCState; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 320 | typedef struct ppc_tb_t ppc_tb_t; |
| 321 | typedef struct ppc_spr_t ppc_spr_t; |
| 322 | typedef struct ppc_dcr_t ppc_dcr_t; |
| 323 | typedef union ppc_avr_t ppc_avr_t; |
| 324 | typedef union ppc_tlb_t ppc_tlb_t; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 325 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 326 | /* SPR access micro-ops generations callbacks */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 327 | struct ppc_spr_t { |
aurel32 | 45d827d | 2008-12-07 13:40:29 +0000 | [diff] [blame] | 328 | void (*uea_read)(void *opaque, int gpr_num, int spr_num); |
| 329 | void (*uea_write)(void *opaque, int spr_num, int gpr_num); |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 330 | #if !defined(CONFIG_USER_ONLY) |
aurel32 | 45d827d | 2008-12-07 13:40:29 +0000 | [diff] [blame] | 331 | void (*oea_read)(void *opaque, int gpr_num, int spr_num); |
| 332 | void (*oea_write)(void *opaque, int spr_num, int gpr_num); |
| 333 | void (*hea_read)(void *opaque, int gpr_num, int spr_num); |
| 334 | void (*hea_write)(void *opaque, int spr_num, int gpr_num); |
j_mayer | be147d0 | 2007-09-30 13:03:23 +0000 | [diff] [blame] | 335 | #endif |
blueswir1 | b55266b | 2008-09-20 08:07:15 +0000 | [diff] [blame] | 336 | const char *name; |
Alexey Kardashevskiy | d197fdb | 2014-03-20 00:03:57 +1100 | [diff] [blame] | 337 | target_ulong default_value; |
David Gibson | d67d40e | 2013-02-20 16:41:50 +0000 | [diff] [blame] | 338 | #ifdef CONFIG_KVM |
| 339 | /* We (ab)use the fact that all the SPRs will have ids for the |
| 340 | * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning, |
| 341 | * don't sync this */ |
| 342 | uint64_t one_reg_id; |
| 343 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 344 | }; |
| 345 | |
| 346 | /* Altivec registers (128 bits) */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 347 | union ppc_avr_t { |
aurel32 | 0f6fbcb | 2009-02-03 19:55:43 +0000 | [diff] [blame] | 348 | float32 f[4]; |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 349 | uint8_t u8[16]; |
| 350 | uint16_t u16[8]; |
| 351 | uint32_t u32[4]; |
aurel32 | ab5f265 | 2008-12-15 07:03:06 +0000 | [diff] [blame] | 352 | int8_t s8[16]; |
| 353 | int16_t s16[8]; |
| 354 | int32_t s32[4]; |
j_mayer | a9d9eb8 | 2007-10-07 18:19:26 +0000 | [diff] [blame] | 355 | uint64_t u64[2]; |
Tom Musta | bb52753 | 2014-02-12 15:22:53 -0600 | [diff] [blame] | 356 | int64_t s64[2]; |
| 357 | #ifdef CONFIG_INT128 |
| 358 | __uint128_t u128; |
| 359 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 360 | }; |
| 361 | |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 362 | #if !defined(CONFIG_USER_ONLY) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 363 | /* Software TLB cache */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 364 | typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; |
| 365 | struct ppc6xx_tlb_t { |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 366 | target_ulong pte0; |
| 367 | target_ulong pte1; |
| 368 | target_ulong EPN; |
j_mayer | 1d0a48f | 2007-03-31 11:10:49 +0000 | [diff] [blame] | 369 | }; |
| 370 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 371 | typedef struct ppcemb_tlb_t ppcemb_tlb_t; |
| 372 | struct ppcemb_tlb_t { |
David Gibson | b162d02 | 2012-12-03 16:42:14 +0000 | [diff] [blame] | 373 | uint64_t RPN; |
j_mayer | 1d0a48f | 2007-03-31 11:10:49 +0000 | [diff] [blame] | 374 | target_ulong EPN; |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 375 | target_ulong PID; |
j_mayer | c55e9ae | 2007-04-16 09:21:46 +0000 | [diff] [blame] | 376 | target_ulong size; |
| 377 | uint32_t prot; |
| 378 | uint32_t attr; /* Storage attributes */ |
j_mayer | 1d0a48f | 2007-03-31 11:10:49 +0000 | [diff] [blame] | 379 | }; |
| 380 | |
Alexander Graf | d1e256f | 2011-06-16 18:45:43 +0200 | [diff] [blame] | 381 | typedef struct ppcmas_tlb_t { |
| 382 | uint32_t mas8; |
| 383 | uint32_t mas1; |
| 384 | uint64_t mas2; |
| 385 | uint64_t mas7_3; |
| 386 | } ppcmas_tlb_t; |
| 387 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 388 | union ppc_tlb_t { |
Alexander Graf | 1c53acc | 2011-06-17 01:00:28 +0200 | [diff] [blame] | 389 | ppc6xx_tlb_t *tlb6; |
| 390 | ppcemb_tlb_t *tlbe; |
| 391 | ppcmas_tlb_t *tlbm; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 392 | }; |
Alexander Graf | 1c53acc | 2011-06-17 01:00:28 +0200 | [diff] [blame] | 393 | |
| 394 | /* possible TLB variants */ |
| 395 | #define TLB_NONE 0 |
| 396 | #define TLB_6XX 1 |
| 397 | #define TLB_EMB 2 |
| 398 | #define TLB_MAS 3 |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 399 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 400 | |
David Gibson | bb59390 | 2011-04-01 15:15:15 +1100 | [diff] [blame] | 401 | #define SDR_32_HTABORG 0xFFFF0000UL |
| 402 | #define SDR_32_HTABMASK 0x000001FFUL |
| 403 | |
| 404 | #if defined(TARGET_PPC64) |
| 405 | #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL |
| 406 | #define SDR_64_HTABSIZE 0x000000000000001FULL |
| 407 | #endif /* defined(TARGET_PPC64 */ |
| 408 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 409 | typedef struct ppc_slb_t ppc_slb_t; |
| 410 | struct ppc_slb_t { |
David Gibson | 81762d6 | 2011-04-01 15:15:08 +1100 | [diff] [blame] | 411 | uint64_t esid; |
| 412 | uint64_t vsid; |
blueswir1 | 8eee0af | 2009-03-07 20:57:42 +0000 | [diff] [blame] | 413 | }; |
| 414 | |
Aneesh Kumar K.V | d83af16 | 2013-10-01 21:49:31 +0530 | [diff] [blame] | 415 | #define MAX_SLB_ENTRIES 64 |
David Gibson | 81762d6 | 2011-04-01 15:15:08 +1100 | [diff] [blame] | 416 | #define SEGMENT_SHIFT_256M 28 |
| 417 | #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1)) |
| 418 | |
David Gibson | cdaee00 | 2011-04-01 15:15:18 +1100 | [diff] [blame] | 419 | #define SEGMENT_SHIFT_1T 40 |
| 420 | #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1)) |
| 421 | |
| 422 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 423 | /*****************************************************************************/ |
| 424 | /* Machine state register bits definition */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 425 | #define MSR_SF 63 /* Sixty-four-bit mode hflags */ |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 426 | #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 427 | #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 428 | #define MSR_SHV 60 /* hypervisor state hflags */ |
j_mayer | 363be49 | 2007-03-30 10:07:33 +0000 | [diff] [blame] | 429 | #define MSR_CM 31 /* Computation mode for BookE hflags */ |
| 430 | #define MSR_ICM 30 /* Interrupt computation mode for BookE */ |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 431 | #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */ |
Alexander Graf | 71afeb6 | 2011-04-30 23:34:56 +0200 | [diff] [blame] | 432 | #define MSR_GS 28 /* guest state for BookE */ |
j_mayer | 363be49 | 2007-03-30 10:07:33 +0000 | [diff] [blame] | 433 | #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 434 | #define MSR_VR 25 /* altivec available x hflags */ |
| 435 | #define MSR_SPE 25 /* SPE enable for BookE x hflags */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 436 | #define MSR_AP 23 /* Access privilege state on 602 hflags */ |
Tom Musta | 1f29871 | 2013-10-22 22:06:17 +1100 | [diff] [blame] | 437 | #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 438 | #define MSR_SA 22 /* Supervisor access mode on 602 hflags */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 439 | #define MSR_KEY 19 /* key bit on 603e */ |
j_mayer | 25ba3a6 | 2007-10-08 02:58:07 +0000 | [diff] [blame] | 440 | #define MSR_POW 18 /* Power management */ |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 441 | #define MSR_TGPR 17 /* TGPR usage on 602/603 x */ |
| 442 | #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 443 | #define MSR_ILE 16 /* Interrupt little-endian mode */ |
| 444 | #define MSR_EE 15 /* External interrupt enable */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 445 | #define MSR_PR 14 /* Problem state hflags */ |
| 446 | #define MSR_FP 13 /* Floating point available hflags */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 447 | #define MSR_ME 12 /* Machine check interrupt enable */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 448 | #define MSR_FE0 11 /* Floating point exception mode 0 hflags */ |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 449 | #define MSR_SE 10 /* Single-step trace enable x hflags */ |
| 450 | #define MSR_DWE 10 /* Debug wait enable on 405 x */ |
| 451 | #define MSR_UBLE 10 /* User BTB lock enable on e500 x */ |
| 452 | #define MSR_BE 9 /* Branch trace enable x hflags */ |
| 453 | #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 454 | #define MSR_FE1 8 /* Floating point exception mode 1 hflags */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 455 | #define MSR_AL 7 /* AL bit on POWER */ |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 456 | #define MSR_EP 6 /* Exception prefix on 601 */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 457 | #define MSR_IR 5 /* Instruction relocate */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 458 | #define MSR_DR 4 /* Data relocate */ |
j_mayer | 25ba3a6 | 2007-10-08 02:58:07 +0000 | [diff] [blame] | 459 | #define MSR_PE 3 /* Protection enable on 403 */ |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 460 | #define MSR_PX 2 /* Protection exclusive on 403 x */ |
| 461 | #define MSR_PMM 2 /* Performance monitor mark on POWER x */ |
| 462 | #define MSR_RI 1 /* Recoverable interrupt 1 */ |
| 463 | #define MSR_LE 0 /* Little-endian mode 1 hflags */ |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 464 | |
Anton Blanchard | 1e0c7e5 | 2013-08-07 10:47:01 +1000 | [diff] [blame] | 465 | #define LPCR_ILE (1 << (63-38)) |
| 466 | |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 467 | #define msr_sf ((env->msr >> MSR_SF) & 1) |
| 468 | #define msr_isf ((env->msr >> MSR_ISF) & 1) |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 469 | #define msr_shv ((env->msr >> MSR_SHV) & 1) |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 470 | #define msr_cm ((env->msr >> MSR_CM) & 1) |
| 471 | #define msr_icm ((env->msr >> MSR_ICM) & 1) |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 472 | #define msr_thv ((env->msr >> MSR_THV) & 1) |
Alexander Graf | 71afeb6 | 2011-04-30 23:34:56 +0200 | [diff] [blame] | 473 | #define msr_gs ((env->msr >> MSR_GS) & 1) |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 474 | #define msr_ucle ((env->msr >> MSR_UCLE) & 1) |
| 475 | #define msr_vr ((env->msr >> MSR_VR) & 1) |
aurel32 | f932041 | 2008-05-06 14:58:15 +0000 | [diff] [blame] | 476 | #define msr_spe ((env->msr >> MSR_SPE) & 1) |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 477 | #define msr_ap ((env->msr >> MSR_AP) & 1) |
Tom Musta | 1f29871 | 2013-10-22 22:06:17 +1100 | [diff] [blame] | 478 | #define msr_vsx ((env->msr >> MSR_VSX) & 1) |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 479 | #define msr_sa ((env->msr >> MSR_SA) & 1) |
| 480 | #define msr_key ((env->msr >> MSR_KEY) & 1) |
| 481 | #define msr_pow ((env->msr >> MSR_POW) & 1) |
| 482 | #define msr_tgpr ((env->msr >> MSR_TGPR) & 1) |
| 483 | #define msr_ce ((env->msr >> MSR_CE) & 1) |
| 484 | #define msr_ile ((env->msr >> MSR_ILE) & 1) |
| 485 | #define msr_ee ((env->msr >> MSR_EE) & 1) |
| 486 | #define msr_pr ((env->msr >> MSR_PR) & 1) |
| 487 | #define msr_fp ((env->msr >> MSR_FP) & 1) |
| 488 | #define msr_me ((env->msr >> MSR_ME) & 1) |
| 489 | #define msr_fe0 ((env->msr >> MSR_FE0) & 1) |
| 490 | #define msr_se ((env->msr >> MSR_SE) & 1) |
| 491 | #define msr_dwe ((env->msr >> MSR_DWE) & 1) |
| 492 | #define msr_uble ((env->msr >> MSR_UBLE) & 1) |
| 493 | #define msr_be ((env->msr >> MSR_BE) & 1) |
| 494 | #define msr_de ((env->msr >> MSR_DE) & 1) |
| 495 | #define msr_fe1 ((env->msr >> MSR_FE1) & 1) |
| 496 | #define msr_al ((env->msr >> MSR_AL) & 1) |
| 497 | #define msr_ep ((env->msr >> MSR_EP) & 1) |
| 498 | #define msr_ir ((env->msr >> MSR_IR) & 1) |
| 499 | #define msr_dr ((env->msr >> MSR_DR) & 1) |
| 500 | #define msr_pe ((env->msr >> MSR_PE) & 1) |
| 501 | #define msr_px ((env->msr >> MSR_PX) & 1) |
| 502 | #define msr_pmm ((env->msr >> MSR_PMM) & 1) |
| 503 | #define msr_ri ((env->msr >> MSR_RI) & 1) |
| 504 | #define msr_le ((env->msr >> MSR_LE) & 1) |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 505 | /* Hypervisor bit is more specific */ |
| 506 | #if defined(TARGET_PPC64) |
| 507 | #define MSR_HVB (1ULL << MSR_SHV) |
| 508 | #define msr_hv msr_shv |
| 509 | #else |
| 510 | #if defined(PPC_EMULATE_32BITS_HYPV) |
| 511 | #define MSR_HVB (1ULL << MSR_THV) |
| 512 | #define msr_hv msr_thv |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 513 | #else |
| 514 | #define MSR_HVB (0ULL) |
| 515 | #define msr_hv (0) |
| 516 | #endif |
| 517 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 518 | |
Edgar E. Iglesias | a586e54 | 2010-09-20 19:06:32 +0200 | [diff] [blame] | 519 | /* Exception state register bits definition */ |
Alexander Graf | 542df9b | 2011-08-23 06:55:42 +0200 | [diff] [blame] | 520 | #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */ |
| 521 | #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */ |
| 522 | #define ESR_PTR (1 << (63 - 38)) /* Trap */ |
| 523 | #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */ |
| 524 | #define ESR_ST (1 << (63 - 40)) /* Store Operation */ |
| 525 | #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */ |
| 526 | #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */ |
| 527 | #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */ |
| 528 | #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */ |
| 529 | #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */ |
| 530 | #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */ |
| 531 | #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */ |
| 532 | #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */ |
| 533 | #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */ |
| 534 | #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */ |
| 535 | #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */ |
Edgar E. Iglesias | a586e54 | 2010-09-20 19:06:32 +0200 | [diff] [blame] | 536 | |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 537 | enum { |
j_mayer | 4018bae | 2007-11-19 01:48:12 +0000 | [diff] [blame] | 538 | POWERPC_FLAG_NONE = 0x00000000, |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 539 | /* Flag for MSR bit 25 signification (VRE/SPE) */ |
j_mayer | 4018bae | 2007-11-19 01:48:12 +0000 | [diff] [blame] | 540 | POWERPC_FLAG_SPE = 0x00000001, |
| 541 | POWERPC_FLAG_VRE = 0x00000002, |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 542 | /* Flag for MSR bit 17 signification (TGPR/CE) */ |
j_mayer | 4018bae | 2007-11-19 01:48:12 +0000 | [diff] [blame] | 543 | POWERPC_FLAG_TGPR = 0x00000004, |
| 544 | POWERPC_FLAG_CE = 0x00000008, |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 545 | /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */ |
j_mayer | 4018bae | 2007-11-19 01:48:12 +0000 | [diff] [blame] | 546 | POWERPC_FLAG_SE = 0x00000010, |
| 547 | POWERPC_FLAG_DWE = 0x00000020, |
| 548 | POWERPC_FLAG_UBLE = 0x00000040, |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 549 | /* Flag for MSR bit 9 signification (BE/DE) */ |
j_mayer | 4018bae | 2007-11-19 01:48:12 +0000 | [diff] [blame] | 550 | POWERPC_FLAG_BE = 0x00000080, |
| 551 | POWERPC_FLAG_DE = 0x00000100, |
j_mayer | a4f3071 | 2007-11-17 21:14:09 +0000 | [diff] [blame] | 552 | /* Flag for MSR bit 2 signification (PX/PMM) */ |
j_mayer | 4018bae | 2007-11-19 01:48:12 +0000 | [diff] [blame] | 553 | POWERPC_FLAG_PX = 0x00000200, |
| 554 | POWERPC_FLAG_PMM = 0x00000400, |
| 555 | /* Flag for special features */ |
| 556 | /* Decrementer clock: RTC clock (POWER, 601) or bus clock */ |
| 557 | POWERPC_FLAG_RTC_CLK = 0x00010000, |
| 558 | POWERPC_FLAG_BUS_CLK = 0x00020000, |
David Gibson | 697ab89 | 2011-08-31 15:45:10 +0000 | [diff] [blame] | 559 | /* Has CFAR */ |
| 560 | POWERPC_FLAG_CFAR = 0x00040000, |
Tom Musta | 74f2399 | 2013-10-22 22:05:46 +1100 | [diff] [blame] | 561 | /* Has VSX */ |
| 562 | POWERPC_FLAG_VSX = 0x00080000, |
j_mayer | d26bfc9 | 2007-10-07 14:41:00 +0000 | [diff] [blame] | 563 | }; |
| 564 | |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 565 | /*****************************************************************************/ |
| 566 | /* Floating point status and control register */ |
| 567 | #define FPSCR_FX 31 /* Floating-point exception summary */ |
| 568 | #define FPSCR_FEX 30 /* Floating-point enabled exception summary */ |
| 569 | #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */ |
| 570 | #define FPSCR_OX 28 /* Floating-point overflow exception */ |
| 571 | #define FPSCR_UX 27 /* Floating-point underflow exception */ |
| 572 | #define FPSCR_ZX 26 /* Floating-point zero divide exception */ |
| 573 | #define FPSCR_XX 25 /* Floating-point inexact exception */ |
| 574 | #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */ |
| 575 | #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */ |
| 576 | #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */ |
| 577 | #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */ |
| 578 | #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */ |
| 579 | #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */ |
| 580 | #define FPSCR_FR 18 /* Floating-point fraction rounded */ |
| 581 | #define FPSCR_FI 17 /* Floating-point fraction inexact */ |
| 582 | #define FPSCR_C 16 /* Floating-point result class descriptor */ |
| 583 | #define FPSCR_FL 15 /* Floating-point less than or negative */ |
| 584 | #define FPSCR_FG 14 /* Floating-point greater than or negative */ |
| 585 | #define FPSCR_FE 13 /* Floating-point equal or zero */ |
| 586 | #define FPSCR_FU 12 /* Floating-point unordered or NaN */ |
| 587 | #define FPSCR_FPCC 12 /* Floating-point condition code */ |
| 588 | #define FPSCR_FPRF 12 /* Floating-point result flags */ |
| 589 | #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */ |
| 590 | #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */ |
| 591 | #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */ |
| 592 | #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */ |
| 593 | #define FPSCR_OE 6 /* Floating-point overflow exception enable */ |
| 594 | #define FPSCR_UE 5 /* Floating-point undeflow exception enable */ |
| 595 | #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */ |
| 596 | #define FPSCR_XE 3 /* Floating-point inexact exception enable */ |
| 597 | #define FPSCR_NI 2 /* Floating-point non-IEEE mode */ |
| 598 | #define FPSCR_RN1 1 |
| 599 | #define FPSCR_RN 0 /* Floating-point rounding control */ |
| 600 | #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1) |
| 601 | #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1) |
| 602 | #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1) |
| 603 | #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1) |
| 604 | #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1) |
| 605 | #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1) |
| 606 | #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1) |
| 607 | #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1) |
| 608 | #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1) |
| 609 | #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1) |
| 610 | #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1) |
| 611 | #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1) |
| 612 | #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF) |
| 613 | #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1) |
| 614 | #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1) |
| 615 | #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1) |
| 616 | #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1) |
| 617 | #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1) |
| 618 | #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1) |
| 619 | #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1) |
| 620 | #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1) |
| 621 | #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1) |
| 622 | #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3) |
| 623 | /* Invalid operation exception summary */ |
| 624 | #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \ |
| 625 | (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \ |
| 626 | (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \ |
| 627 | (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \ |
| 628 | (1 << FPSCR_VXCVI))) |
| 629 | /* exception summary */ |
| 630 | #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F) |
| 631 | /* enabled exception summary */ |
| 632 | #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \ |
| 633 | 0x1F) |
| 634 | |
| 635 | /*****************************************************************************/ |
aurel32 | 6fa724a | 2009-01-03 14:04:11 +0000 | [diff] [blame] | 636 | /* Vector status and control register */ |
| 637 | #define VSCR_NJ 16 /* Vector non-java */ |
| 638 | #define VSCR_SAT 0 /* Vector saturation */ |
| 639 | #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1) |
| 640 | #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1) |
| 641 | |
| 642 | /*****************************************************************************/ |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 643 | /* BookE e500 MMU registers */ |
| 644 | |
| 645 | #define MAS0_NV_SHIFT 0 |
| 646 | #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT) |
| 647 | |
| 648 | #define MAS0_WQ_SHIFT 12 |
| 649 | #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT) |
| 650 | /* Write TLB entry regardless of reservation */ |
| 651 | #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT) |
| 652 | /* Write TLB entry only already in use */ |
| 653 | #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT) |
| 654 | /* Clear TLB entry */ |
| 655 | #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT) |
| 656 | |
| 657 | #define MAS0_HES_SHIFT 14 |
| 658 | #define MAS0_HES (1 << MAS0_HES_SHIFT) |
| 659 | |
| 660 | #define MAS0_ESEL_SHIFT 16 |
| 661 | #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT) |
| 662 | |
| 663 | #define MAS0_TLBSEL_SHIFT 28 |
| 664 | #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT) |
| 665 | #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT) |
| 666 | #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT) |
| 667 | #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT) |
| 668 | #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT) |
| 669 | |
| 670 | #define MAS0_ATSEL_SHIFT 31 |
| 671 | #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT) |
| 672 | #define MAS0_ATSEL_TLB 0 |
| 673 | #define MAS0_ATSEL_LRAT MAS0_ATSEL |
| 674 | |
Scott Wood | 2bd9543 | 2011-08-18 10:38:40 +0000 | [diff] [blame] | 675 | #define MAS1_TSIZE_SHIFT 7 |
| 676 | #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT) |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 677 | |
| 678 | #define MAS1_TS_SHIFT 12 |
| 679 | #define MAS1_TS (1 << MAS1_TS_SHIFT) |
| 680 | |
| 681 | #define MAS1_IND_SHIFT 13 |
| 682 | #define MAS1_IND (1 << MAS1_IND_SHIFT) |
| 683 | |
| 684 | #define MAS1_TID_SHIFT 16 |
| 685 | #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT) |
| 686 | |
| 687 | #define MAS1_IPROT_SHIFT 30 |
| 688 | #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT) |
| 689 | |
| 690 | #define MAS1_VALID_SHIFT 31 |
| 691 | #define MAS1_VALID 0x80000000 |
| 692 | |
| 693 | #define MAS2_EPN_SHIFT 12 |
Alexander Graf | 9609169 | 2012-06-21 13:34:20 +0200 | [diff] [blame] | 694 | #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT) |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 695 | |
| 696 | #define MAS2_ACM_SHIFT 6 |
| 697 | #define MAS2_ACM (1 << MAS2_ACM_SHIFT) |
| 698 | |
| 699 | #define MAS2_VLE_SHIFT 5 |
| 700 | #define MAS2_VLE (1 << MAS2_VLE_SHIFT) |
| 701 | |
| 702 | #define MAS2_W_SHIFT 4 |
| 703 | #define MAS2_W (1 << MAS2_W_SHIFT) |
| 704 | |
| 705 | #define MAS2_I_SHIFT 3 |
| 706 | #define MAS2_I (1 << MAS2_I_SHIFT) |
| 707 | |
| 708 | #define MAS2_M_SHIFT 2 |
| 709 | #define MAS2_M (1 << MAS2_M_SHIFT) |
| 710 | |
| 711 | #define MAS2_G_SHIFT 1 |
| 712 | #define MAS2_G (1 << MAS2_G_SHIFT) |
| 713 | |
| 714 | #define MAS2_E_SHIFT 0 |
| 715 | #define MAS2_E (1 << MAS2_E_SHIFT) |
| 716 | |
| 717 | #define MAS3_RPN_SHIFT 12 |
| 718 | #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT) |
| 719 | |
| 720 | #define MAS3_U0 0x00000200 |
| 721 | #define MAS3_U1 0x00000100 |
| 722 | #define MAS3_U2 0x00000080 |
| 723 | #define MAS3_U3 0x00000040 |
| 724 | #define MAS3_UX 0x00000020 |
| 725 | #define MAS3_SX 0x00000010 |
| 726 | #define MAS3_UW 0x00000008 |
| 727 | #define MAS3_SW 0x00000004 |
| 728 | #define MAS3_UR 0x00000002 |
| 729 | #define MAS3_SR 0x00000001 |
| 730 | #define MAS3_SPSIZE_SHIFT 1 |
| 731 | #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT) |
| 732 | |
| 733 | #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT |
| 734 | #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK |
| 735 | #define MAS4_TIDSELD_MASK 0x00030000 |
| 736 | #define MAS4_TIDSELD_PID0 0x00000000 |
| 737 | #define MAS4_TIDSELD_PID1 0x00010000 |
| 738 | #define MAS4_TIDSELD_PID2 0x00020000 |
| 739 | #define MAS4_TIDSELD_PIDZ 0x00030000 |
| 740 | #define MAS4_INDD 0x00008000 /* Default IND */ |
| 741 | #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT |
| 742 | #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK |
| 743 | #define MAS4_ACMD 0x00000040 |
| 744 | #define MAS4_VLED 0x00000020 |
| 745 | #define MAS4_WD 0x00000010 |
| 746 | #define MAS4_ID 0x00000008 |
| 747 | #define MAS4_MD 0x00000004 |
| 748 | #define MAS4_GD 0x00000002 |
| 749 | #define MAS4_ED 0x00000001 |
| 750 | #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */ |
| 751 | #define MAS4_WIMGED_SHIFT 0 |
| 752 | |
| 753 | #define MAS5_SGS 0x80000000 |
| 754 | #define MAS5_SLPID_MASK 0x00000fff |
| 755 | |
| 756 | #define MAS6_SPID0 0x3fff0000 |
| 757 | #define MAS6_SPID1 0x00007ffe |
| 758 | #define MAS6_ISIZE(x) MAS1_TSIZE(x) |
| 759 | #define MAS6_SAS 0x00000001 |
| 760 | #define MAS6_SPID MAS6_SPID0 |
| 761 | #define MAS6_SIND 0x00000002 /* Indirect page */ |
| 762 | #define MAS6_SIND_SHIFT 1 |
| 763 | #define MAS6_SPID_MASK 0x3fff0000 |
| 764 | #define MAS6_SPID_SHIFT 16 |
| 765 | #define MAS6_ISIZE_MASK 0x00000f80 |
| 766 | #define MAS6_ISIZE_SHIFT 7 |
| 767 | |
| 768 | #define MAS7_RPN 0xffffffff |
| 769 | |
| 770 | #define MAS8_TGS 0x80000000 |
| 771 | #define MAS8_VF 0x40000000 |
| 772 | #define MAS8_TLBPID 0x00000fff |
| 773 | |
| 774 | /* Bit definitions for MMUCFG */ |
| 775 | #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ |
| 776 | #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */ |
| 777 | #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */ |
| 778 | #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */ |
| 779 | #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */ |
| 780 | #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */ |
| 781 | #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */ |
| 782 | #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */ |
| 783 | #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */ |
| 784 | |
| 785 | /* Bit definitions for MMUCSR0 */ |
| 786 | #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */ |
| 787 | #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */ |
| 788 | #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */ |
| 789 | #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */ |
| 790 | #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \ |
| 791 | MMUCSR0_TLB2FI | MMUCSR0_TLB3FI) |
| 792 | #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */ |
| 793 | #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */ |
| 794 | #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */ |
| 795 | #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */ |
| 796 | |
| 797 | /* TLBnCFG encoding */ |
| 798 | #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */ |
| 799 | #define TLBnCFG_HES 0x00002000 /* HW select supported */ |
| 800 | #define TLBnCFG_AVAIL 0x00004000 /* variable page size */ |
| 801 | #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */ |
| 802 | #define TLBnCFG_GTWE 0x00010000 /* Guest can write */ |
| 803 | #define TLBnCFG_IND 0x00020000 /* IND entries supported */ |
| 804 | #define TLBnCFG_PT 0x00040000 /* Can load from page table */ |
| 805 | #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */ |
| 806 | #define TLBnCFG_MINSIZE_SHIFT 20 |
| 807 | #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */ |
| 808 | #define TLBnCFG_MAXSIZE_SHIFT 16 |
| 809 | #define TLBnCFG_ASSOC 0xff000000 /* Associativity */ |
| 810 | #define TLBnCFG_ASSOC_SHIFT 24 |
| 811 | |
| 812 | /* TLBnPS encoding */ |
| 813 | #define TLBnPS_4K 0x00000004 |
| 814 | #define TLBnPS_8K 0x00000008 |
| 815 | #define TLBnPS_16K 0x00000010 |
| 816 | #define TLBnPS_32K 0x00000020 |
| 817 | #define TLBnPS_64K 0x00000040 |
| 818 | #define TLBnPS_128K 0x00000080 |
| 819 | #define TLBnPS_256K 0x00000100 |
| 820 | #define TLBnPS_512K 0x00000200 |
| 821 | #define TLBnPS_1M 0x00000400 |
| 822 | #define TLBnPS_2M 0x00000800 |
| 823 | #define TLBnPS_4M 0x00001000 |
| 824 | #define TLBnPS_8M 0x00002000 |
| 825 | #define TLBnPS_16M 0x00004000 |
| 826 | #define TLBnPS_32M 0x00008000 |
| 827 | #define TLBnPS_64M 0x00010000 |
| 828 | #define TLBnPS_128M 0x00020000 |
| 829 | #define TLBnPS_256M 0x00040000 |
| 830 | #define TLBnPS_512M 0x00080000 |
| 831 | #define TLBnPS_1G 0x00100000 |
| 832 | #define TLBnPS_2G 0x00200000 |
| 833 | #define TLBnPS_4G 0x00400000 |
| 834 | #define TLBnPS_8G 0x00800000 |
| 835 | #define TLBnPS_16G 0x01000000 |
| 836 | #define TLBnPS_32G 0x02000000 |
| 837 | #define TLBnPS_64G 0x04000000 |
| 838 | #define TLBnPS_128G 0x08000000 |
| 839 | #define TLBnPS_256G 0x10000000 |
| 840 | |
| 841 | /* tlbilx action encoding */ |
| 842 | #define TLBILX_T_ALL 0 |
| 843 | #define TLBILX_T_TID 1 |
| 844 | #define TLBILX_T_FULLMATCH 3 |
| 845 | #define TLBILX_T_CLASS0 4 |
| 846 | #define TLBILX_T_CLASS1 5 |
| 847 | #define TLBILX_T_CLASS2 6 |
| 848 | #define TLBILX_T_CLASS3 7 |
| 849 | |
| 850 | /* BookE 2.06 helper defines */ |
| 851 | |
| 852 | #define BOOKE206_FLUSH_TLB0 (1 << 0) |
| 853 | #define BOOKE206_FLUSH_TLB1 (1 << 1) |
| 854 | #define BOOKE206_FLUSH_TLB2 (1 << 2) |
| 855 | #define BOOKE206_FLUSH_TLB3 (1 << 3) |
| 856 | |
| 857 | /* number of possible TLBs */ |
| 858 | #define BOOKE206_MAX_TLBN 4 |
| 859 | |
| 860 | /*****************************************************************************/ |
Alexander Graf | 58e00a2 | 2012-01-31 03:11:32 +0100 | [diff] [blame] | 861 | /* Embedded.Processor Control */ |
| 862 | |
| 863 | #define DBELL_TYPE_SHIFT 27 |
| 864 | #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT) |
| 865 | #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT) |
| 866 | #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT) |
| 867 | #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT) |
| 868 | #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT) |
| 869 | #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT) |
| 870 | |
| 871 | #define DBELL_BRDCAST (1 << 26) |
| 872 | #define DBELL_LPIDTAG_SHIFT 14 |
| 873 | #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT) |
| 874 | #define DBELL_PIRTAG_MASK 0x3fff |
| 875 | |
| 876 | /*****************************************************************************/ |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 877 | /* Segment page size information, used by recent hash MMUs |
| 878 | * The format of this structure mirrors kvm_ppc_smmu_info |
| 879 | */ |
| 880 | |
| 881 | #define PPC_PAGE_SIZES_MAX_SZ 8 |
| 882 | |
| 883 | struct ppc_one_page_size { |
| 884 | uint32_t page_shift; /* Page shift (or 0) */ |
| 885 | uint32_t pte_enc; /* Encoding in the HPTE (>>12) */ |
| 886 | }; |
| 887 | |
| 888 | struct ppc_one_seg_page_size { |
| 889 | uint32_t page_shift; /* Base page shift of segment (or 0) */ |
| 890 | uint32_t slb_enc; /* SLB encoding for BookS */ |
| 891 | struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ]; |
| 892 | }; |
| 893 | |
| 894 | struct ppc_segment_page_sizes { |
| 895 | struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ]; |
| 896 | }; |
| 897 | |
| 898 | |
| 899 | /*****************************************************************************/ |
j_mayer | 7c58044 | 2007-10-27 17:54:30 +0000 | [diff] [blame] | 900 | /* The whole PowerPC CPU context */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 901 | #define NB_MMU_MODES 3 |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 902 | |
Andreas Färber | b048960 | 2013-06-09 22:11:49 +0200 | [diff] [blame] | 903 | #define PPC_CPU_OPCODES_LEN 0x40 |
| 904 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 905 | struct CPUPPCState { |
| 906 | /* First are the most commonly used resources |
| 907 | * during translated code execution |
| 908 | */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 909 | /* general purpose registers */ |
aurel32 | bd7d9a6 | 2008-09-04 05:26:09 +0000 | [diff] [blame] | 910 | target_ulong gpr[32]; |
j_mayer | 65d6c0f | 2007-11-12 23:29:14 +0000 | [diff] [blame] | 911 | #if !defined(TARGET_PPC64) |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 912 | /* Storage for GPR MSB, used by the SPE extension */ |
aurel32 | bd7d9a6 | 2008-09-04 05:26:09 +0000 | [diff] [blame] | 913 | target_ulong gprh[32]; |
j_mayer | 3cd7d1d | 2007-11-12 01:56:18 +0000 | [diff] [blame] | 914 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 915 | /* LR */ |
| 916 | target_ulong lr; |
| 917 | /* CTR */ |
| 918 | target_ulong ctr; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 919 | /* condition register */ |
aurel32 | 47e4661 | 2008-09-04 17:06:47 +0000 | [diff] [blame] | 920 | uint32_t crf[8]; |
David Gibson | 697ab89 | 2011-08-31 15:45:10 +0000 | [diff] [blame] | 921 | #if defined(TARGET_PPC64) |
| 922 | /* CFAR */ |
| 923 | target_ulong cfar; |
| 924 | #endif |
Richard Henderson | da91a00 | 2013-02-19 23:52:13 -0800 | [diff] [blame] | 925 | /* XER (with SO, OV, CA split out) */ |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 926 | target_ulong xer; |
Richard Henderson | da91a00 | 2013-02-19 23:52:13 -0800 | [diff] [blame] | 927 | target_ulong so; |
| 928 | target_ulong ov; |
| 929 | target_ulong ca; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 930 | /* Reservation address */ |
Nathan Froyd | 18b21a2 | 2009-08-03 08:43:25 -0700 | [diff] [blame] | 931 | target_ulong reserve_addr; |
| 932 | /* Reservation value */ |
| 933 | target_ulong reserve_val; |
Tom Musta | 9c294d5 | 2014-02-10 11:27:00 -0600 | [diff] [blame] | 934 | target_ulong reserve_val2; |
Nathan Froyd | 4425265 | 2009-08-03 08:43:26 -0700 | [diff] [blame] | 935 | /* Reservation store address */ |
| 936 | target_ulong reserve_ea; |
| 937 | /* Reserved store source register and size */ |
| 938 | target_ulong reserve_info; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 939 | |
| 940 | /* Those ones are used in supervisor mode only */ |
| 941 | /* machine state register */ |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 942 | target_ulong msr; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 943 | /* temporary general purpose registers */ |
aurel32 | bd7d9a6 | 2008-09-04 05:26:09 +0000 | [diff] [blame] | 944 | target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 945 | |
| 946 | /* Floating point execution context */ |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 947 | float_status fp_status; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 948 | /* floating point registers */ |
| 949 | float64 fpr[32]; |
| 950 | /* floating point status and control register */ |
David Gibson | 3030442 | 2012-10-29 17:24:59 +0000 | [diff] [blame] | 951 | target_ulong fpscr; |
bellard | 4ecc319 | 2005-03-13 17:01:22 +0000 | [diff] [blame] | 952 | |
Aurelien Jarno | cb2dbfc | 2009-10-22 14:55:37 +0200 | [diff] [blame] | 953 | /* Next instruction pointer */ |
| 954 | target_ulong nip; |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 955 | |
bellard | ac9eb07 | 2004-01-04 23:26:24 +0000 | [diff] [blame] | 956 | int access_type; /* when a memory exception occurs, the access |
| 957 | type is stored here */ |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 958 | |
Aurelien Jarno | cb2dbfc | 2009-10-22 14:55:37 +0200 | [diff] [blame] | 959 | CPU_COMMON |
| 960 | |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 961 | /* MMU context - only relevant for full system emulation */ |
| 962 | #if !defined(CONFIG_USER_ONLY) |
| 963 | #if defined(TARGET_PPC64) |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 964 | /* PowerPC 64 SLB area */ |
Aneesh Kumar K.V | d83af16 | 2013-10-01 21:49:31 +0530 | [diff] [blame] | 965 | ppc_slb_t slb[MAX_SLB_ENTRIES]; |
Alexey Kardashevskiy | a90db15 | 2013-07-18 14:32:54 -0500 | [diff] [blame] | 966 | int32_t slb_nr; |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 967 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 968 | /* segment registers */ |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 969 | hwaddr htab_base; |
Aneesh Kumar K.V | f3c75d4 | 2014-02-20 18:52:17 +0100 | [diff] [blame] | 970 | /* mask used to normalize hash value to PTEG index */ |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 971 | hwaddr htab_mask; |
aurel32 | 74d3779 | 2008-12-06 21:46:17 +0000 | [diff] [blame] | 972 | target_ulong sr[32]; |
David Gibson | f43e352 | 2011-04-01 15:15:22 +1100 | [diff] [blame] | 973 | /* externally stored hash table */ |
| 974 | uint8_t *external_htab; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 975 | /* BATs */ |
Alexey Kardashevskiy | a90db15 | 2013-07-18 14:32:54 -0500 | [diff] [blame] | 976 | uint32_t nb_BATs; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 977 | target_ulong DBAT[2][8]; |
| 978 | target_ulong IBAT[2][8]; |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 979 | /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */ |
Alexey Kardashevskiy | a90db15 | 2013-07-18 14:32:54 -0500 | [diff] [blame] | 980 | int32_t nb_tlb; /* Total number of TLB */ |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 981 | int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ |
| 982 | int nb_ways; /* Number of ways in the TLB set */ |
| 983 | int last_way; /* Last used way used to allocate TLB in a LRU way */ |
| 984 | int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ |
j_mayer | 363be49 | 2007-03-30 10:07:33 +0000 | [diff] [blame] | 985 | int nb_pids; /* Number of available PID registers */ |
Alexander Graf | 1c53acc | 2011-06-17 01:00:28 +0200 | [diff] [blame] | 986 | int tlb_type; /* Type of TLB we're dealing with */ |
| 987 | ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 988 | /* 403 dedicated access protection registers */ |
| 989 | target_ulong pb[4]; |
Scott Wood | 93dd5e8 | 2011-08-31 11:26:56 +0000 | [diff] [blame] | 990 | bool tlb_dirty; /* Set to non-zero when modifying TLB */ |
| 991 | bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */ |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 992 | #endif |
| 993 | |
| 994 | /* Other registers */ |
| 995 | /* Special purpose registers */ |
| 996 | target_ulong spr[1024]; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 997 | ppc_spr_t spr_cb[1024]; |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 998 | /* Altivec registers */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 999 | ppc_avr_t avr[32]; |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 1000 | uint32_t vscr; |
David Gibson | 3030442 | 2012-10-29 17:24:59 +0000 | [diff] [blame] | 1001 | /* VSX registers */ |
| 1002 | uint64_t vsr[32]; |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 1003 | /* SPE registers */ |
aurel32 | 2231ef1 | 2008-12-18 22:43:25 +0000 | [diff] [blame] | 1004 | uint64_t spe_acc; |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 1005 | uint32_t spe_fscr; |
aurel32 | fbd265b | 2009-02-03 19:55:51 +0000 | [diff] [blame] | 1006 | /* SPE and Altivec can share a status since they will never be used |
| 1007 | * simultaneously */ |
| 1008 | float_status vec_status; |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 1009 | |
| 1010 | /* Internal devices resources */ |
| 1011 | /* Time base and decrementer */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1012 | ppc_tb_t *tb_env; |
j_mayer | f2e63a4 | 2007-10-07 15:43:50 +0000 | [diff] [blame] | 1013 | /* Device control registers */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1014 | ppc_dcr_t *dcr_env; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1015 | |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 1016 | int dcache_line_size; |
| 1017 | int icache_line_size; |
| 1018 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1019 | /* Those resources are used during exception processing */ |
| 1020 | /* CPU model definition */ |
j_mayer | a750fc0 | 2007-09-26 23:54:22 +0000 | [diff] [blame] | 1021 | target_ulong msr_mask; |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1022 | powerpc_mmu_t mmu_model; |
| 1023 | powerpc_excp_t excp_model; |
| 1024 | powerpc_input_t bus_model; |
j_mayer | 237c0af | 2007-09-29 12:01:46 +0000 | [diff] [blame] | 1025 | int bfd_mach; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1026 | uint32_t flags; |
Nathan Froyd | c29b735 | 2009-05-12 12:26:57 -0700 | [diff] [blame] | 1027 | uint64_t insns_flags; |
Alexander Graf | a5858d7 | 2011-05-01 00:00:58 +0200 | [diff] [blame] | 1028 | uint64_t insns_flags2; |
Benjamin Herrenschmidt | 4656e1f | 2012-06-18 19:56:25 +0000 | [diff] [blame] | 1029 | #if defined(TARGET_PPC64) |
| 1030 | struct ppc_segment_page_sizes sps; |
| 1031 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1032 | |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 1033 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) |
David Gibson | ac7d12b | 2012-10-29 17:24:58 +0000 | [diff] [blame] | 1034 | uint64_t vpa_addr; |
| 1035 | uint64_t slb_shadow_addr, slb_shadow_size; |
| 1036 | uint64_t dtl_addr, dtl_size; |
David Gibson | ed12005 | 2011-04-01 15:15:33 +1100 | [diff] [blame] | 1037 | #endif /* TARGET_PPC64 */ |
| 1038 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1039 | int error_code; |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 1040 | uint32_t pending_interrupts; |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 1041 | #if !defined(CONFIG_USER_ONLY) |
Dong Xu Wang | 4abf79a | 2011-11-22 18:06:21 +0800 | [diff] [blame] | 1042 | /* This is the IRQ controller, which is implementation dependent |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 1043 | * and only relevant when emulating a complete machine. |
| 1044 | */ |
| 1045 | uint32_t irq_input_state; |
| 1046 | void **irq_inputs; |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 1047 | /* Exception vectors */ |
| 1048 | target_ulong excp_vectors[POWERPC_EXCP_NB]; |
| 1049 | target_ulong excp_prefix; |
| 1050 | target_ulong ivor_mask; |
| 1051 | target_ulong ivpr_mask; |
j_mayer | d63001d | 2007-10-04 00:51:58 +0000 | [diff] [blame] | 1052 | target_ulong hreset_vector; |
Alexander Graf | 68c2dd7 | 2013-01-04 11:21:04 +0100 | [diff] [blame] | 1053 | hwaddr mpic_iack; |
| 1054 | /* true when the external proxy facility mode is enabled */ |
| 1055 | bool mpic_proxy; |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 1056 | #endif |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1057 | |
| 1058 | /* Those resources are used only during code translation */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1059 | /* opcode handlers */ |
Andreas Färber | b048960 | 2013-06-09 22:11:49 +0200 | [diff] [blame] | 1060 | opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN]; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1061 | |
Stefan Weil | 5cbdb3a | 2012-04-07 09:23:39 +0200 | [diff] [blame] | 1062 | /* Those resources are used only in QEMU core */ |
j_mayer | 056401e | 2007-11-04 02:55:33 +0000 | [diff] [blame] | 1063 | target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */ |
Dong Xu Wang | 4abf79a | 2011-11-22 18:06:21 +0800 | [diff] [blame] | 1064 | target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1065 | int mmu_idx; /* precomputed MMU index to speed up mem accesses */ |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1066 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1067 | /* Power management */ |
j_mayer | cd34634 | 2007-10-25 23:27:04 +0000 | [diff] [blame] | 1068 | int (*check_pow)(CPUPPCState *env); |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 1069 | |
Edgar E. Iglesias | 2c50e26 | 2010-09-29 15:31:44 +0200 | [diff] [blame] | 1070 | #if !defined(CONFIG_USER_ONLY) |
| 1071 | void *load_info; /* Holds boot loading state. */ |
| 1072 | #endif |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1073 | |
| 1074 | /* booke timers */ |
| 1075 | |
| 1076 | /* Specifies bit locations of the Time Base used to signal a fixed timer |
| 1077 | * exception on a transition from 0 to 1. (watchdog or fixed-interval timer) |
| 1078 | * |
| 1079 | * 0 selects the least significant bit. |
| 1080 | * 63 selects the most significant bit. |
| 1081 | */ |
| 1082 | uint8_t fit_period[4]; |
| 1083 | uint8_t wdt_period[4]; |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1084 | }; |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1085 | |
Fabien Chouteau | ddd1055 | 2011-09-13 04:00:32 +0000 | [diff] [blame] | 1086 | #define SET_FIT_PERIOD(a_, b_, c_, d_) \ |
| 1087 | do { \ |
| 1088 | env->fit_period[0] = (a_); \ |
| 1089 | env->fit_period[1] = (b_); \ |
| 1090 | env->fit_period[2] = (c_); \ |
| 1091 | env->fit_period[3] = (d_); \ |
| 1092 | } while (0) |
| 1093 | |
| 1094 | #define SET_WDT_PERIOD(a_, b_, c_, d_) \ |
| 1095 | do { \ |
| 1096 | env->wdt_period[0] = (a_); \ |
| 1097 | env->wdt_period[1] = (b_); \ |
| 1098 | env->wdt_period[2] = (c_); \ |
| 1099 | env->wdt_period[3] = (d_); \ |
| 1100 | } while (0) |
| 1101 | |
Andreas Färber | 1d0cb67 | 2012-04-06 14:39:03 +0200 | [diff] [blame] | 1102 | #include "cpu-qom.h" |
| 1103 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1104 | /*****************************************************************************/ |
Andreas Färber | 397b457 | 2012-05-03 05:43:05 +0200 | [diff] [blame] | 1105 | PowerPCCPU *cpu_ppc_init(const char *cpu_model); |
pbrook | 2e70f6e | 2008-06-29 01:03:05 +0000 | [diff] [blame] | 1106 | void ppc_translate_init(void); |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 1107 | int cpu_ppc_exec (CPUPPCState *s); |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1108 | /* you can call this signal handler from your SIGBUS and SIGSEGV |
| 1109 | signal handlers to inform the virtual CPU of exceptions. non zero |
| 1110 | is returned if the signal was handled by the virtual CPU. */ |
j_mayer | 3608160 | 2007-09-17 08:21:54 +0000 | [diff] [blame] | 1111 | int cpu_ppc_signal_handler (int host_signum, void *pinfo, |
| 1112 | void *puc); |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 1113 | void ppc_hw_interrupt (CPUPPCState *env); |
David Gibson | cc8eae8 | 2013-03-12 00:31:48 +0000 | [diff] [blame] | 1114 | #if defined(CONFIG_USER_ONLY) |
Andreas Färber | 7510454 | 2013-08-26 03:01:33 +0200 | [diff] [blame] | 1115 | int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, |
| 1116 | int mmu_idx); |
David Gibson | cc8eae8 | 2013-03-12 00:31:48 +0000 | [diff] [blame] | 1117 | #endif |
bellard | a541f29 | 2004-04-12 20:39:29 +0000 | [diff] [blame] | 1118 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1119 | #if !defined(CONFIG_USER_ONLY) |
aurel32 | 45d827d | 2008-12-07 13:40:29 +0000 | [diff] [blame] | 1120 | void ppc_store_sdr1 (CPUPPCState *env, target_ulong value); |
j_mayer | 12de9a3 | 2007-10-05 22:06:02 +0000 | [diff] [blame] | 1121 | #endif /* !defined(CONFIG_USER_ONLY) */ |
j_mayer | 0411a97 | 2007-10-25 21:35:50 +0000 | [diff] [blame] | 1122 | void ppc_store_msr (CPUPPCState *env, target_ulong value); |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1123 | |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 1124 | void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf); |
bellard | aaed909 | 2007-11-10 15:15:54 +0000 | [diff] [blame] | 1125 | |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1126 | /* Time-base and decrementer management */ |
| 1127 | #ifndef NO_CPU_IO_DEFS |
Alexander Graf | e3ea652 | 2009-12-21 12:24:17 +0100 | [diff] [blame] | 1128 | uint64_t cpu_ppc_load_tbl (CPUPPCState *env); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1129 | uint32_t cpu_ppc_load_tbu (CPUPPCState *env); |
| 1130 | void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value); |
| 1131 | void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value); |
Aurelien Jarno | b711de9 | 2009-12-21 13:52:08 +0100 | [diff] [blame] | 1132 | uint64_t cpu_ppc_load_atbl (CPUPPCState *env); |
j_mayer | a062e36 | 2007-09-30 00:38:38 +0000 | [diff] [blame] | 1133 | uint32_t cpu_ppc_load_atbu (CPUPPCState *env); |
| 1134 | void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value); |
| 1135 | void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value); |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1136 | uint32_t cpu_ppc_load_decr (CPUPPCState *env); |
| 1137 | void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value); |
j_mayer | 58a7d32 | 2007-09-29 13:21:37 +0000 | [diff] [blame] | 1138 | uint32_t cpu_ppc_load_hdecr (CPUPPCState *env); |
| 1139 | void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value); |
| 1140 | uint64_t cpu_ppc_load_purr (CPUPPCState *env); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1141 | uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env); |
| 1142 | uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env); |
| 1143 | #if !defined(CONFIG_USER_ONLY) |
| 1144 | void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value); |
| 1145 | void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value); |
| 1146 | target_ulong load_40x_pit (CPUPPCState *env); |
| 1147 | void store_40x_pit (CPUPPCState *env, target_ulong val); |
j_mayer | 8ecc791 | 2007-04-16 20:09:45 +0000 | [diff] [blame] | 1148 | void store_40x_dbcr0 (CPUPPCState *env, uint32_t val); |
j_mayer | c294fc5 | 2007-04-24 06:44:14 +0000 | [diff] [blame] | 1149 | void store_40x_sler (CPUPPCState *env, uint32_t val); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1150 | void store_booke_tcr (CPUPPCState *env, target_ulong val); |
| 1151 | void store_booke_tsr (CPUPPCState *env, target_ulong val); |
j_mayer | 0a032cb | 2007-04-16 08:56:52 +0000 | [diff] [blame] | 1152 | void ppc_tlb_invalidate_all (CPUPPCState *env); |
j_mayer | daf4f96 | 2007-10-01 01:51:12 +0000 | [diff] [blame] | 1153 | void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr); |
j_mayer | d9bce9d | 2007-03-17 14:02:15 +0000 | [diff] [blame] | 1154 | #endif |
bellard | 9fddaa0 | 2004-05-21 12:59:32 +0000 | [diff] [blame] | 1155 | #endif |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1156 | |
Fabien Chouteau | d6478bc | 2013-03-19 07:41:53 +0000 | [diff] [blame] | 1157 | void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask); |
| 1158 | |
Blue Swirl | 636aa20 | 2009-08-16 09:06:54 +0000 | [diff] [blame] | 1159 | static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) |
j_mayer | 6b542af | 2007-11-24 02:03:55 +0000 | [diff] [blame] | 1160 | { |
| 1161 | uint64_t gprv; |
| 1162 | |
| 1163 | gprv = env->gpr[gprn]; |
| 1164 | #if !defined(TARGET_PPC64) |
| 1165 | if (env->flags & POWERPC_FLAG_SPE) { |
| 1166 | /* If the CPU implements the SPE extension, we have to get the |
| 1167 | * high bits of the GPR from the gprh storage area |
| 1168 | */ |
| 1169 | gprv &= 0xFFFFFFFFULL; |
| 1170 | gprv |= (uint64_t)env->gprh[gprn] << 32; |
| 1171 | } |
| 1172 | #endif |
| 1173 | |
| 1174 | return gprv; |
| 1175 | } |
| 1176 | |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1177 | /* Device control registers */ |
Alexander Graf | 73b0196 | 2009-12-21 14:02:39 +0100 | [diff] [blame] | 1178 | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp); |
| 1179 | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val); |
j_mayer | 2e719ba | 2007-04-12 21:11:03 +0000 | [diff] [blame] | 1180 | |
Andreas Färber | 397b457 | 2012-05-03 05:43:05 +0200 | [diff] [blame] | 1181 | static inline CPUPPCState *cpu_init(const char *cpu_model) |
| 1182 | { |
| 1183 | PowerPCCPU *cpu = cpu_ppc_init(cpu_model); |
| 1184 | if (cpu == NULL) { |
| 1185 | return NULL; |
| 1186 | } |
| 1187 | return &cpu->env; |
| 1188 | } |
| 1189 | |
ths | 9467d44 | 2007-06-03 21:02:38 +0000 | [diff] [blame] | 1190 | #define cpu_exec cpu_ppc_exec |
| 1191 | #define cpu_gen_code cpu_ppc_gen_code |
| 1192 | #define cpu_signal_handler cpu_ppc_signal_handler |
j_mayer | c732abe | 2007-10-12 06:47:46 +0000 | [diff] [blame] | 1193 | #define cpu_list ppc_cpu_list |
ths | 9467d44 | 2007-06-03 21:02:38 +0000 | [diff] [blame] | 1194 | |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1195 | /* MMU modes definitions */ |
| 1196 | #define MMU_MODE0_SUFFIX _user |
| 1197 | #define MMU_MODE1_SUFFIX _kernel |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1198 | #define MMU_MODE2_SUFFIX _hypv |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1199 | #define MMU_USER_IDX 0 |
Andreas Färber | 1328c2b | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 1200 | static inline int cpu_mmu_index (CPUPPCState *env) |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1201 | { |
| 1202 | return env->mmu_idx; |
| 1203 | } |
| 1204 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 1205 | #include "exec/cpu-all.h" |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1206 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1207 | /*****************************************************************************/ |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 1208 | /* CRF definitions */ |
aurel32 | 57951c2 | 2008-11-10 11:10:23 +0000 | [diff] [blame] | 1209 | #define CRF_LT 3 |
| 1210 | #define CRF_GT 2 |
| 1211 | #define CRF_EQ 1 |
| 1212 | #define CRF_SO 0 |
Nathan Froyd | e6bba2e | 2010-02-23 11:55:14 -0800 | [diff] [blame] | 1213 | #define CRF_CH (1 << CRF_LT) |
| 1214 | #define CRF_CL (1 << CRF_GT) |
| 1215 | #define CRF_CH_OR_CL (1 << CRF_EQ) |
| 1216 | #define CRF_CH_AND_CL (1 << CRF_SO) |
aurel32 | e157190 | 2008-10-21 11:31:14 +0000 | [diff] [blame] | 1217 | |
| 1218 | /* XER definitions */ |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 1219 | #define XER_SO 31 |
| 1220 | #define XER_OV 30 |
| 1221 | #define XER_CA 29 |
| 1222 | #define XER_CMP 8 |
| 1223 | #define XER_BC 0 |
Richard Henderson | da91a00 | 2013-02-19 23:52:13 -0800 | [diff] [blame] | 1224 | #define xer_so (env->so) |
| 1225 | #define xer_ov (env->ov) |
| 1226 | #define xer_ca (env->ca) |
aurel32 | 3d7b417 | 2008-10-21 11:28:46 +0000 | [diff] [blame] | 1227 | #define xer_cmp ((env->xer >> XER_CMP) & 0xFF) |
| 1228 | #define xer_bc ((env->xer >> XER_BC) & 0x7F) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1229 | |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1230 | /* SPR definitions */ |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1231 | #define SPR_MQ (0x000) |
| 1232 | #define SPR_XER (0x001) |
| 1233 | #define SPR_601_VRTCU (0x004) |
| 1234 | #define SPR_601_VRTCL (0x005) |
| 1235 | #define SPR_601_UDECR (0x006) |
| 1236 | #define SPR_LR (0x008) |
| 1237 | #define SPR_CTR (0x009) |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 1238 | #define SPR_UAMR (0x00C) |
David Gibson | 697ab89 | 2011-08-31 15:45:10 +0000 | [diff] [blame] | 1239 | #define SPR_DSCR (0x011) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1240 | #define SPR_DSISR (0x012) |
| 1241 | #define SPR_DAR (0x013) /* DAE for PowerPC 601 */ |
| 1242 | #define SPR_601_RTCU (0x014) |
| 1243 | #define SPR_601_RTCL (0x015) |
| 1244 | #define SPR_DECR (0x016) |
| 1245 | #define SPR_SDR1 (0x019) |
| 1246 | #define SPR_SRR0 (0x01A) |
| 1247 | #define SPR_SRR1 (0x01B) |
David Gibson | 697ab89 | 2011-08-31 15:45:10 +0000 | [diff] [blame] | 1248 | #define SPR_CFAR (0x01C) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1249 | #define SPR_AMR (0x01D) |
| 1250 | #define SPR_BOOKE_PID (0x030) |
| 1251 | #define SPR_BOOKE_DECAR (0x036) |
| 1252 | #define SPR_BOOKE_CSRR0 (0x03A) |
| 1253 | #define SPR_BOOKE_CSRR1 (0x03B) |
| 1254 | #define SPR_BOOKE_DEAR (0x03D) |
| 1255 | #define SPR_BOOKE_ESR (0x03E) |
| 1256 | #define SPR_BOOKE_IVPR (0x03F) |
| 1257 | #define SPR_MPC_EIE (0x050) |
| 1258 | #define SPR_MPC_EID (0x051) |
| 1259 | #define SPR_MPC_NRI (0x052) |
Alexey Kardashevskiy | 0bfe929 | 2013-12-20 17:41:32 +1100 | [diff] [blame] | 1260 | #define SPR_UCTRL (0x088) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1261 | #define SPR_MPC_CMPA (0x090) |
| 1262 | #define SPR_MPC_CMPB (0x091) |
| 1263 | #define SPR_MPC_CMPC (0x092) |
| 1264 | #define SPR_MPC_CMPD (0x093) |
| 1265 | #define SPR_MPC_ECR (0x094) |
| 1266 | #define SPR_MPC_DER (0x095) |
| 1267 | #define SPR_MPC_COUNTA (0x096) |
| 1268 | #define SPR_MPC_COUNTB (0x097) |
Alexey Kardashevskiy | 0bfe929 | 2013-12-20 17:41:32 +1100 | [diff] [blame] | 1269 | #define SPR_CTRL (0x098) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1270 | #define SPR_MPC_CMPE (0x098) |
| 1271 | #define SPR_MPC_CMPF (0x099) |
| 1272 | #define SPR_MPC_CMPG (0x09A) |
| 1273 | #define SPR_MPC_CMPH (0x09B) |
| 1274 | #define SPR_MPC_LCTRL1 (0x09C) |
| 1275 | #define SPR_MPC_LCTRL2 (0x09D) |
David Gibson | f80872e | 2013-03-12 00:31:47 +0000 | [diff] [blame] | 1276 | #define SPR_UAMOR (0x09D) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1277 | #define SPR_MPC_ICTRL (0x09E) |
| 1278 | #define SPR_MPC_BAR (0x09F) |
| 1279 | #define SPR_VRSAVE (0x100) |
| 1280 | #define SPR_USPRG0 (0x100) |
| 1281 | #define SPR_USPRG1 (0x101) |
| 1282 | #define SPR_USPRG2 (0x102) |
| 1283 | #define SPR_USPRG3 (0x103) |
| 1284 | #define SPR_USPRG4 (0x104) |
| 1285 | #define SPR_USPRG5 (0x105) |
| 1286 | #define SPR_USPRG6 (0x106) |
| 1287 | #define SPR_USPRG7 (0x107) |
| 1288 | #define SPR_VTBL (0x10C) |
| 1289 | #define SPR_VTBU (0x10D) |
| 1290 | #define SPR_SPRG0 (0x110) |
| 1291 | #define SPR_SPRG1 (0x111) |
| 1292 | #define SPR_SPRG2 (0x112) |
| 1293 | #define SPR_SPRG3 (0x113) |
| 1294 | #define SPR_SPRG4 (0x114) |
| 1295 | #define SPR_SCOMC (0x114) |
| 1296 | #define SPR_SPRG5 (0x115) |
| 1297 | #define SPR_SCOMD (0x115) |
| 1298 | #define SPR_SPRG6 (0x116) |
| 1299 | #define SPR_SPRG7 (0x117) |
| 1300 | #define SPR_ASR (0x118) |
| 1301 | #define SPR_EAR (0x11A) |
| 1302 | #define SPR_TBL (0x11C) |
| 1303 | #define SPR_TBU (0x11D) |
| 1304 | #define SPR_TBU40 (0x11E) |
| 1305 | #define SPR_SVR (0x11E) |
| 1306 | #define SPR_BOOKE_PIR (0x11E) |
| 1307 | #define SPR_PVR (0x11F) |
| 1308 | #define SPR_HSPRG0 (0x130) |
| 1309 | #define SPR_BOOKE_DBSR (0x130) |
| 1310 | #define SPR_HSPRG1 (0x131) |
| 1311 | #define SPR_HDSISR (0x132) |
| 1312 | #define SPR_HDAR (0x133) |
Scott Wood | 90dc881 | 2011-04-29 17:10:23 -0500 | [diff] [blame] | 1313 | #define SPR_BOOKE_EPCR (0x133) |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 1314 | #define SPR_SPURR (0x134) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1315 | #define SPR_BOOKE_DBCR0 (0x134) |
| 1316 | #define SPR_IBCR (0x135) |
| 1317 | #define SPR_PURR (0x135) |
| 1318 | #define SPR_BOOKE_DBCR1 (0x135) |
| 1319 | #define SPR_DBCR (0x136) |
| 1320 | #define SPR_HDEC (0x136) |
| 1321 | #define SPR_BOOKE_DBCR2 (0x136) |
| 1322 | #define SPR_HIOR (0x137) |
| 1323 | #define SPR_MBAR (0x137) |
| 1324 | #define SPR_RMOR (0x138) |
| 1325 | #define SPR_BOOKE_IAC1 (0x138) |
| 1326 | #define SPR_HRMOR (0x139) |
| 1327 | #define SPR_BOOKE_IAC2 (0x139) |
| 1328 | #define SPR_HSRR0 (0x13A) |
| 1329 | #define SPR_BOOKE_IAC3 (0x13A) |
| 1330 | #define SPR_HSRR1 (0x13B) |
| 1331 | #define SPR_BOOKE_IAC4 (0x13B) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1332 | #define SPR_BOOKE_DAC1 (0x13C) |
| 1333 | #define SPR_LPIDR (0x13D) |
| 1334 | #define SPR_DABR2 (0x13D) |
| 1335 | #define SPR_BOOKE_DAC2 (0x13D) |
| 1336 | #define SPR_BOOKE_DVC1 (0x13E) |
Alexey Kardashevskiy | 6475c9f | 2013-12-20 17:41:30 +1100 | [diff] [blame] | 1337 | #define SPR_LPCR (0x13E) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1338 | #define SPR_BOOKE_DVC2 (0x13F) |
| 1339 | #define SPR_BOOKE_TSR (0x150) |
| 1340 | #define SPR_BOOKE_TCR (0x154) |
Alexander Graf | a1ef618 | 2012-01-21 04:45:46 +0100 | [diff] [blame] | 1341 | #define SPR_BOOKE_TLB0PS (0x158) |
| 1342 | #define SPR_BOOKE_TLB1PS (0x159) |
| 1343 | #define SPR_BOOKE_TLB2PS (0x15A) |
| 1344 | #define SPR_BOOKE_TLB3PS (0x15B) |
Alexander Graf | 84755ed | 2012-06-20 21:19:09 +0200 | [diff] [blame] | 1345 | #define SPR_BOOKE_MAS7_MAS3 (0x174) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1346 | #define SPR_BOOKE_IVOR0 (0x190) |
| 1347 | #define SPR_BOOKE_IVOR1 (0x191) |
| 1348 | #define SPR_BOOKE_IVOR2 (0x192) |
| 1349 | #define SPR_BOOKE_IVOR3 (0x193) |
| 1350 | #define SPR_BOOKE_IVOR4 (0x194) |
| 1351 | #define SPR_BOOKE_IVOR5 (0x195) |
| 1352 | #define SPR_BOOKE_IVOR6 (0x196) |
| 1353 | #define SPR_BOOKE_IVOR7 (0x197) |
| 1354 | #define SPR_BOOKE_IVOR8 (0x198) |
| 1355 | #define SPR_BOOKE_IVOR9 (0x199) |
| 1356 | #define SPR_BOOKE_IVOR10 (0x19A) |
| 1357 | #define SPR_BOOKE_IVOR11 (0x19B) |
| 1358 | #define SPR_BOOKE_IVOR12 (0x19C) |
| 1359 | #define SPR_BOOKE_IVOR13 (0x19D) |
| 1360 | #define SPR_BOOKE_IVOR14 (0x19E) |
| 1361 | #define SPR_BOOKE_IVOR15 (0x19F) |
Alexander Graf | e920525 | 2012-01-19 19:31:51 +0100 | [diff] [blame] | 1362 | #define SPR_BOOKE_IVOR38 (0x1B0) |
| 1363 | #define SPR_BOOKE_IVOR39 (0x1B1) |
| 1364 | #define SPR_BOOKE_IVOR40 (0x1B2) |
| 1365 | #define SPR_BOOKE_IVOR41 (0x1B3) |
| 1366 | #define SPR_BOOKE_IVOR42 (0x1B4) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1367 | #define SPR_BOOKE_SPEFSCR (0x200) |
| 1368 | #define SPR_Exxx_BBEAR (0x201) |
| 1369 | #define SPR_Exxx_BBTAR (0x202) |
| 1370 | #define SPR_Exxx_L1CFG0 (0x203) |
| 1371 | #define SPR_Exxx_NPIDR (0x205) |
| 1372 | #define SPR_ATBL (0x20E) |
| 1373 | #define SPR_ATBU (0x20F) |
| 1374 | #define SPR_IBAT0U (0x210) |
| 1375 | #define SPR_BOOKE_IVOR32 (0x210) |
| 1376 | #define SPR_RCPU_MI_GRA (0x210) |
| 1377 | #define SPR_IBAT0L (0x211) |
| 1378 | #define SPR_BOOKE_IVOR33 (0x211) |
| 1379 | #define SPR_IBAT1U (0x212) |
| 1380 | #define SPR_BOOKE_IVOR34 (0x212) |
| 1381 | #define SPR_IBAT1L (0x213) |
| 1382 | #define SPR_BOOKE_IVOR35 (0x213) |
| 1383 | #define SPR_IBAT2U (0x214) |
| 1384 | #define SPR_BOOKE_IVOR36 (0x214) |
| 1385 | #define SPR_IBAT2L (0x215) |
| 1386 | #define SPR_BOOKE_IVOR37 (0x215) |
| 1387 | #define SPR_IBAT3U (0x216) |
| 1388 | #define SPR_IBAT3L (0x217) |
| 1389 | #define SPR_DBAT0U (0x218) |
| 1390 | #define SPR_RCPU_L2U_GRA (0x218) |
| 1391 | #define SPR_DBAT0L (0x219) |
| 1392 | #define SPR_DBAT1U (0x21A) |
| 1393 | #define SPR_DBAT1L (0x21B) |
| 1394 | #define SPR_DBAT2U (0x21C) |
| 1395 | #define SPR_DBAT2L (0x21D) |
| 1396 | #define SPR_DBAT3U (0x21E) |
| 1397 | #define SPR_DBAT3L (0x21F) |
| 1398 | #define SPR_IBAT4U (0x230) |
| 1399 | #define SPR_RPCU_BBCMCR (0x230) |
| 1400 | #define SPR_MPC_IC_CST (0x230) |
| 1401 | #define SPR_Exxx_CTXCR (0x230) |
| 1402 | #define SPR_IBAT4L (0x231) |
| 1403 | #define SPR_MPC_IC_ADR (0x231) |
| 1404 | #define SPR_Exxx_DBCR3 (0x231) |
| 1405 | #define SPR_IBAT5U (0x232) |
| 1406 | #define SPR_MPC_IC_DAT (0x232) |
| 1407 | #define SPR_Exxx_DBCNT (0x232) |
| 1408 | #define SPR_IBAT5L (0x233) |
| 1409 | #define SPR_IBAT6U (0x234) |
| 1410 | #define SPR_IBAT6L (0x235) |
| 1411 | #define SPR_IBAT7U (0x236) |
| 1412 | #define SPR_IBAT7L (0x237) |
| 1413 | #define SPR_DBAT4U (0x238) |
| 1414 | #define SPR_RCPU_L2U_MCR (0x238) |
| 1415 | #define SPR_MPC_DC_CST (0x238) |
| 1416 | #define SPR_Exxx_ALTCTXCR (0x238) |
| 1417 | #define SPR_DBAT4L (0x239) |
| 1418 | #define SPR_MPC_DC_ADR (0x239) |
| 1419 | #define SPR_DBAT5U (0x23A) |
| 1420 | #define SPR_BOOKE_MCSRR0 (0x23A) |
| 1421 | #define SPR_MPC_DC_DAT (0x23A) |
| 1422 | #define SPR_DBAT5L (0x23B) |
| 1423 | #define SPR_BOOKE_MCSRR1 (0x23B) |
| 1424 | #define SPR_DBAT6U (0x23C) |
| 1425 | #define SPR_BOOKE_MCSR (0x23C) |
| 1426 | #define SPR_DBAT6L (0x23D) |
| 1427 | #define SPR_Exxx_MCAR (0x23D) |
| 1428 | #define SPR_DBAT7U (0x23E) |
| 1429 | #define SPR_BOOKE_DSRR0 (0x23E) |
| 1430 | #define SPR_DBAT7L (0x23F) |
| 1431 | #define SPR_BOOKE_DSRR1 (0x23F) |
| 1432 | #define SPR_BOOKE_SPRG8 (0x25C) |
| 1433 | #define SPR_BOOKE_SPRG9 (0x25D) |
| 1434 | #define SPR_BOOKE_MAS0 (0x270) |
| 1435 | #define SPR_BOOKE_MAS1 (0x271) |
| 1436 | #define SPR_BOOKE_MAS2 (0x272) |
| 1437 | #define SPR_BOOKE_MAS3 (0x273) |
| 1438 | #define SPR_BOOKE_MAS4 (0x274) |
| 1439 | #define SPR_BOOKE_MAS5 (0x275) |
| 1440 | #define SPR_BOOKE_MAS6 (0x276) |
| 1441 | #define SPR_BOOKE_PID1 (0x279) |
| 1442 | #define SPR_BOOKE_PID2 (0x27A) |
| 1443 | #define SPR_MPC_DPDR (0x280) |
| 1444 | #define SPR_MPC_IMMR (0x288) |
| 1445 | #define SPR_BOOKE_TLB0CFG (0x2B0) |
| 1446 | #define SPR_BOOKE_TLB1CFG (0x2B1) |
| 1447 | #define SPR_BOOKE_TLB2CFG (0x2B2) |
| 1448 | #define SPR_BOOKE_TLB3CFG (0x2B3) |
| 1449 | #define SPR_BOOKE_EPR (0x2BE) |
| 1450 | #define SPR_PERF0 (0x300) |
| 1451 | #define SPR_RCPU_MI_RBA0 (0x300) |
| 1452 | #define SPR_MPC_MI_CTR (0x300) |
| 1453 | #define SPR_PERF1 (0x301) |
| 1454 | #define SPR_RCPU_MI_RBA1 (0x301) |
| 1455 | #define SPR_PERF2 (0x302) |
| 1456 | #define SPR_RCPU_MI_RBA2 (0x302) |
| 1457 | #define SPR_MPC_MI_AP (0x302) |
David Gibson | 702763f | 2013-04-07 19:08:20 +0000 | [diff] [blame] | 1458 | #define SPR_MMCRA (0x302) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1459 | #define SPR_PERF3 (0x303) |
| 1460 | #define SPR_RCPU_MI_RBA3 (0x303) |
| 1461 | #define SPR_MPC_MI_EPN (0x303) |
| 1462 | #define SPR_PERF4 (0x304) |
| 1463 | #define SPR_PERF5 (0x305) |
| 1464 | #define SPR_MPC_MI_TWC (0x305) |
| 1465 | #define SPR_PERF6 (0x306) |
| 1466 | #define SPR_MPC_MI_RPN (0x306) |
| 1467 | #define SPR_PERF7 (0x307) |
| 1468 | #define SPR_PERF8 (0x308) |
| 1469 | #define SPR_RCPU_L2U_RBA0 (0x308) |
| 1470 | #define SPR_MPC_MD_CTR (0x308) |
| 1471 | #define SPR_PERF9 (0x309) |
| 1472 | #define SPR_RCPU_L2U_RBA1 (0x309) |
| 1473 | #define SPR_MPC_MD_CASID (0x309) |
| 1474 | #define SPR_PERFA (0x30A) |
| 1475 | #define SPR_RCPU_L2U_RBA2 (0x30A) |
| 1476 | #define SPR_MPC_MD_AP (0x30A) |
| 1477 | #define SPR_PERFB (0x30B) |
| 1478 | #define SPR_RCPU_L2U_RBA3 (0x30B) |
| 1479 | #define SPR_MPC_MD_EPN (0x30B) |
| 1480 | #define SPR_PERFC (0x30C) |
| 1481 | #define SPR_MPC_MD_TWB (0x30C) |
| 1482 | #define SPR_PERFD (0x30D) |
| 1483 | #define SPR_MPC_MD_TWC (0x30D) |
| 1484 | #define SPR_PERFE (0x30E) |
| 1485 | #define SPR_MPC_MD_RPN (0x30E) |
| 1486 | #define SPR_PERFF (0x30F) |
| 1487 | #define SPR_MPC_MD_TW (0x30F) |
| 1488 | #define SPR_UPERF0 (0x310) |
| 1489 | #define SPR_UPERF1 (0x311) |
| 1490 | #define SPR_UPERF2 (0x312) |
| 1491 | #define SPR_UPERF3 (0x313) |
| 1492 | #define SPR_UPERF4 (0x314) |
| 1493 | #define SPR_UPERF5 (0x315) |
| 1494 | #define SPR_UPERF6 (0x316) |
| 1495 | #define SPR_UPERF7 (0x317) |
| 1496 | #define SPR_UPERF8 (0x318) |
| 1497 | #define SPR_UPERF9 (0x319) |
| 1498 | #define SPR_UPERFA (0x31A) |
| 1499 | #define SPR_UPERFB (0x31B) |
| 1500 | #define SPR_UPERFC (0x31C) |
| 1501 | #define SPR_UPERFD (0x31D) |
| 1502 | #define SPR_UPERFE (0x31E) |
| 1503 | #define SPR_UPERFF (0x31F) |
| 1504 | #define SPR_RCPU_MI_RA0 (0x320) |
| 1505 | #define SPR_MPC_MI_DBCAM (0x320) |
| 1506 | #define SPR_RCPU_MI_RA1 (0x321) |
| 1507 | #define SPR_MPC_MI_DBRAM0 (0x321) |
| 1508 | #define SPR_RCPU_MI_RA2 (0x322) |
| 1509 | #define SPR_MPC_MI_DBRAM1 (0x322) |
| 1510 | #define SPR_RCPU_MI_RA3 (0x323) |
| 1511 | #define SPR_RCPU_L2U_RA0 (0x328) |
| 1512 | #define SPR_MPC_MD_DBCAM (0x328) |
| 1513 | #define SPR_RCPU_L2U_RA1 (0x329) |
| 1514 | #define SPR_MPC_MD_DBRAM0 (0x329) |
| 1515 | #define SPR_RCPU_L2U_RA2 (0x32A) |
| 1516 | #define SPR_MPC_MD_DBRAM1 (0x32A) |
| 1517 | #define SPR_RCPU_L2U_RA3 (0x32B) |
Tom Musta | 6051104 | 2014-02-10 11:26:54 -0600 | [diff] [blame] | 1518 | #define SPR_TAR (0x32F) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1519 | #define SPR_440_INV0 (0x370) |
| 1520 | #define SPR_440_INV1 (0x371) |
| 1521 | #define SPR_440_INV2 (0x372) |
| 1522 | #define SPR_440_INV3 (0x373) |
| 1523 | #define SPR_440_ITV0 (0x374) |
| 1524 | #define SPR_440_ITV1 (0x375) |
| 1525 | #define SPR_440_ITV2 (0x376) |
| 1526 | #define SPR_440_ITV3 (0x377) |
| 1527 | #define SPR_440_CCR1 (0x378) |
| 1528 | #define SPR_DCRIPR (0x37B) |
| 1529 | #define SPR_PPR (0x380) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1530 | #define SPR_750_GQR0 (0x390) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1531 | #define SPR_440_DNV0 (0x390) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1532 | #define SPR_750_GQR1 (0x391) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1533 | #define SPR_440_DNV1 (0x391) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1534 | #define SPR_750_GQR2 (0x392) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1535 | #define SPR_440_DNV2 (0x392) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1536 | #define SPR_750_GQR3 (0x393) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1537 | #define SPR_440_DNV3 (0x393) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1538 | #define SPR_750_GQR4 (0x394) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1539 | #define SPR_440_DTV0 (0x394) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1540 | #define SPR_750_GQR5 (0x395) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1541 | #define SPR_440_DTV1 (0x395) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1542 | #define SPR_750_GQR6 (0x396) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1543 | #define SPR_440_DTV2 (0x396) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1544 | #define SPR_750_GQR7 (0x397) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1545 | #define SPR_440_DTV3 (0x397) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1546 | #define SPR_750_THRM4 (0x398) |
| 1547 | #define SPR_750CL_HID2 (0x398) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1548 | #define SPR_440_DVLIM (0x398) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1549 | #define SPR_750_WPAR (0x399) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1550 | #define SPR_440_IVLIM (0x399) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1551 | #define SPR_750_DMAU (0x39A) |
| 1552 | #define SPR_750_DMAL (0x39B) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1553 | #define SPR_440_RSTCFG (0x39B) |
| 1554 | #define SPR_BOOKE_DCDBTRL (0x39C) |
| 1555 | #define SPR_BOOKE_DCDBTRH (0x39D) |
| 1556 | #define SPR_BOOKE_ICDBTRL (0x39E) |
| 1557 | #define SPR_BOOKE_ICDBTRH (0x39F) |
| 1558 | #define SPR_UMMCR2 (0x3A0) |
| 1559 | #define SPR_UPMC5 (0x3A1) |
| 1560 | #define SPR_UPMC6 (0x3A2) |
| 1561 | #define SPR_UBAMR (0x3A7) |
| 1562 | #define SPR_UMMCR0 (0x3A8) |
| 1563 | #define SPR_UPMC1 (0x3A9) |
| 1564 | #define SPR_UPMC2 (0x3AA) |
| 1565 | #define SPR_USIAR (0x3AB) |
| 1566 | #define SPR_UMMCR1 (0x3AC) |
| 1567 | #define SPR_UPMC3 (0x3AD) |
| 1568 | #define SPR_UPMC4 (0x3AE) |
| 1569 | #define SPR_USDA (0x3AF) |
| 1570 | #define SPR_40x_ZPR (0x3B0) |
| 1571 | #define SPR_BOOKE_MAS7 (0x3B0) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1572 | #define SPR_MMCR2 (0x3B0) |
| 1573 | #define SPR_PMC5 (0x3B1) |
| 1574 | #define SPR_40x_PID (0x3B1) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1575 | #define SPR_PMC6 (0x3B2) |
| 1576 | #define SPR_440_MMUCR (0x3B2) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1577 | #define SPR_4xx_CCR0 (0x3B3) |
| 1578 | #define SPR_BOOKE_EPLC (0x3B3) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1579 | #define SPR_405_IAC3 (0x3B4) |
| 1580 | #define SPR_BOOKE_EPSC (0x3B4) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1581 | #define SPR_405_IAC4 (0x3B5) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1582 | #define SPR_405_DVC1 (0x3B6) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1583 | #define SPR_405_DVC2 (0x3B7) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1584 | #define SPR_BAMR (0x3B7) |
| 1585 | #define SPR_MMCR0 (0x3B8) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1586 | #define SPR_PMC1 (0x3B9) |
| 1587 | #define SPR_40x_SGR (0x3B9) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1588 | #define SPR_PMC2 (0x3BA) |
| 1589 | #define SPR_40x_DCWR (0x3BA) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1590 | #define SPR_SIAR (0x3BB) |
| 1591 | #define SPR_405_SLER (0x3BB) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1592 | #define SPR_MMCR1 (0x3BC) |
| 1593 | #define SPR_405_SU0R (0x3BC) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1594 | #define SPR_401_SKR (0x3BC) |
| 1595 | #define SPR_PMC3 (0x3BD) |
| 1596 | #define SPR_405_DBCR1 (0x3BD) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1597 | #define SPR_PMC4 (0x3BE) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1598 | #define SPR_SDA (0x3BF) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1599 | #define SPR_403_VTBL (0x3CC) |
| 1600 | #define SPR_403_VTBU (0x3CD) |
| 1601 | #define SPR_DMISS (0x3D0) |
| 1602 | #define SPR_DCMP (0x3D1) |
| 1603 | #define SPR_HASH1 (0x3D2) |
| 1604 | #define SPR_HASH2 (0x3D3) |
| 1605 | #define SPR_BOOKE_ICDBDR (0x3D3) |
| 1606 | #define SPR_TLBMISS (0x3D4) |
| 1607 | #define SPR_IMISS (0x3D4) |
| 1608 | #define SPR_40x_ESR (0x3D4) |
| 1609 | #define SPR_PTEHI (0x3D5) |
| 1610 | #define SPR_ICMP (0x3D5) |
| 1611 | #define SPR_40x_DEAR (0x3D5) |
| 1612 | #define SPR_PTELO (0x3D6) |
| 1613 | #define SPR_RPA (0x3D6) |
| 1614 | #define SPR_40x_EVPR (0x3D6) |
| 1615 | #define SPR_L3PM (0x3D7) |
| 1616 | #define SPR_403_CDBCR (0x3D7) |
j_mayer | 4e77744 | 2007-12-10 07:40:16 +0000 | [diff] [blame] | 1617 | #define SPR_L3ITCR0 (0x3D8) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1618 | #define SPR_TCR (0x3D8) |
| 1619 | #define SPR_40x_TSR (0x3D8) |
| 1620 | #define SPR_IBR (0x3DA) |
| 1621 | #define SPR_40x_TCR (0x3DA) |
| 1622 | #define SPR_ESASRR (0x3DB) |
| 1623 | #define SPR_40x_PIT (0x3DB) |
| 1624 | #define SPR_403_TBL (0x3DC) |
| 1625 | #define SPR_403_TBU (0x3DD) |
| 1626 | #define SPR_SEBR (0x3DE) |
| 1627 | #define SPR_40x_SRR2 (0x3DE) |
| 1628 | #define SPR_SER (0x3DF) |
| 1629 | #define SPR_40x_SRR3 (0x3DF) |
j_mayer | 4e77744 | 2007-12-10 07:40:16 +0000 | [diff] [blame] | 1630 | #define SPR_L3OHCR (0x3E8) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1631 | #define SPR_L3ITCR1 (0x3E9) |
| 1632 | #define SPR_L3ITCR2 (0x3EA) |
| 1633 | #define SPR_L3ITCR3 (0x3EB) |
| 1634 | #define SPR_HID0 (0x3F0) |
| 1635 | #define SPR_40x_DBSR (0x3F0) |
| 1636 | #define SPR_HID1 (0x3F1) |
| 1637 | #define SPR_IABR (0x3F2) |
| 1638 | #define SPR_40x_DBCR0 (0x3F2) |
| 1639 | #define SPR_601_HID2 (0x3F2) |
| 1640 | #define SPR_Exxx_L1CSR0 (0x3F2) |
| 1641 | #define SPR_ICTRL (0x3F3) |
| 1642 | #define SPR_HID2 (0x3F3) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1643 | #define SPR_750CL_HID4 (0x3F3) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1644 | #define SPR_Exxx_L1CSR1 (0x3F3) |
| 1645 | #define SPR_440_DBDR (0x3F3) |
| 1646 | #define SPR_LDSTDB (0x3F4) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1647 | #define SPR_750_TDCL (0x3F4) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1648 | #define SPR_40x_IAC1 (0x3F4) |
| 1649 | #define SPR_MMUCSR0 (0x3F4) |
| 1650 | #define SPR_DABR (0x3F5) |
bellard | 3fc6c08 | 2005-07-02 20:59:34 +0000 | [diff] [blame] | 1651 | #define DABR_MASK (~(target_ulong)0x7) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1652 | #define SPR_Exxx_BUCSR (0x3F5) |
| 1653 | #define SPR_40x_IAC2 (0x3F5) |
| 1654 | #define SPR_601_HID5 (0x3F5) |
| 1655 | #define SPR_40x_DAC1 (0x3F6) |
| 1656 | #define SPR_MSSCR0 (0x3F6) |
| 1657 | #define SPR_970_HID5 (0x3F6) |
| 1658 | #define SPR_MSSSR0 (0x3F7) |
j_mayer | 4e77744 | 2007-12-10 07:40:16 +0000 | [diff] [blame] | 1659 | #define SPR_MSSCR1 (0x3F7) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1660 | #define SPR_DABRX (0x3F7) |
| 1661 | #define SPR_40x_DAC2 (0x3F7) |
| 1662 | #define SPR_MMUCFG (0x3F7) |
| 1663 | #define SPR_LDSTCR (0x3F8) |
| 1664 | #define SPR_L2PMCR (0x3F8) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1665 | #define SPR_750FX_HID2 (0x3F8) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1666 | #define SPR_Exxx_L1FINV0 (0x3F8) |
| 1667 | #define SPR_L2CR (0x3F9) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1668 | #define SPR_L3CR (0x3FA) |
j_mayer | bd928eb | 2007-11-21 13:08:23 +0000 | [diff] [blame] | 1669 | #define SPR_750_TDCH (0x3FA) |
j_mayer | 80d11f4 | 2007-11-17 23:02:20 +0000 | [diff] [blame] | 1670 | #define SPR_IABR2 (0x3FA) |
| 1671 | #define SPR_40x_DCCR (0x3FA) |
| 1672 | #define SPR_ICTC (0x3FB) |
| 1673 | #define SPR_40x_ICCR (0x3FB) |
| 1674 | #define SPR_THRM1 (0x3FC) |
| 1675 | #define SPR_403_PBL1 (0x3FC) |
| 1676 | #define SPR_SP (0x3FD) |
| 1677 | #define SPR_THRM2 (0x3FD) |
| 1678 | #define SPR_403_PBU1 (0x3FD) |
| 1679 | #define SPR_604_HID13 (0x3FD) |
| 1680 | #define SPR_LT (0x3FE) |
| 1681 | #define SPR_THRM3 (0x3FE) |
| 1682 | #define SPR_RCPU_FPECR (0x3FE) |
| 1683 | #define SPR_403_PBL2 (0x3FE) |
| 1684 | #define SPR_PIR (0x3FF) |
| 1685 | #define SPR_403_PBU2 (0x3FF) |
| 1686 | #define SPR_601_HID15 (0x3FF) |
| 1687 | #define SPR_604_HID15 (0x3FF) |
| 1688 | #define SPR_E500_SVR (0x3FF) |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1689 | |
Alexander Graf | 84755ed | 2012-06-20 21:19:09 +0200 | [diff] [blame] | 1690 | /* Disable MAS Interrupt Updates for Hypervisor */ |
| 1691 | #define EPCR_DMIUH (1 << 22) |
| 1692 | /* Disable Guest TLB Management Instructions */ |
| 1693 | #define EPCR_DGTMI (1 << 23) |
| 1694 | /* Guest Interrupt Computation Mode */ |
| 1695 | #define EPCR_GICM (1 << 24) |
| 1696 | /* Interrupt Computation Mode */ |
| 1697 | #define EPCR_ICM (1 << 25) |
| 1698 | /* Disable Embedded Hypervisor Debug */ |
| 1699 | #define EPCR_DUVD (1 << 26) |
| 1700 | /* Instruction Storage Interrupt Directed to Guest State */ |
| 1701 | #define EPCR_ISIGS (1 << 27) |
| 1702 | /* Data Storage Interrupt Directed to Guest State */ |
| 1703 | #define EPCR_DSIGS (1 << 28) |
| 1704 | /* Instruction TLB Error Interrupt Directed to Guest State */ |
| 1705 | #define EPCR_ITLBGS (1 << 29) |
| 1706 | /* Data TLB Error Interrupt Directed to Guest State */ |
| 1707 | #define EPCR_DTLBGS (1 << 30) |
| 1708 | /* External Input Interrupt Directed to Guest State */ |
| 1709 | #define EPCR_EXTGS (1 << 31) |
| 1710 | |
j_mayer | 76a6625 | 2007-03-07 08:32:30 +0000 | [diff] [blame] | 1711 | /*****************************************************************************/ |
Nathan Froyd | c29b735 | 2009-05-12 12:26:57 -0700 | [diff] [blame] | 1712 | /* PowerPC Instructions types definitions */ |
| 1713 | enum { |
| 1714 | PPC_NONE = 0x0000000000000000ULL, |
| 1715 | /* PowerPC base instructions set */ |
| 1716 | PPC_INSNS_BASE = 0x0000000000000001ULL, |
| 1717 | /* integer operations instructions */ |
| 1718 | #define PPC_INTEGER PPC_INSNS_BASE |
| 1719 | /* flow control instructions */ |
| 1720 | #define PPC_FLOW PPC_INSNS_BASE |
| 1721 | /* virtual memory instructions */ |
| 1722 | #define PPC_MEM PPC_INSNS_BASE |
| 1723 | /* ld/st with reservation instructions */ |
| 1724 | #define PPC_RES PPC_INSNS_BASE |
| 1725 | /* spr/msr access instructions */ |
| 1726 | #define PPC_MISC PPC_INSNS_BASE |
| 1727 | /* Deprecated instruction sets */ |
| 1728 | /* Original POWER instruction set */ |
| 1729 | PPC_POWER = 0x0000000000000002ULL, |
| 1730 | /* POWER2 instruction set extension */ |
| 1731 | PPC_POWER2 = 0x0000000000000004ULL, |
| 1732 | /* Power RTC support */ |
| 1733 | PPC_POWER_RTC = 0x0000000000000008ULL, |
| 1734 | /* Power-to-PowerPC bridge (601) */ |
| 1735 | PPC_POWER_BR = 0x0000000000000010ULL, |
| 1736 | /* 64 bits PowerPC instruction set */ |
| 1737 | PPC_64B = 0x0000000000000020ULL, |
| 1738 | /* New 64 bits extensions (PowerPC 2.0x) */ |
| 1739 | PPC_64BX = 0x0000000000000040ULL, |
| 1740 | /* 64 bits hypervisor extensions */ |
| 1741 | PPC_64H = 0x0000000000000080ULL, |
| 1742 | /* New wait instruction (PowerPC 2.0x) */ |
| 1743 | PPC_WAIT = 0x0000000000000100ULL, |
| 1744 | /* Time base mftb instruction */ |
| 1745 | PPC_MFTB = 0x0000000000000200ULL, |
| 1746 | |
| 1747 | /* Fixed-point unit extensions */ |
| 1748 | /* PowerPC 602 specific */ |
| 1749 | PPC_602_SPEC = 0x0000000000000400ULL, |
| 1750 | /* isel instruction */ |
| 1751 | PPC_ISEL = 0x0000000000000800ULL, |
| 1752 | /* popcntb instruction */ |
| 1753 | PPC_POPCNTB = 0x0000000000001000ULL, |
| 1754 | /* string load / store */ |
| 1755 | PPC_STRING = 0x0000000000002000ULL, |
| 1756 | |
| 1757 | /* Floating-point unit extensions */ |
| 1758 | /* Optional floating point instructions */ |
| 1759 | PPC_FLOAT = 0x0000000000010000ULL, |
| 1760 | /* New floating-point extensions (PowerPC 2.0x) */ |
| 1761 | PPC_FLOAT_EXT = 0x0000000000020000ULL, |
| 1762 | PPC_FLOAT_FSQRT = 0x0000000000040000ULL, |
| 1763 | PPC_FLOAT_FRES = 0x0000000000080000ULL, |
| 1764 | PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL, |
| 1765 | PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL, |
| 1766 | PPC_FLOAT_FSEL = 0x0000000000400000ULL, |
| 1767 | PPC_FLOAT_STFIWX = 0x0000000000800000ULL, |
| 1768 | |
| 1769 | /* Vector/SIMD extensions */ |
| 1770 | /* Altivec support */ |
| 1771 | PPC_ALTIVEC = 0x0000000001000000ULL, |
| 1772 | /* PowerPC 2.03 SPE extension */ |
| 1773 | PPC_SPE = 0x0000000002000000ULL, |
| 1774 | /* PowerPC 2.03 SPE single-precision floating-point extension */ |
| 1775 | PPC_SPE_SINGLE = 0x0000000004000000ULL, |
| 1776 | /* PowerPC 2.03 SPE double-precision floating-point extension */ |
| 1777 | PPC_SPE_DOUBLE = 0x0000000008000000ULL, |
| 1778 | |
| 1779 | /* Optional memory control instructions */ |
| 1780 | PPC_MEM_TLBIA = 0x0000000010000000ULL, |
| 1781 | PPC_MEM_TLBIE = 0x0000000020000000ULL, |
| 1782 | PPC_MEM_TLBSYNC = 0x0000000040000000ULL, |
| 1783 | /* sync instruction */ |
| 1784 | PPC_MEM_SYNC = 0x0000000080000000ULL, |
| 1785 | /* eieio instruction */ |
| 1786 | PPC_MEM_EIEIO = 0x0000000100000000ULL, |
| 1787 | |
| 1788 | /* Cache control instructions */ |
| 1789 | PPC_CACHE = 0x0000000200000000ULL, |
| 1790 | /* icbi instruction */ |
| 1791 | PPC_CACHE_ICBI = 0x0000000400000000ULL, |
Alexander Graf | 8e33944 | 2013-01-29 13:36:02 +0100 | [diff] [blame] | 1792 | /* dcbz instruction */ |
Nathan Froyd | c29b735 | 2009-05-12 12:26:57 -0700 | [diff] [blame] | 1793 | PPC_CACHE_DCBZ = 0x0000000800000000ULL, |
Nathan Froyd | c29b735 | 2009-05-12 12:26:57 -0700 | [diff] [blame] | 1794 | /* dcba instruction */ |
| 1795 | PPC_CACHE_DCBA = 0x0000002000000000ULL, |
| 1796 | /* Freescale cache locking instructions */ |
| 1797 | PPC_CACHE_LOCK = 0x0000004000000000ULL, |
| 1798 | |
| 1799 | /* MMU related extensions */ |
| 1800 | /* external control instructions */ |
| 1801 | PPC_EXTERN = 0x0000010000000000ULL, |
| 1802 | /* segment register access instructions */ |
| 1803 | PPC_SEGMENT = 0x0000020000000000ULL, |
| 1804 | /* PowerPC 6xx TLB management instructions */ |
| 1805 | PPC_6xx_TLB = 0x0000040000000000ULL, |
| 1806 | /* PowerPC 74xx TLB management instructions */ |
| 1807 | PPC_74xx_TLB = 0x0000080000000000ULL, |
| 1808 | /* PowerPC 40x TLB management instructions */ |
| 1809 | PPC_40x_TLB = 0x0000100000000000ULL, |
| 1810 | /* segment register access instructions for PowerPC 64 "bridge" */ |
| 1811 | PPC_SEGMENT_64B = 0x0000200000000000ULL, |
| 1812 | /* SLB management */ |
| 1813 | PPC_SLBI = 0x0000400000000000ULL, |
| 1814 | |
| 1815 | /* Embedded PowerPC dedicated instructions */ |
| 1816 | PPC_WRTEE = 0x0001000000000000ULL, |
| 1817 | /* PowerPC 40x exception model */ |
| 1818 | PPC_40x_EXCP = 0x0002000000000000ULL, |
| 1819 | /* PowerPC 405 Mac instructions */ |
| 1820 | PPC_405_MAC = 0x0004000000000000ULL, |
| 1821 | /* PowerPC 440 specific instructions */ |
| 1822 | PPC_440_SPEC = 0x0008000000000000ULL, |
| 1823 | /* BookE (embedded) PowerPC specification */ |
| 1824 | PPC_BOOKE = 0x0010000000000000ULL, |
| 1825 | /* mfapidi instruction */ |
| 1826 | PPC_MFAPIDI = 0x0020000000000000ULL, |
| 1827 | /* tlbiva instruction */ |
| 1828 | PPC_TLBIVA = 0x0040000000000000ULL, |
| 1829 | /* tlbivax instruction */ |
| 1830 | PPC_TLBIVAX = 0x0080000000000000ULL, |
| 1831 | /* PowerPC 4xx dedicated instructions */ |
| 1832 | PPC_4xx_COMMON = 0x0100000000000000ULL, |
| 1833 | /* PowerPC 40x ibct instructions */ |
| 1834 | PPC_40x_ICBT = 0x0200000000000000ULL, |
| 1835 | /* rfmci is not implemented in all BookE PowerPC */ |
| 1836 | PPC_RFMCI = 0x0400000000000000ULL, |
| 1837 | /* rfdi instruction */ |
| 1838 | PPC_RFDI = 0x0800000000000000ULL, |
| 1839 | /* DCR accesses */ |
| 1840 | PPC_DCR = 0x1000000000000000ULL, |
| 1841 | /* DCR extended accesse */ |
| 1842 | PPC_DCRX = 0x2000000000000000ULL, |
| 1843 | /* user-mode DCR access, implemented in PowerPC 460 */ |
| 1844 | PPC_DCRUX = 0x4000000000000000ULL, |
David Gibson | eaabeef | 2011-04-01 15:15:13 +1100 | [diff] [blame] | 1845 | /* popcntw and popcntd instructions */ |
| 1846 | PPC_POPCNTWD = 0x8000000000000000ULL, |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 1847 | |
David Gibson | 02d4eae | 2011-10-30 15:51:24 +0000 | [diff] [blame] | 1848 | #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \ |
| 1849 | | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \ |
| 1850 | | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \ |
| 1851 | | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \ |
| 1852 | | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \ |
| 1853 | | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \ |
| 1854 | | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \ |
| 1855 | | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \ |
| 1856 | | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \ |
| 1857 | | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \ |
| 1858 | | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \ |
| 1859 | | PPC_MEM_SYNC | PPC_MEM_EIEIO \ |
| 1860 | | PPC_CACHE | PPC_CACHE_ICBI \ |
Alexander Graf | 8e33944 | 2013-01-29 13:36:02 +0100 | [diff] [blame] | 1861 | | PPC_CACHE_DCBZ \ |
David Gibson | 02d4eae | 2011-10-30 15:51:24 +0000 | [diff] [blame] | 1862 | | PPC_CACHE_DCBA | PPC_CACHE_LOCK \ |
| 1863 | | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \ |
| 1864 | | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \ |
| 1865 | | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \ |
| 1866 | | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \ |
| 1867 | | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \ |
| 1868 | | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \ |
| 1869 | | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \ |
| 1870 | | PPC_POPCNTWD) |
| 1871 | |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 1872 | /* extended type values */ |
| 1873 | |
| 1874 | /* BookE 2.06 PowerPC specification */ |
| 1875 | PPC2_BOOKE206 = 0x0000000000000001ULL, |
David Gibson | a734258 | 2011-10-17 18:15:41 +0000 | [diff] [blame] | 1876 | /* VSX (extensions to Altivec / VMX) */ |
| 1877 | PPC2_VSX = 0x0000000000000002ULL, |
| 1878 | /* Decimal Floating Point (DFP) */ |
| 1879 | PPC2_DFP = 0x0000000000000004ULL, |
Alexander Graf | 3f9f6a5 | 2012-01-31 03:13:30 +0100 | [diff] [blame] | 1880 | /* Embedded.Processor Control */ |
| 1881 | PPC2_PRCNTL = 0x0000000000000008ULL, |
Thomas Huth | cd6e932 | 2012-02-27 17:18:08 +0000 | [diff] [blame] | 1882 | /* Byte-reversed, indexed, double-word load and store */ |
| 1883 | PPC2_DBRX = 0x0000000000000010ULL, |
Aurelien Jarno | 9c2627b | 2013-04-20 08:56:15 +0000 | [diff] [blame] | 1884 | /* Book I 2.05 PowerPC specification */ |
| 1885 | PPC2_ISA205 = 0x0000000000000020ULL, |
Tom Musta | dbcc48f | 2014-01-15 08:10:28 -0600 | [diff] [blame] | 1886 | /* VSX additions in ISA 2.07 */ |
| 1887 | PPC2_VSX207 = 0x0000000000000040ULL, |
Tom Musta | 86ba37e | 2014-01-07 10:05:49 -0600 | [diff] [blame] | 1888 | /* ISA 2.06B bpermd */ |
| 1889 | PPC2_PERM_ISA206 = 0x0000000000000080ULL, |
Tom Musta | a824bc1 | 2014-01-07 10:05:50 -0600 | [diff] [blame] | 1890 | /* ISA 2.06B divide extended variants */ |
| 1891 | PPC2_DIVE_ISA206 = 0x0000000000000100ULL, |
Tom Musta | 1fa6c53 | 2014-01-07 10:05:55 -0600 | [diff] [blame] | 1892 | /* ISA 2.06B larx/stcx. instructions */ |
| 1893 | PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL, |
Tom Musta | 1b0bd00 | 2014-01-07 10:05:58 -0600 | [diff] [blame] | 1894 | /* ISA 2.06B floating point integer conversion */ |
| 1895 | PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL, |
Tom Musta | 29a0e4e | 2014-01-07 10:06:06 -0600 | [diff] [blame] | 1896 | /* ISA 2.06B floating point test instructions */ |
| 1897 | PPC2_FP_TST_ISA206 = 0x0000000000000800ULL, |
Tom Musta | 94840e0 | 2014-02-10 11:26:53 -0600 | [diff] [blame] | 1898 | /* ISA 2.07 bctar instruction */ |
| 1899 | PPC2_BCTAR_ISA207 = 0x0000000000001000ULL, |
Tom Musta | 38a8533 | 2014-02-10 11:26:56 -0600 | [diff] [blame] | 1900 | /* ISA 2.07 load/store quadword */ |
| 1901 | PPC2_LSQ_ISA207 = 0x0000000000002000ULL, |
Tom Musta | 32ea54a | 2014-02-12 15:22:52 -0600 | [diff] [blame] | 1902 | /* ISA 2.07 Altivec */ |
| 1903 | PPC2_ALTIVEC_207 = 0x0000000000004000ULL, |
Alexey Kardashevskiy | df99d30 | 2014-03-07 15:37:39 +1100 | [diff] [blame^] | 1904 | /* PowerISA 2.07 Book3s specification */ |
| 1905 | PPC2_ISA207S = 0x0000000000008000ULL, |
David Gibson | 02d4eae | 2011-10-30 15:51:24 +0000 | [diff] [blame] | 1906 | |
Tom Musta | 74f2399 | 2013-10-22 22:05:46 +1100 | [diff] [blame] | 1907 | #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ |
Tom Musta | a824bc1 | 2014-01-07 10:05:50 -0600 | [diff] [blame] | 1908 | PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ |
Tom Musta | 1b0bd00 | 2014-01-07 10:05:58 -0600 | [diff] [blame] | 1909 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ |
Tom Musta | 94840e0 | 2014-02-10 11:26:53 -0600 | [diff] [blame] | 1910 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ |
Tom Musta | 32ea54a | 2014-02-12 15:22:52 -0600 | [diff] [blame] | 1911 | PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ |
| 1912 | PPC2_ALTIVEC_207) |
Nathan Froyd | c29b735 | 2009-05-12 12:26:57 -0700 | [diff] [blame] | 1913 | }; |
| 1914 | |
| 1915 | /*****************************************************************************/ |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1916 | /* Memory access type : |
| 1917 | * may be needed for precise access rights control and precise exceptions. |
| 1918 | */ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 1919 | enum { |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 1920 | /* 1 bit to define user level / supervisor access */ |
| 1921 | ACCESS_USER = 0x00, |
| 1922 | ACCESS_SUPER = 0x01, |
| 1923 | /* Type of instruction that generated the access */ |
| 1924 | ACCESS_CODE = 0x10, /* Code fetch access */ |
| 1925 | ACCESS_INT = 0x20, /* Integer load/store access */ |
| 1926 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
| 1927 | ACCESS_RES = 0x40, /* load/store with reservation */ |
| 1928 | ACCESS_EXT = 0x50, /* external access */ |
| 1929 | ACCESS_CACHE = 0x60, /* Cache manipulation */ |
| 1930 | }; |
| 1931 | |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 1932 | /* Hardware interruption sources: |
| 1933 | * all those exception can be raised simulteaneously |
| 1934 | */ |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 1935 | /* Input pins definitions */ |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 1936 | enum { |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 1937 | /* 6xx bus input pins */ |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 1938 | PPC6xx_INPUT_HRESET = 0, |
| 1939 | PPC6xx_INPUT_SRESET = 1, |
| 1940 | PPC6xx_INPUT_CKSTP_IN = 2, |
| 1941 | PPC6xx_INPUT_MCP = 3, |
| 1942 | PPC6xx_INPUT_SMI = 4, |
| 1943 | PPC6xx_INPUT_INT = 5, |
j_mayer | d68f130 | 2007-10-14 09:27:16 +0000 | [diff] [blame] | 1944 | PPC6xx_INPUT_TBEN = 6, |
| 1945 | PPC6xx_INPUT_WAKEUP = 7, |
| 1946 | PPC6xx_INPUT_NB, |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 1947 | }; |
| 1948 | |
| 1949 | enum { |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 1950 | /* Embedded PowerPC input pins */ |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 1951 | PPCBookE_INPUT_HRESET = 0, |
| 1952 | PPCBookE_INPUT_SRESET = 1, |
| 1953 | PPCBookE_INPUT_CKSTP_IN = 2, |
| 1954 | PPCBookE_INPUT_MCP = 3, |
| 1955 | PPCBookE_INPUT_SMI = 4, |
| 1956 | PPCBookE_INPUT_INT = 5, |
| 1957 | PPCBookE_INPUT_CINT = 6, |
j_mayer | d68f130 | 2007-10-14 09:27:16 +0000 | [diff] [blame] | 1958 | PPCBookE_INPUT_NB, |
j_mayer | 24be5ae | 2007-04-12 21:24:29 +0000 | [diff] [blame] | 1959 | }; |
| 1960 | |
| 1961 | enum { |
aurel32 | 9fdc60b | 2009-03-02 16:42:32 +0000 | [diff] [blame] | 1962 | /* PowerPC E500 input pins */ |
| 1963 | PPCE500_INPUT_RESET_CORE = 0, |
| 1964 | PPCE500_INPUT_MCK = 1, |
| 1965 | PPCE500_INPUT_CINT = 3, |
| 1966 | PPCE500_INPUT_INT = 4, |
| 1967 | PPCE500_INPUT_DEBUG = 6, |
| 1968 | PPCE500_INPUT_NB, |
| 1969 | }; |
| 1970 | |
| 1971 | enum { |
j_mayer | 4e290a0 | 2007-10-01 01:27:10 +0000 | [diff] [blame] | 1972 | /* PowerPC 40x input pins */ |
| 1973 | PPC40x_INPUT_RESET_CORE = 0, |
| 1974 | PPC40x_INPUT_RESET_CHIP = 1, |
| 1975 | PPC40x_INPUT_RESET_SYS = 2, |
| 1976 | PPC40x_INPUT_CINT = 3, |
| 1977 | PPC40x_INPUT_INT = 4, |
| 1978 | PPC40x_INPUT_HALT = 5, |
| 1979 | PPC40x_INPUT_DEBUG = 6, |
| 1980 | PPC40x_INPUT_NB, |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 1981 | }; |
| 1982 | |
j_mayer | b4095fe | 2007-11-17 22:42:36 +0000 | [diff] [blame] | 1983 | enum { |
| 1984 | /* RCPU input pins */ |
| 1985 | PPCRCPU_INPUT_PORESET = 0, |
| 1986 | PPCRCPU_INPUT_HRESET = 1, |
| 1987 | PPCRCPU_INPUT_SRESET = 2, |
| 1988 | PPCRCPU_INPUT_IRQ0 = 3, |
| 1989 | PPCRCPU_INPUT_IRQ1 = 4, |
| 1990 | PPCRCPU_INPUT_IRQ2 = 5, |
| 1991 | PPCRCPU_INPUT_IRQ3 = 6, |
| 1992 | PPCRCPU_INPUT_IRQ4 = 7, |
| 1993 | PPCRCPU_INPUT_IRQ5 = 8, |
| 1994 | PPCRCPU_INPUT_IRQ6 = 9, |
| 1995 | PPCRCPU_INPUT_IRQ7 = 10, |
| 1996 | PPCRCPU_INPUT_NB, |
| 1997 | }; |
| 1998 | |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 1999 | #if defined(TARGET_PPC64) |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 2000 | enum { |
| 2001 | /* PowerPC 970 input pins */ |
| 2002 | PPC970_INPUT_HRESET = 0, |
| 2003 | PPC970_INPUT_SRESET = 1, |
| 2004 | PPC970_INPUT_CKSTP = 2, |
| 2005 | PPC970_INPUT_TBEN = 3, |
| 2006 | PPC970_INPUT_MCP = 4, |
| 2007 | PPC970_INPUT_INT = 5, |
| 2008 | PPC970_INPUT_THINT = 6, |
j_mayer | 7b62a95 | 2007-11-17 02:04:00 +0000 | [diff] [blame] | 2009 | PPC970_INPUT_NB, |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 2010 | }; |
David Gibson | 9d52e90 | 2011-04-01 15:15:19 +1100 | [diff] [blame] | 2011 | |
| 2012 | enum { |
| 2013 | /* POWER7 input pins */ |
| 2014 | POWER7_INPUT_INT = 0, |
| 2015 | /* POWER7 probably has other inputs, but we don't care about them |
| 2016 | * for any existing machine. We can wire these up when we need |
| 2017 | * them */ |
| 2018 | POWER7_INPUT_NB, |
| 2019 | }; |
j_mayer | 00af685 | 2007-10-03 01:05:39 +0000 | [diff] [blame] | 2020 | #endif |
j_mayer | d0dfae6 | 2007-04-16 07:34:39 +0000 | [diff] [blame] | 2021 | |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 2022 | /* Hardware exceptions definitions */ |
| 2023 | enum { |
| 2024 | /* External hardware exception sources */ |
j_mayer | e1833e1 | 2007-09-29 13:06:16 +0000 | [diff] [blame] | 2025 | PPC_INTERRUPT_RESET = 0, /* Reset exception */ |
j_mayer | d68f130 | 2007-10-14 09:27:16 +0000 | [diff] [blame] | 2026 | PPC_INTERRUPT_WAKEUP, /* Wakeup exception */ |
| 2027 | PPC_INTERRUPT_MCK, /* Machine check exception */ |
| 2028 | PPC_INTERRUPT_EXT, /* External interrupt */ |
| 2029 | PPC_INTERRUPT_SMI, /* System management interrupt */ |
| 2030 | PPC_INTERRUPT_CEXT, /* Critical external interrupt */ |
| 2031 | PPC_INTERRUPT_DEBUG, /* External debug exception */ |
| 2032 | PPC_INTERRUPT_THERM, /* Thermal exception */ |
j_mayer | e9df014 | 2007-04-09 22:45:36 +0000 | [diff] [blame] | 2033 | /* Internal hardware exception sources */ |
j_mayer | d68f130 | 2007-10-14 09:27:16 +0000 | [diff] [blame] | 2034 | PPC_INTERRUPT_DECR, /* Decrementer exception */ |
| 2035 | PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */ |
| 2036 | PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */ |
| 2037 | PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */ |
| 2038 | PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */ |
| 2039 | PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */ |
| 2040 | PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */ |
| 2041 | PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */ |
j_mayer | 4710357 | 2007-03-30 09:38:04 +0000 | [diff] [blame] | 2042 | }; |
| 2043 | |
Alexander Graf | fc0b2c0 | 2012-02-21 19:41:59 +0100 | [diff] [blame] | 2044 | /* CPU should be reset next, restart from scratch afterwards */ |
| 2045 | #define CPU_INTERRUPT_RESET CPU_INTERRUPT_TGT_INT_0 |
| 2046 | |
bellard | 9a64fbe | 2004-01-04 22:58:38 +0000 | [diff] [blame] | 2047 | /*****************************************************************************/ |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2048 | |
Richard Henderson | da91a00 | 2013-02-19 23:52:13 -0800 | [diff] [blame] | 2049 | static inline target_ulong cpu_read_xer(CPUPPCState *env) |
| 2050 | { |
| 2051 | return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA); |
| 2052 | } |
| 2053 | |
| 2054 | static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer) |
| 2055 | { |
| 2056 | env->so = (xer >> XER_SO) & 1; |
| 2057 | env->ov = (xer >> XER_OV) & 1; |
| 2058 | env->ca = (xer >> XER_CA) & 1; |
| 2059 | env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)); |
| 2060 | } |
| 2061 | |
Andreas Färber | 1328c2b | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 2062 | static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 2063 | target_ulong *cs_base, int *flags) |
| 2064 | { |
| 2065 | *pc = env->nip; |
| 2066 | *cs_base = 0; |
| 2067 | *flags = env->hflags; |
| 2068 | } |
| 2069 | |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2070 | #if !defined(CONFIG_USER_ONLY) |
Andreas Färber | 1328c2b | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 2071 | static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm) |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2072 | { |
Alexander Graf | d1e256f | 2011-06-16 18:45:43 +0200 | [diff] [blame] | 2073 | uintptr_t tlbml = (uintptr_t)tlbm; |
Alexander Graf | 1c53acc | 2011-06-17 01:00:28 +0200 | [diff] [blame] | 2074 | uintptr_t tlbl = (uintptr_t)env->tlb.tlbm; |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2075 | |
Alexander Graf | 1c53acc | 2011-06-17 01:00:28 +0200 | [diff] [blame] | 2076 | return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]); |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2077 | } |
| 2078 | |
Andreas Färber | 1328c2b | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 2079 | static inline int booke206_tlb_size(CPUPPCState *env, int tlbn) |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2080 | { |
| 2081 | uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; |
| 2082 | int r = tlbncfg & TLBnCFG_N_ENTRY; |
| 2083 | return r; |
| 2084 | } |
| 2085 | |
Andreas Färber | 1328c2b | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 2086 | static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn) |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2087 | { |
| 2088 | uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; |
| 2089 | int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT; |
| 2090 | return r; |
| 2091 | } |
| 2092 | |
Andreas Färber | 1328c2b | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 2093 | static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm) |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2094 | { |
Alexander Graf | d1e256f | 2011-06-16 18:45:43 +0200 | [diff] [blame] | 2095 | int id = booke206_tlbm_id(env, tlbm); |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2096 | int end = 0; |
| 2097 | int i; |
| 2098 | |
| 2099 | for (i = 0; i < BOOKE206_MAX_TLBN; i++) { |
| 2100 | end += booke206_tlb_size(env, i); |
| 2101 | if (id < end) { |
| 2102 | return i; |
| 2103 | } |
| 2104 | } |
| 2105 | |
Andreas Färber | a47dddd | 2013-09-03 17:38:47 +0200 | [diff] [blame] | 2106 | cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id); |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2107 | return 0; |
| 2108 | } |
| 2109 | |
Andreas Färber | 1328c2b | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 2110 | static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb) |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2111 | { |
Alexander Graf | d1e256f | 2011-06-16 18:45:43 +0200 | [diff] [blame] | 2112 | int tlbn = booke206_tlbm_to_tlbn(env, tlb); |
| 2113 | int tlbid = booke206_tlbm_id(env, tlb); |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2114 | return tlbid & (booke206_tlb_ways(env, tlbn) - 1); |
| 2115 | } |
| 2116 | |
Andreas Färber | 1328c2b | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 2117 | static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn, |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2118 | target_ulong ea, int way) |
| 2119 | { |
| 2120 | int r; |
| 2121 | uint32_t ways = booke206_tlb_ways(env, tlbn); |
| 2122 | int ways_bits = ffs(ways) - 1; |
| 2123 | int tlb_bits = ffs(booke206_tlb_size(env, tlbn)) - 1; |
| 2124 | int i; |
| 2125 | |
| 2126 | way &= ways - 1; |
| 2127 | ea >>= MAS2_EPN_SHIFT; |
| 2128 | ea &= (1 << (tlb_bits - ways_bits)) - 1; |
| 2129 | r = (ea << ways_bits) | way; |
| 2130 | |
Alexander Graf | 3f162d1 | 2012-01-25 16:27:26 +0100 | [diff] [blame] | 2131 | if (r >= booke206_tlb_size(env, tlbn)) { |
| 2132 | return NULL; |
| 2133 | } |
| 2134 | |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2135 | /* bump up to tlbn index */ |
| 2136 | for (i = 0; i < tlbn; i++) { |
| 2137 | r += booke206_tlb_size(env, i); |
| 2138 | } |
| 2139 | |
Alexander Graf | 1c53acc | 2011-06-17 01:00:28 +0200 | [diff] [blame] | 2140 | return &env->tlb.tlbm[r]; |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2141 | } |
| 2142 | |
Alexander Graf | a1ef618 | 2012-01-21 04:45:46 +0100 | [diff] [blame] | 2143 | /* returns bitmap of supported page sizes for a given TLB */ |
Andreas Färber | 1328c2b | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 2144 | static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn) |
Alexander Graf | a1ef618 | 2012-01-21 04:45:46 +0100 | [diff] [blame] | 2145 | { |
| 2146 | bool mav2 = false; |
| 2147 | uint32_t ret = 0; |
| 2148 | |
| 2149 | if (mav2) { |
| 2150 | ret = env->spr[SPR_BOOKE_TLB0PS + tlbn]; |
| 2151 | } else { |
| 2152 | uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; |
| 2153 | uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT; |
| 2154 | uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT; |
| 2155 | int i; |
| 2156 | for (i = min; i <= max; i++) { |
| 2157 | ret |= (1 << (i << 1)); |
| 2158 | } |
| 2159 | } |
| 2160 | |
| 2161 | return ret; |
| 2162 | } |
| 2163 | |
Alexander Graf | 01662f3 | 2011-04-30 23:34:58 +0200 | [diff] [blame] | 2164 | #endif |
| 2165 | |
Alexander Graf | e42a61f | 2012-06-20 21:20:29 +0200 | [diff] [blame] | 2166 | static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr) |
| 2167 | { |
| 2168 | if (env->mmu_model == POWERPC_MMU_BOOKE206) { |
| 2169 | return msr & (1ULL << MSR_CM); |
| 2170 | } |
| 2171 | |
| 2172 | return msr & (1ULL << MSR_SF); |
| 2173 | } |
| 2174 | |
Andreas Färber | 1b14670 | 2012-05-03 06:03:45 +0200 | [diff] [blame] | 2175 | extern void (*cpu_ppc_hypercall)(PowerPCCPU *); |
David Gibson | d569956 | 2011-04-01 15:15:10 +1100 | [diff] [blame] | 2176 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 2177 | #include "exec/exec-all.h" |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 2178 | |
Andreas Färber | 1328c2b | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 2179 | void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env); |
Scott Wood | bebabbc | 2011-08-18 10:38:42 +0000 | [diff] [blame] | 2180 | |
Alexey Kardashevskiy | 0ce470c | 2014-02-02 01:45:51 +1100 | [diff] [blame] | 2181 | /** |
| 2182 | * ppc_get_vcpu_dt_id: |
| 2183 | * @cs: a PowerPCCPU struct. |
| 2184 | * |
| 2185 | * Returns a device-tree ID for a CPU. |
| 2186 | */ |
| 2187 | int ppc_get_vcpu_dt_id(PowerPCCPU *cpu); |
| 2188 | |
| 2189 | /** |
| 2190 | * ppc_get_vcpu_by_dt_id: |
| 2191 | * @cpu_dt_id: a device tree id |
| 2192 | * |
| 2193 | * Searches for a CPU by @cpu_dt_id. |
| 2194 | * |
| 2195 | * Returns: a PowerPCCPU struct |
| 2196 | */ |
| 2197 | PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id); |
| 2198 | |
bellard | 79aceca | 2003-11-23 14:55:54 +0000 | [diff] [blame] | 2199 | #endif /* !defined (__CPU_PPC_H__) */ |