bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * MIPS emulation helpers for qemu. |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 18 | */ |
ths | 2d0e944 | 2007-04-02 15:54:05 +0000 | [diff] [blame] | 19 | #include <stdlib.h> |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 20 | #include "exec.h" |
| 21 | |
ths | 05f778c | 2007-10-27 13:05:54 +0000 | [diff] [blame] | 22 | #include "host-utils.h" |
| 23 | |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 24 | #include "helper.h" |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 25 | /*****************************************************************************/ |
| 26 | /* Exceptions processing helpers */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 27 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 28 | void helper_raise_exception_err (uint32_t exception, int error_code) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 29 | { |
| 30 | #if 1 |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 31 | if (exception < 0x100) |
| 32 | qemu_log("%s: %d %d\n", __func__, exception, error_code); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 33 | #endif |
| 34 | env->exception_index = exception; |
| 35 | env->error_code = error_code; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 36 | cpu_loop_exit(); |
| 37 | } |
| 38 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 39 | void helper_raise_exception (uint32_t exception) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 40 | { |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 41 | helper_raise_exception_err(exception, 0); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 42 | } |
| 43 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 44 | void helper_interrupt_restart (void) |
ths | 48d38ca | 2008-05-18 22:50:49 +0000 | [diff] [blame] | 45 | { |
| 46 | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
| 47 | !(env->CP0_Status & (1 << CP0St_ERL)) && |
| 48 | !(env->hflags & MIPS_HFLAG_DM) && |
| 49 | (env->CP0_Status & (1 << CP0St_IE)) && |
| 50 | (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) { |
| 51 | env->CP0_Cause &= ~(0x1f << CP0Ca_EC); |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 52 | helper_raise_exception(EXCP_EXT_INTERRUPT); |
ths | 48d38ca | 2008-05-18 22:50:49 +0000 | [diff] [blame] | 53 | } |
| 54 | } |
| 55 | |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 56 | #if !defined(CONFIG_USER_ONLY) |
| 57 | static void do_restore_state (void *pc_ptr) |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 58 | { |
bellard | a607922 | 2008-05-10 15:42:17 +0000 | [diff] [blame] | 59 | TranslationBlock *tb; |
| 60 | unsigned long pc = (unsigned long) pc_ptr; |
| 61 | |
| 62 | tb = tb_find_pc (pc); |
| 63 | if (tb) { |
| 64 | cpu_restore_state (tb, env, pc, NULL); |
| 65 | } |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 66 | } |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 67 | #endif |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 68 | |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 69 | #if defined(CONFIG_USER_ONLY) |
| 70 | #define HELPER_LD(name, insn, type) \ |
| 71 | static inline type do_##name(target_ulong addr, int mem_idx) \ |
| 72 | { \ |
| 73 | return (type) insn##_raw(addr); \ |
| 74 | } |
| 75 | #else |
| 76 | #define HELPER_LD(name, insn, type) \ |
| 77 | static inline type do_##name(target_ulong addr, int mem_idx) \ |
| 78 | { \ |
| 79 | switch (mem_idx) \ |
| 80 | { \ |
| 81 | case 0: return (type) insn##_kernel(addr); break; \ |
| 82 | case 1: return (type) insn##_super(addr); break; \ |
| 83 | default: \ |
| 84 | case 2: return (type) insn##_user(addr); break; \ |
| 85 | } \ |
| 86 | } |
| 87 | #endif |
| 88 | HELPER_LD(lbu, ldub, uint8_t) |
| 89 | HELPER_LD(lw, ldl, int32_t) |
| 90 | #ifdef TARGET_MIPS64 |
| 91 | HELPER_LD(ld, ldq, int64_t) |
| 92 | #endif |
| 93 | #undef HELPER_LD |
| 94 | |
| 95 | #if defined(CONFIG_USER_ONLY) |
| 96 | #define HELPER_ST(name, insn, type) \ |
| 97 | static inline void do_##name(target_ulong addr, type val, int mem_idx) \ |
| 98 | { \ |
| 99 | insn##_raw(addr, val); \ |
| 100 | } |
| 101 | #else |
| 102 | #define HELPER_ST(name, insn, type) \ |
| 103 | static inline void do_##name(target_ulong addr, type val, int mem_idx) \ |
| 104 | { \ |
| 105 | switch (mem_idx) \ |
| 106 | { \ |
| 107 | case 0: insn##_kernel(addr, val); break; \ |
| 108 | case 1: insn##_super(addr, val); break; \ |
| 109 | default: \ |
| 110 | case 2: insn##_user(addr, val); break; \ |
| 111 | } \ |
| 112 | } |
| 113 | #endif |
| 114 | HELPER_ST(sb, stb, uint8_t) |
| 115 | HELPER_ST(sw, stl, uint32_t) |
| 116 | #ifdef TARGET_MIPS64 |
| 117 | HELPER_ST(sd, stq, uint64_t) |
| 118 | #endif |
| 119 | #undef HELPER_ST |
| 120 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 121 | target_ulong helper_clo (target_ulong arg1) |
ths | 3089880 | 2008-05-21 02:04:15 +0000 | [diff] [blame] | 122 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 123 | return clo32(arg1); |
ths | 3089880 | 2008-05-21 02:04:15 +0000 | [diff] [blame] | 124 | } |
| 125 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 126 | target_ulong helper_clz (target_ulong arg1) |
ths | 3089880 | 2008-05-21 02:04:15 +0000 | [diff] [blame] | 127 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 128 | return clz32(arg1); |
ths | 3089880 | 2008-05-21 02:04:15 +0000 | [diff] [blame] | 129 | } |
| 130 | |
ths | d26bc21 | 2007-11-08 18:05:37 +0000 | [diff] [blame] | 131 | #if defined(TARGET_MIPS64) |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 132 | target_ulong helper_dclo (target_ulong arg1) |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 133 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 134 | return clo64(arg1); |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 135 | } |
| 136 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 137 | target_ulong helper_dclz (target_ulong arg1) |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 138 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 139 | return clz64(arg1); |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 140 | } |
ths | d26bc21 | 2007-11-08 18:05:37 +0000 | [diff] [blame] | 141 | #endif /* TARGET_MIPS64 */ |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 142 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 143 | /* 64 bits arithmetic for 32 bits hosts */ |
ths | c904ef0 | 2008-07-23 16:16:31 +0000 | [diff] [blame] | 144 | static inline uint64_t get_HILO (void) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 145 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 146 | return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0]; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 147 | } |
| 148 | |
ths | c904ef0 | 2008-07-23 16:16:31 +0000 | [diff] [blame] | 149 | static inline void set_HILO (uint64_t HILO) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 150 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 151 | env->active_tc.LO[0] = (int32_t)HILO; |
| 152 | env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 153 | } |
| 154 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 155 | static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 156 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 157 | env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 158 | arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 159 | } |
| 160 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 161 | static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 162 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 163 | arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 164 | env->active_tc.HI[0] = (int32_t)(HILO >> 32); |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 165 | } |
| 166 | |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 167 | /* Multiplication variants of the vr54xx. */ |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 168 | target_ulong helper_muls (target_ulong arg1, target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 169 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 170 | set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 171 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 172 | return arg1; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 173 | } |
| 174 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 175 | target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 176 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 177 | set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 178 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 179 | return arg1; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 180 | } |
| 181 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 182 | target_ulong helper_macc (target_ulong arg1, target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 183 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 184 | set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 185 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 186 | return arg1; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 187 | } |
| 188 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 189 | target_ulong helper_macchi (target_ulong arg1, target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 190 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 191 | set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 192 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 193 | return arg1; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 194 | } |
| 195 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 196 | target_ulong helper_maccu (target_ulong arg1, target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 197 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 198 | set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 199 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 200 | return arg1; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 201 | } |
| 202 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 203 | target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 204 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 205 | set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 206 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 207 | return arg1; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 208 | } |
| 209 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 210 | target_ulong helper_msac (target_ulong arg1, target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 211 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 212 | set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 213 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 214 | return arg1; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 215 | } |
| 216 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 217 | target_ulong helper_msachi (target_ulong arg1, target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 218 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 219 | set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 220 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 221 | return arg1; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 222 | } |
| 223 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 224 | target_ulong helper_msacu (target_ulong arg1, target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 225 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 226 | set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 227 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 228 | return arg1; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 229 | } |
| 230 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 231 | target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 232 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 233 | set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 234 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 235 | return arg1; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 236 | } |
| 237 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 238 | target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 239 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 240 | set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 241 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 242 | return arg1; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 243 | } |
| 244 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 245 | target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 246 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 247 | set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 248 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 249 | return arg1; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 250 | } |
| 251 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 252 | target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 253 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 254 | set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2)); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 255 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 256 | return arg1; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 257 | } |
| 258 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 259 | target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2) |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 260 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 261 | set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2)); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 262 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 263 | return arg1; |
ths | e9c71dd | 2007-12-25 20:46:56 +0000 | [diff] [blame] | 264 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 265 | |
ths | 214c465 | 2008-06-12 12:43:29 +0000 | [diff] [blame] | 266 | #ifdef TARGET_MIPS64 |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 267 | void helper_dmult (target_ulong arg1, target_ulong arg2) |
ths | 214c465 | 2008-06-12 12:43:29 +0000 | [diff] [blame] | 268 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 269 | muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); |
ths | 214c465 | 2008-06-12 12:43:29 +0000 | [diff] [blame] | 270 | } |
| 271 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 272 | void helper_dmultu (target_ulong arg1, target_ulong arg2) |
ths | 214c465 | 2008-06-12 12:43:29 +0000 | [diff] [blame] | 273 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 274 | mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2); |
ths | 214c465 | 2008-06-12 12:43:29 +0000 | [diff] [blame] | 275 | } |
| 276 | #endif |
| 277 | |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 278 | #ifndef CONFIG_USER_ONLY |
Aurelien Jarno | c36bbb2 | 2010-02-06 17:02:45 +0100 | [diff] [blame] | 279 | |
| 280 | static inline target_phys_addr_t do_translate_address(target_ulong address, int rw) |
| 281 | { |
| 282 | target_phys_addr_t lladdr; |
| 283 | |
| 284 | lladdr = cpu_mips_translate_address(env, address, rw); |
| 285 | |
| 286 | if (lladdr == -1LL) { |
| 287 | cpu_loop_exit(); |
| 288 | } else { |
| 289 | return lladdr; |
| 290 | } |
| 291 | } |
| 292 | |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 293 | #define HELPER_LD_ATOMIC(name, insn) \ |
| 294 | target_ulong helper_##name(target_ulong arg, int mem_idx) \ |
| 295 | { \ |
Aurelien Jarno | c36bbb2 | 2010-02-06 17:02:45 +0100 | [diff] [blame] | 296 | env->lladdr = do_translate_address(arg, 0); \ |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 297 | env->llval = do_##insn(arg, mem_idx); \ |
| 298 | return env->llval; \ |
| 299 | } |
| 300 | HELPER_LD_ATOMIC(ll, lw) |
| 301 | #ifdef TARGET_MIPS64 |
| 302 | HELPER_LD_ATOMIC(lld, ld) |
| 303 | #endif |
| 304 | #undef HELPER_LD_ATOMIC |
| 305 | |
| 306 | #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \ |
| 307 | target_ulong helper_##name(target_ulong arg1, target_ulong arg2, int mem_idx) \ |
| 308 | { \ |
| 309 | target_long tmp; \ |
| 310 | \ |
| 311 | if (arg2 & almask) { \ |
| 312 | env->CP0_BadVAddr = arg2; \ |
| 313 | helper_raise_exception(EXCP_AdES); \ |
| 314 | } \ |
Aurelien Jarno | c36bbb2 | 2010-02-06 17:02:45 +0100 | [diff] [blame] | 315 | if (do_translate_address(arg2, 1) == env->lladdr) { \ |
Aurelien Jarno | e7139c4 | 2009-11-30 15:39:54 +0100 | [diff] [blame] | 316 | tmp = do_##ld_insn(arg2, mem_idx); \ |
| 317 | if (tmp == env->llval) { \ |
| 318 | do_##st_insn(arg2, arg1, mem_idx); \ |
| 319 | return 1; \ |
| 320 | } \ |
| 321 | } \ |
| 322 | return 0; \ |
| 323 | } |
| 324 | HELPER_ST_ATOMIC(sc, lw, sw, 0x3) |
| 325 | #ifdef TARGET_MIPS64 |
| 326 | HELPER_ST_ATOMIC(scd, ld, sd, 0x7) |
| 327 | #endif |
| 328 | #undef HELPER_ST_ATOMIC |
| 329 | #endif |
| 330 | |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 331 | #ifdef TARGET_WORDS_BIGENDIAN |
| 332 | #define GET_LMASK(v) ((v) & 3) |
| 333 | #define GET_OFFSET(addr, offset) (addr + (offset)) |
| 334 | #else |
| 335 | #define GET_LMASK(v) (((v) & 3) ^ 3) |
| 336 | #define GET_OFFSET(addr, offset) (addr - (offset)) |
| 337 | #endif |
| 338 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 339 | target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx) |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 340 | { |
| 341 | target_ulong tmp; |
| 342 | |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 343 | tmp = do_lbu(arg2, mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 344 | arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 345 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 346 | if (GET_LMASK(arg2) <= 2) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 347 | tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 348 | arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 349 | } |
| 350 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 351 | if (GET_LMASK(arg2) <= 1) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 352 | tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 353 | arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 354 | } |
| 355 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 356 | if (GET_LMASK(arg2) == 0) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 357 | tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 358 | arg1 = (arg1 & 0xFFFFFF00) | tmp; |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 359 | } |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 360 | return (int32_t)arg1; |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 361 | } |
| 362 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 363 | target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx) |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 364 | { |
| 365 | target_ulong tmp; |
| 366 | |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 367 | tmp = do_lbu(arg2, mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 368 | arg1 = (arg1 & 0xFFFFFF00) | tmp; |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 369 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 370 | if (GET_LMASK(arg2) >= 1) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 371 | tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 372 | arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 373 | } |
| 374 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 375 | if (GET_LMASK(arg2) >= 2) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 376 | tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 377 | arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 378 | } |
| 379 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 380 | if (GET_LMASK(arg2) == 3) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 381 | tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 382 | arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 383 | } |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 384 | return (int32_t)arg1; |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 385 | } |
| 386 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 387 | void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx) |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 388 | { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 389 | do_sb(arg2, (uint8_t)(arg1 >> 24), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 390 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 391 | if (GET_LMASK(arg2) <= 2) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 392 | do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 393 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 394 | if (GET_LMASK(arg2) <= 1) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 395 | do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 396 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 397 | if (GET_LMASK(arg2) == 0) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 398 | do_sb(GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 399 | } |
| 400 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 401 | void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx) |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 402 | { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 403 | do_sb(arg2, (uint8_t)arg1, mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 404 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 405 | if (GET_LMASK(arg2) >= 1) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 406 | do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 407 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 408 | if (GET_LMASK(arg2) >= 2) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 409 | do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 410 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 411 | if (GET_LMASK(arg2) == 3) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 412 | do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 413 | } |
| 414 | |
| 415 | #if defined(TARGET_MIPS64) |
| 416 | /* "half" load and stores. We must do the memory access inline, |
| 417 | or fault handling won't work. */ |
| 418 | |
| 419 | #ifdef TARGET_WORDS_BIGENDIAN |
| 420 | #define GET_LMASK64(v) ((v) & 7) |
| 421 | #else |
| 422 | #define GET_LMASK64(v) (((v) & 7) ^ 7) |
| 423 | #endif |
| 424 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 425 | target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx) |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 426 | { |
| 427 | uint64_t tmp; |
| 428 | |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 429 | tmp = do_lbu(arg2, mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 430 | arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 431 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 432 | if (GET_LMASK64(arg2) <= 6) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 433 | tmp = do_lbu(GET_OFFSET(arg2, 1), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 434 | arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 435 | } |
| 436 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 437 | if (GET_LMASK64(arg2) <= 5) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 438 | tmp = do_lbu(GET_OFFSET(arg2, 2), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 439 | arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 440 | } |
| 441 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 442 | if (GET_LMASK64(arg2) <= 4) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 443 | tmp = do_lbu(GET_OFFSET(arg2, 3), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 444 | arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 445 | } |
| 446 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 447 | if (GET_LMASK64(arg2) <= 3) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 448 | tmp = do_lbu(GET_OFFSET(arg2, 4), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 449 | arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 450 | } |
| 451 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 452 | if (GET_LMASK64(arg2) <= 2) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 453 | tmp = do_lbu(GET_OFFSET(arg2, 5), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 454 | arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 455 | } |
| 456 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 457 | if (GET_LMASK64(arg2) <= 1) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 458 | tmp = do_lbu(GET_OFFSET(arg2, 6), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 459 | arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 460 | } |
| 461 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 462 | if (GET_LMASK64(arg2) == 0) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 463 | tmp = do_lbu(GET_OFFSET(arg2, 7), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 464 | arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 465 | } |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 466 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 467 | return arg1; |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 468 | } |
| 469 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 470 | target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx) |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 471 | { |
| 472 | uint64_t tmp; |
| 473 | |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 474 | tmp = do_lbu(arg2, mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 475 | arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 476 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 477 | if (GET_LMASK64(arg2) >= 1) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 478 | tmp = do_lbu(GET_OFFSET(arg2, -1), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 479 | arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 480 | } |
| 481 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 482 | if (GET_LMASK64(arg2) >= 2) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 483 | tmp = do_lbu(GET_OFFSET(arg2, -2), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 484 | arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 485 | } |
| 486 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 487 | if (GET_LMASK64(arg2) >= 3) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 488 | tmp = do_lbu(GET_OFFSET(arg2, -3), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 489 | arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 490 | } |
| 491 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 492 | if (GET_LMASK64(arg2) >= 4) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 493 | tmp = do_lbu(GET_OFFSET(arg2, -4), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 494 | arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 495 | } |
| 496 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 497 | if (GET_LMASK64(arg2) >= 5) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 498 | tmp = do_lbu(GET_OFFSET(arg2, -5), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 499 | arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 500 | } |
| 501 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 502 | if (GET_LMASK64(arg2) >= 6) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 503 | tmp = do_lbu(GET_OFFSET(arg2, -6), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 504 | arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 505 | } |
| 506 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 507 | if (GET_LMASK64(arg2) == 7) { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 508 | tmp = do_lbu(GET_OFFSET(arg2, -7), mem_idx); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 509 | arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 510 | } |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 511 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 512 | return arg1; |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 513 | } |
| 514 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 515 | void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx) |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 516 | { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 517 | do_sb(arg2, (uint8_t)(arg1 >> 56), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 518 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 519 | if (GET_LMASK64(arg2) <= 6) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 520 | do_sb(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 521 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 522 | if (GET_LMASK64(arg2) <= 5) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 523 | do_sb(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 524 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 525 | if (GET_LMASK64(arg2) <= 4) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 526 | do_sb(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 527 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 528 | if (GET_LMASK64(arg2) <= 3) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 529 | do_sb(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 530 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 531 | if (GET_LMASK64(arg2) <= 2) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 532 | do_sb(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 533 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 534 | if (GET_LMASK64(arg2) <= 1) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 535 | do_sb(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 536 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 537 | if (GET_LMASK64(arg2) <= 0) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 538 | do_sb(GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 539 | } |
| 540 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 541 | void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx) |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 542 | { |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 543 | do_sb(arg2, (uint8_t)arg1, mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 544 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 545 | if (GET_LMASK64(arg2) >= 1) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 546 | do_sb(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 547 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 548 | if (GET_LMASK64(arg2) >= 2) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 549 | do_sb(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 550 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 551 | if (GET_LMASK64(arg2) >= 3) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 552 | do_sb(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 553 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 554 | if (GET_LMASK64(arg2) >= 4) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 555 | do_sb(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 556 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 557 | if (GET_LMASK64(arg2) >= 5) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 558 | do_sb(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 559 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 560 | if (GET_LMASK64(arg2) >= 6) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 561 | do_sb(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 562 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 563 | if (GET_LMASK64(arg2) == 7) |
Aurelien Jarno | 0ae4304 | 2009-11-30 15:32:47 +0100 | [diff] [blame] | 564 | do_sb(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); |
ths | c8c2227 | 2008-06-20 15:12:14 +0000 | [diff] [blame] | 565 | } |
| 566 | #endif /* TARGET_MIPS64 */ |
| 567 | |
ths | 0eaef5a | 2008-07-23 16:14:22 +0000 | [diff] [blame] | 568 | #ifndef CONFIG_USER_ONLY |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 569 | /* CP0 helpers */ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 570 | target_ulong helper_mfc0_mvpcontrol (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 571 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 572 | return env->mvp->CP0_MVPControl; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 573 | } |
| 574 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 575 | target_ulong helper_mfc0_mvpconf0 (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 576 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 577 | return env->mvp->CP0_MVPConf0; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 578 | } |
| 579 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 580 | target_ulong helper_mfc0_mvpconf1 (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 581 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 582 | return env->mvp->CP0_MVPConf1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 583 | } |
| 584 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 585 | target_ulong helper_mfc0_random (void) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 586 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 587 | return (int32_t)cpu_mips_get_random(env); |
ths | 873eb01 | 2006-12-06 17:59:07 +0000 | [diff] [blame] | 588 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 589 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 590 | target_ulong helper_mfc0_tcstatus (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 591 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 592 | return env->active_tc.CP0_TCStatus; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 593 | } |
| 594 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 595 | target_ulong helper_mftc0_tcstatus(void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 596 | { |
| 597 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 598 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 599 | if (other_tc == env->current_tc) |
| 600 | return env->active_tc.CP0_TCStatus; |
| 601 | else |
| 602 | return env->tcs[other_tc].CP0_TCStatus; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 603 | } |
| 604 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 605 | target_ulong helper_mfc0_tcbind (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 606 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 607 | return env->active_tc.CP0_TCBind; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 608 | } |
| 609 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 610 | target_ulong helper_mftc0_tcbind(void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 611 | { |
| 612 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 613 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 614 | if (other_tc == env->current_tc) |
| 615 | return env->active_tc.CP0_TCBind; |
| 616 | else |
| 617 | return env->tcs[other_tc].CP0_TCBind; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 618 | } |
| 619 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 620 | target_ulong helper_mfc0_tcrestart (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 621 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 622 | return env->active_tc.PC; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 623 | } |
| 624 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 625 | target_ulong helper_mftc0_tcrestart(void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 626 | { |
| 627 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 628 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 629 | if (other_tc == env->current_tc) |
| 630 | return env->active_tc.PC; |
| 631 | else |
| 632 | return env->tcs[other_tc].PC; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 633 | } |
| 634 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 635 | target_ulong helper_mfc0_tchalt (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 636 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 637 | return env->active_tc.CP0_TCHalt; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 638 | } |
| 639 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 640 | target_ulong helper_mftc0_tchalt(void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 641 | { |
| 642 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 643 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 644 | if (other_tc == env->current_tc) |
| 645 | return env->active_tc.CP0_TCHalt; |
| 646 | else |
| 647 | return env->tcs[other_tc].CP0_TCHalt; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 648 | } |
| 649 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 650 | target_ulong helper_mfc0_tccontext (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 651 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 652 | return env->active_tc.CP0_TCContext; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 653 | } |
| 654 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 655 | target_ulong helper_mftc0_tccontext(void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 656 | { |
| 657 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 658 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 659 | if (other_tc == env->current_tc) |
| 660 | return env->active_tc.CP0_TCContext; |
| 661 | else |
| 662 | return env->tcs[other_tc].CP0_TCContext; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 663 | } |
| 664 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 665 | target_ulong helper_mfc0_tcschedule (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 666 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 667 | return env->active_tc.CP0_TCSchedule; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 668 | } |
| 669 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 670 | target_ulong helper_mftc0_tcschedule(void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 671 | { |
| 672 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 673 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 674 | if (other_tc == env->current_tc) |
| 675 | return env->active_tc.CP0_TCSchedule; |
| 676 | else |
| 677 | return env->tcs[other_tc].CP0_TCSchedule; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 678 | } |
| 679 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 680 | target_ulong helper_mfc0_tcschefback (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 681 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 682 | return env->active_tc.CP0_TCScheFBack; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 683 | } |
| 684 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 685 | target_ulong helper_mftc0_tcschefback(void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 686 | { |
| 687 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 688 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 689 | if (other_tc == env->current_tc) |
| 690 | return env->active_tc.CP0_TCScheFBack; |
| 691 | else |
| 692 | return env->tcs[other_tc].CP0_TCScheFBack; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 693 | } |
| 694 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 695 | target_ulong helper_mfc0_count (void) |
ths | 873eb01 | 2006-12-06 17:59:07 +0000 | [diff] [blame] | 696 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 697 | return (int32_t)cpu_mips_get_count(env); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 698 | } |
| 699 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 700 | target_ulong helper_mftc0_entryhi(void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 701 | { |
| 702 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 703 | int32_t tcstatus; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 704 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 705 | if (other_tc == env->current_tc) |
| 706 | tcstatus = env->active_tc.CP0_TCStatus; |
| 707 | else |
| 708 | tcstatus = env->tcs[other_tc].CP0_TCStatus; |
| 709 | |
| 710 | return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 711 | } |
| 712 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 713 | target_ulong helper_mftc0_status(void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 714 | { |
| 715 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
ths | 1a3fd9c | 2008-06-24 21:58:35 +0000 | [diff] [blame] | 716 | target_ulong t0; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 717 | int32_t tcstatus; |
| 718 | |
| 719 | if (other_tc == env->current_tc) |
| 720 | tcstatus = env->active_tc.CP0_TCStatus; |
| 721 | else |
| 722 | tcstatus = env->tcs[other_tc].CP0_TCStatus; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 723 | |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 724 | t0 = env->CP0_Status & ~0xf1000018; |
| 725 | t0 |= tcstatus & (0xf << CP0TCSt_TCU0); |
| 726 | t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX); |
| 727 | t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU); |
| 728 | |
| 729 | return t0; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 730 | } |
| 731 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 732 | target_ulong helper_mfc0_lladdr (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 733 | { |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 734 | return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 735 | } |
| 736 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 737 | target_ulong helper_mfc0_watchlo (uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 738 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 739 | return (int32_t)env->CP0_WatchLo[sel]; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 740 | } |
| 741 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 742 | target_ulong helper_mfc0_watchhi (uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 743 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 744 | return env->CP0_WatchHi[sel]; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 745 | } |
| 746 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 747 | target_ulong helper_mfc0_debug (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 748 | { |
ths | 1a3fd9c | 2008-06-24 21:58:35 +0000 | [diff] [blame] | 749 | target_ulong t0 = env->CP0_Debug; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 750 | if (env->hflags & MIPS_HFLAG_DM) |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 751 | t0 |= 1 << CP0DB_DM; |
| 752 | |
| 753 | return t0; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 754 | } |
| 755 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 756 | target_ulong helper_mftc0_debug(void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 757 | { |
| 758 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 759 | int32_t tcstatus; |
| 760 | |
| 761 | if (other_tc == env->current_tc) |
| 762 | tcstatus = env->active_tc.CP0_Debug_tcstatus; |
| 763 | else |
| 764 | tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 765 | |
| 766 | /* XXX: Might be wrong, check with EJTAG spec. */ |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 767 | return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 768 | (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 769 | } |
| 770 | |
| 771 | #if defined(TARGET_MIPS64) |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 772 | target_ulong helper_dmfc0_tcrestart (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 773 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 774 | return env->active_tc.PC; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 775 | } |
| 776 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 777 | target_ulong helper_dmfc0_tchalt (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 778 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 779 | return env->active_tc.CP0_TCHalt; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 780 | } |
| 781 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 782 | target_ulong helper_dmfc0_tccontext (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 783 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 784 | return env->active_tc.CP0_TCContext; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 785 | } |
| 786 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 787 | target_ulong helper_dmfc0_tcschedule (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 788 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 789 | return env->active_tc.CP0_TCSchedule; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 790 | } |
| 791 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 792 | target_ulong helper_dmfc0_tcschefback (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 793 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 794 | return env->active_tc.CP0_TCScheFBack; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 795 | } |
| 796 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 797 | target_ulong helper_dmfc0_lladdr (void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 798 | { |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 799 | return env->lladdr >> env->CP0_LLAddr_shift; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 800 | } |
| 801 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 802 | target_ulong helper_dmfc0_watchlo (uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 803 | { |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 804 | return env->CP0_WatchLo[sel]; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 805 | } |
| 806 | #endif /* TARGET_MIPS64 */ |
| 807 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 808 | void helper_mtc0_index (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 809 | { |
| 810 | int num = 1; |
| 811 | unsigned int tmp = env->tlb->nb_tlb; |
| 812 | |
| 813 | do { |
| 814 | tmp >>= 1; |
| 815 | num <<= 1; |
| 816 | } while (tmp); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 817 | env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1)); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 818 | } |
| 819 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 820 | void helper_mtc0_mvpcontrol (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 821 | { |
| 822 | uint32_t mask = 0; |
| 823 | uint32_t newval; |
| 824 | |
| 825 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) |
| 826 | mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | |
| 827 | (1 << CP0MVPCo_EVP); |
| 828 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 829 | mask |= (1 << CP0MVPCo_STLB); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 830 | newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 831 | |
| 832 | // TODO: Enable/disable shared TLB, enable/disable VPEs. |
| 833 | |
| 834 | env->mvp->CP0_MVPControl = newval; |
| 835 | } |
| 836 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 837 | void helper_mtc0_vpecontrol (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 838 | { |
| 839 | uint32_t mask; |
| 840 | uint32_t newval; |
| 841 | |
| 842 | mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | |
| 843 | (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 844 | newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 845 | |
| 846 | /* Yield scheduler intercept not implemented. */ |
| 847 | /* Gating storage scheduler intercept not implemented. */ |
| 848 | |
| 849 | // TODO: Enable/disable TCs. |
| 850 | |
| 851 | env->CP0_VPEControl = newval; |
| 852 | } |
| 853 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 854 | void helper_mtc0_vpeconf0 (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 855 | { |
| 856 | uint32_t mask = 0; |
| 857 | uint32_t newval; |
| 858 | |
| 859 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { |
| 860 | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) |
| 861 | mask |= (0xff << CP0VPEC0_XTC); |
| 862 | mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); |
| 863 | } |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 864 | newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 865 | |
| 866 | // TODO: TC exclusive handling due to ERL/EXL. |
| 867 | |
| 868 | env->CP0_VPEConf0 = newval; |
| 869 | } |
| 870 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 871 | void helper_mtc0_vpeconf1 (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 872 | { |
| 873 | uint32_t mask = 0; |
| 874 | uint32_t newval; |
| 875 | |
| 876 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 877 | mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | |
| 878 | (0xff << CP0VPEC1_NCP1); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 879 | newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 880 | |
| 881 | /* UDI not implemented. */ |
| 882 | /* CP2 not implemented. */ |
| 883 | |
| 884 | // TODO: Handle FPU (CP1) binding. |
| 885 | |
| 886 | env->CP0_VPEConf1 = newval; |
| 887 | } |
| 888 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 889 | void helper_mtc0_yqmask (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 890 | { |
| 891 | /* Yield qualifier inputs not implemented. */ |
| 892 | env->CP0_YQMask = 0x00000000; |
| 893 | } |
| 894 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 895 | void helper_mtc0_vpeopt (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 896 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 897 | env->CP0_VPEOpt = arg1 & 0x0000ffff; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 898 | } |
| 899 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 900 | void helper_mtc0_entrylo0 (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 901 | { |
| 902 | /* Large physaddr (PABITS) not implemented */ |
| 903 | /* 1k pages not implemented */ |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 904 | env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 905 | } |
| 906 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 907 | void helper_mtc0_tcstatus (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 908 | { |
| 909 | uint32_t mask = env->CP0_TCStatus_rw_bitmask; |
| 910 | uint32_t newval; |
| 911 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 912 | newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 913 | |
| 914 | // TODO: Sync with CP0_Status. |
| 915 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 916 | env->active_tc.CP0_TCStatus = newval; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 917 | } |
| 918 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 919 | void helper_mttc0_tcstatus (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 920 | { |
| 921 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 922 | |
| 923 | // TODO: Sync with CP0_Status. |
| 924 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 925 | if (other_tc == env->current_tc) |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 926 | env->active_tc.CP0_TCStatus = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 927 | else |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 928 | env->tcs[other_tc].CP0_TCStatus = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 929 | } |
| 930 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 931 | void helper_mtc0_tcbind (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 932 | { |
| 933 | uint32_t mask = (1 << CP0TCBd_TBE); |
| 934 | uint32_t newval; |
| 935 | |
| 936 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 937 | mask |= (1 << CP0TCBd_CurVPE); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 938 | newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 939 | env->active_tc.CP0_TCBind = newval; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 940 | } |
| 941 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 942 | void helper_mttc0_tcbind (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 943 | { |
| 944 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 945 | uint32_t mask = (1 << CP0TCBd_TBE); |
| 946 | uint32_t newval; |
| 947 | |
| 948 | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 949 | mask |= (1 << CP0TCBd_CurVPE); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 950 | if (other_tc == env->current_tc) { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 951 | newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 952 | env->active_tc.CP0_TCBind = newval; |
| 953 | } else { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 954 | newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 955 | env->tcs[other_tc].CP0_TCBind = newval; |
| 956 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 957 | } |
| 958 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 959 | void helper_mtc0_tcrestart (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 960 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 961 | env->active_tc.PC = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 962 | env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); |
Aurelien Jarno | 5499b6f | 2009-11-22 13:08:14 +0100 | [diff] [blame] | 963 | env->lladdr = 0ULL; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 964 | /* MIPS16 not implemented. */ |
| 965 | } |
| 966 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 967 | void helper_mttc0_tcrestart (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 968 | { |
| 969 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 970 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 971 | if (other_tc == env->current_tc) { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 972 | env->active_tc.PC = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 973 | env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS); |
Aurelien Jarno | 5499b6f | 2009-11-22 13:08:14 +0100 | [diff] [blame] | 974 | env->lladdr = 0ULL; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 975 | /* MIPS16 not implemented. */ |
| 976 | } else { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 977 | env->tcs[other_tc].PC = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 978 | env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS); |
Aurelien Jarno | 5499b6f | 2009-11-22 13:08:14 +0100 | [diff] [blame] | 979 | env->lladdr = 0ULL; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 980 | /* MIPS16 not implemented. */ |
| 981 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 982 | } |
| 983 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 984 | void helper_mtc0_tchalt (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 985 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 986 | env->active_tc.CP0_TCHalt = arg1 & 0x1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 987 | |
| 988 | // TODO: Halt TC / Restart (if allocated+active) TC. |
| 989 | } |
| 990 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 991 | void helper_mttc0_tchalt (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 992 | { |
| 993 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 994 | |
| 995 | // TODO: Halt TC / Restart (if allocated+active) TC. |
| 996 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 997 | if (other_tc == env->current_tc) |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 998 | env->active_tc.CP0_TCHalt = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 999 | else |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1000 | env->tcs[other_tc].CP0_TCHalt = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1001 | } |
| 1002 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1003 | void helper_mtc0_tccontext (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1004 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1005 | env->active_tc.CP0_TCContext = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1006 | } |
| 1007 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1008 | void helper_mttc0_tccontext (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1009 | { |
| 1010 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1011 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1012 | if (other_tc == env->current_tc) |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1013 | env->active_tc.CP0_TCContext = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1014 | else |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1015 | env->tcs[other_tc].CP0_TCContext = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1016 | } |
| 1017 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1018 | void helper_mtc0_tcschedule (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1019 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1020 | env->active_tc.CP0_TCSchedule = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1021 | } |
| 1022 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1023 | void helper_mttc0_tcschedule (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1024 | { |
| 1025 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1026 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1027 | if (other_tc == env->current_tc) |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1028 | env->active_tc.CP0_TCSchedule = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1029 | else |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1030 | env->tcs[other_tc].CP0_TCSchedule = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1031 | } |
| 1032 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1033 | void helper_mtc0_tcschefback (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1034 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1035 | env->active_tc.CP0_TCScheFBack = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1036 | } |
| 1037 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1038 | void helper_mttc0_tcschefback (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1039 | { |
| 1040 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1041 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1042 | if (other_tc == env->current_tc) |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1043 | env->active_tc.CP0_TCScheFBack = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1044 | else |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1045 | env->tcs[other_tc].CP0_TCScheFBack = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1046 | } |
| 1047 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1048 | void helper_mtc0_entrylo1 (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1049 | { |
| 1050 | /* Large physaddr (PABITS) not implemented */ |
| 1051 | /* 1k pages not implemented */ |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1052 | env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1053 | } |
| 1054 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1055 | void helper_mtc0_context (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1056 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1057 | env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1058 | } |
| 1059 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1060 | void helper_mtc0_pagemask (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1061 | { |
| 1062 | /* 1k pages not implemented */ |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1063 | env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1064 | } |
| 1065 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1066 | void helper_mtc0_pagegrain (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1067 | { |
| 1068 | /* SmartMIPS not implemented */ |
| 1069 | /* Large physaddr (PABITS) not implemented */ |
| 1070 | /* 1k pages not implemented */ |
| 1071 | env->CP0_PageGrain = 0; |
| 1072 | } |
| 1073 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1074 | void helper_mtc0_wired (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1075 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1076 | env->CP0_Wired = arg1 % env->tlb->nb_tlb; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1077 | } |
| 1078 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1079 | void helper_mtc0_srsconf0 (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1080 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1081 | env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1082 | } |
| 1083 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1084 | void helper_mtc0_srsconf1 (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1085 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1086 | env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1087 | } |
| 1088 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1089 | void helper_mtc0_srsconf2 (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1090 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1091 | env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1092 | } |
| 1093 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1094 | void helper_mtc0_srsconf3 (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1095 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1096 | env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1097 | } |
| 1098 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1099 | void helper_mtc0_srsconf4 (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1100 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1101 | env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1102 | } |
| 1103 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1104 | void helper_mtc0_hwrena (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1105 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1106 | env->CP0_HWREna = arg1 & 0x0000000F; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1107 | } |
| 1108 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1109 | void helper_mtc0_count (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1110 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1111 | cpu_mips_store_count(env, arg1); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1112 | } |
| 1113 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1114 | void helper_mtc0_entryhi (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1115 | { |
| 1116 | target_ulong old, val; |
| 1117 | |
| 1118 | /* 1k pages not implemented */ |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1119 | val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1120 | #if defined(TARGET_MIPS64) |
| 1121 | val &= env->SEGMask; |
| 1122 | #endif |
| 1123 | old = env->CP0_EntryHi; |
| 1124 | env->CP0_EntryHi = val; |
| 1125 | if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1126 | uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff; |
| 1127 | env->active_tc.CP0_TCStatus = tcst | (val & 0xff); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1128 | } |
| 1129 | /* If the ASID changes, flush qemu's TLB. */ |
| 1130 | if ((old & 0xFF) != (val & 0xFF)) |
| 1131 | cpu_mips_tlb_flush(env, 1); |
| 1132 | } |
| 1133 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1134 | void helper_mttc0_entryhi(target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1135 | { |
| 1136 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1137 | int32_t tcstatus; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1138 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1139 | env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1140 | if (other_tc == env->current_tc) { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1141 | tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1142 | env->active_tc.CP0_TCStatus = tcstatus; |
| 1143 | } else { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1144 | tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1145 | env->tcs[other_tc].CP0_TCStatus = tcstatus; |
| 1146 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1147 | } |
| 1148 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1149 | void helper_mtc0_compare (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1150 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1151 | cpu_mips_store_compare(env, arg1); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1152 | } |
| 1153 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1154 | void helper_mtc0_status (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1155 | { |
| 1156 | uint32_t val, old; |
| 1157 | uint32_t mask = env->CP0_Status_rw_bitmask; |
| 1158 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1159 | val = arg1 & mask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1160 | old = env->CP0_Status; |
| 1161 | env->CP0_Status = (env->CP0_Status & ~mask) | val; |
| 1162 | compute_hflags(env); |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1163 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
| 1164 | qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x", |
| 1165 | old, old & env->CP0_Cause & CP0Ca_IP_mask, |
| 1166 | val, val & env->CP0_Cause & CP0Ca_IP_mask, |
| 1167 | env->CP0_Cause); |
| 1168 | switch (env->hflags & MIPS_HFLAG_KSU) { |
| 1169 | case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; |
| 1170 | case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; |
| 1171 | case MIPS_HFLAG_KM: qemu_log("\n"); break; |
| 1172 | default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
Aurelien Jarno | 31e3104 | 2009-11-14 13:10:00 +0100 | [diff] [blame] | 1173 | } |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1174 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1175 | cpu_mips_update_irq(env); |
| 1176 | } |
| 1177 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1178 | void helper_mttc0_status(target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1179 | { |
| 1180 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1181 | int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1182 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1183 | env->CP0_Status = arg1 & ~0xf1000018; |
| 1184 | tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0)); |
| 1185 | tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX)); |
| 1186 | tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU)); |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1187 | if (other_tc == env->current_tc) |
| 1188 | env->active_tc.CP0_TCStatus = tcstatus; |
| 1189 | else |
| 1190 | env->tcs[other_tc].CP0_TCStatus = tcstatus; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1191 | } |
| 1192 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1193 | void helper_mtc0_intctl (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1194 | { |
| 1195 | /* vectored interrupts not implemented, no performance counters. */ |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1196 | env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1197 | } |
| 1198 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1199 | void helper_mtc0_srsctl (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1200 | { |
| 1201 | uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1202 | env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1203 | } |
| 1204 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1205 | void helper_mtc0_cause (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1206 | { |
| 1207 | uint32_t mask = 0x00C00300; |
| 1208 | uint32_t old = env->CP0_Cause; |
| 1209 | |
| 1210 | if (env->insn_flags & ISA_MIPS32R2) |
| 1211 | mask |= 1 << CP0Ca_DC; |
| 1212 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1213 | env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1214 | |
| 1215 | if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { |
| 1216 | if (env->CP0_Cause & (1 << CP0Ca_DC)) |
| 1217 | cpu_mips_stop_count(env); |
| 1218 | else |
| 1219 | cpu_mips_start_count(env); |
| 1220 | } |
| 1221 | |
| 1222 | /* Handle the software interrupt as an hardware one, as they |
| 1223 | are very similar */ |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1224 | if (arg1 & CP0Ca_IP_mask) { |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1225 | cpu_mips_update_irq(env); |
| 1226 | } |
| 1227 | } |
| 1228 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1229 | void helper_mtc0_ebase (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1230 | { |
| 1231 | /* vectored interrupts not implemented */ |
| 1232 | /* Multi-CPU not implemented */ |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1233 | env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1234 | } |
| 1235 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1236 | void helper_mtc0_config0 (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1237 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1238 | env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1239 | } |
| 1240 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1241 | void helper_mtc0_config2 (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1242 | { |
| 1243 | /* tertiary/secondary caches not implemented */ |
| 1244 | env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); |
| 1245 | } |
| 1246 | |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 1247 | void helper_mtc0_lladdr (target_ulong arg1) |
| 1248 | { |
| 1249 | target_long mask = env->CP0_LLAddr_rw_bitmask; |
| 1250 | arg1 = arg1 << env->CP0_LLAddr_shift; |
| 1251 | env->lladdr = (env->lladdr & ~mask) | (arg1 & mask); |
| 1252 | } |
| 1253 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1254 | void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1255 | { |
| 1256 | /* Watch exceptions for instructions, data loads, data stores |
| 1257 | not implemented. */ |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1258 | env->CP0_WatchLo[sel] = (arg1 & ~0x7); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1259 | } |
| 1260 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1261 | void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1262 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1263 | env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8); |
| 1264 | env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1265 | } |
| 1266 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1267 | void helper_mtc0_xcontext (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1268 | { |
| 1269 | target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1270 | env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1271 | } |
| 1272 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1273 | void helper_mtc0_framemask (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1274 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1275 | env->CP0_Framemask = arg1; /* XXX */ |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1276 | } |
| 1277 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1278 | void helper_mtc0_debug (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1279 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1280 | env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); |
| 1281 | if (arg1 & (1 << CP0DB_DM)) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1282 | env->hflags |= MIPS_HFLAG_DM; |
| 1283 | else |
| 1284 | env->hflags &= ~MIPS_HFLAG_DM; |
| 1285 | } |
| 1286 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1287 | void helper_mttc0_debug(target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1288 | { |
| 1289 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1290 | uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1291 | |
| 1292 | /* XXX: Might be wrong, check with EJTAG spec. */ |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1293 | if (other_tc == env->current_tc) |
| 1294 | env->active_tc.CP0_Debug_tcstatus = val; |
| 1295 | else |
| 1296 | env->tcs[other_tc].CP0_Debug_tcstatus = val; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1297 | env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1298 | (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1299 | } |
| 1300 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1301 | void helper_mtc0_performance0 (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1302 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1303 | env->CP0_Performance0 = arg1 & 0x000007ff; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1304 | } |
| 1305 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1306 | void helper_mtc0_taglo (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1307 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1308 | env->CP0_TagLo = arg1 & 0xFFFFFCF6; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1309 | } |
| 1310 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1311 | void helper_mtc0_datalo (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1312 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1313 | env->CP0_DataLo = arg1; /* XXX */ |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1314 | } |
| 1315 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1316 | void helper_mtc0_taghi (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1317 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1318 | env->CP0_TagHi = arg1; /* XXX */ |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1319 | } |
| 1320 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1321 | void helper_mtc0_datahi (target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1322 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1323 | env->CP0_DataHi = arg1; /* XXX */ |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1324 | } |
| 1325 | |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1326 | /* MIPS MT functions */ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1327 | target_ulong helper_mftgpr(uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1328 | { |
| 1329 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1330 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1331 | if (other_tc == env->current_tc) |
| 1332 | return env->active_tc.gpr[sel]; |
| 1333 | else |
| 1334 | return env->tcs[other_tc].gpr[sel]; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1335 | } |
| 1336 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1337 | target_ulong helper_mftlo(uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1338 | { |
| 1339 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1340 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1341 | if (other_tc == env->current_tc) |
| 1342 | return env->active_tc.LO[sel]; |
| 1343 | else |
| 1344 | return env->tcs[other_tc].LO[sel]; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1345 | } |
| 1346 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1347 | target_ulong helper_mfthi(uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1348 | { |
| 1349 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1350 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1351 | if (other_tc == env->current_tc) |
| 1352 | return env->active_tc.HI[sel]; |
| 1353 | else |
| 1354 | return env->tcs[other_tc].HI[sel]; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1355 | } |
| 1356 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1357 | target_ulong helper_mftacx(uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1358 | { |
| 1359 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1360 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1361 | if (other_tc == env->current_tc) |
| 1362 | return env->active_tc.ACX[sel]; |
| 1363 | else |
| 1364 | return env->tcs[other_tc].ACX[sel]; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1365 | } |
| 1366 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1367 | target_ulong helper_mftdsp(void) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1368 | { |
| 1369 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1370 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1371 | if (other_tc == env->current_tc) |
| 1372 | return env->active_tc.DSPControl; |
| 1373 | else |
| 1374 | return env->tcs[other_tc].DSPControl; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1375 | } |
| 1376 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1377 | void helper_mttgpr(target_ulong arg1, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1378 | { |
| 1379 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1380 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1381 | if (other_tc == env->current_tc) |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1382 | env->active_tc.gpr[sel] = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1383 | else |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1384 | env->tcs[other_tc].gpr[sel] = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1385 | } |
| 1386 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1387 | void helper_mttlo(target_ulong arg1, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1388 | { |
| 1389 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1390 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1391 | if (other_tc == env->current_tc) |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1392 | env->active_tc.LO[sel] = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1393 | else |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1394 | env->tcs[other_tc].LO[sel] = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1395 | } |
| 1396 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1397 | void helper_mtthi(target_ulong arg1, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1398 | { |
| 1399 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1400 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1401 | if (other_tc == env->current_tc) |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1402 | env->active_tc.HI[sel] = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1403 | else |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1404 | env->tcs[other_tc].HI[sel] = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1405 | } |
| 1406 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1407 | void helper_mttacx(target_ulong arg1, uint32_t sel) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1408 | { |
| 1409 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1410 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1411 | if (other_tc == env->current_tc) |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1412 | env->active_tc.ACX[sel] = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1413 | else |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1414 | env->tcs[other_tc].ACX[sel] = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1415 | } |
| 1416 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1417 | void helper_mttdsp(target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1418 | { |
| 1419 | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1420 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1421 | if (other_tc == env->current_tc) |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1422 | env->active_tc.DSPControl = arg1; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1423 | else |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1424 | env->tcs[other_tc].DSPControl = arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1425 | } |
| 1426 | |
| 1427 | /* MIPS MT functions */ |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1428 | target_ulong helper_dmt(target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1429 | { |
| 1430 | // TODO |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1431 | arg1 = 0; |
| 1432 | // rt = arg1 |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1433 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1434 | return arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1435 | } |
| 1436 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1437 | target_ulong helper_emt(target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1438 | { |
| 1439 | // TODO |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1440 | arg1 = 0; |
| 1441 | // rt = arg1 |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1442 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1443 | return arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1444 | } |
| 1445 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1446 | target_ulong helper_dvpe(target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1447 | { |
| 1448 | // TODO |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1449 | arg1 = 0; |
| 1450 | // rt = arg1 |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1451 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1452 | return arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1453 | } |
| 1454 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1455 | target_ulong helper_evpe(target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1456 | { |
| 1457 | // TODO |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1458 | arg1 = 0; |
| 1459 | // rt = arg1 |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1460 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1461 | return arg1; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1462 | } |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 1463 | #endif /* !CONFIG_USER_ONLY */ |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1464 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1465 | void helper_fork(target_ulong arg1, target_ulong arg2) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1466 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1467 | // arg1 = rt, arg2 = rs |
| 1468 | arg1 = 0; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1469 | // TODO: store to TC register |
| 1470 | } |
| 1471 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1472 | target_ulong helper_yield(target_ulong arg1) |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1473 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1474 | if (arg1 < 0) { |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1475 | /* No scheduling policy implemented. */ |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1476 | if (arg1 != -2) { |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1477 | if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1478 | env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1479 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
| 1480 | env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1481 | helper_raise_exception(EXCP_THREAD); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1482 | } |
| 1483 | } |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1484 | } else if (arg1 == 0) { |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 1485 | if (0 /* TODO: TC underflow */) { |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1486 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1487 | helper_raise_exception(EXCP_THREAD); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1488 | } else { |
| 1489 | // TODO: Deallocate TC |
| 1490 | } |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1491 | } else if (arg1 > 0) { |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1492 | /* Yield qualifier inputs not implemented. */ |
| 1493 | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); |
| 1494 | env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1495 | helper_raise_exception(EXCP_THREAD); |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1496 | } |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1497 | return env->CP0_YQMask; |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1498 | } |
| 1499 | |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1500 | #ifndef CONFIG_USER_ONLY |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1501 | /* TLB management */ |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1502 | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
| 1503 | { |
| 1504 | /* Flush qemu's TLB and discard all shadowed entries. */ |
| 1505 | tlb_flush (env, flush_global); |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1506 | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1507 | } |
| 1508 | |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 1509 | static void r4k_mips_tlb_flush_extra (CPUState *env, int first) |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1510 | { |
| 1511 | /* Discard entries from env->tlb[first] onwards. */ |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1512 | while (env->tlb->tlb_in_use > first) { |
| 1513 | r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1514 | } |
| 1515 | } |
| 1516 | |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 1517 | static void r4k_fill_tlb (int idx) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1518 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1519 | r4k_tlb_t *tlb; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1520 | |
| 1521 | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1522 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
ths | f2e9ebe | 2007-05-13 14:07:26 +0000 | [diff] [blame] | 1523 | tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); |
ths | d26bc21 | 2007-11-08 18:05:37 +0000 | [diff] [blame] | 1524 | #if defined(TARGET_MIPS64) |
ths | e034e2c | 2007-06-23 18:04:12 +0000 | [diff] [blame] | 1525 | tlb->VPN &= env->SEGMask; |
ths | 100ce98 | 2007-05-13 19:22:13 +0000 | [diff] [blame] | 1526 | #endif |
pbrook | 98c1b82 | 2006-03-11 16:20:36 +0000 | [diff] [blame] | 1527 | tlb->ASID = env->CP0_EntryHi & 0xFF; |
ths | 3b1c8be | 2007-01-22 20:50:42 +0000 | [diff] [blame] | 1528 | tlb->PageMask = env->CP0_PageMask; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1529 | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; |
pbrook | 98c1b82 | 2006-03-11 16:20:36 +0000 | [diff] [blame] | 1530 | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
| 1531 | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
| 1532 | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1533 | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
pbrook | 98c1b82 | 2006-03-11 16:20:36 +0000 | [diff] [blame] | 1534 | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
| 1535 | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
| 1536 | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1537 | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
| 1538 | } |
| 1539 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1540 | void r4k_helper_tlbwi (void) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1541 | { |
aurel32 | bbc0d79 | 2008-09-14 17:09:56 +0000 | [diff] [blame] | 1542 | int idx; |
| 1543 | |
| 1544 | idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; |
| 1545 | |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1546 | /* Discard cached TLB entries. We could avoid doing this if the |
| 1547 | tlbwi is just upgrading access permissions on the current entry; |
| 1548 | that might be a further win. */ |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1549 | r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1550 | |
aurel32 | bbc0d79 | 2008-09-14 17:09:56 +0000 | [diff] [blame] | 1551 | r4k_invalidate_tlb(env, idx, 0); |
| 1552 | r4k_fill_tlb(idx); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1553 | } |
| 1554 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1555 | void r4k_helper_tlbwr (void) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1556 | { |
| 1557 | int r = cpu_mips_get_random(env); |
| 1558 | |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 1559 | r4k_invalidate_tlb(env, r, 1); |
| 1560 | r4k_fill_tlb(r); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1561 | } |
| 1562 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1563 | void r4k_helper_tlbp (void) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1564 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1565 | r4k_tlb_t *tlb; |
ths | f2e9ebe | 2007-05-13 14:07:26 +0000 | [diff] [blame] | 1566 | target_ulong mask; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1567 | target_ulong tag; |
ths | f2e9ebe | 2007-05-13 14:07:26 +0000 | [diff] [blame] | 1568 | target_ulong VPN; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1569 | uint8_t ASID; |
| 1570 | int i; |
| 1571 | |
bellard | 3d9fb9fe | 2006-05-22 22:13:29 +0000 | [diff] [blame] | 1572 | ASID = env->CP0_EntryHi & 0xFF; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1573 | for (i = 0; i < env->tlb->nb_tlb; i++) { |
| 1574 | tlb = &env->tlb->mmu.r4k.tlb[i]; |
ths | f2e9ebe | 2007-05-13 14:07:26 +0000 | [diff] [blame] | 1575 | /* 1k pages are not supported. */ |
| 1576 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
| 1577 | tag = env->CP0_EntryHi & ~mask; |
| 1578 | VPN = tlb->VPN & ~mask; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1579 | /* Check ASID, virtual page number & size */ |
ths | f2e9ebe | 2007-05-13 14:07:26 +0000 | [diff] [blame] | 1580 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1581 | /* TLB match */ |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 1582 | env->CP0_Index = i; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1583 | break; |
| 1584 | } |
| 1585 | } |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1586 | if (i == env->tlb->nb_tlb) { |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1587 | /* No match. Discard any shadow entries, if any of them match. */ |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1588 | for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 1589 | tlb = &env->tlb->mmu.r4k.tlb[i]; |
| 1590 | /* 1k pages are not supported. */ |
| 1591 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
| 1592 | tag = env->CP0_EntryHi & ~mask; |
| 1593 | VPN = tlb->VPN & ~mask; |
| 1594 | /* Check ASID, virtual page number & size */ |
| 1595 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 1596 | r4k_mips_tlb_flush_extra (env, i); |
aurel32 | 6958549 | 2009-01-14 19:40:36 +0000 | [diff] [blame] | 1597 | break; |
| 1598 | } |
| 1599 | } |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1600 | |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 1601 | env->CP0_Index |= 0x80000000; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1602 | } |
| 1603 | } |
| 1604 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1605 | void r4k_helper_tlbr (void) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1606 | { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1607 | r4k_tlb_t *tlb; |
pbrook | 09c56b8 | 2006-03-11 16:39:23 +0000 | [diff] [blame] | 1608 | uint8_t ASID; |
aurel32 | bbc0d79 | 2008-09-14 17:09:56 +0000 | [diff] [blame] | 1609 | int idx; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1610 | |
pbrook | 09c56b8 | 2006-03-11 16:39:23 +0000 | [diff] [blame] | 1611 | ASID = env->CP0_EntryHi & 0xFF; |
aurel32 | bbc0d79 | 2008-09-14 17:09:56 +0000 | [diff] [blame] | 1612 | idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; |
| 1613 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 1614 | |
| 1615 | /* If this will change the current ASID, flush qemu's TLB. */ |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 1616 | if (ASID != tlb->ASID) |
| 1617 | cpu_mips_tlb_flush (env, 1); |
| 1618 | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1619 | r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 1620 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1621 | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
ths | 3b1c8be | 2007-01-22 20:50:42 +0000 | [diff] [blame] | 1622 | env->CP0_PageMask = tlb->PageMask; |
ths | 7495fd0 | 2007-01-01 20:32:08 +0000 | [diff] [blame] | 1623 | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
| 1624 | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
| 1625 | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
| 1626 | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1627 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1628 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1629 | void helper_tlbwi(void) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1630 | { |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1631 | env->tlb->helper_tlbwi(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1632 | } |
| 1633 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1634 | void helper_tlbwr(void) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1635 | { |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1636 | env->tlb->helper_tlbwr(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1637 | } |
| 1638 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1639 | void helper_tlbp(void) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1640 | { |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1641 | env->tlb->helper_tlbp(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1642 | } |
| 1643 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1644 | void helper_tlbr(void) |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1645 | { |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1646 | env->tlb->helper_tlbr(); |
pbrook | a7812ae | 2008-11-17 14:43:54 +0000 | [diff] [blame] | 1647 | } |
| 1648 | |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1649 | /* Specials */ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1650 | target_ulong helper_di (void) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1651 | { |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 1652 | target_ulong t0 = env->CP0_Status; |
| 1653 | |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1654 | env->CP0_Status = t0 & ~(1 << CP0St_IE); |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1655 | cpu_mips_update_irq(env); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1656 | |
| 1657 | return t0; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1658 | } |
| 1659 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1660 | target_ulong helper_ei (void) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1661 | { |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 1662 | target_ulong t0 = env->CP0_Status; |
| 1663 | |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1664 | env->CP0_Status = t0 | (1 << CP0St_IE); |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1665 | cpu_mips_update_irq(env); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1666 | |
| 1667 | return t0; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1668 | } |
| 1669 | |
aurel32 | cd5158e | 2008-12-07 23:26:24 +0000 | [diff] [blame] | 1670 | static void debug_pre_eret (void) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1671 | { |
aliguori | 8fec2b8 | 2009-01-15 22:36:53 +0000 | [diff] [blame] | 1672 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1673 | qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
| 1674 | env->active_tc.PC, env->CP0_EPC); |
| 1675 | if (env->CP0_Status & (1 << CP0St_ERL)) |
| 1676 | qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); |
| 1677 | if (env->hflags & MIPS_HFLAG_DM) |
| 1678 | qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); |
| 1679 | qemu_log("\n"); |
| 1680 | } |
ths | f41c52f | 2007-04-06 18:46:01 +0000 | [diff] [blame] | 1681 | } |
| 1682 | |
aurel32 | cd5158e | 2008-12-07 23:26:24 +0000 | [diff] [blame] | 1683 | static void debug_post_eret (void) |
ths | f41c52f | 2007-04-06 18:46:01 +0000 | [diff] [blame] | 1684 | { |
aliguori | 8fec2b8 | 2009-01-15 22:36:53 +0000 | [diff] [blame] | 1685 | if (qemu_loglevel_mask(CPU_LOG_EXEC)) { |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1686 | qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, |
| 1687 | env->active_tc.PC, env->CP0_EPC); |
| 1688 | if (env->CP0_Status & (1 << CP0St_ERL)) |
| 1689 | qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); |
| 1690 | if (env->hflags & MIPS_HFLAG_DM) |
| 1691 | qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); |
| 1692 | switch (env->hflags & MIPS_HFLAG_KSU) { |
| 1693 | case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; |
| 1694 | case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; |
| 1695 | case MIPS_HFLAG_KM: qemu_log("\n"); break; |
| 1696 | default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
| 1697 | } |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 1698 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1699 | } |
| 1700 | |
Nathan Froyd | 32188a0 | 2009-12-08 08:06:23 -0800 | [diff] [blame] | 1701 | static void set_pc (target_ulong error_pc) |
| 1702 | { |
| 1703 | env->active_tc.PC = error_pc & ~(target_ulong)1; |
| 1704 | if (error_pc & 1) { |
| 1705 | env->hflags |= MIPS_HFLAG_M16; |
| 1706 | } else { |
| 1707 | env->hflags &= ~(MIPS_HFLAG_M16); |
| 1708 | } |
| 1709 | } |
| 1710 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1711 | void helper_eret (void) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1712 | { |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1713 | debug_pre_eret(); |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1714 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
Nathan Froyd | 32188a0 | 2009-12-08 08:06:23 -0800 | [diff] [blame] | 1715 | set_pc(env->CP0_ErrorEPC); |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1716 | env->CP0_Status &= ~(1 << CP0St_ERL); |
| 1717 | } else { |
Nathan Froyd | 32188a0 | 2009-12-08 08:06:23 -0800 | [diff] [blame] | 1718 | set_pc(env->CP0_EPC); |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1719 | env->CP0_Status &= ~(1 << CP0St_EXL); |
| 1720 | } |
| 1721 | compute_hflags(env); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1722 | debug_post_eret(); |
Aurelien Jarno | 5499b6f | 2009-11-22 13:08:14 +0100 | [diff] [blame] | 1723 | env->lladdr = 1; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1724 | } |
| 1725 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1726 | void helper_deret (void) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1727 | { |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1728 | debug_pre_eret(); |
Nathan Froyd | 32188a0 | 2009-12-08 08:06:23 -0800 | [diff] [blame] | 1729 | set_pc(env->CP0_DEPC); |
| 1730 | |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1731 | env->hflags &= MIPS_HFLAG_DM; |
| 1732 | compute_hflags(env); |
aliguori | 93fcfe3 | 2009-01-15 22:34:14 +0000 | [diff] [blame] | 1733 | debug_post_eret(); |
Aurelien Jarno | 5499b6f | 2009-11-22 13:08:14 +0100 | [diff] [blame] | 1734 | env->lladdr = 1; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1735 | } |
ths | 0eaef5a | 2008-07-23 16:14:22 +0000 | [diff] [blame] | 1736 | #endif /* !CONFIG_USER_ONLY */ |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1737 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1738 | target_ulong helper_rdhwr_cpunum(void) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1739 | { |
| 1740 | if ((env->hflags & MIPS_HFLAG_CP0) || |
| 1741 | (env->CP0_HWREna & (1 << 0))) |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 1742 | return env->CP0_EBase & 0x3ff; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1743 | else |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1744 | helper_raise_exception(EXCP_RI); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1745 | |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 1746 | return 0; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1747 | } |
| 1748 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1749 | target_ulong helper_rdhwr_synci_step(void) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1750 | { |
| 1751 | if ((env->hflags & MIPS_HFLAG_CP0) || |
| 1752 | (env->CP0_HWREna & (1 << 1))) |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 1753 | return env->SYNCI_Step; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1754 | else |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1755 | helper_raise_exception(EXCP_RI); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1756 | |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 1757 | return 0; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1758 | } |
| 1759 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1760 | target_ulong helper_rdhwr_cc(void) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1761 | { |
| 1762 | if ((env->hflags & MIPS_HFLAG_CP0) || |
| 1763 | (env->CP0_HWREna & (1 << 2))) |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 1764 | return env->CP0_Count; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1765 | else |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1766 | helper_raise_exception(EXCP_RI); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1767 | |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 1768 | return 0; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1769 | } |
| 1770 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1771 | target_ulong helper_rdhwr_ccres(void) |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1772 | { |
| 1773 | if ((env->hflags & MIPS_HFLAG_CP0) || |
| 1774 | (env->CP0_HWREna & (1 << 3))) |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 1775 | return env->CCRes; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1776 | else |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1777 | helper_raise_exception(EXCP_RI); |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1778 | |
ths | 2796188 | 2008-06-27 10:03:42 +0000 | [diff] [blame] | 1779 | return 0; |
ths | 2b0233a | 2008-06-12 12:42:35 +0000 | [diff] [blame] | 1780 | } |
| 1781 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1782 | void helper_pmon (int function) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1783 | { |
| 1784 | function /= 2; |
| 1785 | switch (function) { |
| 1786 | case 2: /* TODO: char inbyte(int waitflag); */ |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1787 | if (env->active_tc.gpr[4] == 0) |
| 1788 | env->active_tc.gpr[2] = -1; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1789 | /* Fall through */ |
| 1790 | case 11: /* TODO: char inbyte (void); */ |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1791 | env->active_tc.gpr[2] = -1; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1792 | break; |
| 1793 | case 3: |
| 1794 | case 12: |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1795 | printf("%c", (char)(env->active_tc.gpr[4] & 0xFF)); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1796 | break; |
| 1797 | case 17: |
| 1798 | break; |
| 1799 | case 158: |
| 1800 | { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 1801 | unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4]; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1802 | printf("%s", fmt); |
| 1803 | } |
| 1804 | break; |
| 1805 | } |
| 1806 | } |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 1807 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1808 | void helper_wait (void) |
ths | 08ba796 | 2008-06-12 03:15:13 +0000 | [diff] [blame] | 1809 | { |
| 1810 | env->halted = 1; |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1811 | helper_raise_exception(EXCP_HLT); |
ths | 08ba796 | 2008-06-12 03:15:13 +0000 | [diff] [blame] | 1812 | } |
| 1813 | |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 1814 | #if !defined(CONFIG_USER_ONLY) |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 1815 | |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 1816 | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
| 1817 | |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 1818 | #define MMUSUFFIX _mmu |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 1819 | #define ALIGNED_ONLY |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 1820 | |
| 1821 | #define SHIFT 0 |
| 1822 | #include "softmmu_template.h" |
| 1823 | |
| 1824 | #define SHIFT 1 |
| 1825 | #include "softmmu_template.h" |
| 1826 | |
| 1827 | #define SHIFT 2 |
| 1828 | #include "softmmu_template.h" |
| 1829 | |
| 1830 | #define SHIFT 3 |
| 1831 | #include "softmmu_template.h" |
| 1832 | |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 1833 | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
| 1834 | { |
| 1835 | env->CP0_BadVAddr = addr; |
| 1836 | do_restore_state (retaddr); |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1837 | helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL); |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 1838 | } |
| 1839 | |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1840 | void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 1841 | { |
| 1842 | TranslationBlock *tb; |
| 1843 | CPUState *saved_env; |
| 1844 | unsigned long pc; |
| 1845 | int ret; |
| 1846 | |
| 1847 | /* XXX: hack to restore env in all cases, even if not called from |
| 1848 | generated code */ |
| 1849 | saved_env = env; |
| 1850 | env = cpu_single_env; |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 1851 | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1); |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 1852 | if (ret) { |
| 1853 | if (retaddr) { |
| 1854 | /* now we have a real cpu fault */ |
| 1855 | pc = (unsigned long)retaddr; |
| 1856 | tb = tb_find_pc(pc); |
| 1857 | if (tb) { |
| 1858 | /* the PC is inside the translated code. It means that we have |
| 1859 | a virtual CPU fault */ |
| 1860 | cpu_restore_state(tb, env, pc, NULL); |
| 1861 | } |
| 1862 | } |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1863 | helper_raise_exception_err(env->exception_index, env->error_code); |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 1864 | } |
| 1865 | env = saved_env; |
| 1866 | } |
| 1867 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 1868 | void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, |
blueswir1 | e18231a | 2008-10-06 18:46:28 +0000 | [diff] [blame] | 1869 | int unused, int size) |
ths | 647de6c | 2007-10-20 19:45:44 +0000 | [diff] [blame] | 1870 | { |
| 1871 | if (is_exec) |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1872 | helper_raise_exception(EXCP_IBE); |
ths | 647de6c | 2007-10-20 19:45:44 +0000 | [diff] [blame] | 1873 | else |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1874 | helper_raise_exception(EXCP_DBE); |
ths | 647de6c | 2007-10-20 19:45:44 +0000 | [diff] [blame] | 1875 | } |
ths | f1aa632 | 2008-06-09 07:13:38 +0000 | [diff] [blame] | 1876 | #endif /* !CONFIG_USER_ONLY */ |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1877 | |
| 1878 | /* Complex FPU operations which may need stack space. */ |
| 1879 | |
pbrook | f090c9d | 2007-11-18 14:33:24 +0000 | [diff] [blame] | 1880 | #define FLOAT_ONE32 make_float32(0x3f8 << 20) |
| 1881 | #define FLOAT_ONE64 make_float64(0x3ffULL << 52) |
| 1882 | #define FLOAT_TWO32 make_float32(1 << 30) |
| 1883 | #define FLOAT_TWO64 make_float64(1ULL << 62) |
ths | 5445409 | 2007-09-29 19:19:59 +0000 | [diff] [blame] | 1884 | #define FLOAT_QNAN32 0x7fbfffff |
| 1885 | #define FLOAT_QNAN64 0x7ff7ffffffffffffULL |
| 1886 | #define FLOAT_SNAN32 0x7fffffff |
| 1887 | #define FLOAT_SNAN64 0x7fffffffffffffffULL |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 1888 | |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1889 | /* convert MIPS rounding mode in FCR31 to IEEE library */ |
Blue Swirl | 6f4fc36 | 2009-09-21 18:39:26 +0000 | [diff] [blame] | 1890 | static unsigned int ieee_rm[] = { |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1891 | float_round_nearest_even, |
| 1892 | float_round_to_zero, |
| 1893 | float_round_up, |
| 1894 | float_round_down |
| 1895 | }; |
| 1896 | |
| 1897 | #define RESTORE_ROUNDING_MODE \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 1898 | set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1899 | |
aurel32 | 41e0c70 | 2009-03-28 22:22:40 +0000 | [diff] [blame] | 1900 | #define RESTORE_FLUSH_MODE \ |
| 1901 | set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status); |
| 1902 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1903 | target_ulong helper_cfc1 (uint32_t reg) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1904 | { |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1905 | target_ulong arg1; |
ths | 6c5c1e2 | 2008-06-24 15:12:27 +0000 | [diff] [blame] | 1906 | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1907 | switch (reg) { |
| 1908 | case 0: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1909 | arg1 = (int32_t)env->active_fpu.fcr0; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1910 | break; |
| 1911 | case 25: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1912 | arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1); |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1913 | break; |
| 1914 | case 26: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1915 | arg1 = env->active_fpu.fcr31 & 0x0003f07c; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1916 | break; |
| 1917 | case 28: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1918 | arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4); |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1919 | break; |
| 1920 | default: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1921 | arg1 = (int32_t)env->active_fpu.fcr31; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1922 | break; |
| 1923 | } |
ths | be24bb4 | 2008-06-23 12:57:09 +0000 | [diff] [blame] | 1924 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1925 | return arg1; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1926 | } |
| 1927 | |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1928 | void helper_ctc1 (target_ulong arg1, uint32_t reg) |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 1929 | { |
| 1930 | switch(reg) { |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1931 | case 25: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1932 | if (arg1 & 0xffffff00) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1933 | return; |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1934 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) | |
| 1935 | ((arg1 & 0x1) << 23); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1936 | break; |
| 1937 | case 26: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1938 | if (arg1 & 0x007c0000) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1939 | return; |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1940 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1941 | break; |
| 1942 | case 28: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1943 | if (arg1 & 0x007c0000) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1944 | return; |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1945 | env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) | |
| 1946 | ((arg1 & 0x4) << 22); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1947 | break; |
| 1948 | case 31: |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1949 | if (arg1 & 0x007c0000) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1950 | return; |
aurel32 | d9bea11 | 2009-04-15 14:41:44 +0000 | [diff] [blame] | 1951 | env->active_fpu.fcr31 = arg1; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1952 | break; |
| 1953 | default: |
| 1954 | return; |
| 1955 | } |
| 1956 | /* set rounding mode */ |
| 1957 | RESTORE_ROUNDING_MODE; |
aurel32 | 41e0c70 | 2009-03-28 22:22:40 +0000 | [diff] [blame] | 1958 | /* set flush-to-zero mode */ |
| 1959 | RESTORE_FLUSH_MODE; |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 1960 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 1961 | if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1962 | helper_raise_exception(EXCP_FPE); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1963 | } |
| 1964 | |
ths | c904ef0 | 2008-07-23 16:16:31 +0000 | [diff] [blame] | 1965 | static inline char ieee_ex_to_mips(char xcpt) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1966 | { |
| 1967 | return (xcpt & float_flag_inexact) >> 5 | |
| 1968 | (xcpt & float_flag_underflow) >> 3 | |
| 1969 | (xcpt & float_flag_overflow) >> 1 | |
| 1970 | (xcpt & float_flag_divbyzero) << 1 | |
| 1971 | (xcpt & float_flag_invalid) << 4; |
| 1972 | } |
| 1973 | |
ths | c904ef0 | 2008-07-23 16:16:31 +0000 | [diff] [blame] | 1974 | static inline char mips_ex_to_ieee(char xcpt) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1975 | { |
| 1976 | return (xcpt & FP_INEXACT) << 5 | |
| 1977 | (xcpt & FP_UNDERFLOW) << 3 | |
| 1978 | (xcpt & FP_OVERFLOW) << 1 | |
| 1979 | (xcpt & FP_DIV0) >> 1 | |
| 1980 | (xcpt & FP_INVALID) >> 4; |
| 1981 | } |
| 1982 | |
ths | c904ef0 | 2008-07-23 16:16:31 +0000 | [diff] [blame] | 1983 | static inline void update_fcr31(void) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1984 | { |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 1985 | int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status)); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1986 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 1987 | SET_FP_CAUSE(env->active_fpu.fcr31, tmp); |
| 1988 | if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 1989 | helper_raise_exception(EXCP_FPE); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1990 | else |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 1991 | UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 1992 | } |
| 1993 | |
ths | a16336e | 2008-06-19 18:35:02 +0000 | [diff] [blame] | 1994 | /* Float support. |
| 1995 | Single precition routines have a "s" suffix, double precision a |
| 1996 | "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", |
| 1997 | paired single lower "pl", paired single upper "pu". */ |
| 1998 | |
ths | a16336e | 2008-06-19 18:35:02 +0000 | [diff] [blame] | 1999 | /* unary operations, modifying fp status */ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2000 | uint64_t helper_float_sqrt_d(uint64_t fdt0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2001 | { |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2002 | return float64_sqrt(fdt0, &env->active_fpu.fp_status); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2003 | } |
| 2004 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2005 | uint32_t helper_float_sqrt_s(uint32_t fst0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2006 | { |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2007 | return float32_sqrt(fst0, &env->active_fpu.fp_status); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2008 | } |
| 2009 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2010 | uint64_t helper_float_cvtd_s(uint32_t fst0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2011 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2012 | uint64_t fdt2; |
| 2013 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2014 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2015 | fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2016 | update_fcr31(); |
| 2017 | return fdt2; |
| 2018 | } |
| 2019 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2020 | uint64_t helper_float_cvtd_w(uint32_t wt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2021 | { |
| 2022 | uint64_t fdt2; |
| 2023 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2024 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2025 | fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2026 | update_fcr31(); |
| 2027 | return fdt2; |
| 2028 | } |
| 2029 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2030 | uint64_t helper_float_cvtd_l(uint64_t dt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2031 | { |
| 2032 | uint64_t fdt2; |
| 2033 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2034 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2035 | fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2036 | update_fcr31(); |
| 2037 | return fdt2; |
| 2038 | } |
| 2039 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2040 | uint64_t helper_float_cvtl_d(uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2041 | { |
| 2042 | uint64_t dt2; |
| 2043 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2044 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2045 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2046 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2047 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2048 | dt2 = FLOAT_SNAN64; |
| 2049 | return dt2; |
| 2050 | } |
| 2051 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2052 | uint64_t helper_float_cvtl_s(uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2053 | { |
| 2054 | uint64_t dt2; |
| 2055 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2056 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2057 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2058 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2059 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2060 | dt2 = FLOAT_SNAN64; |
| 2061 | return dt2; |
| 2062 | } |
| 2063 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2064 | uint64_t helper_float_cvtps_pw(uint64_t dt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2065 | { |
| 2066 | uint32_t fst2; |
| 2067 | uint32_t fsth2; |
| 2068 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2069 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2070 | fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
| 2071 | fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2072 | update_fcr31(); |
| 2073 | return ((uint64_t)fsth2 << 32) | fst2; |
| 2074 | } |
| 2075 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2076 | uint64_t helper_float_cvtpw_ps(uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2077 | { |
| 2078 | uint32_t wt2; |
| 2079 | uint32_t wth2; |
| 2080 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2081 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2082 | wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
| 2083 | wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2084 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2085 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2086 | wt2 = FLOAT_SNAN32; |
| 2087 | wth2 = FLOAT_SNAN32; |
| 2088 | } |
| 2089 | return ((uint64_t)wth2 << 32) | wt2; |
| 2090 | } |
| 2091 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2092 | uint32_t helper_float_cvts_d(uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2093 | { |
| 2094 | uint32_t fst2; |
| 2095 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2096 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2097 | fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2098 | update_fcr31(); |
| 2099 | return fst2; |
| 2100 | } |
| 2101 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2102 | uint32_t helper_float_cvts_w(uint32_t wt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2103 | { |
| 2104 | uint32_t fst2; |
| 2105 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2106 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2107 | fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2108 | update_fcr31(); |
| 2109 | return fst2; |
| 2110 | } |
| 2111 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2112 | uint32_t helper_float_cvts_l(uint64_t dt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2113 | { |
| 2114 | uint32_t fst2; |
| 2115 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2116 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2117 | fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2118 | update_fcr31(); |
| 2119 | return fst2; |
| 2120 | } |
| 2121 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2122 | uint32_t helper_float_cvts_pl(uint32_t wt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2123 | { |
| 2124 | uint32_t wt2; |
| 2125 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2126 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2127 | wt2 = wt0; |
| 2128 | update_fcr31(); |
| 2129 | return wt2; |
| 2130 | } |
| 2131 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2132 | uint32_t helper_float_cvts_pu(uint32_t wth0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2133 | { |
| 2134 | uint32_t wt2; |
| 2135 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2136 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2137 | wt2 = wth0; |
| 2138 | update_fcr31(); |
| 2139 | return wt2; |
| 2140 | } |
| 2141 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2142 | uint32_t helper_float_cvtw_s(uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2143 | { |
| 2144 | uint32_t wt2; |
| 2145 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2146 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2147 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2148 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2149 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2150 | wt2 = FLOAT_SNAN32; |
| 2151 | return wt2; |
| 2152 | } |
| 2153 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2154 | uint32_t helper_float_cvtw_d(uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2155 | { |
| 2156 | uint32_t wt2; |
| 2157 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2158 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2159 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2160 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2161 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2162 | wt2 = FLOAT_SNAN32; |
| 2163 | return wt2; |
| 2164 | } |
| 2165 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2166 | uint64_t helper_float_roundl_d(uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2167 | { |
| 2168 | uint64_t dt2; |
| 2169 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2170 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
| 2171 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2172 | RESTORE_ROUNDING_MODE; |
| 2173 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2174 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2175 | dt2 = FLOAT_SNAN64; |
| 2176 | return dt2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2177 | } |
| 2178 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2179 | uint64_t helper_float_roundl_s(uint32_t fst0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2180 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2181 | uint64_t dt2; |
| 2182 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2183 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
| 2184 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2185 | RESTORE_ROUNDING_MODE; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2186 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2187 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2188 | dt2 = FLOAT_SNAN64; |
| 2189 | return dt2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2190 | } |
| 2191 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2192 | uint32_t helper_float_roundw_d(uint64_t fdt0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2193 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2194 | uint32_t wt2; |
| 2195 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2196 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
| 2197 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2198 | RESTORE_ROUNDING_MODE; |
| 2199 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2200 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2201 | wt2 = FLOAT_SNAN32; |
| 2202 | return wt2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2203 | } |
| 2204 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2205 | uint32_t helper_float_roundw_s(uint32_t fst0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2206 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2207 | uint32_t wt2; |
| 2208 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2209 | set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); |
| 2210 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2211 | RESTORE_ROUNDING_MODE; |
| 2212 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2213 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2214 | wt2 = FLOAT_SNAN32; |
| 2215 | return wt2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2216 | } |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2217 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2218 | uint64_t helper_float_truncl_d(uint64_t fdt0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2219 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2220 | uint64_t dt2; |
| 2221 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2222 | dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2223 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2224 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2225 | dt2 = FLOAT_SNAN64; |
| 2226 | return dt2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2227 | } |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2228 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2229 | uint64_t helper_float_truncl_s(uint32_t fst0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2230 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2231 | uint64_t dt2; |
| 2232 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2233 | dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2234 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2235 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2236 | dt2 = FLOAT_SNAN64; |
| 2237 | return dt2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2238 | } |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2239 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2240 | uint32_t helper_float_truncw_d(uint64_t fdt0) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2241 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2242 | uint32_t wt2; |
| 2243 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2244 | wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2245 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2246 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2247 | wt2 = FLOAT_SNAN32; |
| 2248 | return wt2; |
| 2249 | } |
| 2250 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2251 | uint32_t helper_float_truncw_s(uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2252 | { |
| 2253 | uint32_t wt2; |
| 2254 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2255 | wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2256 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2257 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2258 | wt2 = FLOAT_SNAN32; |
| 2259 | return wt2; |
| 2260 | } |
| 2261 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2262 | uint64_t helper_float_ceill_d(uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2263 | { |
| 2264 | uint64_t dt2; |
| 2265 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2266 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
| 2267 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2268 | RESTORE_ROUNDING_MODE; |
| 2269 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2270 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2271 | dt2 = FLOAT_SNAN64; |
| 2272 | return dt2; |
| 2273 | } |
| 2274 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2275 | uint64_t helper_float_ceill_s(uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2276 | { |
| 2277 | uint64_t dt2; |
| 2278 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2279 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
| 2280 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2281 | RESTORE_ROUNDING_MODE; |
| 2282 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2283 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2284 | dt2 = FLOAT_SNAN64; |
| 2285 | return dt2; |
| 2286 | } |
| 2287 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2288 | uint32_t helper_float_ceilw_d(uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2289 | { |
| 2290 | uint32_t wt2; |
| 2291 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2292 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
| 2293 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2294 | RESTORE_ROUNDING_MODE; |
| 2295 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2296 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2297 | wt2 = FLOAT_SNAN32; |
| 2298 | return wt2; |
| 2299 | } |
| 2300 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2301 | uint32_t helper_float_ceilw_s(uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2302 | { |
| 2303 | uint32_t wt2; |
| 2304 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2305 | set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); |
| 2306 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2307 | RESTORE_ROUNDING_MODE; |
| 2308 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2309 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2310 | wt2 = FLOAT_SNAN32; |
| 2311 | return wt2; |
| 2312 | } |
| 2313 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2314 | uint64_t helper_float_floorl_d(uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2315 | { |
| 2316 | uint64_t dt2; |
| 2317 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2318 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
| 2319 | dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2320 | RESTORE_ROUNDING_MODE; |
| 2321 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2322 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2323 | dt2 = FLOAT_SNAN64; |
| 2324 | return dt2; |
| 2325 | } |
| 2326 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2327 | uint64_t helper_float_floorl_s(uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2328 | { |
| 2329 | uint64_t dt2; |
| 2330 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2331 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
| 2332 | dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2333 | RESTORE_ROUNDING_MODE; |
| 2334 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2335 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2336 | dt2 = FLOAT_SNAN64; |
| 2337 | return dt2; |
| 2338 | } |
| 2339 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2340 | uint32_t helper_float_floorw_d(uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2341 | { |
| 2342 | uint32_t wt2; |
| 2343 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2344 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
| 2345 | wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2346 | RESTORE_ROUNDING_MODE; |
| 2347 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2348 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2349 | wt2 = FLOAT_SNAN32; |
| 2350 | return wt2; |
| 2351 | } |
| 2352 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2353 | uint32_t helper_float_floorw_s(uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2354 | { |
| 2355 | uint32_t wt2; |
| 2356 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2357 | set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); |
| 2358 | wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2359 | RESTORE_ROUNDING_MODE; |
| 2360 | update_fcr31(); |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2361 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2362 | wt2 = FLOAT_SNAN32; |
| 2363 | return wt2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2364 | } |
| 2365 | |
ths | a16336e | 2008-06-19 18:35:02 +0000 | [diff] [blame] | 2366 | /* unary operations, not modifying fp status */ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2367 | #define FLOAT_UNOP(name) \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2368 | uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2369 | { \ |
| 2370 | return float64_ ## name(fdt0); \ |
| 2371 | } \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2372 | uint32_t helper_float_ ## name ## _s(uint32_t fst0) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2373 | { \ |
| 2374 | return float32_ ## name(fst0); \ |
| 2375 | } \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2376 | uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2377 | { \ |
| 2378 | uint32_t wt0; \ |
| 2379 | uint32_t wth0; \ |
| 2380 | \ |
| 2381 | wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \ |
| 2382 | wth0 = float32_ ## name(fdt0 >> 32); \ |
| 2383 | return ((uint64_t)wth0 << 32) | wt0; \ |
ths | a16336e | 2008-06-19 18:35:02 +0000 | [diff] [blame] | 2384 | } |
| 2385 | FLOAT_UNOP(abs) |
| 2386 | FLOAT_UNOP(chs) |
| 2387 | #undef FLOAT_UNOP |
| 2388 | |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2389 | /* MIPS specific unary operations */ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2390 | uint64_t helper_float_recip_d(uint64_t fdt0) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2391 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2392 | uint64_t fdt2; |
| 2393 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2394 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2395 | fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2396 | update_fcr31(); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2397 | return fdt2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2398 | } |
ths | 57fa1fb | 2007-05-19 20:29:41 +0000 | [diff] [blame] | 2399 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2400 | uint32_t helper_float_recip_s(uint32_t fst0) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2401 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2402 | uint32_t fst2; |
| 2403 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2404 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2405 | fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2406 | update_fcr31(); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2407 | return fst2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2408 | } |
| 2409 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2410 | uint64_t helper_float_rsqrt_d(uint64_t fdt0) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2411 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2412 | uint64_t fdt2; |
| 2413 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2414 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2415 | fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
| 2416 | fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2417 | update_fcr31(); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2418 | return fdt2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2419 | } |
| 2420 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2421 | uint32_t helper_float_rsqrt_s(uint32_t fst0) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2422 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2423 | uint32_t fst2; |
| 2424 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2425 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2426 | fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
| 2427 | fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2428 | update_fcr31(); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2429 | return fst2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2430 | } |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2431 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2432 | uint64_t helper_float_recip1_d(uint64_t fdt0) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2433 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2434 | uint64_t fdt2; |
| 2435 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2436 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2437 | fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2438 | update_fcr31(); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2439 | return fdt2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2440 | } |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2441 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2442 | uint32_t helper_float_recip1_s(uint32_t fst0) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2443 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2444 | uint32_t fst2; |
| 2445 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2446 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2447 | fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2448 | update_fcr31(); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2449 | return fst2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2450 | } |
ths | 57fa1fb | 2007-05-19 20:29:41 +0000 | [diff] [blame] | 2451 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2452 | uint64_t helper_float_recip1_ps(uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2453 | { |
| 2454 | uint32_t fst2; |
| 2455 | uint32_t fsth2; |
| 2456 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2457 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2458 | fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
| 2459 | fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2460 | update_fcr31(); |
| 2461 | return ((uint64_t)fsth2 << 32) | fst2; |
| 2462 | } |
| 2463 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2464 | uint64_t helper_float_rsqrt1_d(uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2465 | { |
| 2466 | uint64_t fdt2; |
| 2467 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2468 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2469 | fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); |
| 2470 | fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2471 | update_fcr31(); |
| 2472 | return fdt2; |
| 2473 | } |
| 2474 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2475 | uint32_t helper_float_rsqrt1_s(uint32_t fst0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2476 | { |
| 2477 | uint32_t fst2; |
| 2478 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2479 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2480 | fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); |
| 2481 | fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2482 | update_fcr31(); |
| 2483 | return fst2; |
| 2484 | } |
| 2485 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2486 | uint64_t helper_float_rsqrt1_ps(uint64_t fdt0) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2487 | { |
| 2488 | uint32_t fst2; |
| 2489 | uint32_t fsth2; |
| 2490 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2491 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2492 | fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); |
| 2493 | fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); |
| 2494 | fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); |
| 2495 | fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2496 | update_fcr31(); |
| 2497 | return ((uint64_t)fsth2 << 32) | fst2; |
| 2498 | } |
| 2499 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2500 | #define FLOAT_OP(name, p) void helper_float_##name##_##p(void) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2501 | |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2502 | /* binary operations */ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2503 | #define FLOAT_BINOP(name) \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2504 | uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2505 | { \ |
| 2506 | uint64_t dt2; \ |
| 2507 | \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2508 | set_float_exception_flags(0, &env->active_fpu.fp_status); \ |
| 2509 | dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 2510 | update_fcr31(); \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2511 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2512 | dt2 = FLOAT_QNAN64; \ |
| 2513 | return dt2; \ |
| 2514 | } \ |
| 2515 | \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2516 | uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2517 | { \ |
| 2518 | uint32_t wt2; \ |
| 2519 | \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2520 | set_float_exception_flags(0, &env->active_fpu.fp_status); \ |
| 2521 | wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 2522 | update_fcr31(); \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2523 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2524 | wt2 = FLOAT_QNAN32; \ |
| 2525 | return wt2; \ |
| 2526 | } \ |
| 2527 | \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2528 | uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2529 | { \ |
| 2530 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ |
| 2531 | uint32_t fsth0 = fdt0 >> 32; \ |
| 2532 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ |
| 2533 | uint32_t fsth1 = fdt1 >> 32; \ |
| 2534 | uint32_t wt2; \ |
| 2535 | uint32_t wth2; \ |
| 2536 | \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2537 | set_float_exception_flags(0, &env->active_fpu.fp_status); \ |
| 2538 | wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ |
| 2539 | wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2540 | update_fcr31(); \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2541 | if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2542 | wt2 = FLOAT_QNAN32; \ |
| 2543 | wth2 = FLOAT_QNAN32; \ |
| 2544 | } \ |
| 2545 | return ((uint64_t)wth2 << 32) | wt2; \ |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2546 | } |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2547 | |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2548 | FLOAT_BINOP(add) |
| 2549 | FLOAT_BINOP(sub) |
| 2550 | FLOAT_BINOP(mul) |
| 2551 | FLOAT_BINOP(div) |
| 2552 | #undef FLOAT_BINOP |
| 2553 | |
ths | a16336e | 2008-06-19 18:35:02 +0000 | [diff] [blame] | 2554 | /* ternary operations */ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2555 | #define FLOAT_TERNOP(name1, name2) \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2556 | uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2557 | uint64_t fdt2) \ |
| 2558 | { \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2559 | fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ |
| 2560 | return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2561 | } \ |
| 2562 | \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2563 | uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2564 | uint32_t fst2) \ |
| 2565 | { \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2566 | fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
| 2567 | return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2568 | } \ |
| 2569 | \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2570 | uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2571 | uint64_t fdt2) \ |
| 2572 | { \ |
| 2573 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ |
| 2574 | uint32_t fsth0 = fdt0 >> 32; \ |
| 2575 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ |
| 2576 | uint32_t fsth1 = fdt1 >> 32; \ |
| 2577 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ |
| 2578 | uint32_t fsth2 = fdt2 >> 32; \ |
| 2579 | \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2580 | fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
| 2581 | fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ |
| 2582 | fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ |
| 2583 | fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2584 | return ((uint64_t)fsth2 << 32) | fst2; \ |
ths | a16336e | 2008-06-19 18:35:02 +0000 | [diff] [blame] | 2585 | } |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2586 | |
ths | a16336e | 2008-06-19 18:35:02 +0000 | [diff] [blame] | 2587 | FLOAT_TERNOP(mul, add) |
| 2588 | FLOAT_TERNOP(mul, sub) |
| 2589 | #undef FLOAT_TERNOP |
| 2590 | |
| 2591 | /* negated ternary operations */ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2592 | #define FLOAT_NTERNOP(name1, name2) \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2593 | uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2594 | uint64_t fdt2) \ |
| 2595 | { \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2596 | fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ |
| 2597 | fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2598 | return float64_chs(fdt2); \ |
| 2599 | } \ |
| 2600 | \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2601 | uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2602 | uint32_t fst2) \ |
| 2603 | { \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2604 | fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
| 2605 | fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2606 | return float32_chs(fst2); \ |
| 2607 | } \ |
| 2608 | \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2609 | uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2610 | uint64_t fdt2) \ |
| 2611 | { \ |
| 2612 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ |
| 2613 | uint32_t fsth0 = fdt0 >> 32; \ |
| 2614 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ |
| 2615 | uint32_t fsth1 = fdt1 >> 32; \ |
| 2616 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ |
| 2617 | uint32_t fsth2 = fdt2 >> 32; \ |
| 2618 | \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2619 | fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ |
| 2620 | fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ |
| 2621 | fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ |
| 2622 | fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2623 | fst2 = float32_chs(fst2); \ |
| 2624 | fsth2 = float32_chs(fsth2); \ |
| 2625 | return ((uint64_t)fsth2 << 32) | fst2; \ |
ths | a16336e | 2008-06-19 18:35:02 +0000 | [diff] [blame] | 2626 | } |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2627 | |
ths | a16336e | 2008-06-19 18:35:02 +0000 | [diff] [blame] | 2628 | FLOAT_NTERNOP(mul, add) |
| 2629 | FLOAT_NTERNOP(mul, sub) |
| 2630 | #undef FLOAT_NTERNOP |
| 2631 | |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2632 | /* MIPS specific binary operations */ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2633 | uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2634 | { |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2635 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2636 | fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); |
| 2637 | fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status)); |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2638 | update_fcr31(); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2639 | return fdt2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2640 | } |
| 2641 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2642 | uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2) |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2643 | { |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2644 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2645 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
| 2646 | fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2647 | update_fcr31(); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2648 | return fst2; |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2649 | } |
ths | 57fa1fb | 2007-05-19 20:29:41 +0000 | [diff] [blame] | 2650 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2651 | uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2652 | { |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2653 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
| 2654 | uint32_t fsth0 = fdt0 >> 32; |
| 2655 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; |
| 2656 | uint32_t fsth2 = fdt2 >> 32; |
| 2657 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2658 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2659 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
| 2660 | fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); |
| 2661 | fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); |
| 2662 | fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status)); |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2663 | update_fcr31(); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2664 | return ((uint64_t)fsth2 << 32) | fst2; |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2665 | } |
| 2666 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2667 | uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2) |
ths | 57fa1fb | 2007-05-19 20:29:41 +0000 | [diff] [blame] | 2668 | { |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2669 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2670 | fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); |
| 2671 | fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status); |
| 2672 | fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); |
ths | 57fa1fb | 2007-05-19 20:29:41 +0000 | [diff] [blame] | 2673 | update_fcr31(); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2674 | return fdt2; |
| 2675 | } |
| 2676 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2677 | uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2678 | { |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2679 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2680 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
| 2681 | fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); |
| 2682 | fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2683 | update_fcr31(); |
| 2684 | return fst2; |
| 2685 | } |
| 2686 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2687 | uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2688 | { |
| 2689 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
| 2690 | uint32_t fsth0 = fdt0 >> 32; |
| 2691 | uint32_t fst2 = fdt2 & 0XFFFFFFFF; |
| 2692 | uint32_t fsth2 = fdt2 >> 32; |
| 2693 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2694 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2695 | fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); |
| 2696 | fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); |
| 2697 | fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); |
| 2698 | fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status); |
| 2699 | fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
| 2700 | fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2701 | update_fcr31(); |
| 2702 | return ((uint64_t)fsth2 << 32) | fst2; |
| 2703 | } |
| 2704 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2705 | uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2706 | { |
| 2707 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
| 2708 | uint32_t fsth0 = fdt0 >> 32; |
| 2709 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; |
| 2710 | uint32_t fsth1 = fdt1 >> 32; |
| 2711 | uint32_t fst2; |
| 2712 | uint32_t fsth2; |
| 2713 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2714 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2715 | fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); |
| 2716 | fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2717 | update_fcr31(); |
| 2718 | return ((uint64_t)fsth2 << 32) | fst2; |
| 2719 | } |
| 2720 | |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2721 | uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1) |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2722 | { |
| 2723 | uint32_t fst0 = fdt0 & 0XFFFFFFFF; |
| 2724 | uint32_t fsth0 = fdt0 >> 32; |
| 2725 | uint32_t fst1 = fdt1 & 0XFFFFFFFF; |
| 2726 | uint32_t fsth1 = fdt1 >> 32; |
| 2727 | uint32_t fst2; |
| 2728 | uint32_t fsth2; |
| 2729 | |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2730 | set_float_exception_flags(0, &env->active_fpu.fp_status); |
| 2731 | fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); |
| 2732 | fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2733 | update_fcr31(); |
| 2734 | return ((uint64_t)fsth2 << 32) | fst2; |
ths | 57fa1fb | 2007-05-19 20:29:41 +0000 | [diff] [blame] | 2735 | } |
| 2736 | |
ths | 8dfdb87 | 2007-06-26 20:26:03 +0000 | [diff] [blame] | 2737 | /* compare operations */ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2738 | #define FOP_COND_D(op, cond) \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2739 | void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2740 | { \ |
| 2741 | int c = cond; \ |
| 2742 | update_fcr31(); \ |
| 2743 | if (c) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2744 | SET_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2745 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2746 | CLEAR_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2747 | } \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2748 | void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2749 | { \ |
| 2750 | int c; \ |
| 2751 | fdt0 = float64_abs(fdt0); \ |
| 2752 | fdt1 = float64_abs(fdt1); \ |
| 2753 | c = cond; \ |
| 2754 | update_fcr31(); \ |
| 2755 | if (c) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2756 | SET_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2757 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2758 | CLEAR_FP_COND(cc, env->active_fpu); \ |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2759 | } |
| 2760 | |
aurel32 | cd5158e | 2008-12-07 23:26:24 +0000 | [diff] [blame] | 2761 | static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2762 | { |
| 2763 | if (float64_is_signaling_nan(a) || |
| 2764 | float64_is_signaling_nan(b) || |
| 2765 | (sig && (float64_is_nan(a) || float64_is_nan(b)))) { |
| 2766 | float_raise(float_flag_invalid, status); |
| 2767 | return 1; |
| 2768 | } else if (float64_is_nan(a) || float64_is_nan(b)) { |
| 2769 | return 1; |
| 2770 | } else { |
| 2771 | return 0; |
| 2772 | } |
| 2773 | } |
| 2774 | |
| 2775 | /* NOTE: the comma operator will make "cond" to eval to false, |
| 2776 | * but float*_is_unordered() is still called. */ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2777 | FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0)) |
| 2778 | FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status)) |
| 2779 | FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 2780 | FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 2781 | FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 2782 | FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 2783 | FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 2784 | FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2785 | /* NOTE: the comma operator will make "cond" to eval to false, |
| 2786 | * but float*_is_unordered() is still called. */ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2787 | FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0)) |
| 2788 | FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status)) |
| 2789 | FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 2790 | FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 2791 | FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 2792 | FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 2793 | FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
| 2794 | FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2795 | |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2796 | #define FOP_COND_S(op, cond) \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2797 | void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2798 | { \ |
| 2799 | int c = cond; \ |
| 2800 | update_fcr31(); \ |
| 2801 | if (c) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2802 | SET_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2803 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2804 | CLEAR_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2805 | } \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2806 | void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2807 | { \ |
| 2808 | int c; \ |
| 2809 | fst0 = float32_abs(fst0); \ |
| 2810 | fst1 = float32_abs(fst1); \ |
| 2811 | c = cond; \ |
| 2812 | update_fcr31(); \ |
| 2813 | if (c) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2814 | SET_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2815 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2816 | CLEAR_FP_COND(cc, env->active_fpu); \ |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2817 | } |
| 2818 | |
aurel32 | cd5158e | 2008-12-07 23:26:24 +0000 | [diff] [blame] | 2819 | static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2820 | { |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2821 | if (float32_is_signaling_nan(a) || |
| 2822 | float32_is_signaling_nan(b) || |
| 2823 | (sig && (float32_is_nan(a) || float32_is_nan(b)))) { |
| 2824 | float_raise(float_flag_invalid, status); |
| 2825 | return 1; |
| 2826 | } else if (float32_is_nan(a) || float32_is_nan(b)) { |
| 2827 | return 1; |
| 2828 | } else { |
| 2829 | return 0; |
| 2830 | } |
| 2831 | } |
| 2832 | |
| 2833 | /* NOTE: the comma operator will make "cond" to eval to false, |
| 2834 | * but float*_is_unordered() is still called. */ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2835 | FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0)) |
| 2836 | FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status)) |
| 2837 | FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status)) |
| 2838 | FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) |
| 2839 | FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status)) |
| 2840 | FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) |
| 2841 | FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
| 2842 | FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2843 | /* NOTE: the comma operator will make "cond" to eval to false, |
| 2844 | * but float*_is_unordered() is still called. */ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2845 | FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0)) |
| 2846 | FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status)) |
| 2847 | FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status)) |
| 2848 | FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status)) |
| 2849 | FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status)) |
| 2850 | FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status)) |
| 2851 | FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
| 2852 | FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status)) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2853 | |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2854 | #define FOP_COND_PS(op, condl, condh) \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2855 | void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2856 | { \ |
| 2857 | uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \ |
| 2858 | uint32_t fsth0 = float32_abs(fdt0 >> 32); \ |
| 2859 | uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \ |
| 2860 | uint32_t fsth1 = float32_abs(fdt1 >> 32); \ |
| 2861 | int cl = condl; \ |
| 2862 | int ch = condh; \ |
| 2863 | \ |
| 2864 | update_fcr31(); \ |
| 2865 | if (cl) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2866 | SET_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2867 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2868 | CLEAR_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2869 | if (ch) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2870 | SET_FP_COND(cc + 1, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2871 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2872 | CLEAR_FP_COND(cc + 1, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2873 | } \ |
aurel32 | c01fccd | 2009-03-08 00:06:01 +0000 | [diff] [blame] | 2874 | void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2875 | { \ |
| 2876 | uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \ |
| 2877 | uint32_t fsth0 = float32_abs(fdt0 >> 32); \ |
| 2878 | uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \ |
| 2879 | uint32_t fsth1 = float32_abs(fdt1 >> 32); \ |
| 2880 | int cl = condl; \ |
| 2881 | int ch = condh; \ |
| 2882 | \ |
| 2883 | update_fcr31(); \ |
| 2884 | if (cl) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2885 | SET_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2886 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2887 | CLEAR_FP_COND(cc, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2888 | if (ch) \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2889 | SET_FP_COND(cc + 1, env->active_fpu); \ |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 2890 | else \ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2891 | CLEAR_FP_COND(cc + 1, env->active_fpu); \ |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2892 | } |
| 2893 | |
| 2894 | /* NOTE: the comma operator will make "cond" to eval to false, |
| 2895 | * but float*_is_unordered() is still called. */ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2896 | FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0), |
| 2897 | (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0)) |
| 2898 | FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), |
| 2899 | float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status)) |
| 2900 | FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status), |
| 2901 | !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 2902 | FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), |
| 2903 | float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 2904 | FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status), |
| 2905 | !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 2906 | FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), |
| 2907 | float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 2908 | FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status), |
| 2909 | !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 2910 | FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), |
| 2911 | float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |
ths | fd4a04e | 2007-05-18 11:55:54 +0000 | [diff] [blame] | 2912 | /* NOTE: the comma operator will make "cond" to eval to false, |
| 2913 | * but float*_is_unordered() is still called. */ |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 2914 | FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0), |
| 2915 | (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0)) |
| 2916 | FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), |
| 2917 | float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status)) |
| 2918 | FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status), |
| 2919 | !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 2920 | FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status), |
| 2921 | float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 2922 | FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status), |
| 2923 | !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 2924 | FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status), |
| 2925 | float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 2926 | FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status), |
| 2927 | !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |
| 2928 | FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status), |
| 2929 | float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status)) |