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Jia Liu4dd044c2012-07-20 15:50:49 +08001/*
2 * OpenRISC system instructions helper routines
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Zhizhou Zhang <etouzh@gmail.com>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
Thomas Huth779fc6a2019-01-23 15:08:54 +010010 * version 2.1 of the License, or (at your option) any later version.
Jia Liu4dd044c2012-07-20 15:50:49 +080011 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
Peter Maydelled2decc2016-01-26 18:17:22 +000021#include "qemu/osdep.h"
Jia Liu4dd044c2012-07-20 15:50:49 +080022#include "cpu.h"
Paolo Bonzini63c91552016-03-15 13:18:37 +010023#include "exec/exec-all.h"
Richard Henderson2ef61752014-04-07 22:31:41 -070024#include "exec/helper-proto.h"
Stafford Hornef4d14142017-04-24 06:07:42 +090025#include "exception.h"
Like Xu5cc87672019-05-19 04:54:21 +080026#ifndef CONFIG_USER_ONLY
27#include "hw/boards.h"
28#endif
Jia Liu4dd044c2012-07-20 15:50:49 +080029
30#define TO_SPR(group, number) (((group) << 11) + (number))
31
Richard Hendersonc28fa812018-05-23 07:13:26 -070032void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
Jia Liu4dd044c2012-07-20 15:50:49 +080033{
34#ifndef CONFIG_USER_ONLY
Richard Henderson5ee2b022019-03-22 18:48:56 -070035 OpenRISCCPU *cpu = env_archcpu(env);
36 CPUState *cs = env_cpu(env);
Richard Hendersonfffde662018-05-22 19:45:51 -070037 target_ulong mr;
Richard Henderson24c32852016-04-05 11:41:48 -070038 int idx;
Richard Hendersona4657722019-08-26 15:10:10 -070039#endif
Jia Liu4dd044c2012-07-20 15:50:49 +080040
41 switch (spr) {
Richard Hendersona4657722019-08-26 15:10:10 -070042#ifndef CONFIG_USER_ONLY
Tim 'mithro' Ansell356a2db2017-04-18 16:15:50 +100043 case TO_SPR(0, 11): /* EVBAR */
44 env->evbar = rb;
45 break;
46
Jia Liu4dd044c2012-07-20 15:50:49 +080047 case TO_SPR(0, 16): /* NPC */
Pavel Dovgalyukafd46fc2018-04-09 12:13:20 +030048 cpu_restore_state(cs, GETPC(), true);
Richard Henderson24c32852016-04-05 11:41:48 -070049 /* ??? Mirror or1ksim in not trashing delayed branch state
50 when "jumping" to the current instruction. */
51 if (env->pc != rb) {
52 env->pc = rb;
Richard Hendersona01deb32016-04-05 18:00:33 -070053 env->dflag = 0;
Richard Henderson24c32852016-04-05 11:41:48 -070054 cpu_loop_exit(cs);
55 }
Jia Liu4dd044c2012-07-20 15:50:49 +080056 break;
57
58 case TO_SPR(0, 17): /* SR */
Richard Henderson84775c42015-02-18 11:45:54 -080059 cpu_set_sr(env, rb);
Jia Liu4dd044c2012-07-20 15:50:49 +080060 break;
61
Jia Liu4dd044c2012-07-20 15:50:49 +080062 case TO_SPR(0, 32): /* EPCR */
63 env->epcr = rb;
64 break;
65
66 case TO_SPR(0, 48): /* EEAR */
67 env->eear = rb;
68 break;
69
70 case TO_SPR(0, 64): /* ESR */
71 env->esr = rb;
72 break;
Stafford Horned89e71e2017-04-06 06:44:56 +090073
74 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
75 idx = (spr - 1024);
76 env->shadow_gpr[idx / 32][idx % 32] = rb;
Richard Hendersonc3513c82018-06-27 08:40:23 -070077 break;
Stafford Horned89e71e2017-04-06 06:44:56 +090078
Richard Henderson56c3a142018-05-22 20:18:20 -070079 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */
Jia Liu4dd044c2012-07-20 15:50:49 +080080 idx = spr - TO_SPR(1, 512);
Richard Hendersonfffde662018-05-22 19:45:51 -070081 mr = env->tlb.dtlb[idx].mr;
82 if (mr & 1) {
83 tlb_flush_page(cs, mr & TARGET_PAGE_MASK);
84 }
85 if (rb & 1) {
86 tlb_flush_page(cs, rb & TARGET_PAGE_MASK);
Jia Liu4dd044c2012-07-20 15:50:49 +080087 }
Richard Henderson2acaa232018-05-22 19:36:27 -070088 env->tlb.dtlb[idx].mr = rb;
Jia Liu4dd044c2012-07-20 15:50:49 +080089 break;
Richard Henderson56c3a142018-05-22 20:18:20 -070090 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */
Jia Liu4dd044c2012-07-20 15:50:49 +080091 idx = spr - TO_SPR(1, 640);
Richard Henderson2acaa232018-05-22 19:36:27 -070092 env->tlb.dtlb[idx].tr = rb;
Jia Liu4dd044c2012-07-20 15:50:49 +080093 break;
94 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
95 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
96 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
97 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
98 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
99 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
100 break;
Richard Hendersonfffde662018-05-22 19:45:51 -0700101
Richard Henderson56c3a142018-05-22 20:18:20 -0700102 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */
Jia Liu4dd044c2012-07-20 15:50:49 +0800103 idx = spr - TO_SPR(2, 512);
Richard Hendersonfffde662018-05-22 19:45:51 -0700104 mr = env->tlb.itlb[idx].mr;
105 if (mr & 1) {
106 tlb_flush_page(cs, mr & TARGET_PAGE_MASK);
107 }
108 if (rb & 1) {
109 tlb_flush_page(cs, rb & TARGET_PAGE_MASK);
Jia Liu4dd044c2012-07-20 15:50:49 +0800110 }
Richard Henderson2acaa232018-05-22 19:36:27 -0700111 env->tlb.itlb[idx].mr = rb;
Jia Liu4dd044c2012-07-20 15:50:49 +0800112 break;
Richard Henderson56c3a142018-05-22 20:18:20 -0700113 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */
Jia Liu4dd044c2012-07-20 15:50:49 +0800114 idx = spr - TO_SPR(2, 640);
Richard Henderson2acaa232018-05-22 19:36:27 -0700115 env->tlb.itlb[idx].tr = rb;
Jia Liu4dd044c2012-07-20 15:50:49 +0800116 break;
117 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
118 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
119 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
120 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
121 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
122 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
123 break;
Richard Hendersonfffde662018-05-22 19:45:51 -0700124
Richard Henderson6f7332b2015-02-18 15:05:05 -0800125 case TO_SPR(5, 1): /* MACLO */
126 env->mac = deposit64(env->mac, 0, 32, rb);
127 break;
128 case TO_SPR(5, 2): /* MACHI */
129 env->mac = deposit64(env->mac, 32, 32, rb);
130 break;
Stafford Hornef4d14142017-04-24 06:07:42 +0900131 case TO_SPR(8, 0): /* PMR */
132 env->pmr = rb;
133 if (env->pmr & PMR_DME || env->pmr & PMR_SME) {
Pavel Dovgalyukafd46fc2018-04-09 12:13:20 +0300134 cpu_restore_state(cs, GETPC(), true);
Stafford Hornef4d14142017-04-24 06:07:42 +0900135 env->pc += 4;
136 cs->halted = 1;
137 raise_exception(cpu, EXCP_HALTED);
138 }
139 break;
Jia Liu4dd044c2012-07-20 15:50:49 +0800140 case TO_SPR(9, 0): /* PICMR */
Stafford Hornedfc84742018-07-01 17:02:54 +0900141 env->picmr = rb;
Jia Liu4dd044c2012-07-20 15:50:49 +0800142 break;
143 case TO_SPR(9, 2): /* PICSR */
144 env->picsr &= ~rb;
145 break;
146 case TO_SPR(10, 0): /* TTMR */
147 {
Sebastian Macked5155212013-10-22 02:12:41 +0200148 if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
149 switch (rb & TTMR_M) {
150 case TIMER_NONE:
151 cpu_openrisc_count_stop(cpu);
152 break;
153 case TIMER_INTR:
154 case TIMER_SHOT:
155 case TIMER_CONT:
156 cpu_openrisc_count_start(cpu);
157 break;
158 default:
159 break;
160 }
161 }
162
Jia Liu4dd044c2012-07-20 15:50:49 +0800163 int ip = env->ttmr & TTMR_IP;
164
165 if (rb & TTMR_IP) { /* Keep IP bit. */
Sebastian Macked5155212013-10-22 02:12:41 +0200166 env->ttmr = (rb & ~TTMR_IP) | ip;
Jia Liu4dd044c2012-07-20 15:50:49 +0800167 } else { /* Clear IP bit. */
168 env->ttmr = rb & ~TTMR_IP;
Andreas Färber259186a2013-01-17 18:51:17 +0100169 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
Jia Liu4dd044c2012-07-20 15:50:49 +0800170 }
171
Sebastian Macked5155212013-10-22 02:12:41 +0200172 cpu_openrisc_timer_update(cpu);
Jia Liu4dd044c2012-07-20 15:50:49 +0800173 }
174 break;
175
176 case TO_SPR(10, 1): /* TTCR */
Stafford Horne6b4bbd62017-08-22 06:37:10 +0900177 cpu_openrisc_count_set(cpu, rb);
Sebastian Macked5155212013-10-22 02:12:41 +0200178 cpu_openrisc_timer_update(cpu);
Jia Liu4dd044c2012-07-20 15:50:49 +0800179 break;
Richard Hendersona4657722019-08-26 15:10:10 -0700180#endif
181
182 case TO_SPR(0, 20): /* FPCSR */
183 cpu_set_fpcsr(env, rb);
Jia Liu4dd044c2012-07-20 15:50:49 +0800184 break;
185 }
Jia Liu4dd044c2012-07-20 15:50:49 +0800186}
187
Richard Hendersonc28fa812018-05-23 07:13:26 -0700188target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
189 target_ulong spr)
Jia Liu4dd044c2012-07-20 15:50:49 +0800190{
191#ifndef CONFIG_USER_ONLY
Like Xu5cc87672019-05-19 04:54:21 +0800192 MachineState *ms = MACHINE(qdev_get_machine());
Richard Henderson5ee2b022019-03-22 18:48:56 -0700193 OpenRISCCPU *cpu = env_archcpu(env);
194 CPUState *cs = env_cpu(env);
Jia Liu4dd044c2012-07-20 15:50:49 +0800195 int idx;
Richard Hendersona4657722019-08-26 15:10:10 -0700196#endif
Jia Liu4dd044c2012-07-20 15:50:49 +0800197
Jia Liu4dd044c2012-07-20 15:50:49 +0800198 switch (spr) {
Richard Hendersona4657722019-08-26 15:10:10 -0700199#ifndef CONFIG_USER_ONLY
Jia Liu4dd044c2012-07-20 15:50:49 +0800200 case TO_SPR(0, 0): /* VR */
Richard Hendersonb72e3ff2019-08-25 14:28:37 -0700201 return env->vr;
Jia Liu4dd044c2012-07-20 15:50:49 +0800202
203 case TO_SPR(0, 1): /* UPR */
Richard Hendersonc7efab42019-08-25 15:02:54 -0700204 return env->upr;
Jia Liu4dd044c2012-07-20 15:50:49 +0800205
206 case TO_SPR(0, 2): /* CPUCFGR */
207 return env->cpucfgr;
208
209 case TO_SPR(0, 3): /* DMMUCFGR */
Richard Hendersonc7efab42019-08-25 15:02:54 -0700210 return env->dmmucfgr;
Jia Liu4dd044c2012-07-20 15:50:49 +0800211
212 case TO_SPR(0, 4): /* IMMUCFGR */
213 return env->immucfgr;
214
Richard Henderson8bebf7d2019-08-25 15:23:42 -0700215 case TO_SPR(0, 9): /* VR2 */
216 return env->vr2;
217
218 case TO_SPR(0, 10): /* AVR */
219 return env->avr;
220
Tim 'mithro' Ansell356a2db2017-04-18 16:15:50 +1000221 case TO_SPR(0, 11): /* EVBAR */
222 return env->evbar;
223
Richard Henderson24c32852016-04-05 11:41:48 -0700224 case TO_SPR(0, 16): /* NPC (equals PC) */
Pavel Dovgalyukafd46fc2018-04-09 12:13:20 +0300225 cpu_restore_state(cs, GETPC(), false);
Richard Henderson24c32852016-04-05 11:41:48 -0700226 return env->pc;
Jia Liu4dd044c2012-07-20 15:50:49 +0800227
228 case TO_SPR(0, 17): /* SR */
Richard Henderson84775c42015-02-18 11:45:54 -0800229 return cpu_get_sr(env);
Jia Liu4dd044c2012-07-20 15:50:49 +0800230
231 case TO_SPR(0, 18): /* PPC */
Pavel Dovgalyukafd46fc2018-04-09 12:13:20 +0300232 cpu_restore_state(cs, GETPC(), false);
Jia Liu4dd044c2012-07-20 15:50:49 +0800233 return env->ppc;
234
235 case TO_SPR(0, 32): /* EPCR */
236 return env->epcr;
237
238 case TO_SPR(0, 48): /* EEAR */
239 return env->eear;
240
241 case TO_SPR(0, 64): /* ESR */
242 return env->esr;
243
Stafford Horneef3f5b92017-04-15 07:25:32 +0900244 case TO_SPR(0, 128): /* COREID */
Stafford Horne8c949952017-06-18 01:50:06 +0900245 return cpu->parent_obj.cpu_index;
Stafford Horneef3f5b92017-04-15 07:25:32 +0900246
247 case TO_SPR(0, 129): /* NUMCORES */
Like Xu5cc87672019-05-19 04:54:21 +0800248 return ms->smp.max_cpus;
Stafford Horneef3f5b92017-04-15 07:25:32 +0900249
Stafford Horned89e71e2017-04-06 06:44:56 +0900250 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
251 idx = (spr - 1024);
252 return env->shadow_gpr[idx / 32][idx % 32];
253
Richard Henderson56c3a142018-05-22 20:18:20 -0700254 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */
Jia Liu4dd044c2012-07-20 15:50:49 +0800255 idx = spr - TO_SPR(1, 512);
Richard Henderson2acaa232018-05-22 19:36:27 -0700256 return env->tlb.dtlb[idx].mr;
Jia Liu4dd044c2012-07-20 15:50:49 +0800257
Richard Henderson56c3a142018-05-22 20:18:20 -0700258 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */
Jia Liu4dd044c2012-07-20 15:50:49 +0800259 idx = spr - TO_SPR(1, 640);
Richard Henderson2acaa232018-05-22 19:36:27 -0700260 return env->tlb.dtlb[idx].tr;
Jia Liu4dd044c2012-07-20 15:50:49 +0800261
262 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
263 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
264 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
265 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
266 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
267 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
268 break;
269
Richard Henderson56c3a142018-05-22 20:18:20 -0700270 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */
Jia Liu4dd044c2012-07-20 15:50:49 +0800271 idx = spr - TO_SPR(2, 512);
Richard Henderson2acaa232018-05-22 19:36:27 -0700272 return env->tlb.itlb[idx].mr;
Jia Liu4dd044c2012-07-20 15:50:49 +0800273
Richard Henderson56c3a142018-05-22 20:18:20 -0700274 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */
Jia Liu4dd044c2012-07-20 15:50:49 +0800275 idx = spr - TO_SPR(2, 640);
Richard Henderson2acaa232018-05-22 19:36:27 -0700276 return env->tlb.itlb[idx].tr;
Jia Liu4dd044c2012-07-20 15:50:49 +0800277
278 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
279 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
280 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
281 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
282 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
283 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
284 break;
285
Richard Henderson6f7332b2015-02-18 15:05:05 -0800286 case TO_SPR(5, 1): /* MACLO */
287 return (uint32_t)env->mac;
288 break;
289 case TO_SPR(5, 2): /* MACHI */
290 return env->mac >> 32;
291 break;
292
Stafford Hornef4d14142017-04-24 06:07:42 +0900293 case TO_SPR(8, 0): /* PMR */
294 return env->pmr;
295
Jia Liu4dd044c2012-07-20 15:50:49 +0800296 case TO_SPR(9, 0): /* PICMR */
297 return env->picmr;
298
299 case TO_SPR(9, 2): /* PICSR */
300 return env->picsr;
301
302 case TO_SPR(10, 0): /* TTMR */
303 return env->ttmr;
304
305 case TO_SPR(10, 1): /* TTCR */
306 cpu_openrisc_count_update(cpu);
Stafford Horne6b4bbd62017-08-22 06:37:10 +0900307 return cpu_openrisc_count_get(cpu);
Jia Liu4dd044c2012-07-20 15:50:49 +0800308#endif
309
Richard Hendersona4657722019-08-26 15:10:10 -0700310 case TO_SPR(0, 20): /* FPCSR */
311 return env->fpcsr;
312 }
313
Jia Liu4dd044c2012-07-20 15:50:49 +0800314 /* for rd is passed in, if rd unchanged, just keep it back. */
315 return rd;
316}