Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 1 | /* |
| 2 | * OpenRISC system instructions helper routines |
| 3 | * |
| 4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> |
| 5 | * Zhizhou Zhang <etouzh@gmail.com> |
| 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
Thomas Huth | 779fc6a | 2019-01-23 15:08:54 +0100 | [diff] [blame] | 10 | * version 2.1 of the License, or (at your option) any later version. |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
| 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
Peter Maydell | ed2decc | 2016-01-26 18:17:22 +0000 | [diff] [blame] | 21 | #include "qemu/osdep.h" |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 22 | #include "cpu.h" |
Paolo Bonzini | 63c9155 | 2016-03-15 13:18:37 +0100 | [diff] [blame] | 23 | #include "exec/exec-all.h" |
Richard Henderson | 2ef6175 | 2014-04-07 22:31:41 -0700 | [diff] [blame] | 24 | #include "exec/helper-proto.h" |
Stafford Horne | f4d1414 | 2017-04-24 06:07:42 +0900 | [diff] [blame] | 25 | #include "exception.h" |
Like Xu | 5cc8767 | 2019-05-19 04:54:21 +0800 | [diff] [blame] | 26 | #ifndef CONFIG_USER_ONLY |
| 27 | #include "hw/boards.h" |
| 28 | #endif |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 29 | |
| 30 | #define TO_SPR(group, number) (((group) << 11) + (number)) |
| 31 | |
Richard Henderson | c28fa81 | 2018-05-23 07:13:26 -0700 | [diff] [blame] | 32 | void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 33 | { |
| 34 | #ifndef CONFIG_USER_ONLY |
Richard Henderson | 5ee2b02 | 2019-03-22 18:48:56 -0700 | [diff] [blame] | 35 | OpenRISCCPU *cpu = env_archcpu(env); |
| 36 | CPUState *cs = env_cpu(env); |
Richard Henderson | fffde66 | 2018-05-22 19:45:51 -0700 | [diff] [blame] | 37 | target_ulong mr; |
Richard Henderson | 24c3285 | 2016-04-05 11:41:48 -0700 | [diff] [blame] | 38 | int idx; |
Richard Henderson | a465772 | 2019-08-26 15:10:10 -0700 | [diff] [blame] | 39 | #endif |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 40 | |
| 41 | switch (spr) { |
Richard Henderson | a465772 | 2019-08-26 15:10:10 -0700 | [diff] [blame] | 42 | #ifndef CONFIG_USER_ONLY |
Tim 'mithro' Ansell | 356a2db | 2017-04-18 16:15:50 +1000 | [diff] [blame] | 43 | case TO_SPR(0, 11): /* EVBAR */ |
| 44 | env->evbar = rb; |
| 45 | break; |
| 46 | |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 47 | case TO_SPR(0, 16): /* NPC */ |
Pavel Dovgalyuk | afd46fc | 2018-04-09 12:13:20 +0300 | [diff] [blame] | 48 | cpu_restore_state(cs, GETPC(), true); |
Richard Henderson | 24c3285 | 2016-04-05 11:41:48 -0700 | [diff] [blame] | 49 | /* ??? Mirror or1ksim in not trashing delayed branch state |
| 50 | when "jumping" to the current instruction. */ |
| 51 | if (env->pc != rb) { |
| 52 | env->pc = rb; |
Richard Henderson | a01deb3 | 2016-04-05 18:00:33 -0700 | [diff] [blame] | 53 | env->dflag = 0; |
Richard Henderson | 24c3285 | 2016-04-05 11:41:48 -0700 | [diff] [blame] | 54 | cpu_loop_exit(cs); |
| 55 | } |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 56 | break; |
| 57 | |
| 58 | case TO_SPR(0, 17): /* SR */ |
Richard Henderson | 84775c4 | 2015-02-18 11:45:54 -0800 | [diff] [blame] | 59 | cpu_set_sr(env, rb); |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 60 | break; |
| 61 | |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 62 | case TO_SPR(0, 32): /* EPCR */ |
| 63 | env->epcr = rb; |
| 64 | break; |
| 65 | |
| 66 | case TO_SPR(0, 48): /* EEAR */ |
| 67 | env->eear = rb; |
| 68 | break; |
| 69 | |
| 70 | case TO_SPR(0, 64): /* ESR */ |
| 71 | env->esr = rb; |
| 72 | break; |
Stafford Horne | d89e71e | 2017-04-06 06:44:56 +0900 | [diff] [blame] | 73 | |
| 74 | case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ |
| 75 | idx = (spr - 1024); |
| 76 | env->shadow_gpr[idx / 32][idx % 32] = rb; |
Richard Henderson | c3513c8 | 2018-06-27 08:40:23 -0700 | [diff] [blame] | 77 | break; |
Stafford Horne | d89e71e | 2017-04-06 06:44:56 +0900 | [diff] [blame] | 78 | |
Richard Henderson | 56c3a14 | 2018-05-22 20:18:20 -0700 | [diff] [blame] | 79 | case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 80 | idx = spr - TO_SPR(1, 512); |
Richard Henderson | fffde66 | 2018-05-22 19:45:51 -0700 | [diff] [blame] | 81 | mr = env->tlb.dtlb[idx].mr; |
| 82 | if (mr & 1) { |
| 83 | tlb_flush_page(cs, mr & TARGET_PAGE_MASK); |
| 84 | } |
| 85 | if (rb & 1) { |
| 86 | tlb_flush_page(cs, rb & TARGET_PAGE_MASK); |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 87 | } |
Richard Henderson | 2acaa23 | 2018-05-22 19:36:27 -0700 | [diff] [blame] | 88 | env->tlb.dtlb[idx].mr = rb; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 89 | break; |
Richard Henderson | 56c3a14 | 2018-05-22 20:18:20 -0700 | [diff] [blame] | 90 | case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 91 | idx = spr - TO_SPR(1, 640); |
Richard Henderson | 2acaa23 | 2018-05-22 19:36:27 -0700 | [diff] [blame] | 92 | env->tlb.dtlb[idx].tr = rb; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 93 | break; |
| 94 | case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ |
| 95 | case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ |
| 96 | case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ |
| 97 | case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ |
| 98 | case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ |
| 99 | case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ |
| 100 | break; |
Richard Henderson | fffde66 | 2018-05-22 19:45:51 -0700 | [diff] [blame] | 101 | |
Richard Henderson | 56c3a14 | 2018-05-22 20:18:20 -0700 | [diff] [blame] | 102 | case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 103 | idx = spr - TO_SPR(2, 512); |
Richard Henderson | fffde66 | 2018-05-22 19:45:51 -0700 | [diff] [blame] | 104 | mr = env->tlb.itlb[idx].mr; |
| 105 | if (mr & 1) { |
| 106 | tlb_flush_page(cs, mr & TARGET_PAGE_MASK); |
| 107 | } |
| 108 | if (rb & 1) { |
| 109 | tlb_flush_page(cs, rb & TARGET_PAGE_MASK); |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 110 | } |
Richard Henderson | 2acaa23 | 2018-05-22 19:36:27 -0700 | [diff] [blame] | 111 | env->tlb.itlb[idx].mr = rb; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 112 | break; |
Richard Henderson | 56c3a14 | 2018-05-22 20:18:20 -0700 | [diff] [blame] | 113 | case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 114 | idx = spr - TO_SPR(2, 640); |
Richard Henderson | 2acaa23 | 2018-05-22 19:36:27 -0700 | [diff] [blame] | 115 | env->tlb.itlb[idx].tr = rb; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 116 | break; |
| 117 | case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ |
| 118 | case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ |
| 119 | case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ |
| 120 | case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ |
| 121 | case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ |
| 122 | case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ |
| 123 | break; |
Richard Henderson | fffde66 | 2018-05-22 19:45:51 -0700 | [diff] [blame] | 124 | |
Richard Henderson | 6f7332b | 2015-02-18 15:05:05 -0800 | [diff] [blame] | 125 | case TO_SPR(5, 1): /* MACLO */ |
| 126 | env->mac = deposit64(env->mac, 0, 32, rb); |
| 127 | break; |
| 128 | case TO_SPR(5, 2): /* MACHI */ |
| 129 | env->mac = deposit64(env->mac, 32, 32, rb); |
| 130 | break; |
Stafford Horne | f4d1414 | 2017-04-24 06:07:42 +0900 | [diff] [blame] | 131 | case TO_SPR(8, 0): /* PMR */ |
| 132 | env->pmr = rb; |
| 133 | if (env->pmr & PMR_DME || env->pmr & PMR_SME) { |
Pavel Dovgalyuk | afd46fc | 2018-04-09 12:13:20 +0300 | [diff] [blame] | 134 | cpu_restore_state(cs, GETPC(), true); |
Stafford Horne | f4d1414 | 2017-04-24 06:07:42 +0900 | [diff] [blame] | 135 | env->pc += 4; |
| 136 | cs->halted = 1; |
| 137 | raise_exception(cpu, EXCP_HALTED); |
| 138 | } |
| 139 | break; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 140 | case TO_SPR(9, 0): /* PICMR */ |
Stafford Horne | dfc8474 | 2018-07-01 17:02:54 +0900 | [diff] [blame] | 141 | env->picmr = rb; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 142 | break; |
| 143 | case TO_SPR(9, 2): /* PICSR */ |
| 144 | env->picsr &= ~rb; |
| 145 | break; |
| 146 | case TO_SPR(10, 0): /* TTMR */ |
| 147 | { |
Sebastian Macke | d515521 | 2013-10-22 02:12:41 +0200 | [diff] [blame] | 148 | if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) { |
| 149 | switch (rb & TTMR_M) { |
| 150 | case TIMER_NONE: |
| 151 | cpu_openrisc_count_stop(cpu); |
| 152 | break; |
| 153 | case TIMER_INTR: |
| 154 | case TIMER_SHOT: |
| 155 | case TIMER_CONT: |
| 156 | cpu_openrisc_count_start(cpu); |
| 157 | break; |
| 158 | default: |
| 159 | break; |
| 160 | } |
| 161 | } |
| 162 | |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 163 | int ip = env->ttmr & TTMR_IP; |
| 164 | |
| 165 | if (rb & TTMR_IP) { /* Keep IP bit. */ |
Sebastian Macke | d515521 | 2013-10-22 02:12:41 +0200 | [diff] [blame] | 166 | env->ttmr = (rb & ~TTMR_IP) | ip; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 167 | } else { /* Clear IP bit. */ |
| 168 | env->ttmr = rb & ~TTMR_IP; |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 169 | cs->interrupt_request &= ~CPU_INTERRUPT_TIMER; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 170 | } |
| 171 | |
Sebastian Macke | d515521 | 2013-10-22 02:12:41 +0200 | [diff] [blame] | 172 | cpu_openrisc_timer_update(cpu); |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 173 | } |
| 174 | break; |
| 175 | |
| 176 | case TO_SPR(10, 1): /* TTCR */ |
Stafford Horne | 6b4bbd6 | 2017-08-22 06:37:10 +0900 | [diff] [blame] | 177 | cpu_openrisc_count_set(cpu, rb); |
Sebastian Macke | d515521 | 2013-10-22 02:12:41 +0200 | [diff] [blame] | 178 | cpu_openrisc_timer_update(cpu); |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 179 | break; |
Richard Henderson | a465772 | 2019-08-26 15:10:10 -0700 | [diff] [blame] | 180 | #endif |
| 181 | |
| 182 | case TO_SPR(0, 20): /* FPCSR */ |
| 183 | cpu_set_fpcsr(env, rb); |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 184 | break; |
| 185 | } |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 186 | } |
| 187 | |
Richard Henderson | c28fa81 | 2018-05-23 07:13:26 -0700 | [diff] [blame] | 188 | target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, |
| 189 | target_ulong spr) |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 190 | { |
| 191 | #ifndef CONFIG_USER_ONLY |
Like Xu | 5cc8767 | 2019-05-19 04:54:21 +0800 | [diff] [blame] | 192 | MachineState *ms = MACHINE(qdev_get_machine()); |
Richard Henderson | 5ee2b02 | 2019-03-22 18:48:56 -0700 | [diff] [blame] | 193 | OpenRISCCPU *cpu = env_archcpu(env); |
| 194 | CPUState *cs = env_cpu(env); |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 195 | int idx; |
Richard Henderson | a465772 | 2019-08-26 15:10:10 -0700 | [diff] [blame] | 196 | #endif |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 197 | |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 198 | switch (spr) { |
Richard Henderson | a465772 | 2019-08-26 15:10:10 -0700 | [diff] [blame] | 199 | #ifndef CONFIG_USER_ONLY |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 200 | case TO_SPR(0, 0): /* VR */ |
Richard Henderson | b72e3ff | 2019-08-25 14:28:37 -0700 | [diff] [blame] | 201 | return env->vr; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 202 | |
| 203 | case TO_SPR(0, 1): /* UPR */ |
Richard Henderson | c7efab4 | 2019-08-25 15:02:54 -0700 | [diff] [blame] | 204 | return env->upr; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 205 | |
| 206 | case TO_SPR(0, 2): /* CPUCFGR */ |
| 207 | return env->cpucfgr; |
| 208 | |
| 209 | case TO_SPR(0, 3): /* DMMUCFGR */ |
Richard Henderson | c7efab4 | 2019-08-25 15:02:54 -0700 | [diff] [blame] | 210 | return env->dmmucfgr; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 211 | |
| 212 | case TO_SPR(0, 4): /* IMMUCFGR */ |
| 213 | return env->immucfgr; |
| 214 | |
Richard Henderson | 8bebf7d | 2019-08-25 15:23:42 -0700 | [diff] [blame] | 215 | case TO_SPR(0, 9): /* VR2 */ |
| 216 | return env->vr2; |
| 217 | |
| 218 | case TO_SPR(0, 10): /* AVR */ |
| 219 | return env->avr; |
| 220 | |
Tim 'mithro' Ansell | 356a2db | 2017-04-18 16:15:50 +1000 | [diff] [blame] | 221 | case TO_SPR(0, 11): /* EVBAR */ |
| 222 | return env->evbar; |
| 223 | |
Richard Henderson | 24c3285 | 2016-04-05 11:41:48 -0700 | [diff] [blame] | 224 | case TO_SPR(0, 16): /* NPC (equals PC) */ |
Pavel Dovgalyuk | afd46fc | 2018-04-09 12:13:20 +0300 | [diff] [blame] | 225 | cpu_restore_state(cs, GETPC(), false); |
Richard Henderson | 24c3285 | 2016-04-05 11:41:48 -0700 | [diff] [blame] | 226 | return env->pc; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 227 | |
| 228 | case TO_SPR(0, 17): /* SR */ |
Richard Henderson | 84775c4 | 2015-02-18 11:45:54 -0800 | [diff] [blame] | 229 | return cpu_get_sr(env); |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 230 | |
| 231 | case TO_SPR(0, 18): /* PPC */ |
Pavel Dovgalyuk | afd46fc | 2018-04-09 12:13:20 +0300 | [diff] [blame] | 232 | cpu_restore_state(cs, GETPC(), false); |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 233 | return env->ppc; |
| 234 | |
| 235 | case TO_SPR(0, 32): /* EPCR */ |
| 236 | return env->epcr; |
| 237 | |
| 238 | case TO_SPR(0, 48): /* EEAR */ |
| 239 | return env->eear; |
| 240 | |
| 241 | case TO_SPR(0, 64): /* ESR */ |
| 242 | return env->esr; |
| 243 | |
Stafford Horne | ef3f5b9 | 2017-04-15 07:25:32 +0900 | [diff] [blame] | 244 | case TO_SPR(0, 128): /* COREID */ |
Stafford Horne | 8c94995 | 2017-06-18 01:50:06 +0900 | [diff] [blame] | 245 | return cpu->parent_obj.cpu_index; |
Stafford Horne | ef3f5b9 | 2017-04-15 07:25:32 +0900 | [diff] [blame] | 246 | |
| 247 | case TO_SPR(0, 129): /* NUMCORES */ |
Like Xu | 5cc8767 | 2019-05-19 04:54:21 +0800 | [diff] [blame] | 248 | return ms->smp.max_cpus; |
Stafford Horne | ef3f5b9 | 2017-04-15 07:25:32 +0900 | [diff] [blame] | 249 | |
Stafford Horne | d89e71e | 2017-04-06 06:44:56 +0900 | [diff] [blame] | 250 | case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ |
| 251 | idx = (spr - 1024); |
| 252 | return env->shadow_gpr[idx / 32][idx % 32]; |
| 253 | |
Richard Henderson | 56c3a14 | 2018-05-22 20:18:20 -0700 | [diff] [blame] | 254 | case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 255 | idx = spr - TO_SPR(1, 512); |
Richard Henderson | 2acaa23 | 2018-05-22 19:36:27 -0700 | [diff] [blame] | 256 | return env->tlb.dtlb[idx].mr; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 257 | |
Richard Henderson | 56c3a14 | 2018-05-22 20:18:20 -0700 | [diff] [blame] | 258 | case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 259 | idx = spr - TO_SPR(1, 640); |
Richard Henderson | 2acaa23 | 2018-05-22 19:36:27 -0700 | [diff] [blame] | 260 | return env->tlb.dtlb[idx].tr; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 261 | |
| 262 | case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ |
| 263 | case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ |
| 264 | case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ |
| 265 | case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ |
| 266 | case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ |
| 267 | case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ |
| 268 | break; |
| 269 | |
Richard Henderson | 56c3a14 | 2018-05-22 20:18:20 -0700 | [diff] [blame] | 270 | case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 271 | idx = spr - TO_SPR(2, 512); |
Richard Henderson | 2acaa23 | 2018-05-22 19:36:27 -0700 | [diff] [blame] | 272 | return env->tlb.itlb[idx].mr; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 273 | |
Richard Henderson | 56c3a14 | 2018-05-22 20:18:20 -0700 | [diff] [blame] | 274 | case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 275 | idx = spr - TO_SPR(2, 640); |
Richard Henderson | 2acaa23 | 2018-05-22 19:36:27 -0700 | [diff] [blame] | 276 | return env->tlb.itlb[idx].tr; |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 277 | |
| 278 | case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ |
| 279 | case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ |
| 280 | case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ |
| 281 | case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ |
| 282 | case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ |
| 283 | case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ |
| 284 | break; |
| 285 | |
Richard Henderson | 6f7332b | 2015-02-18 15:05:05 -0800 | [diff] [blame] | 286 | case TO_SPR(5, 1): /* MACLO */ |
| 287 | return (uint32_t)env->mac; |
| 288 | break; |
| 289 | case TO_SPR(5, 2): /* MACHI */ |
| 290 | return env->mac >> 32; |
| 291 | break; |
| 292 | |
Stafford Horne | f4d1414 | 2017-04-24 06:07:42 +0900 | [diff] [blame] | 293 | case TO_SPR(8, 0): /* PMR */ |
| 294 | return env->pmr; |
| 295 | |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 296 | case TO_SPR(9, 0): /* PICMR */ |
| 297 | return env->picmr; |
| 298 | |
| 299 | case TO_SPR(9, 2): /* PICSR */ |
| 300 | return env->picsr; |
| 301 | |
| 302 | case TO_SPR(10, 0): /* TTMR */ |
| 303 | return env->ttmr; |
| 304 | |
| 305 | case TO_SPR(10, 1): /* TTCR */ |
| 306 | cpu_openrisc_count_update(cpu); |
Stafford Horne | 6b4bbd6 | 2017-08-22 06:37:10 +0900 | [diff] [blame] | 307 | return cpu_openrisc_count_get(cpu); |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 308 | #endif |
| 309 | |
Richard Henderson | a465772 | 2019-08-26 15:10:10 -0700 | [diff] [blame] | 310 | case TO_SPR(0, 20): /* FPCSR */ |
| 311 | return env->fpcsr; |
| 312 | } |
| 313 | |
Jia Liu | 4dd044c | 2012-07-20 15:50:49 +0800 | [diff] [blame] | 314 | /* for rd is passed in, if rd unchanged, just keep it back. */ |
| 315 | return rd; |
| 316 | } |