commit b72e3ff65880f2b894a2692e2b0a14424058a919
author Richard Henderson <richard.henderson@linaro.org> Sun Aug 25 14:28:37 2019 -0700
committer Richard Henderson <richard.henderson@linaro.org> Wed Sep 04 12:48:22 2019 -0700
tree 3c019d506fe32b7f3af87821339291e57614746d
parent d29f4368a71c6fe5de3a4424c67d4a3a2e577843

target/openrisc: Make VR and PPC read-only

These SPRs are read-only.  The writes can simply be ignored,
as we already do for other read-only (or missing) registers.
There is no reason to mask the value in env->vr.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/openrisc/sys_helper.c

diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 1053409..d20f48b 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -39,10 +39,6 @@
     int idx;
 
     switch (spr) {
-    case TO_SPR(0, 0): /* VR */
-        env->vr = rb;
-        break;
-
     case TO_SPR(0, 11): /* EVBAR */
         env->evbar = rb;
         break;
@@ -62,10 +58,6 @@
         cpu_set_sr(env, rb);
         break;
 
-    case TO_SPR(0, 18): /* PPC */
-        env->ppc = rb;
-        break;
-
     case TO_SPR(0, 32): /* EPCR */
         env->epcr = rb;
         break;
@@ -204,7 +196,7 @@
 
     switch (spr) {
     case TO_SPR(0, 0): /* VR */
-        return env->vr & SPR_VR;
+        return env->vr;
 
     case TO_SPR(0, 1): /* UPR */
         return env->upr;    /* TT, DM, IM, UP present */