Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions are met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer in the |
| 11 | * documentation and/or other materials provided with the distribution. |
| 12 | * * Neither the name of the Open Source and Linux Lab nor the |
| 13 | * names of its contributors may be used to endorse or promote products |
| 14 | * derived from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
| 20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #ifndef CPU_XTENSA_H |
| 29 | #define CPU_XTENSA_H |
| 30 | |
Paolo Bonzini | d94f0a8 | 2014-03-28 17:48:12 +0100 | [diff] [blame] | 31 | #define ALIGNED_ONLY |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 32 | #define TARGET_LONG_BITS 32 |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 33 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 34 | #define CPUArchState struct CPUXtensaState |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 35 | |
| 36 | #include "config.h" |
| 37 | #include "qemu-common.h" |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 38 | #include "exec/cpu-defs.h" |
Max Filippov | dd519cb | 2012-09-19 04:23:54 +0400 | [diff] [blame] | 39 | #include "fpu/softfloat.h" |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 40 | |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 41 | #define NB_MMU_MODES 4 |
| 42 | |
| 43 | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
| 44 | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
| 45 | #define TARGET_PAGE_BITS 12 |
| 46 | |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 47 | enum { |
| 48 | /* Additional instructions */ |
| 49 | XTENSA_OPTION_CODE_DENSITY, |
| 50 | XTENSA_OPTION_LOOP, |
| 51 | XTENSA_OPTION_EXTENDED_L32R, |
| 52 | XTENSA_OPTION_16_BIT_IMUL, |
| 53 | XTENSA_OPTION_32_BIT_IMUL, |
Max Filippov | 7f65f4b | 2011-10-16 02:56:01 +0400 | [diff] [blame] | 54 | XTENSA_OPTION_32_BIT_IMUL_HIGH, |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 55 | XTENSA_OPTION_32_BIT_IDIV, |
| 56 | XTENSA_OPTION_MAC16, |
Max Filippov | 7f65f4b | 2011-10-16 02:56:01 +0400 | [diff] [blame] | 57 | XTENSA_OPTION_MISC_OP_NSA, |
| 58 | XTENSA_OPTION_MISC_OP_MINMAX, |
| 59 | XTENSA_OPTION_MISC_OP_SEXT, |
| 60 | XTENSA_OPTION_MISC_OP_CLAMPS, |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 61 | XTENSA_OPTION_COPROCESSOR, |
| 62 | XTENSA_OPTION_BOOLEAN, |
| 63 | XTENSA_OPTION_FP_COPROCESSOR, |
| 64 | XTENSA_OPTION_MP_SYNCHRO, |
| 65 | XTENSA_OPTION_CONDITIONAL_STORE, |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 66 | XTENSA_OPTION_ATOMCTL, |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 67 | |
| 68 | /* Interrupts and exceptions */ |
| 69 | XTENSA_OPTION_EXCEPTION, |
| 70 | XTENSA_OPTION_RELOCATABLE_VECTOR, |
| 71 | XTENSA_OPTION_UNALIGNED_EXCEPTION, |
| 72 | XTENSA_OPTION_INTERRUPT, |
| 73 | XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, |
| 74 | XTENSA_OPTION_TIMER_INTERRUPT, |
| 75 | |
| 76 | /* Local memory */ |
| 77 | XTENSA_OPTION_ICACHE, |
| 78 | XTENSA_OPTION_ICACHE_TEST, |
| 79 | XTENSA_OPTION_ICACHE_INDEX_LOCK, |
| 80 | XTENSA_OPTION_DCACHE, |
| 81 | XTENSA_OPTION_DCACHE_TEST, |
| 82 | XTENSA_OPTION_DCACHE_INDEX_LOCK, |
| 83 | XTENSA_OPTION_IRAM, |
| 84 | XTENSA_OPTION_IROM, |
| 85 | XTENSA_OPTION_DRAM, |
| 86 | XTENSA_OPTION_DROM, |
| 87 | XTENSA_OPTION_XLMI, |
| 88 | XTENSA_OPTION_HW_ALIGNMENT, |
| 89 | XTENSA_OPTION_MEMORY_ECC_PARITY, |
| 90 | |
| 91 | /* Memory protection and translation */ |
| 92 | XTENSA_OPTION_REGION_PROTECTION, |
| 93 | XTENSA_OPTION_REGION_TRANSLATION, |
| 94 | XTENSA_OPTION_MMU, |
Max Filippov | 4e41d2f | 2012-12-05 07:15:21 +0400 | [diff] [blame] | 95 | XTENSA_OPTION_CACHEATTR, |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 96 | |
| 97 | /* Other */ |
| 98 | XTENSA_OPTION_WINDOWED_REGISTER, |
| 99 | XTENSA_OPTION_PROCESSOR_INTERFACE, |
| 100 | XTENSA_OPTION_MISC_SR, |
| 101 | XTENSA_OPTION_THREAD_POINTER, |
| 102 | XTENSA_OPTION_PROCESSOR_ID, |
| 103 | XTENSA_OPTION_DEBUG, |
| 104 | XTENSA_OPTION_TRACE_PORT, |
| 105 | }; |
| 106 | |
Max Filippov | 2af3da9 | 2011-09-06 03:55:33 +0400 | [diff] [blame] | 107 | enum { |
| 108 | THREADPTR = 231, |
| 109 | FCR = 232, |
| 110 | FSR = 233, |
| 111 | }; |
| 112 | |
Max Filippov | 3580eca | 2011-09-06 03:55:35 +0400 | [diff] [blame] | 113 | enum { |
Max Filippov | 797d780 | 2011-09-06 03:55:44 +0400 | [diff] [blame] | 114 | LBEG = 0, |
| 115 | LEND = 1, |
| 116 | LCOUNT = 2, |
Max Filippov | 3580eca | 2011-09-06 03:55:35 +0400 | [diff] [blame] | 117 | SAR = 3, |
Max Filippov | 4dd85b6 | 2011-09-06 03:55:54 +0400 | [diff] [blame] | 118 | BR = 4, |
Max Filippov | 6ad6dbf | 2011-09-06 03:55:45 +0400 | [diff] [blame] | 119 | LITBASE = 5, |
Max Filippov | 809377a | 2011-09-06 03:55:36 +0400 | [diff] [blame] | 120 | SCOMPARE1 = 12, |
Max Filippov | 6825b6c | 2011-10-10 06:25:40 +0400 | [diff] [blame] | 121 | ACCLO = 16, |
| 122 | ACCHI = 17, |
| 123 | MR = 32, |
Max Filippov | 553e44f | 2011-09-06 03:55:43 +0400 | [diff] [blame] | 124 | WINDOW_BASE = 72, |
| 125 | WINDOW_START = 73, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 126 | PTEVADDR = 83, |
| 127 | RASID = 90, |
| 128 | ITLBCFG = 91, |
| 129 | DTLBCFG = 92, |
Max Filippov | e61dc8f | 2012-01-13 09:21:32 +0400 | [diff] [blame] | 130 | IBREAKENABLE = 96, |
Max Filippov | 4e41d2f | 2012-12-05 07:15:21 +0400 | [diff] [blame] | 131 | CACHEATTR = 98, |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 132 | ATOMCTL = 99, |
Max Filippov | e61dc8f | 2012-01-13 09:21:32 +0400 | [diff] [blame] | 133 | IBREAKA = 128, |
Max Filippov | f14c4b5 | 2012-01-29 05:28:21 +0400 | [diff] [blame] | 134 | DBREAKA = 144, |
| 135 | DBREAKC = 160, |
Max Filippov | 604e1f9 | 2014-02-15 20:49:09 +0400 | [diff] [blame] | 136 | CONFIGID0 = 176, |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 137 | EPC1 = 177, |
| 138 | DEPC = 192, |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 139 | EPS2 = 194, |
Max Filippov | 604e1f9 | 2014-02-15 20:49:09 +0400 | [diff] [blame] | 140 | CONFIGID1 = 208, |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 141 | EXCSAVE1 = 209, |
Max Filippov | f3df4c0 | 2011-09-06 03:55:50 +0400 | [diff] [blame] | 142 | CPENABLE = 224, |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 143 | INTSET = 226, |
| 144 | INTCLEAR = 227, |
| 145 | INTENABLE = 228, |
Max Filippov | f0a548b | 2011-09-06 03:55:40 +0400 | [diff] [blame] | 146 | PS = 230, |
Max Filippov | 97836ce | 2011-09-06 03:55:51 +0400 | [diff] [blame] | 147 | VECBASE = 231, |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 148 | EXCCAUSE = 232, |
Max Filippov | ab58c5b | 2011-12-14 02:13:40 +0400 | [diff] [blame] | 149 | DEBUGCAUSE = 233, |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 150 | CCOUNT = 234, |
Max Filippov | f3df4c0 | 2011-09-06 03:55:50 +0400 | [diff] [blame] | 151 | PRID = 235, |
Max Filippov | 35b5c04 | 2012-01-15 05:40:50 +0400 | [diff] [blame] | 152 | ICOUNT = 236, |
| 153 | ICOUNTLEVEL = 237, |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 154 | EXCVADDR = 238, |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 155 | CCOMPARE = 240, |
Max Filippov | b7909d8 | 2012-12-05 07:15:24 +0400 | [diff] [blame] | 156 | MISC = 244, |
Max Filippov | 3580eca | 2011-09-06 03:55:35 +0400 | [diff] [blame] | 157 | }; |
| 158 | |
Max Filippov | f0a548b | 2011-09-06 03:55:40 +0400 | [diff] [blame] | 159 | #define PS_INTLEVEL 0xf |
| 160 | #define PS_INTLEVEL_SHIFT 0 |
| 161 | |
| 162 | #define PS_EXCM 0x10 |
| 163 | #define PS_UM 0x20 |
| 164 | |
| 165 | #define PS_RING 0xc0 |
| 166 | #define PS_RING_SHIFT 6 |
| 167 | |
| 168 | #define PS_OWB 0xf00 |
| 169 | #define PS_OWB_SHIFT 8 |
| 170 | |
| 171 | #define PS_CALLINC 0x30000 |
| 172 | #define PS_CALLINC_SHIFT 16 |
| 173 | #define PS_CALLINC_LEN 2 |
| 174 | |
| 175 | #define PS_WOE 0x40000 |
| 176 | |
Max Filippov | ab58c5b | 2011-12-14 02:13:40 +0400 | [diff] [blame] | 177 | #define DEBUGCAUSE_IC 0x1 |
| 178 | #define DEBUGCAUSE_IB 0x2 |
| 179 | #define DEBUGCAUSE_DB 0x4 |
| 180 | #define DEBUGCAUSE_BI 0x8 |
| 181 | #define DEBUGCAUSE_BN 0x10 |
| 182 | #define DEBUGCAUSE_DI 0x20 |
| 183 | #define DEBUGCAUSE_DBNUM 0xf00 |
| 184 | #define DEBUGCAUSE_DBNUM_SHIFT 8 |
| 185 | |
Max Filippov | f14c4b5 | 2012-01-29 05:28:21 +0400 | [diff] [blame] | 186 | #define DBREAKC_SB 0x80000000 |
| 187 | #define DBREAKC_LB 0x40000000 |
| 188 | #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB) |
| 189 | #define DBREAKC_MASK 0x3f |
| 190 | |
Max Filippov | 553e44f | 2011-09-06 03:55:43 +0400 | [diff] [blame] | 191 | #define MAX_NAREG 64 |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 192 | #define MAX_NINTERRUPT 32 |
| 193 | #define MAX_NLEVEL 6 |
| 194 | #define MAX_NNMI 1 |
| 195 | #define MAX_NCCOMPARE 3 |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 196 | #define MAX_TLB_WAY_SIZE 8 |
Max Filippov | f14c4b5 | 2012-01-29 05:28:21 +0400 | [diff] [blame] | 197 | #define MAX_NDBREAK 2 |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 198 | |
| 199 | #define REGION_PAGE_MASK 0xe0000000 |
Max Filippov | 553e44f | 2011-09-06 03:55:43 +0400 | [diff] [blame] | 200 | |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 201 | #define PAGE_CACHE_MASK 0x700 |
| 202 | #define PAGE_CACHE_SHIFT 8 |
| 203 | #define PAGE_CACHE_INVALID 0x000 |
| 204 | #define PAGE_CACHE_BYPASS 0x100 |
| 205 | #define PAGE_CACHE_WT 0x200 |
| 206 | #define PAGE_CACHE_WB 0x400 |
| 207 | #define PAGE_CACHE_ISOLATE 0x600 |
| 208 | |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 209 | enum { |
| 210 | /* Static vectors */ |
| 211 | EXC_RESET, |
| 212 | EXC_MEMORY_ERROR, |
| 213 | |
| 214 | /* Dynamic vectors */ |
| 215 | EXC_WINDOW_OVERFLOW4, |
| 216 | EXC_WINDOW_UNDERFLOW4, |
| 217 | EXC_WINDOW_OVERFLOW8, |
| 218 | EXC_WINDOW_UNDERFLOW8, |
| 219 | EXC_WINDOW_OVERFLOW12, |
| 220 | EXC_WINDOW_UNDERFLOW12, |
| 221 | EXC_IRQ, |
| 222 | EXC_KERNEL, |
| 223 | EXC_USER, |
| 224 | EXC_DOUBLE, |
Max Filippov | e61dc8f | 2012-01-13 09:21:32 +0400 | [diff] [blame] | 225 | EXC_DEBUG, |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 226 | EXC_MAX |
| 227 | }; |
| 228 | |
| 229 | enum { |
| 230 | ILLEGAL_INSTRUCTION_CAUSE = 0, |
| 231 | SYSCALL_CAUSE, |
| 232 | INSTRUCTION_FETCH_ERROR_CAUSE, |
| 233 | LOAD_STORE_ERROR_CAUSE, |
| 234 | LEVEL1_INTERRUPT_CAUSE, |
| 235 | ALLOCA_CAUSE, |
| 236 | INTEGER_DIVIDE_BY_ZERO_CAUSE, |
| 237 | PRIVILEGED_CAUSE = 8, |
| 238 | LOAD_STORE_ALIGNMENT_CAUSE, |
| 239 | |
| 240 | INSTR_PIF_DATA_ERROR_CAUSE = 12, |
| 241 | LOAD_STORE_PIF_DATA_ERROR_CAUSE, |
| 242 | INSTR_PIF_ADDR_ERROR_CAUSE, |
| 243 | LOAD_STORE_PIF_ADDR_ERROR_CAUSE, |
| 244 | |
| 245 | INST_TLB_MISS_CAUSE, |
| 246 | INST_TLB_MULTI_HIT_CAUSE, |
| 247 | INST_FETCH_PRIVILEGE_CAUSE, |
| 248 | INST_FETCH_PROHIBITED_CAUSE = 20, |
| 249 | LOAD_STORE_TLB_MISS_CAUSE = 24, |
| 250 | LOAD_STORE_TLB_MULTI_HIT_CAUSE, |
| 251 | LOAD_STORE_PRIVILEGE_CAUSE, |
| 252 | LOAD_PROHIBITED_CAUSE = 28, |
| 253 | STORE_PROHIBITED_CAUSE, |
| 254 | |
| 255 | COPROCESSOR0_DISABLED = 32, |
| 256 | }; |
| 257 | |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 258 | typedef enum { |
| 259 | INTTYPE_LEVEL, |
| 260 | INTTYPE_EDGE, |
| 261 | INTTYPE_NMI, |
| 262 | INTTYPE_SOFTWARE, |
| 263 | INTTYPE_TIMER, |
| 264 | INTTYPE_DEBUG, |
| 265 | INTTYPE_WRITE_ERR, |
Max Filippov | dec71d2 | 2014-02-15 19:16:33 +0400 | [diff] [blame] | 266 | INTTYPE_PROFILING, |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 267 | INTTYPE_MAX |
| 268 | } interrupt_type; |
| 269 | |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 270 | typedef struct xtensa_tlb_entry { |
| 271 | uint32_t vaddr; |
| 272 | uint32_t paddr; |
| 273 | uint8_t asid; |
| 274 | uint8_t attr; |
| 275 | bool variable; |
| 276 | } xtensa_tlb_entry; |
| 277 | |
| 278 | typedef struct xtensa_tlb { |
| 279 | unsigned nways; |
| 280 | const unsigned way_size[10]; |
| 281 | bool varway56; |
| 282 | unsigned nrefillentries; |
| 283 | } xtensa_tlb; |
| 284 | |
Max Filippov | ccfcaba | 2011-09-06 03:55:52 +0400 | [diff] [blame] | 285 | typedef struct XtensaGdbReg { |
| 286 | int targno; |
| 287 | int type; |
| 288 | int group; |
Max Filippov | ddd4427 | 2015-06-29 10:50:03 +0300 | [diff] [blame] | 289 | unsigned size; |
Max Filippov | ccfcaba | 2011-09-06 03:55:52 +0400 | [diff] [blame] | 290 | } XtensaGdbReg; |
| 291 | |
| 292 | typedef struct XtensaGdbRegmap { |
| 293 | int num_regs; |
| 294 | int num_core_regs; |
| 295 | /* PC + a + ar + sr + ur */ |
| 296 | XtensaGdbReg reg[1 + 16 + 64 + 256 + 256]; |
| 297 | } XtensaGdbRegmap; |
| 298 | |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 299 | typedef struct XtensaConfig { |
| 300 | const char *name; |
| 301 | uint64_t options; |
Max Filippov | ccfcaba | 2011-09-06 03:55:52 +0400 | [diff] [blame] | 302 | XtensaGdbRegmap gdb_regmap; |
Max Filippov | 553e44f | 2011-09-06 03:55:43 +0400 | [diff] [blame] | 303 | unsigned nareg; |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 304 | int excm_level; |
| 305 | int ndepc; |
Max Filippov | 97836ce | 2011-09-06 03:55:51 +0400 | [diff] [blame] | 306 | uint32_t vecbase; |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 307 | uint32_t exception_vector[EXC_MAX]; |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 308 | unsigned ninterrupt; |
| 309 | unsigned nlevel; |
| 310 | uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1]; |
| 311 | uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1]; |
| 312 | uint32_t inttype_mask[INTTYPE_MAX]; |
| 313 | struct { |
| 314 | uint32_t level; |
| 315 | interrupt_type inttype; |
| 316 | } interrupt[MAX_NINTERRUPT]; |
| 317 | unsigned nccompare; |
| 318 | uint32_t timerint[MAX_NCCOMPARE]; |
Max Filippov | b8929a5 | 2011-10-16 02:56:03 +0400 | [diff] [blame] | 319 | unsigned nextint; |
| 320 | unsigned extint[MAX_NINTERRUPT]; |
Max Filippov | ab58c5b | 2011-12-14 02:13:40 +0400 | [diff] [blame] | 321 | |
| 322 | unsigned debug_level; |
| 323 | unsigned nibreak; |
| 324 | unsigned ndbreak; |
| 325 | |
Max Filippov | 604e1f9 | 2014-02-15 20:49:09 +0400 | [diff] [blame] | 326 | uint32_t configid[2]; |
| 327 | |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 328 | uint32_t clock_freq_khz; |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 329 | |
| 330 | xtensa_tlb itlb; |
| 331 | xtensa_tlb dtlb; |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 332 | } XtensaConfig; |
| 333 | |
Max Filippov | ac8b7db | 2011-10-16 02:56:04 +0400 | [diff] [blame] | 334 | typedef struct XtensaConfigList { |
| 335 | const XtensaConfig *config; |
| 336 | struct XtensaConfigList *next; |
| 337 | } XtensaConfigList; |
| 338 | |
Max Filippov | ddd4427 | 2015-06-29 10:50:03 +0300 | [diff] [blame] | 339 | #ifdef HOST_WORDS_BIGENDIAN |
| 340 | enum { |
| 341 | FP_F32_HIGH, |
| 342 | FP_F32_LOW, |
| 343 | }; |
| 344 | #else |
| 345 | enum { |
| 346 | FP_F32_LOW, |
| 347 | FP_F32_HIGH, |
| 348 | }; |
| 349 | #endif |
| 350 | |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 351 | typedef struct CPUXtensaState { |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 352 | const XtensaConfig *config; |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 353 | uint32_t regs[16]; |
| 354 | uint32_t pc; |
| 355 | uint32_t sregs[256]; |
Max Filippov | 2af3da9 | 2011-09-06 03:55:33 +0400 | [diff] [blame] | 356 | uint32_t uregs[256]; |
Max Filippov | 553e44f | 2011-09-06 03:55:43 +0400 | [diff] [blame] | 357 | uint32_t phys_regs[MAX_NAREG]; |
Max Filippov | ddd4427 | 2015-06-29 10:50:03 +0300 | [diff] [blame] | 358 | union { |
| 359 | float32 f32[2]; |
| 360 | float64 f64; |
| 361 | } fregs[16]; |
Max Filippov | dd519cb | 2012-09-19 04:23:54 +0400 | [diff] [blame] | 362 | float_status fp_status; |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 363 | |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 364 | xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; |
| 365 | xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; |
| 366 | unsigned autorefill_idx; |
| 367 | |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 368 | int pending_irq_level; /* level of last raised IRQ */ |
| 369 | void **irq_inputs; |
| 370 | QEMUTimer *ccompare_timer; |
| 371 | uint32_t wake_ccount; |
| 372 | int64_t halt_clock; |
| 373 | |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 374 | int exception_taken; |
| 375 | |
Max Filippov | f14c4b5 | 2012-01-29 05:28:21 +0400 | [diff] [blame] | 376 | /* Watchpoints for DBREAK registers */ |
Andreas Färber | ff4700b | 2013-08-26 18:23:18 +0200 | [diff] [blame] | 377 | struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; |
Max Filippov | f14c4b5 | 2012-01-29 05:28:21 +0400 | [diff] [blame] | 378 | |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 379 | CPU_COMMON |
| 380 | } CPUXtensaState; |
| 381 | |
Andreas Färber | 15be317 | 2012-05-06 12:41:53 +0200 | [diff] [blame] | 382 | #include "cpu-qom.h" |
| 383 | |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 384 | #define cpu_exec cpu_xtensa_exec |
| 385 | #define cpu_gen_code cpu_xtensa_gen_code |
| 386 | #define cpu_signal_handler cpu_xtensa_signal_handler |
| 387 | #define cpu_list xtensa_cpu_list |
| 388 | |
Max Filippov | e38077f | 2012-08-08 14:07:14 +0400 | [diff] [blame] | 389 | #ifdef TARGET_WORDS_BIGENDIAN |
| 390 | #define XTENSA_DEFAULT_CPU_MODEL "fsf" |
| 391 | #else |
| 392 | #define XTENSA_DEFAULT_CPU_MODEL "dc232b" |
| 393 | #endif |
| 394 | |
Andreas Färber | 15be317 | 2012-05-06 12:41:53 +0200 | [diff] [blame] | 395 | XtensaCPU *cpu_xtensa_init(const char *cpu_model); |
| 396 | |
Eduardo Habkost | 2994fd9 | 2015-02-26 17:37:49 -0300 | [diff] [blame] | 397 | #define cpu_init(cpu_model) CPU(cpu_xtensa_init(cpu_model)) |
Andreas Färber | 15be317 | 2012-05-06 12:41:53 +0200 | [diff] [blame] | 398 | |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 399 | void xtensa_translate_init(void); |
Peter Maydell | 86025ee | 2014-09-12 14:06:48 +0100 | [diff] [blame] | 400 | void xtensa_breakpoint_handler(CPUState *cs); |
Peter Crosthwaite | ea3e984 | 2015-06-18 10:24:55 -0700 | [diff] [blame] | 401 | int cpu_xtensa_exec(CPUState *cpu); |
Max Filippov | 1479073 | 2015-07-01 13:00:29 +0300 | [diff] [blame] | 402 | void xtensa_finalize_config(XtensaConfig *config); |
Max Filippov | ac8b7db | 2011-10-16 02:56:04 +0400 | [diff] [blame] | 403 | void xtensa_register_core(XtensaConfigList *node); |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 404 | void check_interrupts(CPUXtensaState *s); |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 405 | void xtensa_irq_init(CPUXtensaState *env); |
| 406 | void *xtensa_get_extint(CPUXtensaState *env, unsigned extint); |
| 407 | void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d); |
| 408 | void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active); |
| 409 | void xtensa_rearm_ccompare_timer(CPUXtensaState *env); |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 410 | int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); |
| 411 | void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf); |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 412 | void xtensa_sync_window_from_phys(CPUXtensaState *env); |
| 413 | void xtensa_sync_phys_from_window(CPUXtensaState *env); |
| 414 | uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way); |
| 415 | void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 416 | uint32_t *vpn, uint32_t wi, uint32_t *ei); |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 417 | int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 418 | uint32_t *pwi, uint32_t *pei, uint8_t *pring); |
Max Filippov | 16bde77 | 2012-05-27 18:34:51 +0400 | [diff] [blame] | 419 | void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, |
| 420 | xtensa_tlb_entry *entry, bool dtlb, |
| 421 | unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 422 | void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 423 | unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte); |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 424 | int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 425 | uint32_t vaddr, int is_write, int mmu_idx, |
| 426 | uint32_t *paddr, uint32_t *page_size, unsigned *access); |
Andreas Färber | 5087a72 | 2012-04-11 18:24:49 +0200 | [diff] [blame] | 427 | void reset_mmu(CPUXtensaState *env); |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 428 | void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env); |
| 429 | void debug_exception_env(CPUXtensaState *new_env, uint32_t cause); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 430 | |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 431 | |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 432 | #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) |
Max Filippov | fe0bd47 | 2012-12-05 07:15:22 +0400 | [diff] [blame] | 433 | #define XTENSA_OPTION_ALL (~(uint64_t)0) |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 434 | |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 435 | static inline bool xtensa_option_bits_enabled(const XtensaConfig *config, |
| 436 | uint64_t opt) |
| 437 | { |
| 438 | return (config->options & opt) != 0; |
| 439 | } |
| 440 | |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 441 | static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt) |
| 442 | { |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 443 | return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt)); |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 444 | } |
| 445 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 446 | static inline int xtensa_get_cintlevel(const CPUXtensaState *env) |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 447 | { |
| 448 | int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT; |
| 449 | if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) { |
| 450 | level = env->config->excm_level; |
| 451 | } |
| 452 | return level; |
| 453 | } |
| 454 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 455 | static inline int xtensa_get_ring(const CPUXtensaState *env) |
Max Filippov | f0a548b | 2011-09-06 03:55:40 +0400 | [diff] [blame] | 456 | { |
| 457 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { |
| 458 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; |
| 459 | } else { |
| 460 | return 0; |
| 461 | } |
| 462 | } |
| 463 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 464 | static inline int xtensa_get_cring(const CPUXtensaState *env) |
Max Filippov | f0a548b | 2011-09-06 03:55:40 +0400 | [diff] [blame] | 465 | { |
| 466 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) && |
| 467 | (env->sregs[PS] & PS_EXCM) == 0) { |
| 468 | return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT; |
| 469 | } else { |
| 470 | return 0; |
| 471 | } |
| 472 | } |
| 473 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 474 | static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 475 | bool dtlb, unsigned wi, unsigned ei) |
| 476 | { |
| 477 | return dtlb ? |
| 478 | env->dtlb[wi] + ei : |
| 479 | env->itlb[wi] + ei; |
| 480 | } |
| 481 | |
Max Filippov | 1b3e71f | 2014-11-07 21:11:07 +0300 | [diff] [blame] | 482 | static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) |
| 483 | { |
| 484 | return env->sregs[WINDOW_START] | |
| 485 | (env->sregs[WINDOW_START] << env->config->nareg / 4); |
| 486 | } |
| 487 | |
Max Filippov | f0a548b | 2011-09-06 03:55:40 +0400 | [diff] [blame] | 488 | /* MMU modes definitions */ |
| 489 | #define MMU_MODE0_SUFFIX _ring0 |
| 490 | #define MMU_MODE1_SUFFIX _ring1 |
| 491 | #define MMU_MODE2_SUFFIX _ring2 |
| 492 | #define MMU_MODE3_SUFFIX _ring3 |
| 493 | |
Benjamin Herrenschmidt | 97ed5cc | 2015-08-17 17:34:10 +1000 | [diff] [blame] | 494 | static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 495 | { |
Max Filippov | f0a548b | 2011-09-06 03:55:40 +0400 | [diff] [blame] | 496 | return xtensa_get_cring(env); |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 497 | } |
| 498 | |
Max Filippov | f0a548b | 2011-09-06 03:55:40 +0400 | [diff] [blame] | 499 | #define XTENSA_TBFLAG_RING_MASK 0x3 |
| 500 | #define XTENSA_TBFLAG_EXCM 0x4 |
Max Filippov | 6ad6dbf | 2011-09-06 03:55:45 +0400 | [diff] [blame] | 501 | #define XTENSA_TBFLAG_LITBASE 0x8 |
Max Filippov | e61dc8f | 2012-01-13 09:21:32 +0400 | [diff] [blame] | 502 | #define XTENSA_TBFLAG_DEBUG 0x10 |
Max Filippov | 35b5c04 | 2012-01-15 05:40:50 +0400 | [diff] [blame] | 503 | #define XTENSA_TBFLAG_ICOUNT 0x20 |
Max Filippov | ef04a84 | 2012-09-19 04:23:59 +0400 | [diff] [blame] | 504 | #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0 |
| 505 | #define XTENSA_TBFLAG_CPENABLE_SHIFT 6 |
Max Filippov | a00817c | 2013-03-04 07:02:00 +0400 | [diff] [blame] | 506 | #define XTENSA_TBFLAG_EXCEPTION 0x4000 |
Max Filippov | 2db59a7 | 2014-10-30 18:07:47 +0300 | [diff] [blame] | 507 | #define XTENSA_TBFLAG_WINDOW_MASK 0x18000 |
| 508 | #define XTENSA_TBFLAG_WINDOW_SHIFT 15 |
Max Filippov | f0a548b | 2011-09-06 03:55:40 +0400 | [diff] [blame] | 509 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 510 | static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 511 | target_ulong *cs_base, int *flags) |
| 512 | { |
Andreas Färber | 1cf5ccb | 2014-03-09 20:02:29 +0100 | [diff] [blame] | 513 | CPUState *cs = CPU(xtensa_env_get_cpu(env)); |
| 514 | |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 515 | *pc = env->pc; |
| 516 | *cs_base = 0; |
| 517 | *flags = 0; |
Max Filippov | f0a548b | 2011-09-06 03:55:40 +0400 | [diff] [blame] | 518 | *flags |= xtensa_get_ring(env); |
| 519 | if (env->sregs[PS] & PS_EXCM) { |
| 520 | *flags |= XTENSA_TBFLAG_EXCM; |
| 521 | } |
Max Filippov | 6ad6dbf | 2011-09-06 03:55:45 +0400 | [diff] [blame] | 522 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && |
| 523 | (env->sregs[LITBASE] & 1)) { |
| 524 | *flags |= XTENSA_TBFLAG_LITBASE; |
| 525 | } |
Max Filippov | e61dc8f | 2012-01-13 09:21:32 +0400 | [diff] [blame] | 526 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { |
| 527 | if (xtensa_get_cintlevel(env) < env->config->debug_level) { |
| 528 | *flags |= XTENSA_TBFLAG_DEBUG; |
| 529 | } |
Max Filippov | 35b5c04 | 2012-01-15 05:40:50 +0400 | [diff] [blame] | 530 | if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { |
| 531 | *flags |= XTENSA_TBFLAG_ICOUNT; |
| 532 | } |
Max Filippov | e61dc8f | 2012-01-13 09:21:32 +0400 | [diff] [blame] | 533 | } |
Max Filippov | ef04a84 | 2012-09-19 04:23:59 +0400 | [diff] [blame] | 534 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { |
| 535 | *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; |
| 536 | } |
Andreas Färber | 1cf5ccb | 2014-03-09 20:02:29 +0100 | [diff] [blame] | 537 | if (cs->singlestep_enabled && env->exception_taken) { |
Max Filippov | a00817c | 2013-03-04 07:02:00 +0400 | [diff] [blame] | 538 | *flags |= XTENSA_TBFLAG_EXCEPTION; |
| 539 | } |
Max Filippov | 2db59a7 | 2014-10-30 18:07:47 +0300 | [diff] [blame] | 540 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && |
| 541 | (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { |
| 542 | uint32_t windowstart = xtensa_replicate_windowstart(env) >> |
| 543 | (env->sregs[WINDOW_BASE] + 1); |
| 544 | uint32_t w = ctz32(windowstart | 0x8); |
| 545 | |
| 546 | *flags |= w << XTENSA_TBFLAG_WINDOW_SHIFT; |
| 547 | } else { |
| 548 | *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; |
| 549 | } |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 550 | } |
| 551 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 552 | #include "exec/cpu-all.h" |
| 553 | #include "exec/exec-all.h" |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 554 | |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 555 | #endif |