commit | fcc803d119a4c01a9b0ee5bda35fda1eeabffa33 | [log] [tgz] |
---|---|---|
author | Max Filippov <jcmvbkbc@gmail.com> | Wed Dec 05 07:15:20 2012 +0400 |
committer | Blue Swirl <blauwirbel@gmail.com> | Sat Dec 08 18:48:26 2012 +0000 |
tree | bbd6697bd198b45b2322e5b43d3ab5159e093d98 | |
parent | 536b558f5896ebbd635b57fa393e82faaa32ad52 [diff] |
target-xtensa: implement ATOMCTL SR ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory type. See ISA, 4.3.12.4 for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>