blob: 26420aa3cb979d4f6aec466f367b608028e474f0 [file] [log] [blame]
bellard6af0bf92005-07-02 14:58:51 +00001/*
2 * MIPS emulation helpers for qemu.
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard6af0bf92005-07-02 14:58:51 +00004 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
ths2d0e9442007-04-02 15:54:05 +000020#include <stdlib.h>
bellard6af0bf92005-07-02 14:58:51 +000021#include "exec.h"
22
ths05f778c2007-10-27 13:05:54 +000023#include "host-utils.h"
24
ths273af662007-10-29 14:39:49 +000025#ifdef __s390__
26# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
27#else
28# define GETPC() (__builtin_return_address(0))
29#endif
bellard4ad40f32005-12-05 19:59:36 +000030
bellard6af0bf92005-07-02 14:58:51 +000031/*****************************************************************************/
32/* Exceptions processing helpers */
bellard6af0bf92005-07-02 14:58:51 +000033
bellard6af0bf92005-07-02 14:58:51 +000034void do_raise_exception_err (uint32_t exception, int error_code)
35{
36#if 1
37 if (logfile && exception < 0x100)
38 fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
39#endif
40 env->exception_index = exception;
41 env->error_code = error_code;
42 T0 = 0;
43 cpu_loop_exit();
44}
45
bellard6af0bf92005-07-02 14:58:51 +000046void do_raise_exception (uint32_t exception)
47{
48 do_raise_exception_err(exception, 0);
49}
50
bellard4ad40f32005-12-05 19:59:36 +000051void do_restore_state (void *pc_ptr)
52{
53 TranslationBlock *tb;
54 unsigned long pc = (unsigned long) pc_ptr;
55
56 tb = tb_find_pc (pc);
57 cpu_restore_state (tb, env, pc, NULL);
58}
59
thse397ee32007-03-23 00:43:28 +000060void do_raise_exception_direct_err (uint32_t exception, int error_code)
bellard4ad40f32005-12-05 19:59:36 +000061{
62 do_restore_state (GETPC ());
thse397ee32007-03-23 00:43:28 +000063 do_raise_exception_err (exception, error_code);
64}
65
66void do_raise_exception_direct (uint32_t exception)
67{
68 do_raise_exception_direct_err (exception, 0);
bellard4ad40f32005-12-05 19:59:36 +000069}
70
thsd26bc212007-11-08 18:05:37 +000071#if defined(TARGET_MIPS64)
thsc570fd12006-12-21 01:19:56 +000072#if TARGET_LONG_BITS > HOST_LONG_BITS
73/* Those might call libgcc functions. */
74void do_dsll (void)
75{
76 T0 = T0 << T1;
77}
78
79void do_dsll32 (void)
80{
81 T0 = T0 << (T1 + 32);
82}
83
84void do_dsra (void)
85{
86 T0 = (int64_t)T0 >> T1;
87}
88
89void do_dsra32 (void)
90{
91 T0 = (int64_t)T0 >> (T1 + 32);
92}
93
94void do_dsrl (void)
95{
96 T0 = T0 >> T1;
97}
98
99void do_dsrl32 (void)
100{
101 T0 = T0 >> (T1 + 32);
102}
103
104void do_drotr (void)
105{
106 target_ulong tmp;
107
108 if (T1) {
thsc6d6dd72007-11-18 03:36:07 +0000109 tmp = T0 << (0x40 - T1);
110 T0 = (T0 >> T1) | tmp;
ths5a63bcb2007-04-05 23:20:05 +0000111 }
thsc570fd12006-12-21 01:19:56 +0000112}
113
114void do_drotr32 (void)
115{
116 target_ulong tmp;
117
thsc6d6dd72007-11-18 03:36:07 +0000118 tmp = T0 << (0x40 - (32 + T1));
119 T0 = (T0 >> (32 + T1)) | tmp;
thsc570fd12006-12-21 01:19:56 +0000120}
121
122void do_dsllv (void)
123{
124 T0 = T1 << (T0 & 0x3F);
125}
126
127void do_dsrav (void)
128{
129 T0 = (int64_t)T1 >> (T0 & 0x3F);
130}
131
132void do_dsrlv (void)
133{
134 T0 = T1 >> (T0 & 0x3F);
135}
136
137void do_drotrv (void)
138{
139 target_ulong tmp;
140
141 T0 &= 0x3F;
142 if (T0) {
thsc6d6dd72007-11-18 03:36:07 +0000143 tmp = T1 << (0x40 - T0);
144 T0 = (T1 >> T0) | tmp;
thsc570fd12006-12-21 01:19:56 +0000145 } else
thsc6d6dd72007-11-18 03:36:07 +0000146 T0 = T1;
thsc570fd12006-12-21 01:19:56 +0000147}
ths05f778c2007-10-27 13:05:54 +0000148
149void do_dclo (void)
150{
151 T0 = clo64(T0);
152}
153
154void do_dclz (void)
155{
156 T0 = clz64(T0);
157}
158
thsc570fd12006-12-21 01:19:56 +0000159#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
thsd26bc212007-11-08 18:05:37 +0000160#endif /* TARGET_MIPS64 */
thsc570fd12006-12-21 01:19:56 +0000161
bellard6af0bf92005-07-02 14:58:51 +0000162/* 64 bits arithmetic for 32 bits hosts */
thsc570fd12006-12-21 01:19:56 +0000163#if TARGET_LONG_BITS > HOST_LONG_BITS
thsaa343732007-10-09 03:39:58 +0000164static always_inline uint64_t get_HILO (void)
bellard6af0bf92005-07-02 14:58:51 +0000165{
thsd0dc7dc2008-02-12 21:01:26 +0000166 return (env->HI[env->current_tc][0] << 32) | (uint32_t)env->LO[env->current_tc][0];
bellard6af0bf92005-07-02 14:58:51 +0000167}
168
thsaa343732007-10-09 03:39:58 +0000169static always_inline void set_HILO (uint64_t HILO)
bellard6af0bf92005-07-02 14:58:51 +0000170{
thsd0dc7dc2008-02-12 21:01:26 +0000171 env->LO[env->current_tc][0] = (int32_t)HILO;
172 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
bellard6af0bf92005-07-02 14:58:51 +0000173}
174
thse9c71dd2007-12-25 20:46:56 +0000175static always_inline void set_HIT0_LO (uint64_t HILO)
176{
thsd0dc7dc2008-02-12 21:01:26 +0000177 env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
178 T0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
thse9c71dd2007-12-25 20:46:56 +0000179}
180
181static always_inline void set_HI_LOT0 (uint64_t HILO)
182{
thsd0dc7dc2008-02-12 21:01:26 +0000183 T0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
184 env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
thse9c71dd2007-12-25 20:46:56 +0000185}
186
bellard6af0bf92005-07-02 14:58:51 +0000187void do_mult (void)
188{
bellard4ad40f32005-12-05 19:59:36 +0000189 set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
bellard6af0bf92005-07-02 14:58:51 +0000190}
191
192void do_multu (void)
193{
thsc570fd12006-12-21 01:19:56 +0000194 set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
bellard6af0bf92005-07-02 14:58:51 +0000195}
196
197void do_madd (void)
198{
199 int64_t tmp;
200
bellard4ad40f32005-12-05 19:59:36 +0000201 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
bellard6af0bf92005-07-02 14:58:51 +0000202 set_HILO((int64_t)get_HILO() + tmp);
203}
204
205void do_maddu (void)
206{
207 uint64_t tmp;
208
thsc570fd12006-12-21 01:19:56 +0000209 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
bellard6af0bf92005-07-02 14:58:51 +0000210 set_HILO(get_HILO() + tmp);
211}
212
213void do_msub (void)
214{
215 int64_t tmp;
216
bellard4ad40f32005-12-05 19:59:36 +0000217 tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
bellard6af0bf92005-07-02 14:58:51 +0000218 set_HILO((int64_t)get_HILO() - tmp);
219}
220
221void do_msubu (void)
222{
223 uint64_t tmp;
224
thsc570fd12006-12-21 01:19:56 +0000225 tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
bellard6af0bf92005-07-02 14:58:51 +0000226 set_HILO(get_HILO() - tmp);
227}
thse9c71dd2007-12-25 20:46:56 +0000228
229/* Multiplication variants of the vr54xx. */
230void do_muls (void)
231{
232 set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
233}
234
235void do_mulsu (void)
236{
237 set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
238}
239
240void do_macc (void)
241{
242 set_HI_LOT0(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
243}
244
245void do_macchi (void)
246{
247 set_HIT0_LO(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
248}
249
250void do_maccu (void)
251{
252 set_HI_LOT0(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
253}
254
255void do_macchiu (void)
256{
257 set_HIT0_LO(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
258}
259
260void do_msac (void)
261{
262 set_HI_LOT0(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
263}
264
265void do_msachi (void)
266{
267 set_HIT0_LO(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
268}
269
270void do_msacu (void)
271{
272 set_HI_LOT0(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
273}
274
275void do_msachiu (void)
276{
277 set_HIT0_LO(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
278}
279
280void do_mulhi (void)
281{
282 set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
283}
284
285void do_mulhiu (void)
286{
287 set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
288}
289
290void do_mulshi (void)
291{
292 set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
293}
294
295void do_mulshiu (void)
296{
297 set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
298}
299#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
bellard6af0bf92005-07-02 14:58:51 +0000300
ths80c27192007-04-15 21:21:33 +0000301#if HOST_LONG_BITS < 64
302void do_div (void)
303{
304 /* 64bit datatypes because we may see overflow/underflow. */
305 if (T1 != 0) {
thsd0dc7dc2008-02-12 21:01:26 +0000306 env->LO[env->current_tc][0] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
307 env->HI[env->current_tc][0] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
ths80c27192007-04-15 21:21:33 +0000308 }
309}
310#endif
311
thsd26bc212007-11-08 18:05:37 +0000312#if defined(TARGET_MIPS64)
thsc570fd12006-12-21 01:19:56 +0000313void do_ddiv (void)
314{
315 if (T1 != 0) {
ths306ab3e2007-12-25 03:18:19 +0000316 int64_t arg0 = (int64_t)T0;
317 int64_t arg1 = (int64_t)T1;
318 if (arg0 == ((int64_t)-1 << 63) && arg1 == (int64_t)-1) {
thsd0dc7dc2008-02-12 21:01:26 +0000319 env->LO[env->current_tc][0] = arg0;
320 env->HI[env->current_tc][0] = 0;
ths306ab3e2007-12-25 03:18:19 +0000321 } else {
322 lldiv_t res = lldiv(arg0, arg1);
thsd0dc7dc2008-02-12 21:01:26 +0000323 env->LO[env->current_tc][0] = res.quot;
324 env->HI[env->current_tc][0] = res.rem;
ths306ab3e2007-12-25 03:18:19 +0000325 }
thsc570fd12006-12-21 01:19:56 +0000326 }
327}
328
ths12a4b2a2007-05-28 17:36:30 +0000329#if TARGET_LONG_BITS > HOST_LONG_BITS
thsc570fd12006-12-21 01:19:56 +0000330void do_ddivu (void)
331{
332 if (T1 != 0) {
thsd0dc7dc2008-02-12 21:01:26 +0000333 env->LO[env->current_tc][0] = T0 / T1;
334 env->HI[env->current_tc][0] = T0 % T1;
thsc570fd12006-12-21 01:19:56 +0000335 }
336}
337#endif
thsd26bc212007-11-08 18:05:37 +0000338#endif /* TARGET_MIPS64 */
thsc570fd12006-12-21 01:19:56 +0000339
ths5fafdf22007-09-16 21:08:06 +0000340#if defined(CONFIG_USER_ONLY)
ths873eb012006-12-06 17:59:07 +0000341void do_mfc0_random (void)
bellard048f6b42005-11-26 18:47:20 +0000342{
ths873eb012006-12-06 17:59:07 +0000343 cpu_abort(env, "mfc0 random\n");
bellard048f6b42005-11-26 18:47:20 +0000344}
ths873eb012006-12-06 17:59:07 +0000345
346void do_mfc0_count (void)
347{
348 cpu_abort(env, "mfc0 count\n");
349}
350
ths8c0fdd82006-12-06 18:19:33 +0000351void cpu_mips_store_count(CPUState *env, uint32_t value)
bellard048f6b42005-11-26 18:47:20 +0000352{
ths8c0fdd82006-12-06 18:19:33 +0000353 cpu_abort(env, "mtc0 count\n");
354}
355
356void cpu_mips_store_compare(CPUState *env, uint32_t value)
357{
358 cpu_abort(env, "mtc0 compare\n");
359}
360
ths42532182007-09-25 16:53:15 +0000361void cpu_mips_start_count(CPUState *env)
362{
363 cpu_abort(env, "start count\n");
364}
365
366void cpu_mips_stop_count(CPUState *env)
367{
368 cpu_abort(env, "stop count\n");
369}
370
ths4de9b242007-01-24 01:47:51 +0000371void cpu_mips_update_irq(CPUState *env)
372{
373 cpu_abort(env, "mtc0 status / mtc0 cause\n");
374}
375
ths8c0fdd82006-12-06 18:19:33 +0000376void do_mtc0_status_debug(uint32_t old, uint32_t val)
377{
ths7a387ff2006-12-06 20:17:30 +0000378 cpu_abort(env, "mtc0 status debug\n");
ths8c0fdd82006-12-06 18:19:33 +0000379}
380
ths7a387ff2006-12-06 20:17:30 +0000381void do_mtc0_status_irqraise_debug (void)
ths8c0fdd82006-12-06 18:19:33 +0000382{
ths7a387ff2006-12-06 20:17:30 +0000383 cpu_abort(env, "mtc0 status irqraise debug\n");
bellard048f6b42005-11-26 18:47:20 +0000384}
385
ths8c0fdd82006-12-06 18:19:33 +0000386void cpu_mips_tlb_flush (CPUState *env, int flush_global)
387{
388 cpu_abort(env, "mips_tlb_flush\n");
389}
390
bellard048f6b42005-11-26 18:47:20 +0000391#else
392
bellard6af0bf92005-07-02 14:58:51 +0000393/* CP0 helpers */
ths873eb012006-12-06 17:59:07 +0000394void do_mfc0_random (void)
bellard6af0bf92005-07-02 14:58:51 +0000395{
ths5dc4b742006-12-21 13:48:28 +0000396 T0 = (int32_t)cpu_mips_get_random(env);
ths873eb012006-12-06 17:59:07 +0000397}
bellard6af0bf92005-07-02 14:58:51 +0000398
ths873eb012006-12-06 17:59:07 +0000399void do_mfc0_count (void)
400{
ths5dc4b742006-12-21 13:48:28 +0000401 T0 = (int32_t)cpu_mips_get_count(env);
bellard6af0bf92005-07-02 14:58:51 +0000402}
403
ths8c0fdd82006-12-06 18:19:33 +0000404void do_mtc0_status_debug(uint32_t old, uint32_t val)
bellard6af0bf92005-07-02 14:58:51 +0000405{
thsf41c52f2007-04-06 18:46:01 +0000406 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
407 old, old & env->CP0_Cause & CP0Ca_IP_mask,
408 val, val & env->CP0_Cause & CP0Ca_IP_mask,
409 env->CP0_Cause);
ths623a9302007-10-28 19:45:05 +0000410 switch (env->hflags & MIPS_HFLAG_KSU) {
411 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
412 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
413 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
414 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
415 }
ths8c0fdd82006-12-06 18:19:33 +0000416}
bellard6af0bf92005-07-02 14:58:51 +0000417
ths8c0fdd82006-12-06 18:19:33 +0000418void do_mtc0_status_irqraise_debug(void)
419{
420 fprintf(logfile, "Raise pending IRQs\n");
bellard6af0bf92005-07-02 14:58:51 +0000421}
422
bellard6ea83fe2006-06-14 12:56:19 +0000423void fpu_handle_exception(void)
424{
425#ifdef CONFIG_SOFTFLOAT
thsead93602007-09-06 00:18:15 +0000426 int flags = get_float_exception_flags(&env->fpu->fp_status);
bellard6ea83fe2006-06-14 12:56:19 +0000427 unsigned int cpuflags = 0, enable, cause = 0;
428
thsead93602007-09-06 00:18:15 +0000429 enable = GET_FP_ENABLE(env->fpu->fcr31);
bellard6ea83fe2006-06-14 12:56:19 +0000430
ths3b46e622007-09-17 08:09:54 +0000431 /* determine current flags */
bellard6ea83fe2006-06-14 12:56:19 +0000432 if (flags & float_flag_invalid) {
433 cpuflags |= FP_INVALID;
434 cause |= FP_INVALID & enable;
435 }
436 if (flags & float_flag_divbyzero) {
ths3b46e622007-09-17 08:09:54 +0000437 cpuflags |= FP_DIV0;
bellard6ea83fe2006-06-14 12:56:19 +0000438 cause |= FP_DIV0 & enable;
439 }
440 if (flags & float_flag_overflow) {
ths3b46e622007-09-17 08:09:54 +0000441 cpuflags |= FP_OVERFLOW;
bellard6ea83fe2006-06-14 12:56:19 +0000442 cause |= FP_OVERFLOW & enable;
443 }
444 if (flags & float_flag_underflow) {
ths3b46e622007-09-17 08:09:54 +0000445 cpuflags |= FP_UNDERFLOW;
bellard6ea83fe2006-06-14 12:56:19 +0000446 cause |= FP_UNDERFLOW & enable;
447 }
448 if (flags & float_flag_inexact) {
ths5fafdf22007-09-16 21:08:06 +0000449 cpuflags |= FP_INEXACT;
bellard6ea83fe2006-06-14 12:56:19 +0000450 cause |= FP_INEXACT & enable;
451 }
thsead93602007-09-06 00:18:15 +0000452 SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
453 SET_FP_CAUSE(env->fpu->fcr31, cause);
bellard6ea83fe2006-06-14 12:56:19 +0000454#else
thsead93602007-09-06 00:18:15 +0000455 SET_FP_FLAGS(env->fpu->fcr31, 0);
456 SET_FP_CAUSE(env->fpu->fcr31, 0);
bellard6ea83fe2006-06-14 12:56:19 +0000457#endif
458}
bellard6ea83fe2006-06-14 12:56:19 +0000459
bellard6af0bf92005-07-02 14:58:51 +0000460/* TLB management */
ths814b9a42006-12-06 17:42:40 +0000461void cpu_mips_tlb_flush (CPUState *env, int flush_global)
462{
463 /* Flush qemu's TLB and discard all shadowed entries. */
464 tlb_flush (env, flush_global);
thsead93602007-09-06 00:18:15 +0000465 env->tlb->tlb_in_use = env->tlb->nb_tlb;
ths814b9a42006-12-06 17:42:40 +0000466}
467
ths29929e32007-05-13 13:49:44 +0000468static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
ths814b9a42006-12-06 17:42:40 +0000469{
470 /* Discard entries from env->tlb[first] onwards. */
thsead93602007-09-06 00:18:15 +0000471 while (env->tlb->tlb_in_use > first) {
472 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
ths814b9a42006-12-06 17:42:40 +0000473 }
474}
475
ths29929e32007-05-13 13:49:44 +0000476static void r4k_fill_tlb (int idx)
bellard6af0bf92005-07-02 14:58:51 +0000477{
ths29929e32007-05-13 13:49:44 +0000478 r4k_tlb_t *tlb;
bellard6af0bf92005-07-02 14:58:51 +0000479
480 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
thsead93602007-09-06 00:18:15 +0000481 tlb = &env->tlb->mmu.r4k.tlb[idx];
thsf2e9ebe2007-05-13 14:07:26 +0000482 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
thsd26bc212007-11-08 18:05:37 +0000483#if defined(TARGET_MIPS64)
thse034e2c2007-06-23 18:04:12 +0000484 tlb->VPN &= env->SEGMask;
ths100ce982007-05-13 19:22:13 +0000485#endif
pbrook98c1b822006-03-11 16:20:36 +0000486 tlb->ASID = env->CP0_EntryHi & 0xFF;
ths3b1c8be2007-01-22 20:50:42 +0000487 tlb->PageMask = env->CP0_PageMask;
bellard6af0bf92005-07-02 14:58:51 +0000488 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
pbrook98c1b822006-03-11 16:20:36 +0000489 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
490 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
491 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
bellard6af0bf92005-07-02 14:58:51 +0000492 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
pbrook98c1b822006-03-11 16:20:36 +0000493 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
494 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
495 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
bellard6af0bf92005-07-02 14:58:51 +0000496 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
497}
498
ths29929e32007-05-13 13:49:44 +0000499void r4k_do_tlbwi (void)
bellard6af0bf92005-07-02 14:58:51 +0000500{
ths814b9a42006-12-06 17:42:40 +0000501 /* Discard cached TLB entries. We could avoid doing this if the
502 tlbwi is just upgrading access permissions on the current entry;
503 that might be a further win. */
thsead93602007-09-06 00:18:15 +0000504 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
ths814b9a42006-12-06 17:42:40 +0000505
thsead93602007-09-06 00:18:15 +0000506 r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb, 0);
507 r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
bellard6af0bf92005-07-02 14:58:51 +0000508}
509
ths29929e32007-05-13 13:49:44 +0000510void r4k_do_tlbwr (void)
bellard6af0bf92005-07-02 14:58:51 +0000511{
512 int r = cpu_mips_get_random(env);
513
ths29929e32007-05-13 13:49:44 +0000514 r4k_invalidate_tlb(env, r, 1);
515 r4k_fill_tlb(r);
bellard6af0bf92005-07-02 14:58:51 +0000516}
517
ths29929e32007-05-13 13:49:44 +0000518void r4k_do_tlbp (void)
bellard6af0bf92005-07-02 14:58:51 +0000519{
ths29929e32007-05-13 13:49:44 +0000520 r4k_tlb_t *tlb;
thsf2e9ebe2007-05-13 14:07:26 +0000521 target_ulong mask;
bellard6af0bf92005-07-02 14:58:51 +0000522 target_ulong tag;
thsf2e9ebe2007-05-13 14:07:26 +0000523 target_ulong VPN;
bellard6af0bf92005-07-02 14:58:51 +0000524 uint8_t ASID;
525 int i;
526
bellard3d9fb9fe2006-05-22 22:13:29 +0000527 ASID = env->CP0_EntryHi & 0xFF;
thsead93602007-09-06 00:18:15 +0000528 for (i = 0; i < env->tlb->nb_tlb; i++) {
529 tlb = &env->tlb->mmu.r4k.tlb[i];
thsf2e9ebe2007-05-13 14:07:26 +0000530 /* 1k pages are not supported. */
531 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
532 tag = env->CP0_EntryHi & ~mask;
533 VPN = tlb->VPN & ~mask;
bellard6af0bf92005-07-02 14:58:51 +0000534 /* Check ASID, virtual page number & size */
thsf2e9ebe2007-05-13 14:07:26 +0000535 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
bellard6af0bf92005-07-02 14:58:51 +0000536 /* TLB match */
ths9c2149c2007-01-23 22:45:22 +0000537 env->CP0_Index = i;
bellard6af0bf92005-07-02 14:58:51 +0000538 break;
539 }
540 }
thsead93602007-09-06 00:18:15 +0000541 if (i == env->tlb->nb_tlb) {
ths814b9a42006-12-06 17:42:40 +0000542 /* No match. Discard any shadow entries, if any of them match. */
thsead93602007-09-06 00:18:15 +0000543 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
544 tlb = &env->tlb->mmu.r4k.tlb[i];
thsf2e9ebe2007-05-13 14:07:26 +0000545 /* 1k pages are not supported. */
546 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
547 tag = env->CP0_EntryHi & ~mask;
548 VPN = tlb->VPN & ~mask;
ths814b9a42006-12-06 17:42:40 +0000549 /* Check ASID, virtual page number & size */
thsf2e9ebe2007-05-13 14:07:26 +0000550 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
ths29929e32007-05-13 13:49:44 +0000551 r4k_mips_tlb_flush_extra (env, i);
ths814b9a42006-12-06 17:42:40 +0000552 break;
553 }
554 }
555
ths9c2149c2007-01-23 22:45:22 +0000556 env->CP0_Index |= 0x80000000;
bellard6af0bf92005-07-02 14:58:51 +0000557 }
558}
559
ths29929e32007-05-13 13:49:44 +0000560void r4k_do_tlbr (void)
bellard6af0bf92005-07-02 14:58:51 +0000561{
ths29929e32007-05-13 13:49:44 +0000562 r4k_tlb_t *tlb;
pbrook09c56b82006-03-11 16:39:23 +0000563 uint8_t ASID;
bellard6af0bf92005-07-02 14:58:51 +0000564
pbrook09c56b82006-03-11 16:39:23 +0000565 ASID = env->CP0_EntryHi & 0xFF;
thsead93602007-09-06 00:18:15 +0000566 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
bellard4ad40f32005-12-05 19:59:36 +0000567
568 /* If this will change the current ASID, flush qemu's TLB. */
ths814b9a42006-12-06 17:42:40 +0000569 if (ASID != tlb->ASID)
570 cpu_mips_tlb_flush (env, 1);
571
thsead93602007-09-06 00:18:15 +0000572 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
bellard4ad40f32005-12-05 19:59:36 +0000573
bellard6af0bf92005-07-02 14:58:51 +0000574 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
ths3b1c8be2007-01-22 20:50:42 +0000575 env->CP0_PageMask = tlb->PageMask;
ths7495fd02007-01-01 20:32:08 +0000576 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
577 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
578 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
579 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
bellard6af0bf92005-07-02 14:58:51 +0000580}
bellard6af0bf92005-07-02 14:58:51 +0000581
bellard048f6b42005-11-26 18:47:20 +0000582#endif /* !CONFIG_USER_ONLY */
583
thsc570fd12006-12-21 01:19:56 +0000584void dump_ldst (const unsigned char *func)
bellard6af0bf92005-07-02 14:58:51 +0000585{
586 if (loglevel)
ths3594c772007-02-20 23:37:21 +0000587 fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
bellard6af0bf92005-07-02 14:58:51 +0000588}
589
590void dump_sc (void)
591{
592 if (loglevel) {
ths3594c772007-02-20 23:37:21 +0000593 fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
bellard6af0bf92005-07-02 14:58:51 +0000594 T1, T0, env->CP0_LLAddr);
595 }
596}
597
thsf41c52f2007-04-06 18:46:01 +0000598void debug_pre_eret (void)
bellard6af0bf92005-07-02 14:58:51 +0000599{
thsf41c52f2007-04-06 18:46:01 +0000600 fprintf(logfile, "ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
thsead93602007-09-06 00:18:15 +0000601 env->PC[env->current_tc], env->CP0_EPC);
thsf41c52f2007-04-06 18:46:01 +0000602 if (env->CP0_Status & (1 << CP0St_ERL))
603 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
604 if (env->hflags & MIPS_HFLAG_DM)
605 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
606 fputs("\n", logfile);
607}
608
609void debug_post_eret (void)
610{
ths744e0912007-04-13 22:30:36 +0000611 fprintf(logfile, " => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
thsead93602007-09-06 00:18:15 +0000612 env->PC[env->current_tc], env->CP0_EPC);
thsf41c52f2007-04-06 18:46:01 +0000613 if (env->CP0_Status & (1 << CP0St_ERL))
614 fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
615 if (env->hflags & MIPS_HFLAG_DM)
616 fprintf(logfile, " DEPC " TARGET_FMT_lx, env->CP0_DEPC);
ths623a9302007-10-28 19:45:05 +0000617 switch (env->hflags & MIPS_HFLAG_KSU) {
618 case MIPS_HFLAG_UM: fputs(", UM\n", logfile); break;
619 case MIPS_HFLAG_SM: fputs(", SM\n", logfile); break;
620 case MIPS_HFLAG_KM: fputs("\n", logfile); break;
621 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
622 }
bellard6af0bf92005-07-02 14:58:51 +0000623}
624
bellard6af0bf92005-07-02 14:58:51 +0000625void do_pmon (int function)
626{
627 function /= 2;
628 switch (function) {
629 case 2: /* TODO: char inbyte(int waitflag); */
thsd0dc7dc2008-02-12 21:01:26 +0000630 if (env->gpr[env->current_tc][4] == 0)
631 env->gpr[env->current_tc][2] = -1;
bellard6af0bf92005-07-02 14:58:51 +0000632 /* Fall through */
633 case 11: /* TODO: char inbyte (void); */
thsd0dc7dc2008-02-12 21:01:26 +0000634 env->gpr[env->current_tc][2] = -1;
bellard6af0bf92005-07-02 14:58:51 +0000635 break;
636 case 3:
637 case 12:
thsd0dc7dc2008-02-12 21:01:26 +0000638 printf("%c", (char)(env->gpr[env->current_tc][4] & 0xFF));
bellard6af0bf92005-07-02 14:58:51 +0000639 break;
640 case 17:
641 break;
642 case 158:
643 {
thsd0dc7dc2008-02-12 21:01:26 +0000644 unsigned char *fmt = (void *)(unsigned long)env->gpr[env->current_tc][4];
bellard6af0bf92005-07-02 14:58:51 +0000645 printf("%s", fmt);
646 }
647 break;
648 }
649}
bellarde37e8632005-07-04 22:17:33 +0000650
ths5fafdf22007-09-16 21:08:06 +0000651#if !defined(CONFIG_USER_ONLY)
bellarde37e8632005-07-04 22:17:33 +0000652
bellard4ad40f32005-12-05 19:59:36 +0000653static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
654
bellarde37e8632005-07-04 22:17:33 +0000655#define MMUSUFFIX _mmu
bellard4ad40f32005-12-05 19:59:36 +0000656#define ALIGNED_ONLY
bellarde37e8632005-07-04 22:17:33 +0000657
658#define SHIFT 0
659#include "softmmu_template.h"
660
661#define SHIFT 1
662#include "softmmu_template.h"
663
664#define SHIFT 2
665#include "softmmu_template.h"
666
667#define SHIFT 3
668#include "softmmu_template.h"
669
bellard4ad40f32005-12-05 19:59:36 +0000670static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
671{
672 env->CP0_BadVAddr = addr;
673 do_restore_state (retaddr);
674 do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
675}
676
j_mayer6ebbf392007-10-14 07:07:08 +0000677void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
bellarde37e8632005-07-04 22:17:33 +0000678{
679 TranslationBlock *tb;
680 CPUState *saved_env;
681 unsigned long pc;
682 int ret;
683
684 /* XXX: hack to restore env in all cases, even if not called from
685 generated code */
686 saved_env = env;
687 env = cpu_single_env;
j_mayer6ebbf392007-10-14 07:07:08 +0000688 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
bellarde37e8632005-07-04 22:17:33 +0000689 if (ret) {
690 if (retaddr) {
691 /* now we have a real cpu fault */
692 pc = (unsigned long)retaddr;
693 tb = tb_find_pc(pc);
694 if (tb) {
695 /* the PC is inside the translated code. It means that we have
696 a virtual CPU fault */
697 cpu_restore_state(tb, env, pc, NULL);
698 }
699 }
700 do_raise_exception_err(env->exception_index, env->error_code);
701 }
702 env = saved_env;
703}
704
ths647de6c2007-10-20 19:45:44 +0000705void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
706 int unused)
707{
708 if (is_exec)
709 do_raise_exception(EXCP_IBE);
710 else
711 do_raise_exception(EXCP_DBE);
712}
bellarde37e8632005-07-04 22:17:33 +0000713#endif
thsfd4a04e2007-05-18 11:55:54 +0000714
715/* Complex FPU operations which may need stack space. */
716
pbrookf090c9d2007-11-18 14:33:24 +0000717#define FLOAT_ONE32 make_float32(0x3f8 << 20)
718#define FLOAT_ONE64 make_float64(0x3ffULL << 52)
719#define FLOAT_TWO32 make_float32(1 << 30)
720#define FLOAT_TWO64 make_float64(1ULL << 62)
ths54454092007-09-29 19:19:59 +0000721#define FLOAT_QNAN32 0x7fbfffff
722#define FLOAT_QNAN64 0x7ff7ffffffffffffULL
723#define FLOAT_SNAN32 0x7fffffff
724#define FLOAT_SNAN64 0x7fffffffffffffffULL
ths8dfdb872007-06-26 20:26:03 +0000725
thsfd4a04e2007-05-18 11:55:54 +0000726/* convert MIPS rounding mode in FCR31 to IEEE library */
727unsigned int ieee_rm[] = {
728 float_round_nearest_even,
729 float_round_to_zero,
730 float_round_up,
731 float_round_down
732};
733
734#define RESTORE_ROUNDING_MODE \
thsead93602007-09-06 00:18:15 +0000735 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
thsfd4a04e2007-05-18 11:55:54 +0000736
thsead93602007-09-06 00:18:15 +0000737void do_cfc1 (int reg)
thsfd4a04e2007-05-18 11:55:54 +0000738{
thsead93602007-09-06 00:18:15 +0000739 switch (reg) {
740 case 0:
741 T0 = (int32_t)env->fpu->fcr0;
742 break;
743 case 25:
744 T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
745 break;
746 case 26:
747 T0 = env->fpu->fcr31 & 0x0003f07c;
748 break;
749 case 28:
750 T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
751 break;
752 default:
753 T0 = (int32_t)env->fpu->fcr31;
754 break;
755 }
756}
757
758void do_ctc1 (int reg)
759{
760 switch(reg) {
thsfd4a04e2007-05-18 11:55:54 +0000761 case 25:
762 if (T0 & 0xffffff00)
763 return;
thsead93602007-09-06 00:18:15 +0000764 env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
thsfd4a04e2007-05-18 11:55:54 +0000765 ((T0 & 0x1) << 23);
766 break;
767 case 26:
768 if (T0 & 0x007c0000)
769 return;
thsead93602007-09-06 00:18:15 +0000770 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
thsfd4a04e2007-05-18 11:55:54 +0000771 break;
772 case 28:
773 if (T0 & 0x007c0000)
774 return;
thsead93602007-09-06 00:18:15 +0000775 env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
thsfd4a04e2007-05-18 11:55:54 +0000776 ((T0 & 0x4) << 22);
777 break;
778 case 31:
779 if (T0 & 0x007c0000)
780 return;
thsead93602007-09-06 00:18:15 +0000781 env->fpu->fcr31 = T0;
thsfd4a04e2007-05-18 11:55:54 +0000782 break;
783 default:
784 return;
785 }
786 /* set rounding mode */
787 RESTORE_ROUNDING_MODE;
thsead93602007-09-06 00:18:15 +0000788 set_float_exception_flags(0, &env->fpu->fp_status);
789 if ((GET_FP_ENABLE(env->fpu->fcr31) | 0x20) & GET_FP_CAUSE(env->fpu->fcr31))
thsfd4a04e2007-05-18 11:55:54 +0000790 do_raise_exception(EXCP_FPE);
791}
792
thsaa343732007-10-09 03:39:58 +0000793static always_inline char ieee_ex_to_mips(char xcpt)
thsfd4a04e2007-05-18 11:55:54 +0000794{
795 return (xcpt & float_flag_inexact) >> 5 |
796 (xcpt & float_flag_underflow) >> 3 |
797 (xcpt & float_flag_overflow) >> 1 |
798 (xcpt & float_flag_divbyzero) << 1 |
799 (xcpt & float_flag_invalid) << 4;
800}
801
thsaa343732007-10-09 03:39:58 +0000802static always_inline char mips_ex_to_ieee(char xcpt)
thsfd4a04e2007-05-18 11:55:54 +0000803{
804 return (xcpt & FP_INEXACT) << 5 |
805 (xcpt & FP_UNDERFLOW) << 3 |
806 (xcpt & FP_OVERFLOW) << 1 |
807 (xcpt & FP_DIV0) >> 1 |
808 (xcpt & FP_INVALID) >> 4;
809}
810
thsaa343732007-10-09 03:39:58 +0000811static always_inline void update_fcr31(void)
thsfd4a04e2007-05-18 11:55:54 +0000812{
thsead93602007-09-06 00:18:15 +0000813 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->fpu->fp_status));
thsfd4a04e2007-05-18 11:55:54 +0000814
thsead93602007-09-06 00:18:15 +0000815 SET_FP_CAUSE(env->fpu->fcr31, tmp);
816 if (GET_FP_ENABLE(env->fpu->fcr31) & tmp)
thsfd4a04e2007-05-18 11:55:54 +0000817 do_raise_exception(EXCP_FPE);
818 else
thsead93602007-09-06 00:18:15 +0000819 UPDATE_FP_FLAGS(env->fpu->fcr31, tmp);
thsfd4a04e2007-05-18 11:55:54 +0000820}
821
822#define FLOAT_OP(name, p) void do_float_##name##_##p(void)
823
824FLOAT_OP(cvtd, s)
825{
thsead93602007-09-06 00:18:15 +0000826 set_float_exception_flags(0, &env->fpu->fp_status);
827 FDT2 = float32_to_float64(FST0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000828 update_fcr31();
829}
830FLOAT_OP(cvtd, w)
831{
thsead93602007-09-06 00:18:15 +0000832 set_float_exception_flags(0, &env->fpu->fp_status);
833 FDT2 = int32_to_float64(WT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000834 update_fcr31();
835}
836FLOAT_OP(cvtd, l)
837{
thsead93602007-09-06 00:18:15 +0000838 set_float_exception_flags(0, &env->fpu->fp_status);
839 FDT2 = int64_to_float64(DT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000840 update_fcr31();
841}
842FLOAT_OP(cvtl, d)
843{
thsead93602007-09-06 00:18:15 +0000844 set_float_exception_flags(0, &env->fpu->fp_status);
845 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000846 update_fcr31();
thsead93602007-09-06 00:18:15 +0000847 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +0000848 DT2 = FLOAT_SNAN64;
thsfd4a04e2007-05-18 11:55:54 +0000849}
850FLOAT_OP(cvtl, s)
851{
thsead93602007-09-06 00:18:15 +0000852 set_float_exception_flags(0, &env->fpu->fp_status);
853 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000854 update_fcr31();
thsead93602007-09-06 00:18:15 +0000855 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +0000856 DT2 = FLOAT_SNAN64;
thsfd4a04e2007-05-18 11:55:54 +0000857}
858
859FLOAT_OP(cvtps, pw)
860{
thsead93602007-09-06 00:18:15 +0000861 set_float_exception_flags(0, &env->fpu->fp_status);
862 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
863 FSTH2 = int32_to_float32(WTH0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000864 update_fcr31();
865}
866FLOAT_OP(cvtpw, ps)
867{
thsead93602007-09-06 00:18:15 +0000868 set_float_exception_flags(0, &env->fpu->fp_status);
869 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
870 WTH2 = float32_to_int32(FSTH0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000871 update_fcr31();
thsead93602007-09-06 00:18:15 +0000872 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +0000873 WT2 = FLOAT_SNAN32;
thsfd4a04e2007-05-18 11:55:54 +0000874}
875FLOAT_OP(cvts, d)
876{
thsead93602007-09-06 00:18:15 +0000877 set_float_exception_flags(0, &env->fpu->fp_status);
878 FST2 = float64_to_float32(FDT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000879 update_fcr31();
880}
881FLOAT_OP(cvts, w)
882{
thsead93602007-09-06 00:18:15 +0000883 set_float_exception_flags(0, &env->fpu->fp_status);
884 FST2 = int32_to_float32(WT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000885 update_fcr31();
886}
887FLOAT_OP(cvts, l)
888{
thsead93602007-09-06 00:18:15 +0000889 set_float_exception_flags(0, &env->fpu->fp_status);
890 FST2 = int64_to_float32(DT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000891 update_fcr31();
892}
893FLOAT_OP(cvts, pl)
894{
thsead93602007-09-06 00:18:15 +0000895 set_float_exception_flags(0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000896 WT2 = WT0;
897 update_fcr31();
898}
899FLOAT_OP(cvts, pu)
900{
thsead93602007-09-06 00:18:15 +0000901 set_float_exception_flags(0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000902 WT2 = WTH0;
903 update_fcr31();
904}
905FLOAT_OP(cvtw, s)
906{
thsead93602007-09-06 00:18:15 +0000907 set_float_exception_flags(0, &env->fpu->fp_status);
908 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000909 update_fcr31();
thsead93602007-09-06 00:18:15 +0000910 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +0000911 WT2 = FLOAT_SNAN32;
thsfd4a04e2007-05-18 11:55:54 +0000912}
913FLOAT_OP(cvtw, d)
914{
thsead93602007-09-06 00:18:15 +0000915 set_float_exception_flags(0, &env->fpu->fp_status);
916 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000917 update_fcr31();
thsead93602007-09-06 00:18:15 +0000918 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +0000919 WT2 = FLOAT_SNAN32;
thsfd4a04e2007-05-18 11:55:54 +0000920}
921
922FLOAT_OP(roundl, d)
923{
thsead93602007-09-06 00:18:15 +0000924 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
925 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000926 RESTORE_ROUNDING_MODE;
927 update_fcr31();
thsead93602007-09-06 00:18:15 +0000928 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +0000929 DT2 = FLOAT_SNAN64;
thsfd4a04e2007-05-18 11:55:54 +0000930}
931FLOAT_OP(roundl, s)
932{
thsead93602007-09-06 00:18:15 +0000933 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
934 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000935 RESTORE_ROUNDING_MODE;
936 update_fcr31();
thsead93602007-09-06 00:18:15 +0000937 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +0000938 DT2 = FLOAT_SNAN64;
thsfd4a04e2007-05-18 11:55:54 +0000939}
940FLOAT_OP(roundw, d)
941{
thsead93602007-09-06 00:18:15 +0000942 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
943 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000944 RESTORE_ROUNDING_MODE;
945 update_fcr31();
thsead93602007-09-06 00:18:15 +0000946 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +0000947 WT2 = FLOAT_SNAN32;
thsfd4a04e2007-05-18 11:55:54 +0000948}
949FLOAT_OP(roundw, s)
950{
thsead93602007-09-06 00:18:15 +0000951 set_float_rounding_mode(float_round_nearest_even, &env->fpu->fp_status);
952 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000953 RESTORE_ROUNDING_MODE;
954 update_fcr31();
thsead93602007-09-06 00:18:15 +0000955 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +0000956 WT2 = FLOAT_SNAN32;
thsfd4a04e2007-05-18 11:55:54 +0000957}
958
959FLOAT_OP(truncl, d)
960{
thsead93602007-09-06 00:18:15 +0000961 DT2 = float64_to_int64_round_to_zero(FDT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000962 update_fcr31();
thsead93602007-09-06 00:18:15 +0000963 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +0000964 DT2 = FLOAT_SNAN64;
thsfd4a04e2007-05-18 11:55:54 +0000965}
966FLOAT_OP(truncl, s)
967{
thsead93602007-09-06 00:18:15 +0000968 DT2 = float32_to_int64_round_to_zero(FST0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000969 update_fcr31();
thsead93602007-09-06 00:18:15 +0000970 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +0000971 DT2 = FLOAT_SNAN64;
thsfd4a04e2007-05-18 11:55:54 +0000972}
973FLOAT_OP(truncw, d)
974{
thsead93602007-09-06 00:18:15 +0000975 WT2 = float64_to_int32_round_to_zero(FDT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000976 update_fcr31();
thsead93602007-09-06 00:18:15 +0000977 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +0000978 WT2 = FLOAT_SNAN32;
thsfd4a04e2007-05-18 11:55:54 +0000979}
980FLOAT_OP(truncw, s)
981{
thsead93602007-09-06 00:18:15 +0000982 WT2 = float32_to_int32_round_to_zero(FST0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000983 update_fcr31();
thsead93602007-09-06 00:18:15 +0000984 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +0000985 WT2 = FLOAT_SNAN32;
thsfd4a04e2007-05-18 11:55:54 +0000986}
987
988FLOAT_OP(ceill, d)
989{
thsead93602007-09-06 00:18:15 +0000990 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
991 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +0000992 RESTORE_ROUNDING_MODE;
993 update_fcr31();
thsead93602007-09-06 00:18:15 +0000994 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +0000995 DT2 = FLOAT_SNAN64;
thsfd4a04e2007-05-18 11:55:54 +0000996}
997FLOAT_OP(ceill, s)
998{
thsead93602007-09-06 00:18:15 +0000999 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
1000 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +00001001 RESTORE_ROUNDING_MODE;
1002 update_fcr31();
thsead93602007-09-06 00:18:15 +00001003 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +00001004 DT2 = FLOAT_SNAN64;
thsfd4a04e2007-05-18 11:55:54 +00001005}
1006FLOAT_OP(ceilw, d)
1007{
thsead93602007-09-06 00:18:15 +00001008 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
1009 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +00001010 RESTORE_ROUNDING_MODE;
1011 update_fcr31();
thsead93602007-09-06 00:18:15 +00001012 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +00001013 WT2 = FLOAT_SNAN32;
thsfd4a04e2007-05-18 11:55:54 +00001014}
1015FLOAT_OP(ceilw, s)
1016{
thsead93602007-09-06 00:18:15 +00001017 set_float_rounding_mode(float_round_up, &env->fpu->fp_status);
1018 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +00001019 RESTORE_ROUNDING_MODE;
1020 update_fcr31();
thsead93602007-09-06 00:18:15 +00001021 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +00001022 WT2 = FLOAT_SNAN32;
thsfd4a04e2007-05-18 11:55:54 +00001023}
1024
1025FLOAT_OP(floorl, d)
1026{
thsead93602007-09-06 00:18:15 +00001027 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1028 DT2 = float64_to_int64(FDT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +00001029 RESTORE_ROUNDING_MODE;
1030 update_fcr31();
thsead93602007-09-06 00:18:15 +00001031 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +00001032 DT2 = FLOAT_SNAN64;
thsfd4a04e2007-05-18 11:55:54 +00001033}
1034FLOAT_OP(floorl, s)
1035{
thsead93602007-09-06 00:18:15 +00001036 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1037 DT2 = float32_to_int64(FST0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +00001038 RESTORE_ROUNDING_MODE;
1039 update_fcr31();
thsead93602007-09-06 00:18:15 +00001040 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +00001041 DT2 = FLOAT_SNAN64;
thsfd4a04e2007-05-18 11:55:54 +00001042}
1043FLOAT_OP(floorw, d)
1044{
thsead93602007-09-06 00:18:15 +00001045 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1046 WT2 = float64_to_int32(FDT0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +00001047 RESTORE_ROUNDING_MODE;
1048 update_fcr31();
thsead93602007-09-06 00:18:15 +00001049 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +00001050 WT2 = FLOAT_SNAN32;
thsfd4a04e2007-05-18 11:55:54 +00001051}
1052FLOAT_OP(floorw, s)
1053{
thsead93602007-09-06 00:18:15 +00001054 set_float_rounding_mode(float_round_down, &env->fpu->fp_status);
1055 WT2 = float32_to_int32(FST0, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +00001056 RESTORE_ROUNDING_MODE;
1057 update_fcr31();
thsead93602007-09-06 00:18:15 +00001058 if (GET_FP_CAUSE(env->fpu->fcr31) & (FP_OVERFLOW | FP_INVALID))
ths54454092007-09-29 19:19:59 +00001059 WT2 = FLOAT_SNAN32;
thsfd4a04e2007-05-18 11:55:54 +00001060}
1061
ths8dfdb872007-06-26 20:26:03 +00001062/* MIPS specific unary operations */
1063FLOAT_OP(recip, d)
1064{
thsead93602007-09-06 00:18:15 +00001065 set_float_exception_flags(0, &env->fpu->fp_status);
1066 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
ths8dfdb872007-06-26 20:26:03 +00001067 update_fcr31();
ths57fa1fb2007-05-19 20:29:41 +00001068}
ths8dfdb872007-06-26 20:26:03 +00001069FLOAT_OP(recip, s)
1070{
thsead93602007-09-06 00:18:15 +00001071 set_float_exception_flags(0, &env->fpu->fp_status);
1072 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
ths8dfdb872007-06-26 20:26:03 +00001073 update_fcr31();
1074}
ths57fa1fb2007-05-19 20:29:41 +00001075
ths8dfdb872007-06-26 20:26:03 +00001076FLOAT_OP(rsqrt, d)
1077{
thsead93602007-09-06 00:18:15 +00001078 set_float_exception_flags(0, &env->fpu->fp_status);
1079 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
1080 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
ths8dfdb872007-06-26 20:26:03 +00001081 update_fcr31();
ths57fa1fb2007-05-19 20:29:41 +00001082}
ths8dfdb872007-06-26 20:26:03 +00001083FLOAT_OP(rsqrt, s)
1084{
thsead93602007-09-06 00:18:15 +00001085 set_float_exception_flags(0, &env->fpu->fp_status);
1086 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1087 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
ths8dfdb872007-06-26 20:26:03 +00001088 update_fcr31();
1089}
1090
1091FLOAT_OP(recip1, d)
1092{
thsead93602007-09-06 00:18:15 +00001093 set_float_exception_flags(0, &env->fpu->fp_status);
1094 FDT2 = float64_div(FLOAT_ONE64, FDT0, &env->fpu->fp_status);
ths8dfdb872007-06-26 20:26:03 +00001095 update_fcr31();
1096}
1097FLOAT_OP(recip1, s)
1098{
thsead93602007-09-06 00:18:15 +00001099 set_float_exception_flags(0, &env->fpu->fp_status);
1100 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
ths8dfdb872007-06-26 20:26:03 +00001101 update_fcr31();
1102}
1103FLOAT_OP(recip1, ps)
1104{
thsead93602007-09-06 00:18:15 +00001105 set_float_exception_flags(0, &env->fpu->fp_status);
1106 FST2 = float32_div(FLOAT_ONE32, FST0, &env->fpu->fp_status);
1107 FSTH2 = float32_div(FLOAT_ONE32, FSTH0, &env->fpu->fp_status);
ths8dfdb872007-06-26 20:26:03 +00001108 update_fcr31();
1109}
1110
1111FLOAT_OP(rsqrt1, d)
1112{
thsead93602007-09-06 00:18:15 +00001113 set_float_exception_flags(0, &env->fpu->fp_status);
1114 FDT2 = float64_sqrt(FDT0, &env->fpu->fp_status);
1115 FDT2 = float64_div(FLOAT_ONE64, FDT2, &env->fpu->fp_status);
ths8dfdb872007-06-26 20:26:03 +00001116 update_fcr31();
1117}
1118FLOAT_OP(rsqrt1, s)
1119{
thsead93602007-09-06 00:18:15 +00001120 set_float_exception_flags(0, &env->fpu->fp_status);
1121 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1122 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
ths8dfdb872007-06-26 20:26:03 +00001123 update_fcr31();
1124}
1125FLOAT_OP(rsqrt1, ps)
1126{
thsead93602007-09-06 00:18:15 +00001127 set_float_exception_flags(0, &env->fpu->fp_status);
1128 FST2 = float32_sqrt(FST0, &env->fpu->fp_status);
1129 FSTH2 = float32_sqrt(FSTH0, &env->fpu->fp_status);
1130 FST2 = float32_div(FLOAT_ONE32, FST2, &env->fpu->fp_status);
1131 FSTH2 = float32_div(FLOAT_ONE32, FSTH2, &env->fpu->fp_status);
ths8dfdb872007-06-26 20:26:03 +00001132 update_fcr31();
1133}
ths57fa1fb2007-05-19 20:29:41 +00001134
thsfd4a04e2007-05-18 11:55:54 +00001135/* binary operations */
1136#define FLOAT_BINOP(name) \
1137FLOAT_OP(name, d) \
1138{ \
thsead93602007-09-06 00:18:15 +00001139 set_float_exception_flags(0, &env->fpu->fp_status); \
1140 FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status); \
1141 update_fcr31(); \
1142 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
pbrook5747c072007-11-17 14:53:06 +00001143 DT2 = FLOAT_QNAN64; \
thsfd4a04e2007-05-18 11:55:54 +00001144} \
1145FLOAT_OP(name, s) \
1146{ \
thsead93602007-09-06 00:18:15 +00001147 set_float_exception_flags(0, &env->fpu->fp_status); \
1148 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1149 update_fcr31(); \
1150 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) \
pbrook5747c072007-11-17 14:53:06 +00001151 WT2 = FLOAT_QNAN32; \
thsfd4a04e2007-05-18 11:55:54 +00001152} \
1153FLOAT_OP(name, ps) \
1154{ \
thsead93602007-09-06 00:18:15 +00001155 set_float_exception_flags(0, &env->fpu->fp_status); \
1156 FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status); \
1157 FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
thsfd4a04e2007-05-18 11:55:54 +00001158 update_fcr31(); \
thsead93602007-09-06 00:18:15 +00001159 if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) { \
pbrook5747c072007-11-17 14:53:06 +00001160 WT2 = FLOAT_QNAN32; \
1161 WTH2 = FLOAT_QNAN32; \
ths3a5b3602007-05-20 13:27:58 +00001162 } \
thsfd4a04e2007-05-18 11:55:54 +00001163}
1164FLOAT_BINOP(add)
1165FLOAT_BINOP(sub)
1166FLOAT_BINOP(mul)
1167FLOAT_BINOP(div)
1168#undef FLOAT_BINOP
1169
ths8dfdb872007-06-26 20:26:03 +00001170/* MIPS specific binary operations */
1171FLOAT_OP(recip2, d)
1172{
thsead93602007-09-06 00:18:15 +00001173 set_float_exception_flags(0, &env->fpu->fp_status);
1174 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
pbrook5747c072007-11-17 14:53:06 +00001175 FDT2 = float64_chs(float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status));
ths8dfdb872007-06-26 20:26:03 +00001176 update_fcr31();
ths57fa1fb2007-05-19 20:29:41 +00001177}
ths8dfdb872007-06-26 20:26:03 +00001178FLOAT_OP(recip2, s)
1179{
thsead93602007-09-06 00:18:15 +00001180 set_float_exception_flags(0, &env->fpu->fp_status);
1181 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
pbrook5747c072007-11-17 14:53:06 +00001182 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
ths8dfdb872007-06-26 20:26:03 +00001183 update_fcr31();
1184}
1185FLOAT_OP(recip2, ps)
1186{
thsead93602007-09-06 00:18:15 +00001187 set_float_exception_flags(0, &env->fpu->fp_status);
1188 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1189 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
pbrook5747c072007-11-17 14:53:06 +00001190 FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
1191 FSTH2 = float32_chs(float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status));
ths8dfdb872007-06-26 20:26:03 +00001192 update_fcr31();
1193}
1194
1195FLOAT_OP(rsqrt2, d)
1196{
thsead93602007-09-06 00:18:15 +00001197 set_float_exception_flags(0, &env->fpu->fp_status);
1198 FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
1199 FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
pbrook5747c072007-11-17 14:53:06 +00001200 FDT2 = float64_chs(float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status));
ths8dfdb872007-06-26 20:26:03 +00001201 update_fcr31();
1202}
1203FLOAT_OP(rsqrt2, s)
1204{
thsead93602007-09-06 00:18:15 +00001205 set_float_exception_flags(0, &env->fpu->fp_status);
1206 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1207 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
pbrook5747c072007-11-17 14:53:06 +00001208 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
ths8dfdb872007-06-26 20:26:03 +00001209 update_fcr31();
1210}
1211FLOAT_OP(rsqrt2, ps)
1212{
thsead93602007-09-06 00:18:15 +00001213 set_float_exception_flags(0, &env->fpu->fp_status);
1214 FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
1215 FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
1216 FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
1217 FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
pbrook5747c072007-11-17 14:53:06 +00001218 FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
1219 FSTH2 = float32_chs(float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status));
ths8dfdb872007-06-26 20:26:03 +00001220 update_fcr31();
1221}
ths57fa1fb2007-05-19 20:29:41 +00001222
thsfd4a04e2007-05-18 11:55:54 +00001223FLOAT_OP(addr, ps)
1224{
thsead93602007-09-06 00:18:15 +00001225 set_float_exception_flags(0, &env->fpu->fp_status);
1226 FST2 = float32_add (FST0, FSTH0, &env->fpu->fp_status);
1227 FSTH2 = float32_add (FST1, FSTH1, &env->fpu->fp_status);
thsfd4a04e2007-05-18 11:55:54 +00001228 update_fcr31();
1229}
1230
ths57fa1fb2007-05-19 20:29:41 +00001231FLOAT_OP(mulr, ps)
1232{
thsead93602007-09-06 00:18:15 +00001233 set_float_exception_flags(0, &env->fpu->fp_status);
1234 FST2 = float32_mul (FST0, FSTH0, &env->fpu->fp_status);
1235 FSTH2 = float32_mul (FST1, FSTH1, &env->fpu->fp_status);
ths57fa1fb2007-05-19 20:29:41 +00001236 update_fcr31();
1237}
1238
ths8dfdb872007-06-26 20:26:03 +00001239/* compare operations */
thsfd4a04e2007-05-18 11:55:54 +00001240#define FOP_COND_D(op, cond) \
1241void do_cmp_d_ ## op (long cc) \
1242{ \
1243 int c = cond; \
1244 update_fcr31(); \
1245 if (c) \
thsead93602007-09-06 00:18:15 +00001246 SET_FP_COND(cc, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001247 else \
thsead93602007-09-06 00:18:15 +00001248 CLEAR_FP_COND(cc, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001249} \
1250void do_cmpabs_d_ ## op (long cc) \
1251{ \
1252 int c; \
ths6b5435d2008-01-08 18:11:08 +00001253 FDT0 = float64_abs(FDT0); \
1254 FDT1 = float64_abs(FDT1); \
thsfd4a04e2007-05-18 11:55:54 +00001255 c = cond; \
1256 update_fcr31(); \
1257 if (c) \
thsead93602007-09-06 00:18:15 +00001258 SET_FP_COND(cc, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001259 else \
thsead93602007-09-06 00:18:15 +00001260 CLEAR_FP_COND(cc, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001261}
1262
1263int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
1264{
1265 if (float64_is_signaling_nan(a) ||
1266 float64_is_signaling_nan(b) ||
1267 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
1268 float_raise(float_flag_invalid, status);
1269 return 1;
1270 } else if (float64_is_nan(a) || float64_is_nan(b)) {
1271 return 1;
1272 } else {
1273 return 0;
1274 }
1275}
1276
1277/* NOTE: the comma operator will make "cond" to eval to false,
1278 * but float*_is_unordered() is still called. */
thsead93602007-09-06 00:18:15 +00001279FOP_COND_D(f, (float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status), 0))
1280FOP_COND_D(un, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status))
1281FOP_COND_D(eq, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1282FOP_COND_D(ueq, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1283FOP_COND_D(olt, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1284FOP_COND_D(ult, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1285FOP_COND_D(ole, !float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1286FOP_COND_D(ule, float64_is_unordered(0, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
thsfd4a04e2007-05-18 11:55:54 +00001287/* NOTE: the comma operator will make "cond" to eval to false,
1288 * but float*_is_unordered() is still called. */
thsead93602007-09-06 00:18:15 +00001289FOP_COND_D(sf, (float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status), 0))
1290FOP_COND_D(ngle,float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status))
1291FOP_COND_D(seq, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1292FOP_COND_D(ngl, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_eq(FDT0, FDT1, &env->fpu->fp_status))
1293FOP_COND_D(lt, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1294FOP_COND_D(nge, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_lt(FDT0, FDT1, &env->fpu->fp_status))
1295FOP_COND_D(le, !float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) && float64_le(FDT0, FDT1, &env->fpu->fp_status))
1296FOP_COND_D(ngt, float64_is_unordered(1, FDT1, FDT0, &env->fpu->fp_status) || float64_le(FDT0, FDT1, &env->fpu->fp_status))
thsfd4a04e2007-05-18 11:55:54 +00001297
1298#define FOP_COND_S(op, cond) \
1299void do_cmp_s_ ## op (long cc) \
1300{ \
1301 int c = cond; \
1302 update_fcr31(); \
1303 if (c) \
thsead93602007-09-06 00:18:15 +00001304 SET_FP_COND(cc, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001305 else \
thsead93602007-09-06 00:18:15 +00001306 CLEAR_FP_COND(cc, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001307} \
1308void do_cmpabs_s_ ## op (long cc) \
1309{ \
1310 int c; \
pbrook5747c072007-11-17 14:53:06 +00001311 FST0 = float32_abs(FST0); \
1312 FST1 = float32_abs(FST1); \
thsfd4a04e2007-05-18 11:55:54 +00001313 c = cond; \
1314 update_fcr31(); \
1315 if (c) \
thsead93602007-09-06 00:18:15 +00001316 SET_FP_COND(cc, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001317 else \
thsead93602007-09-06 00:18:15 +00001318 CLEAR_FP_COND(cc, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001319}
1320
1321flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
1322{
thsfd4a04e2007-05-18 11:55:54 +00001323 if (float32_is_signaling_nan(a) ||
1324 float32_is_signaling_nan(b) ||
1325 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
1326 float_raise(float_flag_invalid, status);
1327 return 1;
1328 } else if (float32_is_nan(a) || float32_is_nan(b)) {
1329 return 1;
1330 } else {
1331 return 0;
1332 }
1333}
1334
1335/* NOTE: the comma operator will make "cond" to eval to false,
1336 * but float*_is_unordered() is still called. */
thsead93602007-09-06 00:18:15 +00001337FOP_COND_S(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0))
1338FOP_COND_S(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status))
1339FOP_COND_S(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1340FOP_COND_S(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1341FOP_COND_S(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1342FOP_COND_S(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1343FOP_COND_S(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1344FOP_COND_S(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
thsfd4a04e2007-05-18 11:55:54 +00001345/* NOTE: the comma operator will make "cond" to eval to false,
1346 * but float*_is_unordered() is still called. */
thsead93602007-09-06 00:18:15 +00001347FOP_COND_S(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0))
1348FOP_COND_S(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status))
1349FOP_COND_S(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status))
1350FOP_COND_S(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status))
1351FOP_COND_S(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status))
1352FOP_COND_S(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status))
1353FOP_COND_S(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status))
1354FOP_COND_S(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status))
thsfd4a04e2007-05-18 11:55:54 +00001355
1356#define FOP_COND_PS(op, condl, condh) \
1357void do_cmp_ps_ ## op (long cc) \
1358{ \
1359 int cl = condl; \
1360 int ch = condh; \
1361 update_fcr31(); \
1362 if (cl) \
thsead93602007-09-06 00:18:15 +00001363 SET_FP_COND(cc, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001364 else \
thsead93602007-09-06 00:18:15 +00001365 CLEAR_FP_COND(cc, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001366 if (ch) \
thsead93602007-09-06 00:18:15 +00001367 SET_FP_COND(cc + 1, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001368 else \
thsead93602007-09-06 00:18:15 +00001369 CLEAR_FP_COND(cc + 1, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001370} \
1371void do_cmpabs_ps_ ## op (long cc) \
1372{ \
1373 int cl, ch; \
pbrook5747c072007-11-17 14:53:06 +00001374 FST0 = float32_abs(FST0); \
1375 FSTH0 = float32_abs(FSTH0); \
1376 FST1 = float32_abs(FST1); \
1377 FSTH1 = float32_abs(FSTH1); \
thsfd4a04e2007-05-18 11:55:54 +00001378 cl = condl; \
1379 ch = condh; \
1380 update_fcr31(); \
1381 if (cl) \
thsead93602007-09-06 00:18:15 +00001382 SET_FP_COND(cc, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001383 else \
thsead93602007-09-06 00:18:15 +00001384 CLEAR_FP_COND(cc, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001385 if (ch) \
thsead93602007-09-06 00:18:15 +00001386 SET_FP_COND(cc + 1, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001387 else \
thsead93602007-09-06 00:18:15 +00001388 CLEAR_FP_COND(cc + 1, env->fpu); \
thsfd4a04e2007-05-18 11:55:54 +00001389}
1390
1391/* NOTE: the comma operator will make "cond" to eval to false,
1392 * but float*_is_unordered() is still called. */
thsead93602007-09-06 00:18:15 +00001393FOP_COND_PS(f, (float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status), 0),
1394 (float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1395FOP_COND_PS(un, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status),
1396 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status))
1397FOP_COND_PS(eq, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1398 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1399FOP_COND_PS(ueq, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1400 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1401FOP_COND_PS(olt, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1402 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1403FOP_COND_PS(ult, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1404 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1405FOP_COND_PS(ole, !float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1406 !float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1407FOP_COND_PS(ule, float32_is_unordered(0, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1408 float32_is_unordered(0, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
thsfd4a04e2007-05-18 11:55:54 +00001409/* NOTE: the comma operator will make "cond" to eval to false,
1410 * but float*_is_unordered() is still called. */
thsead93602007-09-06 00:18:15 +00001411FOP_COND_PS(sf, (float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status), 0),
1412 (float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status), 0))
1413FOP_COND_PS(ngle,float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status),
1414 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status))
1415FOP_COND_PS(seq, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_eq(FST0, FST1, &env->fpu->fp_status),
1416 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1417FOP_COND_PS(ngl, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_eq(FST0, FST1, &env->fpu->fp_status),
1418 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_eq(FSTH0, FSTH1, &env->fpu->fp_status))
1419FOP_COND_PS(lt, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_lt(FST0, FST1, &env->fpu->fp_status),
1420 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1421FOP_COND_PS(nge, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_lt(FST0, FST1, &env->fpu->fp_status),
1422 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_lt(FSTH0, FSTH1, &env->fpu->fp_status))
1423FOP_COND_PS(le, !float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) && float32_le(FST0, FST1, &env->fpu->fp_status),
1424 !float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) && float32_le(FSTH0, FSTH1, &env->fpu->fp_status))
1425FOP_COND_PS(ngt, float32_is_unordered(1, FST1, FST0, &env->fpu->fp_status) || float32_le(FST0, FST1, &env->fpu->fp_status),
1426 float32_is_unordered(1, FSTH1, FSTH0, &env->fpu->fp_status) || float32_le(FSTH0, FSTH1, &env->fpu->fp_status))