Add MIPS32R2 instructions, and generally straighten out the instruction
decoding. This is also the first percent towards MIPS64 support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2224 c046a42c-6fe2-441c-8c8c-71466251a162
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 11e12c0..87a043d 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -153,12 +153,12 @@
void do_mtc0_status_debug(uint32_t old, uint32_t val)
{
- cpu_abort(env, "mtc0 status\n");
+ cpu_abort(env, "mtc0 status debug\n");
}
-void do_mtc0_status_irqraise_debug(void)
+void do_mtc0_status_irqraise_debug (void)
{
- cpu_abort(env, "mtc0 status\n");
+ cpu_abort(env, "mtc0 status irqraise debug\n");
}
void do_tlbwi (void)
