1. 8f972e5 hw/riscv: Use error_fatal for SoC realisation by Alistair Francis · 3 years, 3 months ago
  2. e2b3ef7 hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id by Bin Meng · 3 years, 5 months ago
  3. b8fb878 hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT by Anup Patel · 3 years, 7 months ago
  4. cc63a18 hw/intc: Rename sifive_clint sources to riscv_aclint sources by Anup Patel · 3 years, 7 months ago
  5. f436ecc hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines by Alistair Francis · 3 years, 7 months ago
  6. 7f4c520 arch_init.h: Don't include arch_init.h unnecessarily by Peter Maydell · 3 years, 8 months ago
  7. 3de70ce hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] by Bin Meng · 4 years ago
  8. ee86213 Do not include exec/address-spaces.h if it's not really necessary by Thomas Huth · 4 years ago
  9. 19f4ed3 hw: Do not include qemu/log.h if it is not necessary by Thomas Huth · 4 years ago
  10. 7326128 hw/riscv: Drop 'struct MemmapEntry' by Bin Meng · 4 years, 1 month ago
  11. 38bc4e3 hw/riscv: Load the kernel after the firmware by Alistair Francis · 4 years, 6 months ago
  12. fabbcbd sifive_e: Register "revb" as class property by Eduardo Habkost · 4 years, 6 months ago
  13. 5488f27 sifive_e: Rename memmap enum constants by Eduardo Habkost · 4 years, 7 months ago
  14. b609b7e hw/riscv: Move sifive_uart model to hw/char by Bin Meng · 4 years, 7 months ago
  15. 84fcf3c hw/riscv: Move sifive_plic model to hw/intc by Bin Meng · 4 years, 7 months ago
  16. 406fafd hw/riscv: Move sifive_clint model to hw/intc by Bin Meng · 4 years, 7 months ago
  17. 89ece6f hw/riscv: Move sifive_e_prci model to hw/misc by Bin Meng · 4 years, 7 months ago
  18. a47ef6e hw/riscv: clint: Avoid using hard-coded timebase frequency by Bin Meng · 4 years, 7 months ago
  19. 73f6ed9 target/riscv: cpu: Set reset vector based on the configured property value by Bin Meng · 4 years, 7 months ago
  20. c9270e1 hw/riscv: Allow creating multiple instances of PLIC by Anup Patel · 4 years, 11 months ago
  21. 3bf03f0 hw/riscv: Allow creating multiple instances of CLINT by Anup Patel · 4 years, 11 months ago
  22. e79d27c hw/riscv: sifive_e: Correct debug block size by Bin Meng · 4 years, 9 months ago
  23. 668f62e error: Eliminate error_propagate() with Coccinelle, part 1 by Markus Armbruster · 4 years, 9 months ago
  24. 5325cc3 qom: Put name parameter before value / visitor parameter by Markus Armbruster · 4 years, 9 months ago
  25. 118bfd7 qdev: Use returned bool to check for qdev_realize() etc. failure by Markus Armbruster · 4 years, 9 months ago
  26. 495134b hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 by Bin Meng · 4 years, 10 months ago
  27. 8f8c6c1 hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions by Bin Meng · 4 years, 10 months ago
  28. 5a84206 sifive_e: Support the revB machine by Alistair Francis · 4 years, 11 months ago
  29. ce189ab qdev: Convert bus-less devices to qdev_realize() with Coccinelle by Markus Armbruster · 4 years, 10 months ago
  30. db873cc sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 2 by Markus Armbruster · 4 years, 10 months ago
  31. 9fc7fc4 qom: Less verbose object_initialize_child() by Markus Armbruster · 4 years, 10 months ago
  32. 75a6ed8 riscv: Fix to put "riscv.hart_array" devices on sysbus by Markus Armbruster · 4 years, 10 months ago
  33. 0869490 riscv: sifive_e: Manually define the machine by Alistair Francis · 4 years, 11 months ago
  34. 74dbba9 riscv: sifive_e: Support changing CPU type by Corey Wharton · 5 years ago
  35. 414c47d hw/riscv: Let devices own the MemoryRegion they create by Philippe Mathieu-Daudé · 5 years ago
  36. cc588b2 hw/riscv: Use memory_region_init_rom() with read-only regions by Philippe Mathieu-Daudé · 5 years ago
  37. 5f3616c hw/riscv: Provide rdtime callback for TCG in CLINT emulation by Anup Patel · 5 years ago
  38. 6478dd7 hw/riscv: Add optional symbol callback ptr to riscv_load_kernel() by Zhuang, Siwei (Data61, Kensington NSW) · 5 years ago
  39. 68c9a9b riscv: sifive_e: Drop sifive_mmio_emulate() by Bin Meng · 6 years ago
  40. 56449d2 riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} by Bin Meng · 6 years ago
  41. 46517dd Include sysemu/sysemu.h a lot less by Markus Armbruster · 6 years ago
  42. 650d103 Include hw/hw.h exactly where needed by Markus Armbruster · 6 years ago
  43. c447312 hw/riscv: Replace global smp variables with machine smp properties by Like Xu · 6 years ago
  44. 0ac24d5 hw/riscv: Split out the boot functions by Alistair Francis · 6 years ago
  45. c988de4 RISC-V: Fix a memory leak when realizing a sifive_e by Palmer Dabbelt · 6 years ago
  46. 30efbf3 SiFive RISC-V GPIO Device by Fabien Chouteau · 6 years ago
  47. 40e46e5 riscv: Ensure the kernel start address is correctly cast by Alistair Francis · 6 years ago
  48. 4366e1d elf: Add optional function ptr to load_elf() to parse ELF notes by Liam Merwick · 6 years ago
  49. 194eef0 RISC-V: Enable second UART on sifive_e and sifive_u by Michael Clark · 6 years ago
  50. 371b74e Drop "qemu:" prefix from error_report() arguments by Mao Zhongyi · 7 years ago
  51. 54f3141 sifive_e: Fix crash when introspecting the device by Alistair Francis · 7 years ago
  52. 647a70a hw/riscv/sifive_plic: Use gpios instead of irqs by Alistair Francis · 7 years ago
  53. 651cd8b hw/riscv/sifive_e: Create a SiFive E SoC object by Alistair Francis · 7 years ago
  54. 5aec324 RISC-V: Mark ROM read-only after copying in code by Michael Clark · 7 years ago
  55. 8985480 RISC-V: Remove EM_RISCV ELF_MACHINE indirection by Michael Clark · 7 years ago
  56. 42b3a4b RISC-V: Remove unused class definitions by Michael Clark · 7 years ago
  57. b793898 RISC-V: Remove identity_translate from load_elf by Michael Clark · 7 years ago
  58. 9bca0ed Change references to serial_hds[] to serial_hd() by Peter Maydell · 7 years ago
  59. eb637ed SiFive Freedom E Series RISC-V Machine by Michael Clark · 7 years ago