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qemu / qemu / 23654d45f8ac08e3725831d812eb8dcf74e5a0a0 / target-xtensa / translate.c
  1. 4910e6e target-*: dfilter support for in_asm by Richard Henderson · 9 years ago
  2. 63c9155 cpu: move exec-all.h inclusion out of cpu.h by Paolo Bonzini · 9 years ago
  3. 90aa39a tcg: Allow goto_tb to any target PC in user mode by Sergey Fedorov · 9 years ago
  4. 1bcea73 tcg: Add type for vCPU pointers by Lluís Vilanova · 9 years ago
  5. e1ccc05 tcg: Change tcg_global_mem_new_* to take a TCGv_ptr by Richard Henderson · 11 years ago
  6. 508127e log: do not unnecessarily include qom/cpu.h by Paolo Bonzini · 9 years ago
  7. 09aae23 xtensa: Clean up includes by Peter Maydell · 9 years ago
  8. c30f0d1 xtensa: avoid "naked" qemu_log by Paolo Bonzini · 9 years ago
  9. 522a0d4 target-*: Advance pc after recognizing a breakpoint by Richard Henderson · 9 years ago
  10. 19b7bec target-xtensa: implement S32NB by Max Filippov · 10 years ago
  11. 5eeb40c target-xtensa: implement depbits instruction by Max Filippov · 10 years ago
  12. f822b7e target-xtensa: add window overflow check to L32E/S32E by Max Filippov · 10 years ago
  13. 4e5e121 tcg: Remove gen_intermediate_code_pc by Richard Henderson · 10 years ago
  14. bad729e tcg: Pass data argument to restore_state_to_opc by Richard Henderson · 10 years ago
  15. 190ce7f tcg: Add TCG_MAX_INSNS by Richard Henderson · 10 years ago
  16. b933066 target-*: Introduce and use cpu_breakpoint_test by Richard Henderson · 9 years ago
  17. 959082f target-*: Increment num_insns immediately after tcg_gen_insn_start by Richard Henderson · 9 years ago
  18. 667b8e2 target-*: Unconditionally emit tcg_gen_insn_start by Richard Henderson · 10 years ago
  19. 765b842 tcg: Rename debug_insn_start to insn_start by Richard Henderson · 10 years ago
  20. ecc7b3a tcg: Remove tcg_gen_trunc_i64_i32 by Richard Henderson · 10 years ago
  21. ddd4427 target-xtensa: add 64-bit floating point registers by Max Filippov · 10 years ago
  22. d49190c disas: Remove uses of CPU env by Peter Crosthwaite · 10 years ago
  23. cfe67ce semihosting: create SemihostingConfig structure and semihost.h by Leon Alrae · 10 years ago
  24. 42a268c tcg: Change translator-side labels to a pointer by Richard Henderson · 10 years ago
  25. fe700ad tcg: Introduce tcg_op_buf_count and tcg_op_buf_full by Richard Henderson · 11 years ago
  26. 0a7df5d tcg: Move emit of INDEX_op_end into gen_tb_end by Richard Henderson · 11 years ago
  27. cd42d5b gen-icount: check cflags instead of use_icount global by Paolo Bonzini · 10 years ago
  28. 97e89ee target-xtensa: don't generate dead code by Max Filippov · 10 years ago
  29. 2db59a7 target-xtensa: record available window in TB flags by Max Filippov · 10 years ago
  30. 01673a3 target-xtensa: fix translation for opcodes crossing page boundary by Max Filippov · 10 years ago
  31. a7e30d8 trace: [tcg] Include TCG-tracing header on all targets by Lluís Vilanova · 11 years ago
  32. f08b617 softmmu: introduce cpu_ldst.h by Paolo Bonzini · 11 years ago
  33. 2ef6175 tcg: Invert the inclusion of helper.h by Richard Henderson · 11 years ago
  34. 433d33c target-xtensa: fix cross-page jumps/calls at the end of TB by Max Filippov · 11 years ago
  35. f0c3c50 cpu: Move breakpoints field from CPU_COMMON to CPUState by Andreas Färber · 12 years ago
  36. 604e1f9 target-xtensa: provide HW confg ID registers by Max Filippov · 11 years ago
  37. e848dd4 target-xtensa: add basic checks to icache opcodes by Max Filippov · 11 years ago
  38. 7c84259 target-xtensa: add basic checks to dcache opcodes by Max Filippov · 11 years ago
  39. 6502668 target-xtensa: add RRRI4 opcode format fields by Max Filippov · 11 years ago
  40. ca529f8 target-xtensa: add in_asm logging by Max Filippov · 12 years ago
  41. 5cd8f62 tcg: Move helper registration into tcg_context_init by Richard Henderson · 11 years ago
  42. 8cfd049 tcg: Change tcg_gen_exit_tb argument to uintptr_t by Richard Henderson · 12 years ago
  43. 908c67f target-xtensa: check register window inline by Max Filippov · 12 years ago
  44. 0857a06 target-xtensa: don't generate dead code to access invalid SRs by Max Filippov · 12 years ago
  45. a00817c target-xtensa: avoid double-stopping at breakpoints by Max Filippov · 12 years ago
  46. ed2803d cpu: Move singlestep_enabled field from CPU_COMMON to CPUState by Andreas Färber · 12 years ago
  47. 90b85b7 target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU by Andreas Färber · 12 years ago
  48. ae06d49 target-xtensa: gen_intermediate_code_internal() should be inlined by Andreas Färber · 12 years ago
  49. 878096e cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks by Andreas Färber · 12 years ago
  50. 806f352 gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end by Peter Maydell · 12 years ago
  51. d2123a0 target-xtensa: Use add2/sub2 for mac by Richard Henderson · 12 years ago
  52. c9cda20 target-xtensa: Use mul*2 for mul*hi by Richard Henderson · 12 years ago
  53. 36f25d2 target-xtensa: fix search_pc for the last TB opcode by Max Filippov · 12 years ago
  54. 9c17d61 softmmu: move include files to include/sysemu/ by Paolo Bonzini · 12 years ago
  55. 1de7afc misc: move include files to include/qemu/ by Paolo Bonzini · 12 years ago
  56. 022c62c exec: move include files to include/exec/ by Paolo Bonzini · 12 years ago
  57. 76cad71 build: kill libdis, move disassemblers to disas/ by Paolo Bonzini · 12 years ago
  58. f877d09 target-xtensa: use movcond where possible by Max Filippov · 12 years ago
  59. b7909d8 target-xtensa: implement MISC SR by Max Filippov · 12 years ago
  60. 53593e9 target-xtensa: better control rsr/wsr/xsr access to SRs by Max Filippov · 12 years ago
  61. fe0bd47 target-xtensa: restrict available SRs by enabled options by Max Filippov · 12 years ago
  62. 4e41d2f target-xtensa: implement CACHEATTR SR by Max Filippov · 12 years ago
  63. fcc803d target-xtensa: implement ATOMCTL SR by Max Filippov · 12 years ago
  64. ab1103d TCG: Use gen_opc_instr_start from context instead of global variable. by Evgeny Voevodin · 12 years ago
  65. c9c99c2 TCG: Use gen_opc_icount from context instead of global variable. by Evgeny Voevodin · 12 years ago
  66. 25983ca TCG: Use gen_opc_pc from context instead of global variable. by Evgeny Voevodin · 12 years ago
  67. 92414b3 TCG: Use gen_opc_buf from context instead of global variable. by Evgeny Voevodin · 12 years ago
  68. efd7f48 TCG: Use gen_opc_ptr from context instead of global variable. by Evgeny Voevodin · 12 years ago
  69. 0c4fabe target-xtensa: avoid using cpu_single_env by Blue Swirl · 13 years ago
  70. f783cb2 target-xtensa: de-optimize EXTUI by Aurelien Jarno · 12 years ago
  71. fdefe51 Emit debug_insn for CPU_LOG_TB_OP_OPT as well. by Richard Henderson · 12 years ago
  72. ef04a84 target-xtensa: implement coprocessor context option by Max Filippov · 12 years ago
  73. 4e27386 target-xtensa: implement FP1 group by Max Filippov · 12 years ago
  74. b7ee8c6 target-xtensa: implement FP0 conversions by Max Filippov · 12 years ago
  75. 0b6df83 target-xtensa: implement FP0 arithmetic by Max Filippov · 12 years ago
  76. 9ed7ae1 target-xtensa: implement LSCX and LSCI groups by Max Filippov · 12 years ago
  77. dd519cb target-xtensa: add FP registers by Max Filippov · 12 years ago
  78. c26032b target-xtensa: don't emit extra tcg_gen_goto_tb by Max Filippov · 12 years ago
  79. f9cb504 target-xtensa: fix extui shift amount by Max Filippov · 12 years ago
  80. 7ff7563 target-xtensa: fix big-endian BBS/BBC implementation by Max Filippov · 13 years ago
  81. f492b82 target-xtensa: switch to AREG0-free mode by Max Filippov · 13 years ago
  82. d865f30 target-xtensa: fix CCOUNT for conditional branches by Max Filippov · 13 years ago
  83. b18b37f target-xtensa: fix LOOPNEZ/LOOPGTZ translation by Max Filippov · 13 years ago
  84. 3d0be8a target-xtensa: fix tb invalidation for IBREAK and LOOP by Max Filippov · 13 years ago
  85. 16c1dea target-xtensa: Move helpers.h to helper.h by Lluís Vilanova · 13 years ago
  86. 97129ac target-xtensa: Don't overuse CPUState by Andreas Färber · 13 years ago
  87. f14c4b5 target-xtensa: add DBREAK data breakpoints by Max Filippov · 13 years ago
  88. 35b5c04 target-xtensa: add ICOUNT SR and debug exception by Max Filippov · 13 years ago
  89. e61dc8f target-xtensa: implement instruction breakpoints by Max Filippov · 13 years ago
  90. ab58c5b target-xtensa: add DEBUGCAUSE SR and configuration by Max Filippov · 13 years ago
  91. a044ec2 target-xtensa: fetch 3rd opcode byte only when needed by Max Filippov · 13 years ago
  92. 6b81471 target-xtensa: raise an exception for invalid and reserved opcodes by Max Filippov · 13 years ago
  93. 53a72df target-xtensa: mask out undefined bits of WINDOWSTART SR by Max Filippov · 13 years ago
  94. 7f65f4b target-xtensa: increase xtensa options accuracy by Max Filippov · 13 years ago
  95. 6825b6c target-xtensa: implement MAC16 option by Max Filippov · 13 years ago
  96. 4dd85b6 target-xtensa: implement boolean option by Max Filippov · 14 years ago
  97. b67ea0c target-xtensa: implement memory protection options by Max Filippov · 14 years ago
  98. 97836ce target-xtensa: implement relocatable vectors by Max Filippov · 14 years ago
  99. f3df4c0 target-xtensa: implement CPENABLE and PRID SRs by Max Filippov · 14 years ago
  100. 772177c target-xtensa: implement accurate window check by Max Filippov · 14 years ago