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ths33d68b52007-03-18 00:30:29 +00001/*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
Chetan Pant89975212020-10-16 14:35:09 +000010 * version 2.1 of the License, or (at your option) any later version.
ths33d68b52007-03-18 00:30:29 +000011 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000018 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
ths33d68b52007-03-18 00:30:29 +000019 */
20
ths3953d782007-03-21 11:04:42 +000021/* CPU / CPU family specific config register values. */
22
ths6d355242007-12-25 03:13:56 +000023/* Have config1, uncached coherency */
ths3953d782007-03-21 11:04:42 +000024#define MIPS_CONFIG0 \
Peter Maydellf45cb2f2014-03-17 16:00:34 +000025 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
ths3953d782007-03-21 11:04:42 +000026
thsae5d8052007-07-29 22:11:46 +000027/* Have config2, no coprocessor2 attached, no MDMX support attached,
ths3953d782007-03-21 11:04:42 +000028 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30#define MIPS_CONFIG1 \
Peter Maydellf45cb2f2014-03-17 16:00:34 +000031((1U << CP0C1_M) | \
ths3953d782007-03-21 11:04:42 +000032 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36/* Have config3, no tertiary/secondary caches implemented */
37#define MIPS_CONFIG2 \
Peter Maydellf45cb2f2014-03-17 16:00:34 +000038((1U << CP0C2_M))
ths3953d782007-03-21 11:04:42 +000039
ths6d355242007-12-25 03:13:56 +000040/* No config4, no DSP ASE, no large physaddr (PABITS),
Stefan Weilff2712b2011-04-28 17:20:35 +020041 no external interrupt controller, no vectored interrupts,
thsead93602007-09-06 00:18:15 +000042 no 1kb pages, no SmartMIPS ASE, no trace logic */
ths3953d782007-03-21 11:04:42 +000043#define MIPS_CONFIG3 \
44((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
thsead93602007-09-06 00:18:15 +000046 (0 << CP0C3_SM) | (0 << CP0C3_TL))
ths3953d782007-03-21 11:04:42 +000047
Petar Jovanovicb4160af2014-01-24 13:45:05 +010048#define MIPS_CONFIG4 \
49((0 << CP0C4_M))
50
Petar Jovanovicb4dd99a2014-01-17 19:25:57 +010051#define MIPS_CONFIG5 \
52((0 << CP0C5_M))
53
ths33d68b52007-03-18 00:30:29 +000054/*****************************************************************************/
55/* MIPS CPU definitions */
Igor Mammedov41da2122017-09-20 16:49:33 -030056const mips_def_t mips_defs[] =
ths33d68b52007-03-18 00:30:29 +000057{
ths33d68b52007-03-18 00:30:29 +000058 {
59 .name = "4Kc",
60 .CP0_PRid = 0x00018000,
ths6d355242007-12-25 03:13:56 +000061 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +000062 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +000063 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -080064 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
Stefan Weilab3aee22009-12-15 14:03:03 +010065 (0 << CP0C1_CA),
ths3953d782007-03-21 11:04:42 +000066 .CP0_Config2 = MIPS_CONFIG2,
67 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +010068 .CP0_LLAddr_rw_bitmask = 0,
69 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +000070 .SYNCI_Step = 32,
71 .CCRes = 2,
thsead93602007-09-06 00:18:15 +000072 .CP0_Status_rw_bitmask = 0x1278FF17,
ths6d355242007-12-25 03:13:56 +000073 .SEGBITS = 32,
74 .PABITS = 32,
Philippe Mathieu-Daudé8b0ea9b2020-12-16 23:59:07 +010075 .insn_flags = CPU_MIPS32R1,
ths6d355242007-12-25 03:13:56 +000076 .mmu_type = MMU_TYPE_R4000,
ths33d68b52007-03-18 00:30:29 +000077 },
78 {
ths8d162c22007-11-19 16:10:33 +000079 .name = "4Km",
80 .CP0_PRid = 0x00018300,
81 /* Config1 implemented, fixed mapping MMU,
82 no virtual icache, uncached coherency. */
ths6d355242007-12-25 03:13:56 +000083 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
ths8d162c22007-11-19 16:10:33 +000084 .CP0_Config1 = MIPS_CONFIG1 |
aurel3269585492009-01-14 19:40:36 +000085 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -080086 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
87 (1 << CP0C1_CA),
ths8d162c22007-11-19 16:10:33 +000088 .CP0_Config2 = MIPS_CONFIG2,
89 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +010090 .CP0_LLAddr_rw_bitmask = 0,
91 .CP0_LLAddr_shift = 4,
ths8d162c22007-11-19 16:10:33 +000092 .SYNCI_Step = 32,
93 .CCRes = 2,
94 .CP0_Status_rw_bitmask = 0x1258FF17,
ths6d355242007-12-25 03:13:56 +000095 .SEGBITS = 32,
96 .PABITS = 32,
Philippe Mathieu-Daudé8b0ea9b2020-12-16 23:59:07 +010097 .insn_flags = CPU_MIPS32R1 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +000098 .mmu_type = MMU_TYPE_FMT,
ths8d162c22007-11-19 16:10:33 +000099 },
100 {
ths34ee2ed2007-03-24 23:36:18 +0000101 .name = "4KEcR1",
ths33d68b52007-03-18 00:30:29 +0000102 .CP0_PRid = 0x00018400,
ths6d355242007-12-25 03:13:56 +0000103 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +0000104 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000105 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800106 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
Stefan Weilab3aee22009-12-15 14:03:03 +0100107 (0 << CP0C1_CA),
ths34ee2ed2007-03-24 23:36:18 +0000108 .CP0_Config2 = MIPS_CONFIG2,
109 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100110 .CP0_LLAddr_rw_bitmask = 0,
111 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000112 .SYNCI_Step = 32,
113 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000114 .CP0_Status_rw_bitmask = 0x1278FF17,
ths6d355242007-12-25 03:13:56 +0000115 .SEGBITS = 32,
116 .PABITS = 32,
Philippe Mathieu-Daudé8b0ea9b2020-12-16 23:59:07 +0100117 .insn_flags = CPU_MIPS32R1,
ths6d355242007-12-25 03:13:56 +0000118 .mmu_type = MMU_TYPE_R4000,
ths34ee2ed2007-03-24 23:36:18 +0000119 },
120 {
ths8d162c22007-11-19 16:10:33 +0000121 .name = "4KEmR1",
122 .CP0_PRid = 0x00018500,
ths6d355242007-12-25 03:13:56 +0000123 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
ths8d162c22007-11-19 16:10:33 +0000124 .CP0_Config1 = MIPS_CONFIG1 |
aurel3269585492009-01-14 19:40:36 +0000125 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800126 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
127 (1 << CP0C1_CA),
ths8d162c22007-11-19 16:10:33 +0000128 .CP0_Config2 = MIPS_CONFIG2,
129 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100130 .CP0_LLAddr_rw_bitmask = 0,
131 .CP0_LLAddr_shift = 4,
ths8d162c22007-11-19 16:10:33 +0000132 .SYNCI_Step = 32,
133 .CCRes = 2,
134 .CP0_Status_rw_bitmask = 0x1258FF17,
ths6d355242007-12-25 03:13:56 +0000135 .SEGBITS = 32,
136 .PABITS = 32,
Philippe Mathieu-Daudé8b0ea9b2020-12-16 23:59:07 +0100137 .insn_flags = CPU_MIPS32R1 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +0000138 .mmu_type = MMU_TYPE_FMT,
ths8d162c22007-11-19 16:10:33 +0000139 },
140 {
ths34ee2ed2007-03-24 23:36:18 +0000141 .name = "4KEc",
142 .CP0_PRid = 0x00019000,
ths6d355242007-12-25 03:13:56 +0000143 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
144 (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +0000145 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000146 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800147 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
Stefan Weilab3aee22009-12-15 14:03:03 +0100148 (0 << CP0C1_CA),
ths34ee2ed2007-03-24 23:36:18 +0000149 .CP0_Config2 = MIPS_CONFIG2,
thsead93602007-09-06 00:18:15 +0000150 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100151 .CP0_LLAddr_rw_bitmask = 0,
152 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000153 .SYNCI_Step = 32,
154 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000155 .CP0_Status_rw_bitmask = 0x1278FF17,
ths6d355242007-12-25 03:13:56 +0000156 .SEGBITS = 32,
157 .PABITS = 32,
Stefan Weil73642f52009-12-15 14:43:40 +0100158 .insn_flags = CPU_MIPS32R2,
ths6d355242007-12-25 03:13:56 +0000159 .mmu_type = MMU_TYPE_R4000,
ths34ee2ed2007-03-24 23:36:18 +0000160 },
161 {
ths3e4587d2007-11-14 03:11:17 +0000162 .name = "4KEm",
163 .CP0_PRid = 0x00019100,
ths6d355242007-12-25 03:13:56 +0000164 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
aurel3269585492009-01-14 19:40:36 +0000165 (MMU_TYPE_FMT << CP0C0_MT),
ths3e4587d2007-11-14 03:11:17 +0000166 .CP0_Config1 = MIPS_CONFIG1 |
aurel3269585492009-01-14 19:40:36 +0000167 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800168 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
169 (1 << CP0C1_CA),
ths3e4587d2007-11-14 03:11:17 +0000170 .CP0_Config2 = MIPS_CONFIG2,
171 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100172 .CP0_LLAddr_rw_bitmask = 0,
173 .CP0_LLAddr_shift = 4,
ths3e4587d2007-11-14 03:11:17 +0000174 .SYNCI_Step = 32,
175 .CCRes = 2,
176 .CP0_Status_rw_bitmask = 0x1258FF17,
ths6d355242007-12-25 03:13:56 +0000177 .SEGBITS = 32,
178 .PABITS = 32,
ths3e4587d2007-11-14 03:11:17 +0000179 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +0000180 .mmu_type = MMU_TYPE_FMT,
ths3e4587d2007-11-14 03:11:17 +0000181 },
182 {
ths34ee2ed2007-03-24 23:36:18 +0000183 .name = "24Kc",
184 .CP0_PRid = 0x00019300,
ths6d355242007-12-25 03:13:56 +0000185 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
aurel3269585492009-01-14 19:40:36 +0000186 (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +0000187 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000188 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800189 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
190 (1 << CP0C1_CA),
ths3953d782007-03-21 11:04:42 +0000191 .CP0_Config2 = MIPS_CONFIG2,
thsead93602007-09-06 00:18:15 +0000192 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100193 .CP0_LLAddr_rw_bitmask = 0,
194 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000195 .SYNCI_Step = 32,
196 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000197 /* No DSP implemented. */
ths671880e2007-09-29 19:21:36 +0000198 .CP0_Status_rw_bitmask = 0x1278FF1F,
ths6d355242007-12-25 03:13:56 +0000199 .SEGBITS = 32,
200 .PABITS = 32,
ths3e4587d2007-11-14 03:11:17 +0000201 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +0000202 .mmu_type = MMU_TYPE_R4000,
ths33d68b52007-03-18 00:30:29 +0000203 },
204 {
André Draszike9deaad2016-07-26 00:42:45 +0100205 .name = "24KEc",
206 .CP0_PRid = 0x00019600,
207 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
208 (MMU_TYPE_R4000 << CP0C0_MT),
209 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
210 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
211 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
212 (1 << CP0C1_CA),
213 .CP0_Config2 = MIPS_CONFIG2,
214 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt),
215 .CP0_LLAddr_rw_bitmask = 0,
216 .CP0_LLAddr_shift = 4,
217 .SYNCI_Step = 32,
218 .CCRes = 2,
219 /* we have a DSP, but no FPU */
220 .CP0_Status_rw_bitmask = 0x1378FF1F,
221 .SEGBITS = 32,
222 .PABITS = 32,
223 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP,
224 .mmu_type = MMU_TYPE_R4000,
225 },
226 {
ths33d68b52007-03-18 00:30:29 +0000227 .name = "24Kf",
228 .CP0_PRid = 0x00019300,
ths6d355242007-12-25 03:13:56 +0000229 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
230 (MMU_TYPE_R4000 << CP0C0_MT),
thsae5d8052007-07-29 22:11:46 +0000231 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000232 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800233 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
234 (1 << CP0C1_CA),
ths3953d782007-03-21 11:04:42 +0000235 .CP0_Config2 = MIPS_CONFIG2,
thsead93602007-09-06 00:18:15 +0000236 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100237 .CP0_LLAddr_rw_bitmask = 0,
238 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000239 .SYNCI_Step = 32,
240 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000241 /* No DSP implemented. */
ths671880e2007-09-29 19:21:36 +0000242 .CP0_Status_rw_bitmask = 0x3678FF1F,
ths5a5012e2007-05-07 13:55:33 +0000243 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
Aleksandar Markovic599bc5e2016-06-10 11:57:36 +0200245 .CP1_fcr31 = 0,
246 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
ths6d355242007-12-25 03:13:56 +0000247 .SEGBITS = 32,
248 .PABITS = 32,
ths3e4587d2007-11-14 03:11:17 +0000249 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
ths6d355242007-12-25 03:13:56 +0000250 .mmu_type = MMU_TYPE_R4000,
ths33d68b52007-03-18 00:30:29 +0000251 },
thsead93602007-09-06 00:18:15 +0000252 {
253 .name = "34Kf",
254 .CP0_PRid = 0x00019500,
ths6d355242007-12-25 03:13:56 +0000255 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
aurel3269585492009-01-14 19:40:36 +0000256 (MMU_TYPE_R4000 << CP0C0_MT),
Philippe Mathieu-Daudé68fa5192020-10-16 15:20:37 +0200257 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000258 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
Nathan Froydd19954f2009-12-08 08:06:32 -0800259 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
260 (1 << CP0C1_CA),
thsead93602007-09-06 00:18:15 +0000261 .CP0_Config2 = MIPS_CONFIG2,
Yongbok Kimb9ac5d92013-08-02 10:33:43 +0100262 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
263 (1 << CP0C3_DSPP),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100264 .CP0_LLAddr_rw_bitmask = 0,
265 .CP0_LLAddr_shift = 0,
thsead93602007-09-06 00:18:15 +0000266 .SYNCI_Step = 32,
267 .CCRes = 2,
Yongbok Kimb9ac5d92013-08-02 10:33:43 +0100268 .CP0_Status_rw_bitmask = 0x3778FF1F,
thsead93602007-09-06 00:18:15 +0000269 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
270 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
271 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
272 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
273 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
274 (0xff << CP0TCSt_TASID),
275 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
Aleksandar Markovic599bc5e2016-06-10 11:57:36 +0200277 .CP1_fcr31 = 0,
278 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
thsead93602007-09-06 00:18:15 +0000279 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
280 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
Peter Maydellf45cb2f2014-03-17 16:00:34 +0000281 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
thsead93602007-09-06 00:18:15 +0000282 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
283 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
Peter Maydellf45cb2f2014-03-17 16:00:34 +0000284 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
thsead93602007-09-06 00:18:15 +0000285 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
286 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
Peter Maydellf45cb2f2014-03-17 16:00:34 +0000287 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
thsead93602007-09-06 00:18:15 +0000288 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
289 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
Peter Maydellf45cb2f2014-03-17 16:00:34 +0000290 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
thsead93602007-09-06 00:18:15 +0000291 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
292 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
293 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
294 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
ths6d355242007-12-25 03:13:56 +0000295 .SEGBITS = 32,
296 .PABITS = 32,
ths7385ac02007-10-23 17:04:27 +0000297 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
ths6d355242007-12-25 03:13:56 +0000298 .mmu_type = MMU_TYPE_R4000,
thsead93602007-09-06 00:18:15 +0000299 },
Jia Liuaf13ae02012-10-24 22:17:12 +0800300 {
301 .name = "74Kf",
302 .CP0_PRid = 0x00019700,
303 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
304 (MMU_TYPE_R4000 << CP0C0_MT),
305 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
306 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
307 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
308 (1 << CP0C1_CA),
309 .CP0_Config2 = MIPS_CONFIG2,
Maciej W. Rozyckie30614d2014-11-04 15:41:20 +0000310 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
Maciej W. Rozycki4386f082014-11-04 15:42:19 +0000311 (1 << CP0C3_VInt),
Jia Liuaf13ae02012-10-24 22:17:12 +0800312 .CP0_LLAddr_rw_bitmask = 0,
313 .CP0_LLAddr_shift = 4,
314 .SYNCI_Step = 32,
315 .CCRes = 2,
316 .CP0_Status_rw_bitmask = 0x3778FF1F,
317 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
318 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
Aleksandar Markovic599bc5e2016-06-10 11:57:36 +0200319 .CP1_fcr31 = 0,
320 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
Jia Liuaf13ae02012-10-24 22:17:12 +0800321 .SEGBITS = 32,
322 .PABITS = 32,
Stefan Markovic908f6be2018-10-08 17:20:24 +0200323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
Jia Liuaf13ae02012-10-24 22:17:12 +0800324 .mmu_type = MMU_TYPE_R4000,
325 },
Petar Jovanovice5275262014-01-15 17:01:46 +0100326 {
Maciej W. Rozycki11f5ea12014-11-04 15:39:48 +0000327 .name = "M14K",
328 .CP0_PRid = 0x00019b00,
329 /* Config1 implemented, fixed mapping MMU,
330 no virtual icache, uncached coherency. */
331 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
332 (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
333 .CP0_Config1 = MIPS_CONFIG1,
334 .CP0_Config2 = MIPS_CONFIG2,
335 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
336 .CP0_LLAddr_rw_bitmask = 0,
337 .CP0_LLAddr_shift = 4,
338 .SYNCI_Step = 32,
339 .CCRes = 2,
340 .CP0_Status_rw_bitmask = 0x1258FF17,
341 .SEGBITS = 32,
342 .PABITS = 32,
343 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
344 .mmu_type = MMU_TYPE_FMT,
345 },
346 {
347 .name = "M14Kc",
348 /* This is the TLB-based MMU core. */
349 .CP0_PRid = 0x00019c00,
350 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
351 (MMU_TYPE_R4000 << CP0C0_MT),
352 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
353 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
354 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
355 .CP0_Config2 = MIPS_CONFIG2,
356 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
357 .CP0_LLAddr_rw_bitmask = 0,
358 .CP0_LLAddr_shift = 4,
359 .SYNCI_Step = 32,
360 .CCRes = 2,
361 .CP0_Status_rw_bitmask = 0x1278FF17,
362 .SEGBITS = 32,
363 .PABITS = 32,
364 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
365 .mmu_type = MMU_TYPE_R4000,
366 },
367 {
Yongbok Kimaff2bc62015-07-10 12:10:52 +0100368 /* FIXME:
Andrea Oliveri6db06112020-04-25 20:20:04 +0200369 * Config3: VZ, CTXTC, CDMM, TL
Yongbok Kimaff2bc62015-07-10 12:10:52 +0100370 * Config4: MMUExtDef
James Hogan574da582017-07-18 12:55:58 +0100371 * Config5: MRP
Yongbok Kimaff2bc62015-07-10 12:10:52 +0100372 * */
373 .name = "P5600",
374 .CP0_PRid = 0x0001A800,
375 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
Petar Jovanovice5275262014-01-15 17:01:46 +0100376 (MMU_TYPE_R4000 << CP0C0_MT),
Yongbok Kimaff2bc62015-07-10 12:10:52 +0100377 .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
378 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
379 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
380 (1 << CP0C1_PC) | (1 << CP0C1_FP),
Petar Jovanovice5275262014-01-15 17:01:46 +0100381 .CP0_Config2 = MIPS_CONFIG2,
Andrea Oliveri6db06112020-04-25 20:20:04 +0200382 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
383 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
James Hogan574da582017-07-18 12:55:58 +0100384 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
Andrea Oliveri6db06112020-04-25 20:20:04 +0200385 (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
386 (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
Yongbok Kimaff2bc62015-07-10 12:10:52 +0100387 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
388 (0x1c << CP0C4_KScrExist),
Petar Jovanovicb4160af2014-01-24 13:45:05 +0100389 .CP0_Config4_rw_bitmask = 0,
James Hogan574da582017-07-18 12:55:58 +0100390 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) |
391 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
Yongbok Kimaff2bc62015-07-10 12:10:52 +0100392 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
393 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
394 (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
Petar Jovanovice5275262014-01-15 17:01:46 +0100395 .CP0_LLAddr_rw_bitmask = 0,
Yongbok Kimaff2bc62015-07-10 12:10:52 +0100396 .CP0_LLAddr_shift = 0,
Petar Jovanovice5275262014-01-15 17:01:46 +0100397 .SYNCI_Step = 32,
398 .CCRes = 2,
Yongbok Kimaff2bc62015-07-10 12:10:52 +0100399 .CP0_Status_rw_bitmask = 0x3C68FF1F,
400 .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
401 (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
James Hogan574da582017-07-18 12:55:58 +0100402 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
Leon Alraeba5c79f2016-02-24 10:47:10 +0000403 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) |
404 (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
405 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID),
406 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
Aleksandar Markovic599bc5e2016-06-10 11:57:36 +0200407 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
Petar Jovanovice5275262014-01-15 17:01:46 +0100408 .SEGBITS = 32,
Leon Alrae6773f9b2015-04-14 10:33:43 +0100409 .PABITS = 40,
Philippe Mathieu-Daudé7e2a6192020-11-29 23:32:40 +0100410 .insn_flags = CPU_MIPS32R5,
Petar Jovanovice5275262014-01-15 17:01:46 +0100411 .mmu_type = MMU_TYPE_R4000,
412 },
Yongbok Kim4b3bcd02015-06-25 00:24:27 +0100413 {
414 /* A generic CPU supporting MIPS32 Release 6 ISA.
415 FIXME: Support IEEE 754-2008 FP.
416 Eventually this should be replaced by a real CPU model. */
417 .name = "mips32r6-generic",
418 .CP0_PRid = 0x00010000,
419 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
420 (MMU_TYPE_R4000 << CP0C0_MT),
421 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
422 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
423 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
424 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
425 .CP0_Config2 = MIPS_CONFIG2,
426 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
427 (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
428 (1 << CP0C3_RXI) | (1U << CP0C3_M),
429 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
430 (3 << CP0C4_IE) | (1U << CP0C4_M),
Yongbok Kim35ac9e32015-10-05 14:45:45 +0100431 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
Yongbok Kim4b3bcd02015-06-25 00:24:27 +0100432 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
433 (1 << CP0C5_UFE),
434 .CP0_LLAddr_rw_bitmask = 0,
435 .CP0_LLAddr_shift = 0,
436 .SYNCI_Step = 32,
437 .CCRes = 2,
438 .CP0_Status_rw_bitmask = 0x3058FF1F,
439 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
440 (1U << CP0PG_RIE),
441 .CP0_PageGrain_rw_bitmask = 0,
Leon Alraeba5c79f2016-02-24 10:47:10 +0000442 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
443 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
444 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
445 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
Aleksandar Markovic599bc5e2016-06-10 11:57:36 +0200446 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
Yongbok Kim4b3bcd02015-06-25 00:24:27 +0100447 .SEGBITS = 32,
448 .PABITS = 32,
449 .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
450 .mmu_type = MMU_TYPE_R4000,
451 },
Stefan Markovicd45942d2018-08-02 16:16:47 +0200452 {
453 .name = "I7200",
454 .CP0_PRid = 0x00010000,
455 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) |
456 (MMU_TYPE_R4000 << CP0C0_MT),
457 .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) |
458 (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) |
459 (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) |
460 (1 << CP0C1_EP),
461 .CP0_Config2 = MIPS_CONFIG2,
462 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) |
463 (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) |
464 (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) |
465 (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) |
466 (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
467 (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) |
468 (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL),
469 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
470 (2 << CP0C4_IE) | (1U << CP0C4_M),
471 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
472 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
473 (1 << CP0C5_UFE),
474 .CP0_LLAddr_rw_bitmask = 0,
475 .CP0_LLAddr_shift = 0,
476 .SYNCI_Step = 32,
477 .CCRes = 2,
478 .CP0_Status_rw_bitmask = 0x3158FF1F,
479 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
480 (1U << CP0PG_RIE),
481 .CP0_PageGrain_rw_bitmask = 0,
482 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
483 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
484 (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV),
485 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
486 .SEGBITS = 32,
487 .PABITS = 32,
Philippe Mathieu-Daudéfc630102021-01-10 22:44:59 +0100488 .insn_flags = CPU_MIPS32R6 | ISA_NANOMIPS32 |
489 ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | ASE_MT,
Stefan Markovicd45942d2018-08-02 16:16:47 +0200490 .mmu_type = MMU_TYPE_R4000,
491 },
thsd26bc212007-11-08 18:05:37 +0000492#if defined(TARGET_MIPS64)
ths33d68b52007-03-18 00:30:29 +0000493 {
494 .name = "R4000",
495 .CP0_PRid = 0x00000400,
ths6d355242007-12-25 03:13:56 +0000496 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
Philippe Mathieu-Daudéb4cbbb42020-12-01 12:41:39 +0100497 .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) |
498 (2 << CP0C0_K0),
aurel3269585492009-01-14 19:40:36 +0000499 /* Note: Config1 is only used internally, the R4000 has only Config0. */
ths6d355242007-12-25 03:13:56 +0000500 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100501 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
502 .CP0_LLAddr_shift = 4,
ths2f644542007-04-11 20:34:23 +0000503 .SYNCI_Step = 16,
504 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000505 .CP0_Status_rw_bitmask = 0x3678FFFF,
aurel3269585492009-01-14 19:40:36 +0000506 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
thsc9c1a062007-06-01 14:58:56 +0000507 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
Aleksandar Markovic599bc5e2016-06-10 11:57:36 +0200508 .CP1_fcr31 = 0,
509 .CP1_fcr31_rw_bitmask = 0x0183FFFF,
thse034e2c2007-06-23 18:04:12 +0000510 .SEGBITS = 40,
ths6d355242007-12-25 03:13:56 +0000511 .PABITS = 36,
thse189e742007-09-24 12:48:00 +0000512 .insn_flags = CPU_MIPS3,
ths6d355242007-12-25 03:13:56 +0000513 .mmu_type = MMU_TYPE_R4000,
thsc9c1a062007-06-01 14:58:56 +0000514 },
515 {
thse9c71dd2007-12-25 20:46:56 +0000516 .name = "VR5432",
517 .CP0_PRid = 0x00005400,
518 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
Philippe Mathieu-Daudéb4cbbb42020-12-01 12:41:39 +0100519 .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) |
520 (2 << CP0C0_K0),
thse9c71dd2007-12-25 20:46:56 +0000521 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100522 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
523 .CP0_LLAddr_shift = 4,
thse9c71dd2007-12-25 20:46:56 +0000524 .SYNCI_Step = 16,
525 .CCRes = 2,
526 .CP0_Status_rw_bitmask = 0x3678FFFF,
527 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
528 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
Aleksandar Markovic599bc5e2016-06-10 11:57:36 +0200529 .CP1_fcr31 = 0,
530 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
thse9c71dd2007-12-25 20:46:56 +0000531 .SEGBITS = 40,
532 .PABITS = 32,
Philippe Mathieu-Daudéeaca8572021-01-10 22:46:43 +0100533 .insn_flags = CPU_MIPS4 | INSN_VR54XX,
thse9c71dd2007-12-25 20:46:56 +0000534 .mmu_type = MMU_TYPE_R4000,
535 },
536 {
thsc9c1a062007-06-01 14:58:56 +0000537 .name = "5Kc",
538 .CP0_PRid = 0x00018100,
ths29fe0e32007-12-25 17:32:46 +0000539 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
aurel3269585492009-01-14 19:40:36 +0000540 (MMU_TYPE_R4000 << CP0C0_MT),
thsc9c1a062007-06-01 14:58:56 +0000541 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000542 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
543 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
544 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
thsc9c1a062007-06-01 14:58:56 +0000545 .CP0_Config2 = MIPS_CONFIG2,
546 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100547 .CP0_LLAddr_rw_bitmask = 0,
548 .CP0_LLAddr_shift = 4,
thsc9c1a062007-06-01 14:58:56 +0000549 .SYNCI_Step = 32,
550 .CCRes = 2,
Maciej W. Rozycki196a7952014-12-20 23:00:25 +0000551 .CP0_Status_rw_bitmask = 0x12F8FFFF,
thse034e2c2007-06-23 18:04:12 +0000552 .SEGBITS = 42,
ths6d355242007-12-25 03:13:56 +0000553 .PABITS = 36,
Philippe Mathieu-Daudé8b0ea9b2020-12-16 23:59:07 +0100554 .insn_flags = CPU_MIPS64R1,
ths6d355242007-12-25 03:13:56 +0000555 .mmu_type = MMU_TYPE_R4000,
thsc9c1a062007-06-01 14:58:56 +0000556 },
557 {
558 .name = "5Kf",
559 .CP0_PRid = 0x00018100,
ths29fe0e32007-12-25 17:32:46 +0000560 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
aurel3269585492009-01-14 19:40:36 +0000561 (MMU_TYPE_R4000 << CP0C0_MT),
thsc9c1a062007-06-01 14:58:56 +0000562 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000563 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
564 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
565 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
thsc9c1a062007-06-01 14:58:56 +0000566 .CP0_Config2 = MIPS_CONFIG2,
567 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100568 .CP0_LLAddr_rw_bitmask = 0,
569 .CP0_LLAddr_shift = 4,
thsc9c1a062007-06-01 14:58:56 +0000570 .SYNCI_Step = 32,
571 .CCRes = 2,
thsead93602007-09-06 00:18:15 +0000572 .CP0_Status_rw_bitmask = 0x36F8FFFF,
aurel3269585492009-01-14 19:40:36 +0000573 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
thsc9c1a062007-06-01 14:58:56 +0000574 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
575 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
Aleksandar Markovic599bc5e2016-06-10 11:57:36 +0200576 .CP1_fcr31 = 0,
577 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
thse034e2c2007-06-23 18:04:12 +0000578 .SEGBITS = 42,
ths6d355242007-12-25 03:13:56 +0000579 .PABITS = 36,
Philippe Mathieu-Daudé8b0ea9b2020-12-16 23:59:07 +0100580 .insn_flags = CPU_MIPS64R1,
ths6d355242007-12-25 03:13:56 +0000581 .mmu_type = MMU_TYPE_R4000,
thsc9c1a062007-06-01 14:58:56 +0000582 },
583 {
584 .name = "20Kc",
aurel3269585492009-01-14 19:40:36 +0000585 /* We emulate a later version of the 20Kc, earlier ones had a broken
thsbd04c6f2007-06-12 12:43:47 +0000586 WAIT instruction. */
587 .CP0_PRid = 0x000182a0,
ths29fe0e32007-12-25 17:32:46 +0000588 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
ths6d355242007-12-25 03:13:56 +0000589 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
thsc9c1a062007-06-01 14:58:56 +0000590 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000591 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
592 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
593 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
thsc9c1a062007-06-01 14:58:56 +0000594 .CP0_Config2 = MIPS_CONFIG2,
595 .CP0_Config3 = MIPS_CONFIG3,
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100596 .CP0_LLAddr_rw_bitmask = 0,
597 .CP0_LLAddr_shift = 0,
thsc9c1a062007-06-01 14:58:56 +0000598 .SYNCI_Step = 32,
thsa1daafd2007-12-24 14:33:57 +0000599 .CCRes = 1,
thsead93602007-09-06 00:18:15 +0000600 .CP0_Status_rw_bitmask = 0x36FBFFFF,
aurel3269585492009-01-14 19:40:36 +0000601 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
thsc9c1a062007-06-01 14:58:56 +0000602 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
ths5a5012e2007-05-07 13:55:33 +0000603 (1 << FCR0_D) | (1 << FCR0_S) |
thsc9c1a062007-06-01 14:58:56 +0000604 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
Aleksandar Markovic599bc5e2016-06-10 11:57:36 +0200605 .CP1_fcr31 = 0,
606 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
thse034e2c2007-06-23 18:04:12 +0000607 .SEGBITS = 40,
ths6d355242007-12-25 03:13:56 +0000608 .PABITS = 36,
Philippe Mathieu-Daudé8b0ea9b2020-12-16 23:59:07 +0100609 .insn_flags = CPU_MIPS64R1 | ASE_MIPS3D,
ths6d355242007-12-25 03:13:56 +0000610 .mmu_type = MMU_TYPE_R4000,
ths33d68b52007-03-18 00:30:29 +0000611 },
thsd2123ea2007-10-29 09:38:43 +0000612 {
aurel3269585492009-01-14 19:40:36 +0000613 /* A generic CPU providing MIPS64 Release 2 features.
thsd2123ea2007-10-29 09:38:43 +0000614 FIXME: Eventually this should be replaced by a real CPU model. */
615 .name = "MIPS64R2-generic",
ths8c893952007-11-18 03:19:58 +0000616 .CP0_PRid = 0x00010000,
ths6d355242007-12-25 03:13:56 +0000617 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
aurel3269585492009-01-14 19:40:36 +0000618 (MMU_TYPE_R4000 << CP0C0_MT),
thsd2123ea2007-10-29 09:38:43 +0000619 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
aurel3269585492009-01-14 19:40:36 +0000620 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
621 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
622 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
thsd2123ea2007-10-29 09:38:43 +0000623 .CP0_Config2 = MIPS_CONFIG2,
ths6d355242007-12-25 03:13:56 +0000624 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
Aurelien Jarno2a6e32d2009-11-22 13:22:54 +0100625 .CP0_LLAddr_rw_bitmask = 0,
626 .CP0_LLAddr_shift = 0,
thsd2123ea2007-10-29 09:38:43 +0000627 .SYNCI_Step = 32,
628 .CCRes = 2,
629 .CP0_Status_rw_bitmask = 0x36FBFFFF,
James Hoganbad63a82017-07-18 12:55:59 +0100630 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
thsea4b07f2007-12-28 12:35:05 +0000631 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
632 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
633 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
Aleksandar Markovic599bc5e2016-06-10 11:57:36 +0200634 .CP1_fcr31 = 0,
635 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
ths6d355242007-12-25 03:13:56 +0000636 .SEGBITS = 42,
ths6d355242007-12-25 03:13:56 +0000637 .PABITS = 36,
thsd2123ea2007-10-29 09:38:43 +0000638 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
ths6d355242007-12-25 03:13:56 +0000639 .mmu_type = MMU_TYPE_R4000,
thsd2123ea2007-10-29 09:38:43 +0000640 },
Huacai Chen5bc6fba2010-06-29 10:50:27 +0800641 {
Maciej W. Rozycki36b86e02014-11-03 19:31:26 +0000642 .name = "5KEc",
643 .CP0_PRid = 0x00018900,
644 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
645 (MMU_TYPE_R4000 << CP0C0_MT),
646 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
647 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
648 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
649 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
650 .CP0_Config2 = MIPS_CONFIG2,
651 .CP0_Config3 = MIPS_CONFIG3,
652 .CP0_LLAddr_rw_bitmask = 0,
653 .CP0_LLAddr_shift = 4,
654 .SYNCI_Step = 32,
655 .CCRes = 2,
Maciej W. Rozycki196a7952014-12-20 23:00:25 +0000656 .CP0_Status_rw_bitmask = 0x12F8FFFF,
Maciej W. Rozycki36b86e02014-11-03 19:31:26 +0000657 .SEGBITS = 42,
658 .PABITS = 36,
659 .insn_flags = CPU_MIPS64R2,
660 .mmu_type = MMU_TYPE_R4000,
661 },
662 {
663 .name = "5KEf",
664 .CP0_PRid = 0x00018900,
665 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
666 (MMU_TYPE_R4000 << CP0C0_MT),
667 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
668 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
669 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
670 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
671 .CP0_Config2 = MIPS_CONFIG2,
672 .CP0_Config3 = MIPS_CONFIG3,
673 .CP0_LLAddr_rw_bitmask = 0,
674 .CP0_LLAddr_shift = 4,
675 .SYNCI_Step = 32,
676 .CCRes = 2,
677 .CP0_Status_rw_bitmask = 0x36F8FFFF,
678 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
679 (1 << FCR0_D) | (1 << FCR0_S) |
680 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
681 .SEGBITS = 42,
682 .PABITS = 36,
683 .insn_flags = CPU_MIPS64R2,
684 .mmu_type = MMU_TYPE_R4000,
685 },
686 {
Leon Alrae8f95ad12016-06-27 11:11:39 +0100687 .name = "I6400",
688 .CP0_PRid = 0x1A900,
Leon Alraea773cc72014-06-27 08:49:09 +0100689 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
690 (MMU_TYPE_R4000 << CP0C0_MT),
Leon Alrae8f95ad12016-06-27 11:11:39 +0100691 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
692 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
693 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
Leon Alraea773cc72014-06-27 08:49:09 +0100694 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
695 .CP0_Config2 = MIPS_CONFIG2,
Leon Alraea9a95062016-03-15 09:59:36 +0000696 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
697 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
Yongbok Kim4dc89b72015-06-29 10:11:23 +0100698 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
Leon Alrae8f95ad12016-06-27 11:11:39 +0100699 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
Yongbok Kim4dc89b72015-06-29 10:11:23 +0100700 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
Leon Alraecdc46fa2016-06-27 16:19:12 +0100701 (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
Yongbok Kim01bc4352016-02-03 12:31:07 +0000702 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
Leon Alrae8f95ad12016-06-27 11:11:39 +0100703 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
Yongbok Kim4dc89b72015-06-29 10:11:23 +0100704 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
705 (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
Leon Alraea773cc72014-06-27 08:49:09 +0100706 .CP0_LLAddr_rw_bitmask = 0,
707 .CP0_LLAddr_shift = 0,
708 .SYNCI_Step = 32,
709 .CCRes = 2,
710 .CP0_Status_rw_bitmask = 0x30D8FFFF,
Leon Alrae2d9e48b2014-07-11 16:11:35 +0100711 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
712 (1U << CP0PG_RIE),
Leon Alrae6773f9b2015-04-14 10:33:43 +0100713 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
James Hoganbad63a82017-07-18 12:55:59 +0100714 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
Leon Alraeba5c79f2016-02-24 10:47:10 +0000715 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
716 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
Leon Alrae8f95ad12016-06-27 11:11:39 +0100717 (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
Leon Alraeba5c79f2016-02-24 10:47:10 +0000718 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
Aleksandar Markovic599bc5e2016-06-10 11:57:36 +0200719 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
Leon Alrae8f95ad12016-06-27 11:11:39 +0100720 .MSAIR = 0x03 << MSAIR_ProcID,
Yongbok Kim4dc89b72015-06-29 10:11:23 +0100721 .SEGBITS = 48,
Leon Alrae6773f9b2015-04-14 10:33:43 +0100722 .PABITS = 48,
Philippe Mathieu-Daudé7e2a6192020-11-29 23:32:40 +0100723 .insn_flags = CPU_MIPS64R6,
Leon Alraea773cc72014-06-27 08:49:09 +0100724 .mmu_type = MMU_TYPE_R4000,
725 },
726 {
Yongbok Kimca1ffd12019-01-21 21:07:29 +0100727 .name = "I6500",
728 .CP0_PRid = 0x1B000,
729 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
730 (MMU_TYPE_R4000 << CP0C0_MT),
731 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
732 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
733 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
734 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
735 .CP0_Config2 = MIPS_CONFIG2,
736 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) |
737 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
738 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
739 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
740 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
741 (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),
742 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |
743 (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
744 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
745 (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
746 .CP0_LLAddr_rw_bitmask = 0,
747 .CP0_LLAddr_shift = 0,
748 .SYNCI_Step = 64,
749 .CCRes = 2,
750 .CP0_Status_rw_bitmask = 0x30D8FFFF,
751 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
752 (1U << CP0PG_RIE),
753 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
754 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG),
755 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) |
756 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
757 (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV),
758 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
759 .CP1_fcr31_rw_bitmask = 0x0103FFFF,
760 .MSAIR = 0x03 << MSAIR_ProcID,
761 .SEGBITS = 48,
762 .PABITS = 48,
Philippe Mathieu-Daudé7e2a6192020-11-29 23:32:40 +0100763 .insn_flags = CPU_MIPS64R6,
Yongbok Kimca1ffd12019-01-21 21:07:29 +0100764 .mmu_type = MMU_TYPE_R4000,
765 },
766 {
Huacai Chen5bc6fba2010-06-29 10:50:27 +0800767 .name = "Loongson-2E",
768 .CP0_PRid = 0x6302,
Maciej W. Rozycki6225a4a2014-11-05 15:34:58 +0000769 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
Philippe Mathieu-Daudéb4cbbb42020-12-01 12:41:39 +0100770 .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) |
771 (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0),
Maciej W. Rozycki6225a4a2014-11-05 15:34:58 +0000772 /* Note: Config1 is only used internally,
773 Loongson-2E has only Config0. */
Huacai Chen5bc6fba2010-06-29 10:50:27 +0800774 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
775 .SYNCI_Step = 16,
776 .CCRes = 2,
777 .CP0_Status_rw_bitmask = 0x35D0FFFF,
778 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
Aleksandar Markovic599bc5e2016-06-10 11:57:36 +0200779 .CP1_fcr31 = 0,
780 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
Huacai Chen5bc6fba2010-06-29 10:50:27 +0800781 .SEGBITS = 40,
782 .PABITS = 40,
Philippe Mathieu-Daudéeaca8572021-01-10 22:46:43 +0100783 .insn_flags = CPU_MIPS3 | INSN_LOONGSON2E,
Huacai Chen5bc6fba2010-06-29 10:50:27 +0800784 .mmu_type = MMU_TYPE_R4000,
785 },
786 {
Maciej W. Rozycki6225a4a2014-11-05 15:34:58 +0000787 .name = "Loongson-2F",
788 .CP0_PRid = 0x6303,
789 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
Philippe Mathieu-Daudéb4cbbb42020-12-01 12:41:39 +0100790 .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) |
791 (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0),
Maciej W. Rozycki6225a4a2014-11-05 15:34:58 +0000792 /* Note: Config1 is only used internally,
793 Loongson-2F has only Config0. */
794 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
795 .SYNCI_Step = 16,
796 .CCRes = 2,
797 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
798 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
Aleksandar Markovic599bc5e2016-06-10 11:57:36 +0200799 .CP1_fcr31 = 0,
800 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
Maciej W. Rozycki6225a4a2014-11-05 15:34:58 +0000801 .SEGBITS = 40,
802 .PABITS = 40,
Philippe Mathieu-Daudéeaca8572021-01-10 22:46:43 +0100803 .insn_flags = CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI,
Maciej W. Rozycki6225a4a2014-11-05 15:34:58 +0000804 .mmu_type = MMU_TYPE_R4000,
Huacai Chen5bc6fba2010-06-29 10:50:27 +0800805 },
Jia Liuaf13ae02012-10-24 22:17:12 +0800806 {
Philippe Mathieu-Daudé98d207c2021-08-13 12:37:12 +0200807 .name = "Loongson-3A1000", /* Loongson-3A R1, GS464-based */
Huacai Chenaf868992020-06-02 10:39:15 +0800808 .CP0_PRid = 0x6305,
809 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
810 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
811 (MMU_TYPE_R4000 << CP0C0_MT),
812 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
813 (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
814 (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
815 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
816 .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) |
817 (3 << CP0C2_SA),
818 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
819 .CP0_LLAddr_rw_bitmask = 0,
820 .SYNCI_Step = 32,
821 .CCRes = 2,
822 .CP0_Status_rw_bitmask = 0x74D8FFFF,
823 .CP0_PageGrain = (1 << CP0PG_ELPA),
824 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
825 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
826 (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
827 (0x1 << FCR0_D) | (0x1 << FCR0_S),
828 .CP1_fcr31 = 0,
829 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
Philippe Mathieu-Daudé71ed30b2021-08-13 12:36:46 +0200830 .SEGBITS = 48,
Huacai Chenaf868992020-06-02 10:39:15 +0800831 .PABITS = 48,
Philippe Mathieu-Daudéeaca8572021-01-10 22:46:43 +0100832 .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
833 ASE_LMMI | ASE_LEXT,
Huacai Chenaf868992020-06-02 10:39:15 +0800834 .mmu_type = MMU_TYPE_R4000,
835 },
836 {
Philippe Mathieu-Daudé98d207c2021-08-13 12:37:12 +0200837 .name = "Loongson-3A4000", /* Loongson-3A R4, GS464V-based */
Huacai Chenaf868992020-06-02 10:39:15 +0800838 .CP0_PRid = 0x14C000,
839 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
840 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
841 (MMU_TYPE_R4000 << CP0C0_MT),
842 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
843 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
844 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
845 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
846 .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) |
847 (15 << CP0C2_SA),
848 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
849 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
850 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
851 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
852 (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist),
853 .CP0_Config4_rw_bitmask = 0,
854 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists),
855 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) |
856 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
857 (1 << CP0C5_FRE) | (1 << CP0C5_SBRI),
858 .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) |
859 (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) |
860 (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF),
861 .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) |
862 (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) |
863 (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) |
864 (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) |
865 (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) |
866 (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) |
867 (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) |
868 (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) |
869 (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) |
870 (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) |
871 (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) |
872 (1 << CP0C6_DATAPREF),
873 .CP0_Config7 = 0,
874 .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) |
875 (1 << CP0C7_VFPUCGEN),
876 .CP0_LLAddr_rw_bitmask = 1,
877 .SYNCI_Step = 16,
878 .CCRes = 2,
879 .CP0_Status_rw_bitmask = 0x7DDBFFFF,
880 .CP0_PageGrain = (1 << CP0PG_ELPA),
881 .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) |
882 (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
883 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) |
884 (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) |
885 (0x1 << FCR0_D) | (0x1 << FCR0_S),
886 .CP1_fcr31 = 0,
887 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
Philippe Mathieu-Daudéba7b6f02021-10-21 15:58:42 +0200888 .MSAIR = (0x01 << MSAIR_ProcID) | (0x40 << MSAIR_Rev),
Huacai Chenaf868992020-06-02 10:39:15 +0800889 .SEGBITS = 48,
890 .PABITS = 48,
Philippe Mathieu-Daudéeaca8572021-01-10 22:46:43 +0100891 .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
892 ASE_LMMI | ASE_LEXT,
Huacai Chenaf868992020-06-02 10:39:15 +0800893 .mmu_type = MMU_TYPE_R4000,
894 },
895 {
Stefan Markovic908f6be2018-10-08 17:20:24 +0200896 /* A generic CPU providing MIPS64 DSP R2 ASE features.
Jia Liuaf13ae02012-10-24 22:17:12 +0800897 FIXME: Eventually this should be replaced by a real CPU model. */
898 .name = "mips64dspr2",
899 .CP0_PRid = 0x00010000,
900 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
901 (MMU_TYPE_R4000 << CP0C0_MT),
902 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
903 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
904 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
905 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
906 .CP0_Config2 = MIPS_CONFIG2,
Maciej W. Rozyckie30614d2014-11-04 15:41:20 +0000907 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
908 (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
Jia Liuaf13ae02012-10-24 22:17:12 +0800909 .CP0_LLAddr_rw_bitmask = 0,
910 .CP0_LLAddr_shift = 0,
911 .SYNCI_Step = 32,
912 .CCRes = 2,
913 .CP0_Status_rw_bitmask = 0x37FBFFFF,
914 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
915 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
916 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
Aleksandar Markovic599bc5e2016-06-10 11:57:36 +0200917 .CP1_fcr31 = 0,
918 .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
Jia Liuaf13ae02012-10-24 22:17:12 +0800919 .SEGBITS = 42,
Jia Liuaf13ae02012-10-24 22:17:12 +0800920 .PABITS = 36,
Stefan Markovic908f6be2018-10-08 17:20:24 +0200921 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
Jia Liuaf13ae02012-10-24 22:17:12 +0800922 .mmu_type = MMU_TYPE_R4000,
923 },
Pavel Dovgalyuk9a6046a2022-06-20 15:05:37 +0300924 {
925 /*
926 * Octeon 68xx with MIPS64 Cavium Octeon features.
927 */
928 .name = "Octeon68XX",
929 .CP0_PRid = 0x000D9100,
930 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
931 (MMU_TYPE_R4000 << CP0C0_MT),
932 .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
933 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
934 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
935 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
936 .CP0_Config2 = MIPS_CONFIG2,
Jiaxun Yang4bfc8952022-10-31 13:25:31 +0000937 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
Pavel Dovgalyuk9a6046a2022-06-20 15:05:37 +0300938 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) |
939 (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) |
940 (3U << CP0C4_MMUSizeExt),
941 .CP0_LLAddr_rw_bitmask = 0,
942 .CP0_LLAddr_shift = 4,
943 .CP0_PageGrain = (1 << CP0PG_ELPA),
944 .SYNCI_Step = 32,
945 .CCRes = 2,
946 .CP0_Status_rw_bitmask = 0x12F8FFFF,
947 .SEGBITS = 42,
948 .PABITS = 49,
Jiaxun Yang4bfc8952022-10-31 13:25:31 +0000949 .insn_flags = CPU_MIPS64R2 | INSN_OCTEON,
Pavel Dovgalyuk9a6046a2022-06-20 15:05:37 +0300950 .mmu_type = MMU_TYPE_R4000,
951 },
Huacai Chen5bc6fba2010-06-29 10:50:27 +0800952
ths33d68b52007-03-18 00:30:29 +0000953#endif
954};
Igor Mammedov41da2122017-09-20 16:49:33 -0300955const int mips_defs_number = ARRAY_SIZE(mips_defs);
ths33d68b52007-03-18 00:30:29 +0000956
Markus Armbruster04424282019-04-17 21:17:57 +0200957void mips_cpu_list(void)
ths33d68b52007-03-18 00:30:29 +0000958{
959 int i;
960
malcb1503cd2008-12-22 20:33:55 +0000961 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
Markus Armbruster04424282019-04-17 21:17:57 +0200962 qemu_printf("MIPS '%s'\n", mips_defs[i].name);
ths33d68b52007-03-18 00:30:29 +0000963 }
964}
965
Anthony Liguoric227f092009-10-01 16:12:16 -0500966static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
thsead93602007-09-06 00:18:15 +0000967{
thsf01be152008-09-18 11:57:27 +0000968 int i;
thsead93602007-09-06 00:18:15 +0000969
thsf01be152008-09-18 11:57:27 +0000970 for (i = 0; i < MIPS_FPU_MAX; i++)
971 env->fpus[i].fcr0 = def->CP1_fcr0;
972
973 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
thsead93602007-09-06 00:18:15 +0000974}
975
Philippe Mathieu-Daudé585c80a2020-11-30 10:04:39 +0100976static void mvp_init(CPUMIPSState *env)
thsead93602007-09-06 00:18:15 +0000977{
Anthony Liguori7267c092011-08-20 22:09:37 -0500978 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
thsead93602007-09-06 00:18:15 +0000979
Philippe Mathieu-Daudéecc268e2020-12-02 18:53:20 +0100980 if (!ase_mt_available(env)) {
981 return;
982 }
983
thsead93602007-09-06 00:18:15 +0000984 /* MVPConf1 implemented, TLB sharable, no gating storage support,
985 programmable cache partitioning implemented, number of allocatable
zhaolichang8cdf8862020-10-09 14:44:41 +0800986 and shareable TLB entries, MVP has allocatable TCs, 2 VPEs
thsead93602007-09-06 00:18:15 +0000987 implemented, 5 TCs implemented. */
Peter Maydellf45cb2f2014-03-17 16:00:34 +0000988 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
thsead93602007-09-06 00:18:15 +0000989 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
thsead93602007-09-06 00:18:15 +0000990// TODO: actually do 2 VPEs.
991// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
992// (0x04 << CP0MVPC0_PTC);
993 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
Edgar E. Iglesias1dab0052011-08-29 23:07:38 +0200994 (0x00 << CP0MVPC0_PTC);
aurel32932e71c2009-01-12 21:33:13 +0000995#if !defined(CONFIG_USER_ONLY)
ths0eaef5a2008-07-23 16:14:22 +0000996 /* Usermode has no TLB support */
aurel32932e71c2009-01-12 21:33:13 +0000997 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
998#endif
ths0eaef5a2008-07-23 16:14:22 +0000999
thsead93602007-09-06 00:18:15 +00001000 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
1001 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
Peter Maydellf45cb2f2014-03-17 16:00:34 +00001002 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
thsead93602007-09-06 00:18:15 +00001003 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
1004 (0x1 << CP0MVPC1_PCP1);
1005}