commit 2f6445458e5e9eec54c9f47071bbc6ac70c54c02
author ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Wed Apr 11 20:34:23 2007 +0000
committer ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Wed Apr 11 20:34:23 2007 +0000
tree 692682c50a261030cbc71acaec04159e668cdc96
parent b48cfdffd9f15432355c8e4ed9d2781eab9e4358

Make SYNCI_Step and CCRes CPU-specific.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2651 c046a42c-6fe2-441c-8c8c-71466251a162

target-mips/translate_init.c

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 456a6cd..f2966ea 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -67,6 +67,8 @@
     int32_t CP0_Config3;
     int32_t CP0_Config6;
     int32_t CP0_Config7;
+    int32_t SYNCI_Step;
+    int32_t CCRes;
     int32_t CP1_fcr0;
 };
 
@@ -82,6 +84,8 @@
         .CP0_Config1 = MIPS_CONFIG1,
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
         .CP1_fcr0 = MIPS_FCR0,
     },
     {
@@ -91,6 +95,8 @@
         .CP0_Config1 = MIPS_CONFIG1,
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
         .CP1_fcr0 = MIPS_FCR0,
     },
     {
@@ -100,6 +106,8 @@
         .CP0_Config1 = MIPS_CONFIG1,
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
         .CP1_fcr0 = MIPS_FCR0,
     },
     {
@@ -109,6 +117,8 @@
         .CP0_Config1 = MIPS_CONFIG1,
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
         .CP1_fcr0 = MIPS_FCR0,
     },
     {
@@ -118,6 +128,8 @@
         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
         .CP1_fcr0 = MIPS_FCR0,
     },
 #else
@@ -128,6 +140,8 @@
         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 16,
+        .CCRes = 2,
         .CP1_fcr0 = MIPS_FCR0,
     },
 #endif
@@ -175,6 +189,8 @@
     env->CP0_Config3 = def->CP0_Config3;
     env->CP0_Config6 = def->CP0_Config6;
     env->CP0_Config7 = def->CP0_Config7;
+    env->SYNCI_Step = def->SYNCI_Step;
+    env->CCRes = def->CCRes;
     env->fcr0 = def->CP1_fcr0;
     return 0;
 }