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bellardc896fe22008-02-01 10:05:41 +00001/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Richard Hendersone58eb532013-08-27 13:13:44 -070024
25#ifndef TCG_H
26#define TCG_H
27
aurel32f8393942009-04-13 18:45:38 +000028#include "qemu-common.h"
Richard Henderson0ec9eab2013-09-19 12:16:45 -070029#include "qemu/bitops.h"
Richard Henderson78cd7b82013-08-20 14:41:29 -070030#include "tcg-target.h"
31
32/* Default target word size to pointer size. */
33#ifndef TCG_TARGET_REG_BITS
34# if UINTPTR_MAX == UINT32_MAX
35# define TCG_TARGET_REG_BITS 32
36# elif UINTPTR_MAX == UINT64_MAX
37# define TCG_TARGET_REG_BITS 64
38# else
39# error Unknown pointer size for tcg target
40# endif
Stefan Weil817b8382011-09-17 22:00:27 +020041#endif
42
bellardc896fe22008-02-01 10:05:41 +000043#if TCG_TARGET_REG_BITS == 32
44typedef int32_t tcg_target_long;
45typedef uint32_t tcg_target_ulong;
46#define TCG_PRIlx PRIx32
47#define TCG_PRIld PRId32
48#elif TCG_TARGET_REG_BITS == 64
49typedef int64_t tcg_target_long;
50typedef uint64_t tcg_target_ulong;
51#define TCG_PRIlx PRIx64
52#define TCG_PRIld PRId64
53#else
54#error unsupported
55#endif
56
Stefan Weilc38bb942012-03-02 23:30:03 +010057#include "tcg-runtime.h"
58
bellardc896fe22008-02-01 10:05:41 +000059#if TCG_TARGET_NB_REGS <= 32
60typedef uint32_t TCGRegSet;
61#elif TCG_TARGET_NB_REGS <= 64
62typedef uint64_t TCGRegSet;
63#else
64#error unsupported
65#endif
66
Richard Henderson25c4d9c2011-08-17 14:11:46 -070067#if TCG_TARGET_REG_BITS == 32
Richard Hendersone6a72732013-02-19 23:51:49 -080068/* Turn some undef macros into false macros. */
Richard Henderson4bb7a412013-09-09 17:03:24 -070069#define TCG_TARGET_HAS_trunc_shr_i32 0
Richard Henderson25c4d9c2011-08-17 14:11:46 -070070#define TCG_TARGET_HAS_div_i64 0
Richard Hendersonca675f42013-03-11 22:41:47 -070071#define TCG_TARGET_HAS_rem_i64 0
Richard Henderson25c4d9c2011-08-17 14:11:46 -070072#define TCG_TARGET_HAS_div2_i64 0
73#define TCG_TARGET_HAS_rot_i64 0
74#define TCG_TARGET_HAS_ext8s_i64 0
75#define TCG_TARGET_HAS_ext16s_i64 0
76#define TCG_TARGET_HAS_ext32s_i64 0
77#define TCG_TARGET_HAS_ext8u_i64 0
78#define TCG_TARGET_HAS_ext16u_i64 0
79#define TCG_TARGET_HAS_ext32u_i64 0
80#define TCG_TARGET_HAS_bswap16_i64 0
81#define TCG_TARGET_HAS_bswap32_i64 0
82#define TCG_TARGET_HAS_bswap64_i64 0
83#define TCG_TARGET_HAS_neg_i64 0
84#define TCG_TARGET_HAS_not_i64 0
85#define TCG_TARGET_HAS_andc_i64 0
86#define TCG_TARGET_HAS_orc_i64 0
87#define TCG_TARGET_HAS_eqv_i64 0
88#define TCG_TARGET_HAS_nand_i64 0
89#define TCG_TARGET_HAS_nor_i64 0
90#define TCG_TARGET_HAS_deposit_i64 0
Richard Hendersonffc5ea02012-09-21 10:13:34 -070091#define TCG_TARGET_HAS_movcond_i64 0
Richard Hendersond7156f72013-02-19 23:51:52 -080092#define TCG_TARGET_HAS_add2_i64 0
93#define TCG_TARGET_HAS_sub2_i64 0
94#define TCG_TARGET_HAS_mulu2_i64 0
Richard Henderson4d3203f2013-02-19 23:51:53 -080095#define TCG_TARGET_HAS_muls2_i64 0
Richard Henderson03271522013-08-14 14:35:56 -070096#define TCG_TARGET_HAS_muluh_i64 0
97#define TCG_TARGET_HAS_mulsh_i64 0
Richard Hendersone6a72732013-02-19 23:51:49 -080098/* Turn some undef macros into true macros. */
99#define TCG_TARGET_HAS_add2_i32 1
100#define TCG_TARGET_HAS_sub2_i32 1
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700101#endif
102
Jan Kiszkaa4773322011-09-29 18:52:11 +0200103#ifndef TCG_TARGET_deposit_i32_valid
104#define TCG_TARGET_deposit_i32_valid(ofs, len) 1
105#endif
106#ifndef TCG_TARGET_deposit_i64_valid
107#define TCG_TARGET_deposit_i64_valid(ofs, len) 1
108#endif
109
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700110/* Only one of DIV or DIV2 should be defined. */
111#if defined(TCG_TARGET_HAS_div_i32)
112#define TCG_TARGET_HAS_div2_i32 0
113#elif defined(TCG_TARGET_HAS_div2_i32)
114#define TCG_TARGET_HAS_div_i32 0
Richard Hendersonca675f42013-03-11 22:41:47 -0700115#define TCG_TARGET_HAS_rem_i32 0
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700116#endif
117#if defined(TCG_TARGET_HAS_div_i64)
118#define TCG_TARGET_HAS_div2_i64 0
119#elif defined(TCG_TARGET_HAS_div2_i64)
120#define TCG_TARGET_HAS_div_i64 0
Richard Hendersonca675f42013-03-11 22:41:47 -0700121#define TCG_TARGET_HAS_rem_i64 0
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700122#endif
123
Richard Hendersondf9ebea2014-03-26 10:59:14 -0700124/* For 32-bit targets, some sort of unsigned widening multiply is required. */
125#if TCG_TARGET_REG_BITS == 32 \
126 && !(defined(TCG_TARGET_HAS_mulu2_i32) \
127 || defined(TCG_TARGET_HAS_muluh_i32))
128# error "Missing unsigned widening multiply"
129#endif
130
Richard Hendersona9751602010-03-19 11:12:29 -0700131typedef enum TCGOpcode {
Aurelien Jarnoc61aaf72010-06-03 19:40:04 +0200132#define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
bellardc896fe22008-02-01 10:05:41 +0000133#include "tcg-opc.h"
134#undef DEF
135 NB_OPS,
Richard Hendersona9751602010-03-19 11:12:29 -0700136} TCGOpcode;
bellardc896fe22008-02-01 10:05:41 +0000137
138#define tcg_regset_clear(d) (d) = 0
139#define tcg_regset_set(d, s) (d) = (s)
140#define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)
Aurelien Jarno7d301752009-10-28 22:44:34 +0100141#define tcg_regset_set_reg(d, r) (d) |= 1L << (r)
142#define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r))
bellardc896fe22008-02-01 10:05:41 +0000143#define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
144#define tcg_regset_or(d, a, b) (d) = (a) | (b)
145#define tcg_regset_and(d, a, b) (d) = (a) & (b)
146#define tcg_regset_andnot(d, a, b) (d) = (a) & ~(b)
147#define tcg_regset_not(d, a) (d) = ~(a)
148
149typedef struct TCGRelocation {
150 struct TCGRelocation *next;
151 int type;
152 uint8_t *ptr;
Richard Henderson2ba7fae22013-08-20 15:30:10 -0700153 intptr_t addend;
bellardc896fe22008-02-01 10:05:41 +0000154} TCGRelocation;
155
156typedef struct TCGLabel {
blueswir1c44f9452008-05-19 16:32:18 +0000157 int has_value;
bellardc896fe22008-02-01 10:05:41 +0000158 union {
Richard Henderson2ba7fae22013-08-20 15:30:10 -0700159 uintptr_t value;
bellardc896fe22008-02-01 10:05:41 +0000160 TCGRelocation *first_reloc;
161 } u;
162} TCGLabel;
163
164typedef struct TCGPool {
165 struct TCGPool *next;
blueswir1c44f9452008-05-19 16:32:18 +0000166 int size;
167 uint8_t data[0] __attribute__ ((aligned));
bellardc896fe22008-02-01 10:05:41 +0000168} TCGPool;
169
170#define TCG_POOL_CHUNK_SIZE 32768
171
172#define TCG_MAX_LABELS 512
173
blueswir1c4071c92008-03-16 19:21:07 +0000174#define TCG_MAX_TEMPS 512
bellardc896fe22008-02-01 10:05:41 +0000175
bellardb03cce82008-05-10 10:52:05 +0000176/* when the size of the arguments of a called function is smaller than
177 this value, they are statically allocated in the TB stack frame */
178#define TCG_STATIC_CALL_ARGS_SIZE 128
179
Richard Hendersonc02244a2010-03-19 11:36:30 -0700180typedef enum TCGType {
181 TCG_TYPE_I32,
182 TCG_TYPE_I64,
183 TCG_TYPE_COUNT, /* number of different types */
bellardc896fe22008-02-01 10:05:41 +0000184
Richard Henderson3b6dac32010-06-02 17:26:55 -0700185 /* An alias for the size of the host register. */
bellardc896fe22008-02-01 10:05:41 +0000186#if TCG_TARGET_REG_BITS == 32
Richard Henderson3b6dac32010-06-02 17:26:55 -0700187 TCG_TYPE_REG = TCG_TYPE_I32,
bellardc896fe22008-02-01 10:05:41 +0000188#else
Richard Henderson3b6dac32010-06-02 17:26:55 -0700189 TCG_TYPE_REG = TCG_TYPE_I64,
bellardc896fe22008-02-01 10:05:41 +0000190#endif
Richard Henderson3b6dac32010-06-02 17:26:55 -0700191
Richard Hendersond2898372013-08-20 14:48:46 -0700192 /* An alias for the size of the native pointer. */
193#if UINTPTR_MAX == UINT32_MAX
194 TCG_TYPE_PTR = TCG_TYPE_I32,
195#else
196 TCG_TYPE_PTR = TCG_TYPE_I64,
197#endif
Richard Henderson3b6dac32010-06-02 17:26:55 -0700198
199 /* An alias for the size of the target "long", aka register. */
Richard Hendersonc02244a2010-03-19 11:36:30 -0700200#if TARGET_LONG_BITS == 64
201 TCG_TYPE_TL = TCG_TYPE_I64,
202#else
203 TCG_TYPE_TL = TCG_TYPE_I32,
204#endif
205} TCGType;
bellardc896fe22008-02-01 10:05:41 +0000206
Richard Henderson6c5f4ea2013-09-03 13:52:19 -0700207/* Constants for qemu_ld and qemu_st for the Memory Operation field. */
208typedef enum TCGMemOp {
209 MO_8 = 0,
210 MO_16 = 1,
211 MO_32 = 2,
212 MO_64 = 3,
213 MO_SIZE = 3, /* Mask for the above. */
214
215 MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */
216
217 MO_BSWAP = 8, /* Host reverse endian. */
218#ifdef HOST_WORDS_BIGENDIAN
219 MO_LE = MO_BSWAP,
220 MO_BE = 0,
221#else
222 MO_LE = 0,
223 MO_BE = MO_BSWAP,
224#endif
225#ifdef TARGET_WORDS_BIGENDIAN
226 MO_TE = MO_BE,
227#else
228 MO_TE = MO_LE,
229#endif
230
231 /* Combinations of the above, for ease of use. */
232 MO_UB = MO_8,
233 MO_UW = MO_16,
234 MO_UL = MO_32,
235 MO_SB = MO_SIGN | MO_8,
236 MO_SW = MO_SIGN | MO_16,
237 MO_SL = MO_SIGN | MO_32,
238 MO_Q = MO_64,
239
240 MO_LEUW = MO_LE | MO_UW,
241 MO_LEUL = MO_LE | MO_UL,
242 MO_LESW = MO_LE | MO_SW,
243 MO_LESL = MO_LE | MO_SL,
244 MO_LEQ = MO_LE | MO_Q,
245
246 MO_BEUW = MO_BE | MO_UW,
247 MO_BEUL = MO_BE | MO_UL,
248 MO_BESW = MO_BE | MO_SW,
249 MO_BESL = MO_BE | MO_SL,
250 MO_BEQ = MO_BE | MO_Q,
251
252 MO_TEUW = MO_TE | MO_UW,
253 MO_TEUL = MO_TE | MO_UL,
254 MO_TESW = MO_TE | MO_SW,
255 MO_TESL = MO_TE | MO_SL,
256 MO_TEQ = MO_TE | MO_Q,
257
258 MO_SSIZE = MO_SIZE | MO_SIGN,
259} TCGMemOp;
260
bellardc896fe22008-02-01 10:05:41 +0000261typedef tcg_target_ulong TCGArg;
262
Stefan Weil8ef935b2011-10-11 19:43:15 +0200263/* Define a type and accessor macros for variables. Using a struct is
pbrookac56dd42008-02-03 19:56:33 +0000264 nice because it gives some level of type safely. Ideally the compiler
265 be able to see through all this. However in practice this is not true,
Dong Xu Wang9814dd22011-11-22 18:06:22 +0800266 especially on targets with braindamaged ABIs (e.g. i386).
pbrookac56dd42008-02-03 19:56:33 +0000267 We use plain int by default to avoid this runtime overhead.
268 Users of tcg_gen_* don't need to know about any of this, and should
pbrooka7812ae2008-11-17 14:43:54 +0000269 treat TCGv as an opaque type.
Stefan Weil06ea77b2011-05-22 14:02:40 +0200270 In addition we do typechecking for different types of variables. TCGv_i32
pbrooka7812ae2008-11-17 14:43:54 +0000271 and TCGv_i64 are 32/64-bit variables respectively. TCGv and TCGv_ptr
272 are aliases for target_ulong and host pointer sized values respectively.
273 */
pbrookac56dd42008-02-03 19:56:33 +0000274
Juan Quintela092c73e2009-07-27 16:13:04 +0200275#ifdef CONFIG_DEBUG_TCG
aurel32f8393942009-04-13 18:45:38 +0000276#define DEBUG_TCGV 1
277#endif
pbrookac56dd42008-02-03 19:56:33 +0000278
279#ifdef DEBUG_TCGV
280
281typedef struct
282{
blueswir1a810a2d2008-12-07 17:16:42 +0000283 int i32;
pbrooka7812ae2008-11-17 14:43:54 +0000284} TCGv_i32;
pbrookac56dd42008-02-03 19:56:33 +0000285
pbrooka7812ae2008-11-17 14:43:54 +0000286typedef struct
287{
blueswir1a810a2d2008-12-07 17:16:42 +0000288 int i64;
pbrooka7812ae2008-11-17 14:43:54 +0000289} TCGv_i64;
290
Peter Maydellebecf362011-05-27 13:12:13 +0100291typedef struct {
292 int iptr;
293} TCGv_ptr;
294
pbrooka7812ae2008-11-17 14:43:54 +0000295#define MAKE_TCGV_I32(i) __extension__ \
296 ({ TCGv_i32 make_tcgv_tmp = {i}; make_tcgv_tmp;})
297#define MAKE_TCGV_I64(i) __extension__ \
298 ({ TCGv_i64 make_tcgv_tmp = {i}; make_tcgv_tmp;})
Peter Maydellebecf362011-05-27 13:12:13 +0100299#define MAKE_TCGV_PTR(i) __extension__ \
300 ({ TCGv_ptr make_tcgv_tmp = {i}; make_tcgv_tmp; })
blueswir1a810a2d2008-12-07 17:16:42 +0000301#define GET_TCGV_I32(t) ((t).i32)
302#define GET_TCGV_I64(t) ((t).i64)
Peter Maydellebecf362011-05-27 13:12:13 +0100303#define GET_TCGV_PTR(t) ((t).iptr)
pbrookac56dd42008-02-03 19:56:33 +0000304#if TCG_TARGET_REG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +0000305#define TCGV_LOW(t) MAKE_TCGV_I32(GET_TCGV_I64(t))
306#define TCGV_HIGH(t) MAKE_TCGV_I32(GET_TCGV_I64(t) + 1)
pbrookac56dd42008-02-03 19:56:33 +0000307#endif
308
309#else /* !DEBUG_TCGV */
310
pbrooka7812ae2008-11-17 14:43:54 +0000311typedef int TCGv_i32;
312typedef int TCGv_i64;
Peter Maydellebecf362011-05-27 13:12:13 +0100313#if TCG_TARGET_REG_BITS == 32
314#define TCGv_ptr TCGv_i32
315#else
316#define TCGv_ptr TCGv_i64
317#endif
pbrooka7812ae2008-11-17 14:43:54 +0000318#define MAKE_TCGV_I32(x) (x)
319#define MAKE_TCGV_I64(x) (x)
Peter Maydellebecf362011-05-27 13:12:13 +0100320#define MAKE_TCGV_PTR(x) (x)
pbrooka7812ae2008-11-17 14:43:54 +0000321#define GET_TCGV_I32(t) (t)
322#define GET_TCGV_I64(t) (t)
Peter Maydellebecf362011-05-27 13:12:13 +0100323#define GET_TCGV_PTR(t) (t)
aurel3244e6acb2009-03-10 08:56:30 +0000324
pbrookac56dd42008-02-03 19:56:33 +0000325#if TCG_TARGET_REG_BITS == 32
pbrooka7812ae2008-11-17 14:43:54 +0000326#define TCGV_LOW(t) (t)
pbrookac56dd42008-02-03 19:56:33 +0000327#define TCGV_HIGH(t) ((t) + 1)
328#endif
329
330#endif /* DEBUG_TCGV */
331
aurel3243e860e2009-03-10 10:29:45 +0000332#define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
333#define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
Peter Maydellc1de7882014-02-08 14:46:55 +0000334#define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b))
aurel3243e860e2009-03-10 10:29:45 +0000335
pbrooka50f5b92008-06-29 15:25:29 +0000336/* Dummy definition to avoid compiler warnings. */
pbrooka7812ae2008-11-17 14:43:54 +0000337#define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1)
338#define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1)
Peter Maydellc1de7882014-02-08 14:46:55 +0000339#define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1)
pbrooka50f5b92008-06-29 15:25:29 +0000340
Richard Hendersonafcb92b2012-12-07 15:07:17 -0600341#define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1)
342#define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1)
Peter Maydellc1de7882014-02-08 14:46:55 +0000343#define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1)
Richard Hendersonafcb92b2012-12-07 15:07:17 -0600344
bellardc896fe22008-02-01 10:05:41 +0000345/* call flags */
Aurelien Jarno78505272012-10-09 21:53:08 +0200346/* Helper does not read globals (either directly or through an exception). It
347 implies TCG_CALL_NO_WRITE_GLOBALS. */
348#define TCG_CALL_NO_READ_GLOBALS 0x0010
349/* Helper does not write globals */
350#define TCG_CALL_NO_WRITE_GLOBALS 0x0020
351/* Helper can be safely suppressed if the return value is not used. */
352#define TCG_CALL_NO_SIDE_EFFECTS 0x0040
353
354/* convenience version of most used call flags */
355#define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS
356#define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS
357#define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS
358#define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
359#define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
360
bellard39cf05d2008-05-22 14:59:57 +0000361/* used to align parameters */
pbrooka7812ae2008-11-17 14:43:54 +0000362#define TCG_CALL_DUMMY_TCGV MAKE_TCGV_I32(-1)
bellard39cf05d2008-05-22 14:59:57 +0000363#define TCG_CALL_DUMMY_ARG ((TCGArg)(-1))
364
Stefan Weila93cf9d2012-11-02 08:29:53 +0100365/* Conditions. Note that these are laid out for easy manipulation by
366 the functions below:
Richard Henderson0aed2572012-09-24 14:21:40 -0700367 bit 0 is used for inverting;
368 bit 1 is signed,
369 bit 2 is unsigned,
370 bit 3 is used with bit 0 for swapping signed/unsigned. */
bellardc896fe22008-02-01 10:05:41 +0000371typedef enum {
Richard Henderson0aed2572012-09-24 14:21:40 -0700372 /* non-signed */
373 TCG_COND_NEVER = 0 | 0 | 0 | 0,
374 TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
375 TCG_COND_EQ = 8 | 0 | 0 | 0,
376 TCG_COND_NE = 8 | 0 | 0 | 1,
377 /* signed */
378 TCG_COND_LT = 0 | 0 | 2 | 0,
379 TCG_COND_GE = 0 | 0 | 2 | 1,
380 TCG_COND_LE = 8 | 0 | 2 | 0,
381 TCG_COND_GT = 8 | 0 | 2 | 1,
bellardc896fe22008-02-01 10:05:41 +0000382 /* unsigned */
Richard Henderson0aed2572012-09-24 14:21:40 -0700383 TCG_COND_LTU = 0 | 4 | 0 | 0,
384 TCG_COND_GEU = 0 | 4 | 0 | 1,
385 TCG_COND_LEU = 8 | 4 | 0 | 0,
386 TCG_COND_GTU = 8 | 4 | 0 | 1,
bellardc896fe22008-02-01 10:05:41 +0000387} TCGCond;
388
Richard Henderson1c086222010-02-09 12:33:09 -0800389/* Invert the sense of the comparison. */
Richard Henderson401d4662010-01-07 10:15:20 -0800390static inline TCGCond tcg_invert_cond(TCGCond c)
391{
392 return (TCGCond)(c ^ 1);
393}
394
Richard Henderson1c086222010-02-09 12:33:09 -0800395/* Swap the operands in a comparison. */
396static inline TCGCond tcg_swap_cond(TCGCond c)
397{
Richard Henderson0aed2572012-09-24 14:21:40 -0700398 return c & 6 ? (TCGCond)(c ^ 9) : c;
Richard Henderson1c086222010-02-09 12:33:09 -0800399}
400
Richard Hendersond1e321b2012-09-24 14:21:41 -0700401/* Create an "unsigned" version of a "signed" comparison. */
Richard Hendersonff44c2f2009-12-27 09:09:41 +0000402static inline TCGCond tcg_unsigned_cond(TCGCond c)
403{
Richard Henderson0aed2572012-09-24 14:21:40 -0700404 return c & 2 ? (TCGCond)(c ^ 6) : c;
Richard Hendersonff44c2f2009-12-27 09:09:41 +0000405}
406
Richard Hendersond1e321b2012-09-24 14:21:41 -0700407/* Must a comparison be considered unsigned? */
Richard Hendersonbcc66562012-09-24 14:21:39 -0700408static inline bool is_unsigned_cond(TCGCond c)
409{
Richard Henderson0aed2572012-09-24 14:21:40 -0700410 return (c & 4) != 0;
Richard Hendersonbcc66562012-09-24 14:21:39 -0700411}
412
Richard Hendersond1e321b2012-09-24 14:21:41 -0700413/* Create a "high" version of a double-word comparison.
414 This removes equality from a LTE or GTE comparison. */
415static inline TCGCond tcg_high_cond(TCGCond c)
416{
417 switch (c) {
418 case TCG_COND_GE:
419 case TCG_COND_LE:
420 case TCG_COND_GEU:
421 case TCG_COND_LEU:
422 return (TCGCond)(c ^ 8);
423 default:
424 return c;
425 }
426}
427
bellardc896fe22008-02-01 10:05:41 +0000428#define TEMP_VAL_DEAD 0
429#define TEMP_VAL_REG 1
430#define TEMP_VAL_MEM 2
431#define TEMP_VAL_CONST 3
432
433/* XXX: optimize memory layout */
434typedef struct TCGTemp {
435 TCGType base_type;
436 TCGType type;
437 int val_type;
438 int reg;
439 tcg_target_long val;
440 int mem_reg;
Richard Henderson2f2f2442013-08-20 15:17:25 -0700441 intptr_t mem_offset;
bellardc896fe22008-02-01 10:05:41 +0000442 unsigned int fixed_reg:1;
443 unsigned int mem_coherent:1;
444 unsigned int mem_allocated:1;
Stefan Weil5225d662011-04-28 17:20:26 +0200445 unsigned int temp_local:1; /* If true, the temp is saved across
bellard641d5fb2008-05-25 17:24:00 +0000446 basic blocks. Otherwise, it is not
Stefan Weil5225d662011-04-28 17:20:26 +0200447 preserved across basic blocks. */
bellarde8996ee2008-05-23 17:33:39 +0000448 unsigned int temp_allocated:1; /* never used for code gen */
bellardc896fe22008-02-01 10:05:41 +0000449 const char *name;
450} TCGTemp;
451
bellardc896fe22008-02-01 10:05:41 +0000452typedef struct TCGContext TCGContext;
453
Richard Henderson0ec9eab2013-09-19 12:16:45 -0700454typedef struct TCGTempSet {
455 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
456} TCGTempSet;
457
bellardc896fe22008-02-01 10:05:41 +0000458struct TCGContext {
459 uint8_t *pool_cur, *pool_end;
Kirill Batuzov40552992012-03-02 13:22:17 +0400460 TCGPool *pool_first, *pool_current, *pool_first_large;
bellardc896fe22008-02-01 10:05:41 +0000461 TCGLabel *labels;
462 int nb_labels;
bellardc896fe22008-02-01 10:05:41 +0000463 int nb_globals;
464 int nb_temps;
bellardc896fe22008-02-01 10:05:41 +0000465
466 /* goto_tb support */
467 uint8_t *code_buf;
Richard Hendersonfe7e1d32012-09-17 08:28:52 -0700468 uintptr_t *tb_next;
bellardc896fe22008-02-01 10:05:41 +0000469 uint16_t *tb_next_offset;
470 uint16_t *tb_jmp_offset; /* != NULL if USE_DIRECT_JUMP */
471
bellard641d5fb2008-05-25 17:24:00 +0000472 /* liveness analysis */
Aurelien Jarno866cb6c2011-05-17 18:25:45 +0200473 uint16_t *op_dead_args; /* for each operation, each bit tells if the
474 corresponding argument is dead */
Aurelien Jarnoec7a8692012-10-09 21:53:07 +0200475 uint8_t *op_sync_args; /* for each operation, each bit tells if the
476 corresponding output argument needs to be
477 sync to memory. */
bellard641d5fb2008-05-25 17:24:00 +0000478
bellardc896fe22008-02-01 10:05:41 +0000479 /* tells in which temporary a given register is. It does not take
480 into account fixed registers */
481 int reg_to_temp[TCG_TARGET_NB_REGS];
482 TCGRegSet reserved_regs;
Richard Hendersone2c6d1b2013-08-20 15:12:31 -0700483 intptr_t current_frame_offset;
484 intptr_t frame_start;
485 intptr_t frame_end;
bellardc896fe22008-02-01 10:05:41 +0000486 int frame_reg;
487
488 uint8_t *code_ptr;
Stefan Weild8382012012-10-04 20:29:02 +0200489 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
Richard Henderson0ec9eab2013-09-19 12:16:45 -0700490 TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
bellardc896fe22008-02-01 10:05:41 +0000491
Richard Henderson6e085f72013-09-14 14:37:06 -0700492 GHashTable *helpers;
bellarda23a9ec2008-05-23 09:52:20 +0000493
494#ifdef CONFIG_PROFILER
495 /* profiling info */
496 int64_t tb_count1;
497 int64_t tb_count;
498 int64_t op_count; /* total insn count */
499 int op_count_max; /* max insn per TB */
500 int64_t temp_count;
501 int temp_count_max;
bellarda23a9ec2008-05-23 09:52:20 +0000502 int64_t del_op_count;
503 int64_t code_in_len;
504 int64_t code_out_len;
505 int64_t interm_time;
506 int64_t code_time;
507 int64_t la_time;
Aurelien Jarnoc5cc28f2012-09-06 16:47:13 +0200508 int64_t opt_time;
bellarda23a9ec2008-05-23 09:52:20 +0000509 int64_t restore_count;
510 int64_t restore_time;
511#endif
Peter Maydell27bfd832011-03-06 21:39:53 +0000512
513#ifdef CONFIG_DEBUG_TCG
514 int temps_in_use;
Richard Henderson0a209d42012-09-21 17:18:16 -0700515 int goto_tb_issue_mask;
Peter Maydell27bfd832011-03-06 21:39:53 +0000516#endif
Yeongkyoon Leeb76f0d82012-10-31 16:04:25 +0900517
Evgeny Voevodin8232a462012-11-12 13:27:44 +0400518 uint16_t gen_opc_buf[OPC_BUF_SIZE];
519 TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE];
520
521 uint16_t *gen_opc_ptr;
522 TCGArg *gen_opparam_ptr;
Evgeny Voevodinc3a43602012-11-21 11:43:03 +0400523 target_ulong gen_opc_pc[OPC_BUF_SIZE];
524 uint16_t gen_opc_icount[OPC_BUF_SIZE];
525 uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
Evgeny Voevodin8232a462012-11-12 13:27:44 +0400526
Evgeny Voevodin0b0d3322013-02-01 01:47:22 +0700527 /* Code generation */
528 int code_gen_max_blocks;
529 uint8_t *code_gen_prologue;
530 uint8_t *code_gen_buffer;
531 size_t code_gen_buffer_size;
532 /* threshold to flush the translated code buffer */
533 size_t code_gen_buffer_max_size;
534 uint8_t *code_gen_ptr;
535
Evgeny Voevodin5e5f07e2013-02-01 01:47:23 +0700536 TBContext tb_ctx;
537
Richard Henderson9ecefc82013-10-03 14:51:24 -0500538 /* The TCGBackendData structure is private to tcg-target.c. */
539 struct TCGBackendData *be;
bellardc896fe22008-02-01 10:05:41 +0000540};
541
542extern TCGContext tcg_ctx;
bellardc896fe22008-02-01 10:05:41 +0000543
544/* pool based memory allocation */
545
546void *tcg_malloc_internal(TCGContext *s, int size);
547void tcg_pool_reset(TCGContext *s);
548void tcg_pool_delete(TCGContext *s);
549
550static inline void *tcg_malloc(int size)
551{
552 TCGContext *s = &tcg_ctx;
553 uint8_t *ptr, *ptr_end;
554 size = (size + sizeof(long) - 1) & ~(sizeof(long) - 1);
555 ptr = s->pool_cur;
556 ptr_end = ptr + size;
557 if (unlikely(ptr_end > s->pool_end)) {
558 return tcg_malloc_internal(&tcg_ctx, size);
559 } else {
560 s->pool_cur = ptr_end;
561 return ptr;
562 }
563}
564
565void tcg_context_init(TCGContext *s);
Richard Henderson9002ec72010-05-06 08:50:41 -0700566void tcg_prologue_init(TCGContext *s);
bellardc896fe22008-02-01 10:05:41 +0000567void tcg_func_start(TCGContext *s);
568
aurel3254604f72008-12-07 20:35:00 +0000569int tcg_gen_code(TCGContext *s, uint8_t *gen_code_buf);
570int tcg_gen_code_search_pc(TCGContext *s, uint8_t *gen_code_buf, long offset);
bellardc896fe22008-02-01 10:05:41 +0000571
Richard Hendersone2c6d1b2013-08-20 15:12:31 -0700572void tcg_set_frame(TCGContext *s, int reg, intptr_t start, intptr_t size);
pbrooka7812ae2008-11-17 14:43:54 +0000573
574TCGv_i32 tcg_global_reg_new_i32(int reg, const char *name);
Richard Henderson2f2f2442013-08-20 15:17:25 -0700575TCGv_i32 tcg_global_mem_new_i32(int reg, intptr_t offset, const char *name);
pbrooka7812ae2008-11-17 14:43:54 +0000576TCGv_i32 tcg_temp_new_internal_i32(int temp_local);
577static inline TCGv_i32 tcg_temp_new_i32(void)
bellard641d5fb2008-05-25 17:24:00 +0000578{
pbrooka7812ae2008-11-17 14:43:54 +0000579 return tcg_temp_new_internal_i32(0);
bellard641d5fb2008-05-25 17:24:00 +0000580}
pbrooka7812ae2008-11-17 14:43:54 +0000581static inline TCGv_i32 tcg_temp_local_new_i32(void)
bellard641d5fb2008-05-25 17:24:00 +0000582{
pbrooka7812ae2008-11-17 14:43:54 +0000583 return tcg_temp_new_internal_i32(1);
bellard641d5fb2008-05-25 17:24:00 +0000584}
pbrooka7812ae2008-11-17 14:43:54 +0000585void tcg_temp_free_i32(TCGv_i32 arg);
586char *tcg_get_arg_str_i32(TCGContext *s, char *buf, int buf_size, TCGv_i32 arg);
587
588TCGv_i64 tcg_global_reg_new_i64(int reg, const char *name);
Richard Henderson2f2f2442013-08-20 15:17:25 -0700589TCGv_i64 tcg_global_mem_new_i64(int reg, intptr_t offset, const char *name);
pbrooka7812ae2008-11-17 14:43:54 +0000590TCGv_i64 tcg_temp_new_internal_i64(int temp_local);
591static inline TCGv_i64 tcg_temp_new_i64(void)
592{
593 return tcg_temp_new_internal_i64(0);
594}
595static inline TCGv_i64 tcg_temp_local_new_i64(void)
596{
597 return tcg_temp_new_internal_i64(1);
598}
599void tcg_temp_free_i64(TCGv_i64 arg);
600char *tcg_get_arg_str_i64(TCGContext *s, char *buf, int buf_size, TCGv_i64 arg);
601
Peter Maydell27bfd832011-03-06 21:39:53 +0000602#if defined(CONFIG_DEBUG_TCG)
603/* If you call tcg_clear_temp_count() at the start of a section of
604 * code which is not supposed to leak any TCG temporaries, then
605 * calling tcg_check_temp_count() at the end of the section will
606 * return 1 if the section did in fact leak a temporary.
607 */
608void tcg_clear_temp_count(void);
609int tcg_check_temp_count(void);
610#else
611#define tcg_clear_temp_count() do { } while (0)
612#define tcg_check_temp_count() 0
613#endif
614
Stefan Weil405cf9f2010-10-22 23:03:31 +0200615void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf);
bellardc896fe22008-02-01 10:05:41 +0000616
617#define TCG_CT_ALIAS 0x80
618#define TCG_CT_IALIAS 0x40
619#define TCG_CT_REG 0x01
620#define TCG_CT_CONST 0x02 /* any constant of register size */
621
622typedef struct TCGArgConstraint {
bellard5ff9d6a2008-02-04 00:37:54 +0000623 uint16_t ct;
624 uint8_t alias_index;
bellardc896fe22008-02-01 10:05:41 +0000625 union {
626 TCGRegSet regs;
627 } u;
628} TCGArgConstraint;
629
630#define TCG_MAX_OP_ARGS 16
631
Richard Henderson8399ad52011-08-17 14:11:45 -0700632/* Bits for TCGOpDef->flags, 8 bits available. */
633enum {
634 /* Instruction defines the end of a basic block. */
635 TCG_OPF_BB_END = 0x01,
636 /* Instruction clobbers call registers and potentially update globals. */
637 TCG_OPF_CALL_CLOBBER = 0x02,
Aurelien Jarno3d5c5f82012-10-09 21:53:08 +0200638 /* Instruction has side effects: it cannot be removed if its outputs
639 are not used, and might trigger exceptions. */
Richard Henderson8399ad52011-08-17 14:11:45 -0700640 TCG_OPF_SIDE_EFFECTS = 0x04,
641 /* Instruction operands are 64-bits (otherwise 32-bits). */
642 TCG_OPF_64BIT = 0x08,
Richard Hendersonc1a61f62013-05-02 11:57:40 +0100643 /* Instruction is optional and not implemented by the host, or insn
644 is generic and should not be implemened by the host. */
Richard Henderson25c4d9c2011-08-17 14:11:46 -0700645 TCG_OPF_NOT_PRESENT = 0x10,
Richard Henderson8399ad52011-08-17 14:11:45 -0700646};
bellardc896fe22008-02-01 10:05:41 +0000647
648typedef struct TCGOpDef {
649 const char *name;
650 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
651 uint8_t flags;
bellardc896fe22008-02-01 10:05:41 +0000652 TCGArgConstraint *args_ct;
653 int *sorted_args;
Stefan Weilc68aaa12010-02-15 17:17:21 +0100654#if defined(CONFIG_DEBUG_TCG)
655 int used;
656#endif
bellardc896fe22008-02-01 10:05:41 +0000657} TCGOpDef;
Richard Henderson8399ad52011-08-17 14:11:45 -0700658
659extern TCGOpDef tcg_op_defs[];
Stefan Weil2a243742011-09-29 18:33:21 +0200660extern const size_t tcg_op_defs_max;
661
bellardc896fe22008-02-01 10:05:41 +0000662typedef struct TCGTargetOpDef {
Richard Hendersona9751602010-03-19 11:12:29 -0700663 TCGOpcode op;
bellardc896fe22008-02-01 10:05:41 +0000664 const char *args_ct_str[TCG_MAX_OP_ARGS];
665} TCGTargetOpDef;
666
bellardc896fe22008-02-01 10:05:41 +0000667#define tcg_abort() \
668do {\
669 fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
670 abort();\
671} while (0)
672
Richard Hendersonc552d6c2012-09-21 17:18:14 -0700673#ifdef CONFIG_DEBUG_TCG
674# define tcg_debug_assert(X) do { assert(X); } while (0)
675#elif QEMU_GNUC_PREREQ(4, 5)
676# define tcg_debug_assert(X) \
677 do { if (!(X)) { __builtin_unreachable(); } } while (0)
678#else
679# define tcg_debug_assert(X) do { (void)(X); } while (0)
680#endif
681
bellardc896fe22008-02-01 10:05:41 +0000682void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs);
683
Richard Henderson8b73d492013-08-20 15:07:08 -0700684#if UINTPTR_MAX == UINT32_MAX
Peter Maydellebecf362011-05-27 13:12:13 +0100685#define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I32(n))
686#define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n))
687
Richard Henderson8b73d492013-08-20 15:07:08 -0700688#define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V)))
Peter Maydellebecf362011-05-27 13:12:13 +0100689#define tcg_global_reg_new_ptr(R, N) \
690 TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N)))
691#define tcg_global_mem_new_ptr(R, O, N) \
692 TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N)))
693#define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32())
694#define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T))
bellardc896fe22008-02-01 10:05:41 +0000695#else
Peter Maydellebecf362011-05-27 13:12:13 +0100696#define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I64(n))
697#define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n))
698
Richard Henderson8b73d492013-08-20 15:07:08 -0700699#define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V)))
Peter Maydellebecf362011-05-27 13:12:13 +0100700#define tcg_global_reg_new_ptr(R, N) \
701 TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N)))
702#define tcg_global_mem_new_ptr(R, O, N) \
703 TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N)))
704#define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64())
705#define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T))
bellardc896fe22008-02-01 10:05:41 +0000706#endif
707
pbrooka7812ae2008-11-17 14:43:54 +0000708void tcg_gen_callN(TCGContext *s, TCGv_ptr func, unsigned int flags,
709 int sizemask, TCGArg ret, int nargs, TCGArg *args);
710
711void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
712 int c, int right, int arith);
713
Kirill Batuzov8f2e8c02011-07-07 16:37:12 +0400714TCGArg *tcg_optimize(TCGContext *s, uint16_t *tcg_opc_ptr, TCGArg *args,
715 TCGOpDef *tcg_op_def);
716
pbrooka7812ae2008-11-17 14:43:54 +0000717/* only used for debugging purposes */
Blue Swirleeacee42012-06-03 16:35:32 +0000718void tcg_dump_ops(TCGContext *s);
pbrooka7812ae2008-11-17 14:43:54 +0000719
720void dump_ops(const uint16_t *opc_buf, const TCGArg *opparam_buf);
721TCGv_i32 tcg_const_i32(int32_t val);
722TCGv_i64 tcg_const_i64(int64_t val);
723TCGv_i32 tcg_const_local_i32(int32_t val);
724TCGv_i64 tcg_const_local_i64(int64_t val);
725
Peter Maydell09800112013-02-22 18:10:00 +0000726/**
727 * tcg_qemu_tb_exec:
728 * @env: CPUArchState * for the CPU
729 * @tb_ptr: address of generated code for the TB to execute
730 *
731 * Start executing code from a given translation block.
732 * Where translation blocks have been linked, execution
733 * may proceed from the given TB into successive ones.
734 * Control eventually returns only when some action is needed
735 * from the top-level loop: either control must pass to a TB
736 * which has not yet been directly linked, or an asynchronous
737 * event such as an interrupt needs handling.
738 *
739 * The return value is a pointer to the next TB to execute
740 * (if known; otherwise zero). This pointer is assumed to be
741 * 4-aligned, and the bottom two bits are used to return further
742 * information:
743 * 0, 1: the link between this TB and the next is via the specified
744 * TB index (0 or 1). That is, we left the TB via (the equivalent
745 * of) "goto_tb <index>". The main loop uses this to determine
746 * how to link the TB just executed to the next.
747 * 2: we are using instruction counting code generation, and we
748 * did not start executing this TB because the instruction counter
749 * would hit zero midway through it. In this case the next-TB pointer
750 * returned is the TB we were about to execute, and the caller must
751 * arrange to execute the remaining count of instructions.
Peter Maydell378df4b2013-02-22 18:10:03 +0000752 * 3: we stopped because the CPU's exit_request flag was set
753 * (usually meaning that there is an interrupt that needs to be
754 * handled). The next-TB pointer returned is the TB we were
755 * about to execute when we noticed the pending exit request.
Peter Maydell09800112013-02-22 18:10:00 +0000756 *
757 * If the bottom two bits indicate an exit-via-index then the CPU
758 * state is correctly synchronised and ready for execution of the next
759 * TB (and in particular the guest PC is the address to execute next).
760 * Otherwise, we gave up on execution of this TB before it started, and
761 * the caller must fix up the CPU state by calling cpu_pc_from_tb()
762 * with the next-TB pointer we return.
763 *
764 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
765 * to this default (which just calls the prologue.code emitted by
766 * tcg_target_qemu_prologue()).
767 */
768#define TB_EXIT_MASK 3
769#define TB_EXIT_IDX0 0
770#define TB_EXIT_IDX1 1
771#define TB_EXIT_ICOUNT_EXPIRED 2
Peter Maydell378df4b2013-02-22 18:10:03 +0000772#define TB_EXIT_REQUESTED 3
Peter Maydell09800112013-02-22 18:10:00 +0000773
Stefan Weilce285b12011-09-30 21:23:06 +0200774#if !defined(tcg_qemu_tb_exec)
775# define tcg_qemu_tb_exec(env, tb_ptr) \
Richard Henderson04d5a1d2013-08-20 14:35:34 -0700776 ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr)
bellard932a6902008-05-30 20:56:52 +0000777#endif
Richard Henderson813da622012-03-19 12:25:11 -0700778
779void tcg_register_jit(void *buf, size_t buf_size);
Yeongkyoon Leeb76f0d82012-10-31 16:04:25 +0900780
Richard Hendersone58eb532013-08-27 13:13:44 -0700781/*
782 * Memory helpers that will be used by TCG generated code.
783 */
784#ifdef CONFIG_SOFTMMU
Richard Hendersonc8f94df2013-08-27 14:09:14 -0700785/* Value zero-extended to tcg register size. */
786tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
787 int mmu_idx, uintptr_t retaddr);
Richard Henderson867b3202013-09-04 11:45:20 -0700788tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
789 int mmu_idx, uintptr_t retaddr);
790tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
791 int mmu_idx, uintptr_t retaddr);
792uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
793 int mmu_idx, uintptr_t retaddr);
794tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
795 int mmu_idx, uintptr_t retaddr);
796tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
797 int mmu_idx, uintptr_t retaddr);
798uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
799 int mmu_idx, uintptr_t retaddr);
Richard Hendersone58eb532013-08-27 13:13:44 -0700800
Richard Hendersonc8f94df2013-08-27 14:09:14 -0700801/* Value sign-extended to tcg register size. */
802tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
803 int mmu_idx, uintptr_t retaddr);
Richard Henderson867b3202013-09-04 11:45:20 -0700804tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
805 int mmu_idx, uintptr_t retaddr);
806tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
807 int mmu_idx, uintptr_t retaddr);
808tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
809 int mmu_idx, uintptr_t retaddr);
810tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
811 int mmu_idx, uintptr_t retaddr);
Richard Hendersonc8f94df2013-08-27 14:09:14 -0700812
Richard Hendersone58eb532013-08-27 13:13:44 -0700813void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
814 int mmu_idx, uintptr_t retaddr);
Richard Henderson867b3202013-09-04 11:45:20 -0700815void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
816 int mmu_idx, uintptr_t retaddr);
817void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
818 int mmu_idx, uintptr_t retaddr);
819void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
820 int mmu_idx, uintptr_t retaddr);
821void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
822 int mmu_idx, uintptr_t retaddr);
823void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
824 int mmu_idx, uintptr_t retaddr);
825void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
826 int mmu_idx, uintptr_t retaddr);
827
828/* Temporary aliases until backends are converted. */
829#ifdef TARGET_WORDS_BIGENDIAN
830# define helper_ret_ldsw_mmu helper_be_ldsw_mmu
831# define helper_ret_lduw_mmu helper_be_lduw_mmu
832# define helper_ret_ldsl_mmu helper_be_ldsl_mmu
833# define helper_ret_ldul_mmu helper_be_ldul_mmu
834# define helper_ret_ldq_mmu helper_be_ldq_mmu
835# define helper_ret_stw_mmu helper_be_stw_mmu
836# define helper_ret_stl_mmu helper_be_stl_mmu
837# define helper_ret_stq_mmu helper_be_stq_mmu
838#else
839# define helper_ret_ldsw_mmu helper_le_ldsw_mmu
840# define helper_ret_lduw_mmu helper_le_lduw_mmu
841# define helper_ret_ldsl_mmu helper_le_ldsl_mmu
842# define helper_ret_ldul_mmu helper_le_ldul_mmu
843# define helper_ret_ldq_mmu helper_le_ldq_mmu
844# define helper_ret_stw_mmu helper_le_stw_mmu
845# define helper_ret_stl_mmu helper_le_stl_mmu
846# define helper_ret_stq_mmu helper_le_stq_mmu
847#endif
Richard Hendersone58eb532013-08-27 13:13:44 -0700848
849uint8_t helper_ldb_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
850uint16_t helper_ldw_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
851uint32_t helper_ldl_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
852uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
853
854void helper_stb_mmu(CPUArchState *env, target_ulong addr,
855 uint8_t val, int mmu_idx);
856void helper_stw_mmu(CPUArchState *env, target_ulong addr,
857 uint16_t val, int mmu_idx);
858void helper_stl_mmu(CPUArchState *env, target_ulong addr,
859 uint32_t val, int mmu_idx);
860void helper_stq_mmu(CPUArchState *env, target_ulong addr,
861 uint64_t val, int mmu_idx);
862#endif /* CONFIG_SOFTMMU */
863
864#endif /* TCG_H */