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balrogc1713132007-04-30 01:26:42 +00001/*
2 * Intel XScale PXA255/270 GPIO controller emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
Peter Maydell12b16722015-12-07 16:23:45 +000010#include "qemu/osdep.h"
Paolo Bonzini33c11872016-03-15 16:58:45 +010011#include "cpu.h"
Markus Armbruster64552b62019-08-12 07:23:42 +020012#include "hw/irq.h"
Markus Armbrustera27bd6c2019-08-12 07:23:51 +020013#include "hw/qdev-properties.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010014#include "hw/sysbus.h"
Markus Armbrusterd6454272019-08-12 07:23:45 +020015#include "migration/vmstate.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010016#include "hw/arm/pxa.h"
Markus Armbruster3e80f692020-06-10 07:31:58 +020017#include "qapi/error.h"
Paolo Bonzini03dd0242015-12-15 13:16:16 +010018#include "qemu/log.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020019#include "qemu/module.h"
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040020#include "qom/object.h"
balrogc1713132007-04-30 01:26:42 +000021
22#define PXA2XX_GPIO_BANKS 4
23
Andreas Färber922bb312013-07-24 02:03:39 +020024#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
Eduardo Habkost80633962020-09-16 14:25:19 -040025OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxGPIOInfo, PXA2XX_GPIO)
Andreas Färber922bb312013-07-24 02:03:39 +020026
Paul Brookbc24a222009-05-10 01:44:56 +010027struct PXA2xxGPIOInfo {
Andreas Färber922bb312013-07-24 02:03:39 +020028 /*< private >*/
29 SysBusDevice parent_obj;
30 /*< public >*/
31
Benoît Canet55a8b802011-10-30 14:50:11 +010032 MemoryRegion iomem;
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030033 qemu_irq irq0, irq1, irqX;
balrogc1713132007-04-30 01:26:42 +000034 int lines;
Andreas Färber95d42bb2012-05-04 00:23:14 +020035 ARMCPU *cpu;
balrogc1713132007-04-30 01:26:42 +000036
37 /* XXX: GNU C vectors are more suitable */
38 uint32_t ilevel[PXA2XX_GPIO_BANKS];
39 uint32_t olevel[PXA2XX_GPIO_BANKS];
40 uint32_t dir[PXA2XX_GPIO_BANKS];
41 uint32_t rising[PXA2XX_GPIO_BANKS];
42 uint32_t falling[PXA2XX_GPIO_BANKS];
43 uint32_t status[PXA2XX_GPIO_BANKS];
44 uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
45
46 uint32_t prev_level[PXA2XX_GPIO_BANKS];
balrog38641a52007-11-17 14:07:13 +000047 qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
48 qemu_irq read_notify;
balrogc1713132007-04-30 01:26:42 +000049};
50
51static struct {
52 enum {
53 GPIO_NONE,
54 GPLR,
55 GPSR,
56 GPCR,
57 GPDR,
58 GRER,
59 GFER,
60 GEDR,
61 GAFR_L,
62 GAFR_U,
63 } reg;
64 int bank;
65} pxa2xx_gpio_regs[0x200] = {
66 [0 ... 0x1ff] = { GPIO_NONE, 0 },
67#define PXA2XX_REG(reg, a0, a1, a2, a3) \
ths5fafdf22007-09-16 21:08:06 +000068 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
balrogc1713132007-04-30 01:26:42 +000069
70 PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
71 PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
72 PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
73 PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
74 PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
75 PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
76 PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
77 PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
78 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
79};
80
Paul Brookbc24a222009-05-10 01:44:56 +010081static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
balrogc1713132007-04-30 01:26:42 +000082{
83 if (s->status[0] & (1 << 0))
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030084 qemu_irq_raise(s->irq0);
balrogc1713132007-04-30 01:26:42 +000085 else
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030086 qemu_irq_lower(s->irq0);
balrogc1713132007-04-30 01:26:42 +000087
88 if (s->status[0] & (1 << 1))
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030089 qemu_irq_raise(s->irq1);
balrogc1713132007-04-30 01:26:42 +000090 else
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030091 qemu_irq_lower(s->irq1);
balrogc1713132007-04-30 01:26:42 +000092
93 if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030094 qemu_irq_raise(s->irqX);
balrogc1713132007-04-30 01:26:42 +000095 else
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030096 qemu_irq_lower(s->irqX);
balrogc1713132007-04-30 01:26:42 +000097}
98
99/* Bitmap of pins used as standby and sleep wake-up sources. */
balrog38641a52007-11-17 14:07:13 +0000100static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
balrogc1713132007-04-30 01:26:42 +0000101 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
102};
103
balrog38641a52007-11-17 14:07:13 +0000104static void pxa2xx_gpio_set(void *opaque, int line, int level)
balrogc1713132007-04-30 01:26:42 +0000105{
Paul Brookbc24a222009-05-10 01:44:56 +0100106 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
Andreas Färber259186a2013-01-17 18:51:17 +0100107 CPUState *cpu = CPU(s->cpu);
balrogc1713132007-04-30 01:26:42 +0000108 int bank;
109 uint32_t mask;
110
111 if (line >= s->lines) {
Alistair Francisa89f3642017-11-08 14:56:31 -0800112 printf("%s: No GPIO pin %i\n", __func__, line);
balrogc1713132007-04-30 01:26:42 +0000113 return;
114 }
115
116 bank = line >> 5;
Peter Maydell43a32ed2014-03-10 14:56:29 +0000117 mask = 1U << (line & 31);
balrogc1713132007-04-30 01:26:42 +0000118
119 if (level) {
120 s->status[bank] |= s->rising[bank] & mask &
121 ~s->ilevel[bank] & ~s->dir[bank];
122 s->ilevel[bank] |= mask;
123 } else {
124 s->status[bank] |= s->falling[bank] & mask &
125 s->ilevel[bank] & ~s->dir[bank];
126 s->ilevel[bank] &= ~mask;
127 }
128
129 if (s->status[bank] & mask)
130 pxa2xx_gpio_irq_update(s);
131
132 /* Wake-up GPIOs */
Andreas Färber259186a2013-01-17 18:51:17 +0100133 if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
Andreas Färberc3affe52013-01-18 15:03:43 +0100134 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
Andreas Färber95d42bb2012-05-04 00:23:14 +0200135 }
balrogc1713132007-04-30 01:26:42 +0000136}
137
Paul Brookbc24a222009-05-10 01:44:56 +0100138static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
balrogc1713132007-04-30 01:26:42 +0000139 uint32_t level, diff;
140 int i, bit, line;
141 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
142 level = s->olevel[i] & s->dir[i];
143
144 for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
Stefan Hajnoczi786a4ea2015-03-23 15:29:26 +0000145 bit = ctz32(diff);
balrogc1713132007-04-30 01:26:42 +0000146 line = bit + 32 * i;
balrog38641a52007-11-17 14:07:13 +0000147 qemu_set_irq(s->handler[line], (level >> bit) & 1);
balrogc1713132007-04-30 01:26:42 +0000148 }
149
150 s->prev_level[i] = level;
151 }
152}
153
Avi Kivitya8170e52012-10-23 12:30:10 +0200154static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
Benoît Canet55a8b802011-10-30 14:50:11 +0100155 unsigned size)
balrogc1713132007-04-30 01:26:42 +0000156{
Paul Brookbc24a222009-05-10 01:44:56 +0100157 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
balrogc1713132007-04-30 01:26:42 +0000158 uint32_t ret;
159 int bank;
balrogc1713132007-04-30 01:26:42 +0000160 if (offset >= 0x200)
161 return 0;
162
163 bank = pxa2xx_gpio_regs[offset].bank;
164 switch (pxa2xx_gpio_regs[offset].reg) {
165 case GPDR: /* GPIO Pin-Direction registers */
166 return s->dir[bank];
167
balrog2b76bdc2007-10-04 19:41:17 +0000168 case GPSR: /* GPIO Pin-Output Set registers */
Peter Maydellab7a0f02014-06-29 18:38:40 +0100169 qemu_log_mask(LOG_GUEST_ERROR,
170 "pxa2xx GPIO: read from write only register GPSR\n");
171 return 0;
balrog2b76bdc2007-10-04 19:41:17 +0000172
balroge1dad5a2007-11-17 18:43:47 +0000173 case GPCR: /* GPIO Pin-Output Clear registers */
Peter Maydellab7a0f02014-06-29 18:38:40 +0100174 qemu_log_mask(LOG_GUEST_ERROR,
175 "pxa2xx GPIO: read from write only register GPCR\n");
176 return 0;
balroge1dad5a2007-11-17 18:43:47 +0000177
balrogc1713132007-04-30 01:26:42 +0000178 case GRER: /* GPIO Rising-Edge Detect Enable registers */
179 return s->rising[bank];
180
181 case GFER: /* GPIO Falling-Edge Detect Enable registers */
182 return s->falling[bank];
183
184 case GAFR_L: /* GPIO Alternate Function registers */
185 return s->gafr[bank * 2];
186
187 case GAFR_U: /* GPIO Alternate Function registers */
188 return s->gafr[bank * 2 + 1];
189
190 case GPLR: /* GPIO Pin-Level registers */
191 ret = (s->olevel[bank] & s->dir[bank]) |
192 (s->ilevel[bank] & ~s->dir[bank]);
balrog38641a52007-11-17 14:07:13 +0000193 qemu_irq_raise(s->read_notify);
balrogc1713132007-04-30 01:26:42 +0000194 return ret;
195
196 case GEDR: /* GPIO Edge Detect Status registers */
197 return s->status[bank];
198
199 default:
Philippe Mathieu-Daudé5a0001e2020-05-18 16:03:07 +0200200 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
201 __func__, offset);
balrogc1713132007-04-30 01:26:42 +0000202 }
203
204 return 0;
205}
206
Avi Kivitya8170e52012-10-23 12:30:10 +0200207static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
Benoît Canet55a8b802011-10-30 14:50:11 +0100208 uint64_t value, unsigned size)
balrogc1713132007-04-30 01:26:42 +0000209{
Paul Brookbc24a222009-05-10 01:44:56 +0100210 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
balrogc1713132007-04-30 01:26:42 +0000211 int bank;
balrogc1713132007-04-30 01:26:42 +0000212 if (offset >= 0x200)
213 return;
214
215 bank = pxa2xx_gpio_regs[offset].bank;
216 switch (pxa2xx_gpio_regs[offset].reg) {
217 case GPDR: /* GPIO Pin-Direction registers */
218 s->dir[bank] = value;
219 pxa2xx_gpio_handler_update(s);
220 break;
221
222 case GPSR: /* GPIO Pin-Output Set registers */
223 s->olevel[bank] |= value;
224 pxa2xx_gpio_handler_update(s);
225 break;
226
227 case GPCR: /* GPIO Pin-Output Clear registers */
228 s->olevel[bank] &= ~value;
229 pxa2xx_gpio_handler_update(s);
230 break;
231
232 case GRER: /* GPIO Rising-Edge Detect Enable registers */
233 s->rising[bank] = value;
234 break;
235
236 case GFER: /* GPIO Falling-Edge Detect Enable registers */
237 s->falling[bank] = value;
238 break;
239
240 case GAFR_L: /* GPIO Alternate Function registers */
241 s->gafr[bank * 2] = value;
242 break;
243
244 case GAFR_U: /* GPIO Alternate Function registers */
245 s->gafr[bank * 2 + 1] = value;
246 break;
247
248 case GEDR: /* GPIO Edge Detect Status registers */
249 s->status[bank] &= ~value;
250 pxa2xx_gpio_irq_update(s);
251 break;
252
253 default:
Philippe Mathieu-Daudé5a0001e2020-05-18 16:03:07 +0200254 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
255 __func__, offset);
balrogc1713132007-04-30 01:26:42 +0000256 }
257}
258
Benoît Canet55a8b802011-10-30 14:50:11 +0100259static const MemoryRegionOps pxa_gpio_ops = {
260 .read = pxa2xx_gpio_read,
261 .write = pxa2xx_gpio_write,
262 .endianness = DEVICE_NATIVE_ENDIAN,
balrogc1713132007-04-30 01:26:42 +0000263};
264
Avi Kivitya8170e52012-10-23 12:30:10 +0200265DeviceState *pxa2xx_gpio_init(hwaddr base,
Andreas Färber55e5c282012-12-17 06:18:02 +0100266 ARMCPU *cpu, DeviceState *pic, int lines)
balrogc1713132007-04-30 01:26:42 +0000267{
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300268 DeviceState *dev;
269
Markus Armbruster3e80f692020-06-10 07:31:58 +0200270 dev = qdev_new(TYPE_PXA2XX_GPIO);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300271 qdev_prop_set_int32(dev, "lines", lines);
Philippe Mathieu-Daudé7df9a222023-10-30 09:37:05 +0100272 object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
Markus Armbruster3c6ef472020-06-10 07:32:34 +0200273 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300274
Andreas Färber1356b982013-01-20 02:47:33 +0100275 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
276 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
Dmitry Eremin-Solenikove1f8c722011-02-25 12:13:38 +0100277 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
Andreas Färber1356b982013-01-20 02:47:33 +0100278 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
Dmitry Eremin-Solenikove1f8c722011-02-25 12:13:38 +0100279 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
Andreas Färber1356b982013-01-20 02:47:33 +0100280 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
Dmitry Eremin-Solenikove1f8c722011-02-25 12:13:38 +0100281 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300282
283 return dev;
284}
285
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100286static void pxa2xx_gpio_initfn(Object *obj)
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300287{
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100288 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
Andreas Färber922bb312013-07-24 02:03:39 +0200289 DeviceState *dev = DEVICE(sbd);
290 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300291
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100292 memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
293 s, "pxa2xx-gpio", 0x1000);
294 sysbus_init_mmio(sbd, &s->iomem);
295 sysbus_init_irq(sbd, &s->irq0);
296 sysbus_init_irq(sbd, &s->irq1);
297 sysbus_init_irq(sbd, &s->irqX);
298}
299
300static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
301{
302 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
303
Andreas Färber922bb312013-07-24 02:03:39 +0200304 qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
305 qdev_init_gpio_out(dev, s->handler, s->lines);
balrogc1713132007-04-30 01:26:42 +0000306}
307
308/*
309 * Registers a callback to notify on GPLR reads. This normally
310 * shouldn't be needed but it is used for the hack on Spitz machines.
311 */
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300312void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
balrog38641a52007-11-17 14:07:13 +0000313{
Andreas Färber922bb312013-07-24 02:03:39 +0200314 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
315
balrogc1713132007-04-30 01:26:42 +0000316 s->read_notify = handler;
balrogc1713132007-04-30 01:26:42 +0000317}
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300318
319static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
320 .name = "pxa2xx-gpio",
321 .version_id = 1,
322 .minimum_version_id = 1,
Richard Henderson607ef572023-12-21 14:15:59 +1100323 .fields = (const VMStateField[]) {
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300324 VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
325 VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
326 VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
327 VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
328 VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
329 VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
330 VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
Peter Maydell166fa992014-06-29 18:38:40 +0100331 VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300332 VMSTATE_END_OF_LIST(),
333 },
334};
335
Anthony Liguori999e12b2012-01-24 13:12:29 -0600336static Property pxa2xx_gpio_properties[] = {
337 DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
Philippe Mathieu-Daudé7df9a222023-10-30 09:37:05 +0100338 DEFINE_PROP_LINK("cpu", PXA2xxGPIOInfo, cpu, TYPE_ARM_CPU, ARMCPU *),
Anthony Liguori999e12b2012-01-24 13:12:29 -0600339 DEFINE_PROP_END_OF_LIST(),
340};
341
342static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
343{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600344 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600345
Anthony Liguori39bffca2011-12-07 21:34:16 -0600346 dc->desc = "PXA2xx GPIO controller";
Marc-André Lureau4f67d302020-01-10 19:30:32 +0400347 device_class_set_props(dc, pxa2xx_gpio_properties);
Peter Maydell166fa992014-06-29 18:38:40 +0100348 dc->vmsd = &vmstate_pxa2xx_gpio_regs;
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100349 dc->realize = pxa2xx_gpio_realize;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600350}
351
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100352static const TypeInfo pxa2xx_gpio_info = {
Andreas Färber922bb312013-07-24 02:03:39 +0200353 .name = TYPE_PXA2XX_GPIO,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600354 .parent = TYPE_SYS_BUS_DEVICE,
355 .instance_size = sizeof(PXA2xxGPIOInfo),
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100356 .instance_init = pxa2xx_gpio_initfn,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600357 .class_init = pxa2xx_gpio_class_init,
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300358};
359
Andreas Färber83f7d432012-02-09 15:20:55 +0100360static void pxa2xx_gpio_register_types(void)
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300361{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600362 type_register_static(&pxa2xx_gpio_info);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300363}
Andreas Färber83f7d432012-02-09 15:20:55 +0100364
365type_init(pxa2xx_gpio_register_types)