balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Intel XScale PXA255/270 GPIO controller emulation. |
| 3 | * |
| 4 | * Copyright (c) 2006 Openedhand Ltd. |
| 5 | * Written by Andrzej Zaborowski <balrog@zabor.org> |
| 6 | * |
| 7 | * This code is licensed under the GPL. |
| 8 | */ |
| 9 | |
Peter Maydell | 12b1672 | 2015-12-07 16:23:45 +0000 | [diff] [blame] | 10 | #include "qemu/osdep.h" |
Paolo Bonzini | 33c1187 | 2016-03-15 16:58:45 +0100 | [diff] [blame] | 11 | #include "cpu.h" |
Markus Armbruster | 64552b6 | 2019-08-12 07:23:42 +0200 | [diff] [blame] | 12 | #include "hw/irq.h" |
Markus Armbruster | a27bd6c | 2019-08-12 07:23:51 +0200 | [diff] [blame] | 13 | #include "hw/qdev-properties.h" |
Paolo Bonzini | 83c9f4c | 2013-02-04 15:40:22 +0100 | [diff] [blame] | 14 | #include "hw/sysbus.h" |
Markus Armbruster | d645427 | 2019-08-12 07:23:45 +0200 | [diff] [blame] | 15 | #include "migration/vmstate.h" |
Paolo Bonzini | 0d09e41 | 2013-02-05 17:06:20 +0100 | [diff] [blame] | 16 | #include "hw/arm/pxa.h" |
Markus Armbruster | 3e80f69 | 2020-06-10 07:31:58 +0200 | [diff] [blame] | 17 | #include "qapi/error.h" |
Paolo Bonzini | 03dd024 | 2015-12-15 13:16:16 +0100 | [diff] [blame] | 18 | #include "qemu/log.h" |
Markus Armbruster | 0b8fa32 | 2019-05-23 16:35:07 +0200 | [diff] [blame] | 19 | #include "qemu/module.h" |
Eduardo Habkost | db1015e | 2020-09-03 16:43:22 -0400 | [diff] [blame] | 20 | #include "qom/object.h" |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 21 | |
| 22 | #define PXA2XX_GPIO_BANKS 4 |
| 23 | |
Andreas Färber | 922bb31 | 2013-07-24 02:03:39 +0200 | [diff] [blame] | 24 | #define TYPE_PXA2XX_GPIO "pxa2xx-gpio" |
Eduardo Habkost | 8063396 | 2020-09-16 14:25:19 -0400 | [diff] [blame] | 25 | OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxGPIOInfo, PXA2XX_GPIO) |
Andreas Färber | 922bb31 | 2013-07-24 02:03:39 +0200 | [diff] [blame] | 26 | |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 27 | struct PXA2xxGPIOInfo { |
Andreas Färber | 922bb31 | 2013-07-24 02:03:39 +0200 | [diff] [blame] | 28 | /*< private >*/ |
| 29 | SysBusDevice parent_obj; |
| 30 | /*< public >*/ |
| 31 | |
Benoît Canet | 55a8b80 | 2011-10-30 14:50:11 +0100 | [diff] [blame] | 32 | MemoryRegion iomem; |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 33 | qemu_irq irq0, irq1, irqX; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 34 | int lines; |
Andreas Färber | 95d42bb | 2012-05-04 00:23:14 +0200 | [diff] [blame] | 35 | ARMCPU *cpu; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 36 | |
| 37 | /* XXX: GNU C vectors are more suitable */ |
| 38 | uint32_t ilevel[PXA2XX_GPIO_BANKS]; |
| 39 | uint32_t olevel[PXA2XX_GPIO_BANKS]; |
| 40 | uint32_t dir[PXA2XX_GPIO_BANKS]; |
| 41 | uint32_t rising[PXA2XX_GPIO_BANKS]; |
| 42 | uint32_t falling[PXA2XX_GPIO_BANKS]; |
| 43 | uint32_t status[PXA2XX_GPIO_BANKS]; |
| 44 | uint32_t gafr[PXA2XX_GPIO_BANKS * 2]; |
| 45 | |
| 46 | uint32_t prev_level[PXA2XX_GPIO_BANKS]; |
balrog | 38641a5 | 2007-11-17 14:07:13 +0000 | [diff] [blame] | 47 | qemu_irq handler[PXA2XX_GPIO_BANKS * 32]; |
| 48 | qemu_irq read_notify; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 49 | }; |
| 50 | |
| 51 | static struct { |
| 52 | enum { |
| 53 | GPIO_NONE, |
| 54 | GPLR, |
| 55 | GPSR, |
| 56 | GPCR, |
| 57 | GPDR, |
| 58 | GRER, |
| 59 | GFER, |
| 60 | GEDR, |
| 61 | GAFR_L, |
| 62 | GAFR_U, |
| 63 | } reg; |
| 64 | int bank; |
| 65 | } pxa2xx_gpio_regs[0x200] = { |
| 66 | [0 ... 0x1ff] = { GPIO_NONE, 0 }, |
| 67 | #define PXA2XX_REG(reg, a0, a1, a2, a3) \ |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 68 | [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 }, |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 69 | |
| 70 | PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100) |
| 71 | PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118) |
| 72 | PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124) |
| 73 | PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c) |
| 74 | PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130) |
| 75 | PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c) |
| 76 | PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148) |
| 77 | PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c) |
| 78 | PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070) |
| 79 | }; |
| 80 | |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 81 | static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s) |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 82 | { |
| 83 | if (s->status[0] & (1 << 0)) |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 84 | qemu_irq_raise(s->irq0); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 85 | else |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 86 | qemu_irq_lower(s->irq0); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 87 | |
| 88 | if (s->status[0] & (1 << 1)) |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 89 | qemu_irq_raise(s->irq1); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 90 | else |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 91 | qemu_irq_lower(s->irq1); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 92 | |
| 93 | if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3]) |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 94 | qemu_irq_raise(s->irqX); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 95 | else |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 96 | qemu_irq_lower(s->irqX); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 97 | } |
| 98 | |
| 99 | /* Bitmap of pins used as standby and sleep wake-up sources. */ |
balrog | 38641a5 | 2007-11-17 14:07:13 +0000 | [diff] [blame] | 100 | static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = { |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 101 | 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f, |
| 102 | }; |
| 103 | |
balrog | 38641a5 | 2007-11-17 14:07:13 +0000 | [diff] [blame] | 104 | static void pxa2xx_gpio_set(void *opaque, int line, int level) |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 105 | { |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 106 | PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 107 | CPUState *cpu = CPU(s->cpu); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 108 | int bank; |
| 109 | uint32_t mask; |
| 110 | |
| 111 | if (line >= s->lines) { |
Alistair Francis | a89f364 | 2017-11-08 14:56:31 -0800 | [diff] [blame] | 112 | printf("%s: No GPIO pin %i\n", __func__, line); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 113 | return; |
| 114 | } |
| 115 | |
| 116 | bank = line >> 5; |
Peter Maydell | 43a32ed | 2014-03-10 14:56:29 +0000 | [diff] [blame] | 117 | mask = 1U << (line & 31); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 118 | |
| 119 | if (level) { |
| 120 | s->status[bank] |= s->rising[bank] & mask & |
| 121 | ~s->ilevel[bank] & ~s->dir[bank]; |
| 122 | s->ilevel[bank] |= mask; |
| 123 | } else { |
| 124 | s->status[bank] |= s->falling[bank] & mask & |
| 125 | s->ilevel[bank] & ~s->dir[bank]; |
| 126 | s->ilevel[bank] &= ~mask; |
| 127 | } |
| 128 | |
| 129 | if (s->status[bank] & mask) |
| 130 | pxa2xx_gpio_irq_update(s); |
| 131 | |
| 132 | /* Wake-up GPIOs */ |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 133 | if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) { |
Andreas Färber | c3affe5 | 2013-01-18 15:03:43 +0100 | [diff] [blame] | 134 | cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB); |
Andreas Färber | 95d42bb | 2012-05-04 00:23:14 +0200 | [diff] [blame] | 135 | } |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 136 | } |
| 137 | |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 138 | static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) { |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 139 | uint32_t level, diff; |
| 140 | int i, bit, line; |
| 141 | for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) { |
| 142 | level = s->olevel[i] & s->dir[i]; |
| 143 | |
| 144 | for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) { |
Stefan Hajnoczi | 786a4ea | 2015-03-23 15:29:26 +0000 | [diff] [blame] | 145 | bit = ctz32(diff); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 146 | line = bit + 32 * i; |
balrog | 38641a5 | 2007-11-17 14:07:13 +0000 | [diff] [blame] | 147 | qemu_set_irq(s->handler[line], (level >> bit) & 1); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 148 | } |
| 149 | |
| 150 | s->prev_level[i] = level; |
| 151 | } |
| 152 | } |
| 153 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 154 | static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset, |
Benoît Canet | 55a8b80 | 2011-10-30 14:50:11 +0100 | [diff] [blame] | 155 | unsigned size) |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 156 | { |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 157 | PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 158 | uint32_t ret; |
| 159 | int bank; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 160 | if (offset >= 0x200) |
| 161 | return 0; |
| 162 | |
| 163 | bank = pxa2xx_gpio_regs[offset].bank; |
| 164 | switch (pxa2xx_gpio_regs[offset].reg) { |
| 165 | case GPDR: /* GPIO Pin-Direction registers */ |
| 166 | return s->dir[bank]; |
| 167 | |
balrog | 2b76bdc | 2007-10-04 19:41:17 +0000 | [diff] [blame] | 168 | case GPSR: /* GPIO Pin-Output Set registers */ |
Peter Maydell | ab7a0f0 | 2014-06-29 18:38:40 +0100 | [diff] [blame] | 169 | qemu_log_mask(LOG_GUEST_ERROR, |
| 170 | "pxa2xx GPIO: read from write only register GPSR\n"); |
| 171 | return 0; |
balrog | 2b76bdc | 2007-10-04 19:41:17 +0000 | [diff] [blame] | 172 | |
balrog | e1dad5a | 2007-11-17 18:43:47 +0000 | [diff] [blame] | 173 | case GPCR: /* GPIO Pin-Output Clear registers */ |
Peter Maydell | ab7a0f0 | 2014-06-29 18:38:40 +0100 | [diff] [blame] | 174 | qemu_log_mask(LOG_GUEST_ERROR, |
| 175 | "pxa2xx GPIO: read from write only register GPCR\n"); |
| 176 | return 0; |
balrog | e1dad5a | 2007-11-17 18:43:47 +0000 | [diff] [blame] | 177 | |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 178 | case GRER: /* GPIO Rising-Edge Detect Enable registers */ |
| 179 | return s->rising[bank]; |
| 180 | |
| 181 | case GFER: /* GPIO Falling-Edge Detect Enable registers */ |
| 182 | return s->falling[bank]; |
| 183 | |
| 184 | case GAFR_L: /* GPIO Alternate Function registers */ |
| 185 | return s->gafr[bank * 2]; |
| 186 | |
| 187 | case GAFR_U: /* GPIO Alternate Function registers */ |
| 188 | return s->gafr[bank * 2 + 1]; |
| 189 | |
| 190 | case GPLR: /* GPIO Pin-Level registers */ |
| 191 | ret = (s->olevel[bank] & s->dir[bank]) | |
| 192 | (s->ilevel[bank] & ~s->dir[bank]); |
balrog | 38641a5 | 2007-11-17 14:07:13 +0000 | [diff] [blame] | 193 | qemu_irq_raise(s->read_notify); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 194 | return ret; |
| 195 | |
| 196 | case GEDR: /* GPIO Edge Detect Status registers */ |
| 197 | return s->status[bank]; |
| 198 | |
| 199 | default: |
Philippe Mathieu-Daudé | 5a0001e | 2020-05-18 16:03:07 +0200 | [diff] [blame] | 200 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", |
| 201 | __func__, offset); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 202 | } |
| 203 | |
| 204 | return 0; |
| 205 | } |
| 206 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 207 | static void pxa2xx_gpio_write(void *opaque, hwaddr offset, |
Benoît Canet | 55a8b80 | 2011-10-30 14:50:11 +0100 | [diff] [blame] | 208 | uint64_t value, unsigned size) |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 209 | { |
Paul Brook | bc24a22 | 2009-05-10 01:44:56 +0100 | [diff] [blame] | 210 | PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 211 | int bank; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 212 | if (offset >= 0x200) |
| 213 | return; |
| 214 | |
| 215 | bank = pxa2xx_gpio_regs[offset].bank; |
| 216 | switch (pxa2xx_gpio_regs[offset].reg) { |
| 217 | case GPDR: /* GPIO Pin-Direction registers */ |
| 218 | s->dir[bank] = value; |
| 219 | pxa2xx_gpio_handler_update(s); |
| 220 | break; |
| 221 | |
| 222 | case GPSR: /* GPIO Pin-Output Set registers */ |
| 223 | s->olevel[bank] |= value; |
| 224 | pxa2xx_gpio_handler_update(s); |
| 225 | break; |
| 226 | |
| 227 | case GPCR: /* GPIO Pin-Output Clear registers */ |
| 228 | s->olevel[bank] &= ~value; |
| 229 | pxa2xx_gpio_handler_update(s); |
| 230 | break; |
| 231 | |
| 232 | case GRER: /* GPIO Rising-Edge Detect Enable registers */ |
| 233 | s->rising[bank] = value; |
| 234 | break; |
| 235 | |
| 236 | case GFER: /* GPIO Falling-Edge Detect Enable registers */ |
| 237 | s->falling[bank] = value; |
| 238 | break; |
| 239 | |
| 240 | case GAFR_L: /* GPIO Alternate Function registers */ |
| 241 | s->gafr[bank * 2] = value; |
| 242 | break; |
| 243 | |
| 244 | case GAFR_U: /* GPIO Alternate Function registers */ |
| 245 | s->gafr[bank * 2 + 1] = value; |
| 246 | break; |
| 247 | |
| 248 | case GEDR: /* GPIO Edge Detect Status registers */ |
| 249 | s->status[bank] &= ~value; |
| 250 | pxa2xx_gpio_irq_update(s); |
| 251 | break; |
| 252 | |
| 253 | default: |
Philippe Mathieu-Daudé | 5a0001e | 2020-05-18 16:03:07 +0200 | [diff] [blame] | 254 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", |
| 255 | __func__, offset); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 256 | } |
| 257 | } |
| 258 | |
Benoît Canet | 55a8b80 | 2011-10-30 14:50:11 +0100 | [diff] [blame] | 259 | static const MemoryRegionOps pxa_gpio_ops = { |
| 260 | .read = pxa2xx_gpio_read, |
| 261 | .write = pxa2xx_gpio_write, |
| 262 | .endianness = DEVICE_NATIVE_ENDIAN, |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 263 | }; |
| 264 | |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 265 | DeviceState *pxa2xx_gpio_init(hwaddr base, |
Andreas Färber | 55e5c28 | 2012-12-17 06:18:02 +0100 | [diff] [blame] | 266 | ARMCPU *cpu, DeviceState *pic, int lines) |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 267 | { |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 268 | DeviceState *dev; |
| 269 | |
Markus Armbruster | 3e80f69 | 2020-06-10 07:31:58 +0200 | [diff] [blame] | 270 | dev = qdev_new(TYPE_PXA2XX_GPIO); |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 271 | qdev_prop_set_int32(dev, "lines", lines); |
Philippe Mathieu-Daudé | 7df9a22 | 2023-10-30 09:37:05 +0100 | [diff] [blame] | 272 | object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); |
Markus Armbruster | 3c6ef47 | 2020-06-10 07:32:34 +0200 | [diff] [blame] | 273 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 274 | |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 275 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); |
| 276 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, |
Dmitry Eremin-Solenikov | e1f8c72 | 2011-02-25 12:13:38 +0100 | [diff] [blame] | 277 | qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0)); |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 278 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, |
Dmitry Eremin-Solenikov | e1f8c72 | 2011-02-25 12:13:38 +0100 | [diff] [blame] | 279 | qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1)); |
Andreas Färber | 1356b98 | 2013-01-20 02:47:33 +0100 | [diff] [blame] | 280 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, |
Dmitry Eremin-Solenikov | e1f8c72 | 2011-02-25 12:13:38 +0100 | [diff] [blame] | 281 | qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X)); |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 282 | |
| 283 | return dev; |
| 284 | } |
| 285 | |
xiaoqiang zhao | f79a7ff | 2016-10-24 16:26:55 +0100 | [diff] [blame] | 286 | static void pxa2xx_gpio_initfn(Object *obj) |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 287 | { |
xiaoqiang zhao | f79a7ff | 2016-10-24 16:26:55 +0100 | [diff] [blame] | 288 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
Andreas Färber | 922bb31 | 2013-07-24 02:03:39 +0200 | [diff] [blame] | 289 | DeviceState *dev = DEVICE(sbd); |
| 290 | PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 291 | |
xiaoqiang zhao | f79a7ff | 2016-10-24 16:26:55 +0100 | [diff] [blame] | 292 | memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops, |
| 293 | s, "pxa2xx-gpio", 0x1000); |
| 294 | sysbus_init_mmio(sbd, &s->iomem); |
| 295 | sysbus_init_irq(sbd, &s->irq0); |
| 296 | sysbus_init_irq(sbd, &s->irq1); |
| 297 | sysbus_init_irq(sbd, &s->irqX); |
| 298 | } |
| 299 | |
| 300 | static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp) |
| 301 | { |
| 302 | PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); |
| 303 | |
Andreas Färber | 922bb31 | 2013-07-24 02:03:39 +0200 | [diff] [blame] | 304 | qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines); |
| 305 | qdev_init_gpio_out(dev, s->handler, s->lines); |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 306 | } |
| 307 | |
| 308 | /* |
| 309 | * Registers a callback to notify on GPLR reads. This normally |
| 310 | * shouldn't be needed but it is used for the hack on Spitz machines. |
| 311 | */ |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 312 | void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler) |
balrog | 38641a5 | 2007-11-17 14:07:13 +0000 | [diff] [blame] | 313 | { |
Andreas Färber | 922bb31 | 2013-07-24 02:03:39 +0200 | [diff] [blame] | 314 | PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev); |
| 315 | |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 316 | s->read_notify = handler; |
balrog | c171313 | 2007-04-30 01:26:42 +0000 | [diff] [blame] | 317 | } |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 318 | |
| 319 | static const VMStateDescription vmstate_pxa2xx_gpio_regs = { |
| 320 | .name = "pxa2xx-gpio", |
| 321 | .version_id = 1, |
| 322 | .minimum_version_id = 1, |
Richard Henderson | 607ef57 | 2023-12-21 14:15:59 +1100 | [diff] [blame] | 323 | .fields = (const VMStateField[]) { |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 324 | VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
| 325 | VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
| 326 | VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
| 327 | VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
| 328 | VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
| 329 | VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
| 330 | VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2), |
Peter Maydell | 166fa99 | 2014-06-29 18:38:40 +0100 | [diff] [blame] | 331 | VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS), |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 332 | VMSTATE_END_OF_LIST(), |
| 333 | }, |
| 334 | }; |
| 335 | |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 336 | static Property pxa2xx_gpio_properties[] = { |
| 337 | DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0), |
Philippe Mathieu-Daudé | 7df9a22 | 2023-10-30 09:37:05 +0100 | [diff] [blame] | 338 | DEFINE_PROP_LINK("cpu", PXA2xxGPIOInfo, cpu, TYPE_ARM_CPU, ARMCPU *), |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 339 | DEFINE_PROP_END_OF_LIST(), |
| 340 | }; |
| 341 | |
| 342 | static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data) |
| 343 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 344 | DeviceClass *dc = DEVICE_CLASS(klass); |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 345 | |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 346 | dc->desc = "PXA2xx GPIO controller"; |
Marc-André Lureau | 4f67d30 | 2020-01-10 19:30:32 +0400 | [diff] [blame] | 347 | device_class_set_props(dc, pxa2xx_gpio_properties); |
Peter Maydell | 166fa99 | 2014-06-29 18:38:40 +0100 | [diff] [blame] | 348 | dc->vmsd = &vmstate_pxa2xx_gpio_regs; |
xiaoqiang zhao | f79a7ff | 2016-10-24 16:26:55 +0100 | [diff] [blame] | 349 | dc->realize = pxa2xx_gpio_realize; |
Anthony Liguori | 999e12b | 2012-01-24 13:12:29 -0600 | [diff] [blame] | 350 | } |
| 351 | |
Andreas Färber | 8c43a6f | 2013-01-10 16:19:07 +0100 | [diff] [blame] | 352 | static const TypeInfo pxa2xx_gpio_info = { |
Andreas Färber | 922bb31 | 2013-07-24 02:03:39 +0200 | [diff] [blame] | 353 | .name = TYPE_PXA2XX_GPIO, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 354 | .parent = TYPE_SYS_BUS_DEVICE, |
| 355 | .instance_size = sizeof(PXA2xxGPIOInfo), |
xiaoqiang zhao | f79a7ff | 2016-10-24 16:26:55 +0100 | [diff] [blame] | 356 | .instance_init = pxa2xx_gpio_initfn, |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 357 | .class_init = pxa2xx_gpio_class_init, |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 358 | }; |
| 359 | |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 360 | static void pxa2xx_gpio_register_types(void) |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 361 | { |
Anthony Liguori | 39bffca | 2011-12-07 21:34:16 -0600 | [diff] [blame] | 362 | type_register_static(&pxa2xx_gpio_info); |
Dmitry Eremin-Solenikov | 0bb5333 | 2011-01-21 19:57:50 +0300 | [diff] [blame] | 363 | } |
Andreas Färber | 83f7d43 | 2012-02-09 15:20:55 +0100 | [diff] [blame] | 364 | |
| 365 | type_init(pxa2xx_gpio_register_types) |