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balrogc1713132007-04-30 01:26:42 +00001/*
2 * Intel XScale PXA255/270 GPIO controller emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
Peter Maydell12b16722015-12-07 16:23:45 +000010#include "qemu/osdep.h"
Paolo Bonzini33c11872016-03-15 16:58:45 +010011#include "cpu.h"
Markus Armbruster64552b62019-08-12 07:23:42 +020012#include "hw/irq.h"
Markus Armbrustera27bd6c2019-08-12 07:23:51 +020013#include "hw/qdev-properties.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010014#include "hw/sysbus.h"
Markus Armbrusterd6454272019-08-12 07:23:45 +020015#include "migration/vmstate.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010016#include "hw/arm/pxa.h"
Markus Armbruster3e80f692020-06-10 07:31:58 +020017#include "qapi/error.h"
Paolo Bonzini03dd0242015-12-15 13:16:16 +010018#include "qemu/log.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020019#include "qemu/module.h"
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040020#include "qom/object.h"
balrogc1713132007-04-30 01:26:42 +000021
22#define PXA2XX_GPIO_BANKS 4
23
Andreas Färber922bb312013-07-24 02:03:39 +020024#define TYPE_PXA2XX_GPIO "pxa2xx-gpio"
Eduardo Habkost80633962020-09-16 14:25:19 -040025OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxGPIOInfo, PXA2XX_GPIO)
Andreas Färber922bb312013-07-24 02:03:39 +020026
Paul Brookbc24a222009-05-10 01:44:56 +010027struct PXA2xxGPIOInfo {
Andreas Färber922bb312013-07-24 02:03:39 +020028 /*< private >*/
29 SysBusDevice parent_obj;
30 /*< public >*/
31
Benoît Canet55a8b802011-10-30 14:50:11 +010032 MemoryRegion iomem;
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030033 qemu_irq irq0, irq1, irqX;
balrogc1713132007-04-30 01:26:42 +000034 int lines;
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030035 int ncpu;
Andreas Färber95d42bb2012-05-04 00:23:14 +020036 ARMCPU *cpu;
balrogc1713132007-04-30 01:26:42 +000037
38 /* XXX: GNU C vectors are more suitable */
39 uint32_t ilevel[PXA2XX_GPIO_BANKS];
40 uint32_t olevel[PXA2XX_GPIO_BANKS];
41 uint32_t dir[PXA2XX_GPIO_BANKS];
42 uint32_t rising[PXA2XX_GPIO_BANKS];
43 uint32_t falling[PXA2XX_GPIO_BANKS];
44 uint32_t status[PXA2XX_GPIO_BANKS];
45 uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
46
47 uint32_t prev_level[PXA2XX_GPIO_BANKS];
balrog38641a52007-11-17 14:07:13 +000048 qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
49 qemu_irq read_notify;
balrogc1713132007-04-30 01:26:42 +000050};
51
52static struct {
53 enum {
54 GPIO_NONE,
55 GPLR,
56 GPSR,
57 GPCR,
58 GPDR,
59 GRER,
60 GFER,
61 GEDR,
62 GAFR_L,
63 GAFR_U,
64 } reg;
65 int bank;
66} pxa2xx_gpio_regs[0x200] = {
67 [0 ... 0x1ff] = { GPIO_NONE, 0 },
68#define PXA2XX_REG(reg, a0, a1, a2, a3) \
ths5fafdf22007-09-16 21:08:06 +000069 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
balrogc1713132007-04-30 01:26:42 +000070
71 PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
72 PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
73 PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
74 PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
75 PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
76 PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
77 PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
78 PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
79 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
80};
81
Paul Brookbc24a222009-05-10 01:44:56 +010082static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
balrogc1713132007-04-30 01:26:42 +000083{
84 if (s->status[0] & (1 << 0))
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030085 qemu_irq_raise(s->irq0);
balrogc1713132007-04-30 01:26:42 +000086 else
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030087 qemu_irq_lower(s->irq0);
balrogc1713132007-04-30 01:26:42 +000088
89 if (s->status[0] & (1 << 1))
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030090 qemu_irq_raise(s->irq1);
balrogc1713132007-04-30 01:26:42 +000091 else
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030092 qemu_irq_lower(s->irq1);
balrogc1713132007-04-30 01:26:42 +000093
94 if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030095 qemu_irq_raise(s->irqX);
balrogc1713132007-04-30 01:26:42 +000096 else
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030097 qemu_irq_lower(s->irqX);
balrogc1713132007-04-30 01:26:42 +000098}
99
100/* Bitmap of pins used as standby and sleep wake-up sources. */
balrog38641a52007-11-17 14:07:13 +0000101static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
balrogc1713132007-04-30 01:26:42 +0000102 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
103};
104
balrog38641a52007-11-17 14:07:13 +0000105static void pxa2xx_gpio_set(void *opaque, int line, int level)
balrogc1713132007-04-30 01:26:42 +0000106{
Paul Brookbc24a222009-05-10 01:44:56 +0100107 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
Andreas Färber259186a2013-01-17 18:51:17 +0100108 CPUState *cpu = CPU(s->cpu);
balrogc1713132007-04-30 01:26:42 +0000109 int bank;
110 uint32_t mask;
111
112 if (line >= s->lines) {
Alistair Francisa89f3642017-11-08 14:56:31 -0800113 printf("%s: No GPIO pin %i\n", __func__, line);
balrogc1713132007-04-30 01:26:42 +0000114 return;
115 }
116
117 bank = line >> 5;
Peter Maydell43a32ed2014-03-10 14:56:29 +0000118 mask = 1U << (line & 31);
balrogc1713132007-04-30 01:26:42 +0000119
120 if (level) {
121 s->status[bank] |= s->rising[bank] & mask &
122 ~s->ilevel[bank] & ~s->dir[bank];
123 s->ilevel[bank] |= mask;
124 } else {
125 s->status[bank] |= s->falling[bank] & mask &
126 s->ilevel[bank] & ~s->dir[bank];
127 s->ilevel[bank] &= ~mask;
128 }
129
130 if (s->status[bank] & mask)
131 pxa2xx_gpio_irq_update(s);
132
133 /* Wake-up GPIOs */
Andreas Färber259186a2013-01-17 18:51:17 +0100134 if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
Andreas Färberc3affe52013-01-18 15:03:43 +0100135 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
Andreas Färber95d42bb2012-05-04 00:23:14 +0200136 }
balrogc1713132007-04-30 01:26:42 +0000137}
138
Paul Brookbc24a222009-05-10 01:44:56 +0100139static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
balrogc1713132007-04-30 01:26:42 +0000140 uint32_t level, diff;
141 int i, bit, line;
142 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
143 level = s->olevel[i] & s->dir[i];
144
145 for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
Stefan Hajnoczi786a4ea2015-03-23 15:29:26 +0000146 bit = ctz32(diff);
balrogc1713132007-04-30 01:26:42 +0000147 line = bit + 32 * i;
balrog38641a52007-11-17 14:07:13 +0000148 qemu_set_irq(s->handler[line], (level >> bit) & 1);
balrogc1713132007-04-30 01:26:42 +0000149 }
150
151 s->prev_level[i] = level;
152 }
153}
154
Avi Kivitya8170e52012-10-23 12:30:10 +0200155static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
Benoît Canet55a8b802011-10-30 14:50:11 +0100156 unsigned size)
balrogc1713132007-04-30 01:26:42 +0000157{
Paul Brookbc24a222009-05-10 01:44:56 +0100158 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
balrogc1713132007-04-30 01:26:42 +0000159 uint32_t ret;
160 int bank;
balrogc1713132007-04-30 01:26:42 +0000161 if (offset >= 0x200)
162 return 0;
163
164 bank = pxa2xx_gpio_regs[offset].bank;
165 switch (pxa2xx_gpio_regs[offset].reg) {
166 case GPDR: /* GPIO Pin-Direction registers */
167 return s->dir[bank];
168
balrog2b76bdc2007-10-04 19:41:17 +0000169 case GPSR: /* GPIO Pin-Output Set registers */
Peter Maydellab7a0f02014-06-29 18:38:40 +0100170 qemu_log_mask(LOG_GUEST_ERROR,
171 "pxa2xx GPIO: read from write only register GPSR\n");
172 return 0;
balrog2b76bdc2007-10-04 19:41:17 +0000173
balroge1dad5a2007-11-17 18:43:47 +0000174 case GPCR: /* GPIO Pin-Output Clear registers */
Peter Maydellab7a0f02014-06-29 18:38:40 +0100175 qemu_log_mask(LOG_GUEST_ERROR,
176 "pxa2xx GPIO: read from write only register GPCR\n");
177 return 0;
balroge1dad5a2007-11-17 18:43:47 +0000178
balrogc1713132007-04-30 01:26:42 +0000179 case GRER: /* GPIO Rising-Edge Detect Enable registers */
180 return s->rising[bank];
181
182 case GFER: /* GPIO Falling-Edge Detect Enable registers */
183 return s->falling[bank];
184
185 case GAFR_L: /* GPIO Alternate Function registers */
186 return s->gafr[bank * 2];
187
188 case GAFR_U: /* GPIO Alternate Function registers */
189 return s->gafr[bank * 2 + 1];
190
191 case GPLR: /* GPIO Pin-Level registers */
192 ret = (s->olevel[bank] & s->dir[bank]) |
193 (s->ilevel[bank] & ~s->dir[bank]);
balrog38641a52007-11-17 14:07:13 +0000194 qemu_irq_raise(s->read_notify);
balrogc1713132007-04-30 01:26:42 +0000195 return ret;
196
197 case GEDR: /* GPIO Edge Detect Status registers */
198 return s->status[bank];
199
200 default:
Philippe Mathieu-Daudé5a0001e2020-05-18 16:03:07 +0200201 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
202 __func__, offset);
balrogc1713132007-04-30 01:26:42 +0000203 }
204
205 return 0;
206}
207
Avi Kivitya8170e52012-10-23 12:30:10 +0200208static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
Benoît Canet55a8b802011-10-30 14:50:11 +0100209 uint64_t value, unsigned size)
balrogc1713132007-04-30 01:26:42 +0000210{
Paul Brookbc24a222009-05-10 01:44:56 +0100211 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
balrogc1713132007-04-30 01:26:42 +0000212 int bank;
balrogc1713132007-04-30 01:26:42 +0000213 if (offset >= 0x200)
214 return;
215
216 bank = pxa2xx_gpio_regs[offset].bank;
217 switch (pxa2xx_gpio_regs[offset].reg) {
218 case GPDR: /* GPIO Pin-Direction registers */
219 s->dir[bank] = value;
220 pxa2xx_gpio_handler_update(s);
221 break;
222
223 case GPSR: /* GPIO Pin-Output Set registers */
224 s->olevel[bank] |= value;
225 pxa2xx_gpio_handler_update(s);
226 break;
227
228 case GPCR: /* GPIO Pin-Output Clear registers */
229 s->olevel[bank] &= ~value;
230 pxa2xx_gpio_handler_update(s);
231 break;
232
233 case GRER: /* GPIO Rising-Edge Detect Enable registers */
234 s->rising[bank] = value;
235 break;
236
237 case GFER: /* GPIO Falling-Edge Detect Enable registers */
238 s->falling[bank] = value;
239 break;
240
241 case GAFR_L: /* GPIO Alternate Function registers */
242 s->gafr[bank * 2] = value;
243 break;
244
245 case GAFR_U: /* GPIO Alternate Function registers */
246 s->gafr[bank * 2 + 1] = value;
247 break;
248
249 case GEDR: /* GPIO Edge Detect Status registers */
250 s->status[bank] &= ~value;
251 pxa2xx_gpio_irq_update(s);
252 break;
253
254 default:
Philippe Mathieu-Daudé5a0001e2020-05-18 16:03:07 +0200255 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n",
256 __func__, offset);
balrogc1713132007-04-30 01:26:42 +0000257 }
258}
259
Benoît Canet55a8b802011-10-30 14:50:11 +0100260static const MemoryRegionOps pxa_gpio_ops = {
261 .read = pxa2xx_gpio_read,
262 .write = pxa2xx_gpio_write,
263 .endianness = DEVICE_NATIVE_ENDIAN,
balrogc1713132007-04-30 01:26:42 +0000264};
265
Avi Kivitya8170e52012-10-23 12:30:10 +0200266DeviceState *pxa2xx_gpio_init(hwaddr base,
Andreas Färber55e5c282012-12-17 06:18:02 +0100267 ARMCPU *cpu, DeviceState *pic, int lines)
balrogc1713132007-04-30 01:26:42 +0000268{
Andreas Färber55e5c282012-12-17 06:18:02 +0100269 CPUState *cs = CPU(cpu);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300270 DeviceState *dev;
271
Markus Armbruster3e80f692020-06-10 07:31:58 +0200272 dev = qdev_new(TYPE_PXA2XX_GPIO);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300273 qdev_prop_set_int32(dev, "lines", lines);
Andreas Färber55e5c282012-12-17 06:18:02 +0100274 qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
Markus Armbruster3c6ef472020-06-10 07:32:34 +0200275 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300276
Andreas Färber1356b982013-01-20 02:47:33 +0100277 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
278 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
Dmitry Eremin-Solenikove1f8c722011-02-25 12:13:38 +0100279 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
Andreas Färber1356b982013-01-20 02:47:33 +0100280 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
Dmitry Eremin-Solenikove1f8c722011-02-25 12:13:38 +0100281 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
Andreas Färber1356b982013-01-20 02:47:33 +0100282 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
Dmitry Eremin-Solenikove1f8c722011-02-25 12:13:38 +0100283 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300284
285 return dev;
286}
287
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100288static void pxa2xx_gpio_initfn(Object *obj)
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300289{
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100290 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
Andreas Färber922bb312013-07-24 02:03:39 +0200291 DeviceState *dev = DEVICE(sbd);
292 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300293
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100294 memory_region_init_io(&s->iomem, obj, &pxa_gpio_ops,
295 s, "pxa2xx-gpio", 0x1000);
296 sysbus_init_mmio(sbd, &s->iomem);
297 sysbus_init_irq(sbd, &s->irq0);
298 sysbus_init_irq(sbd, &s->irq1);
299 sysbus_init_irq(sbd, &s->irqX);
300}
301
302static void pxa2xx_gpio_realize(DeviceState *dev, Error **errp)
303{
304 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
305
Andreas Färber38d8f5c2012-12-17 19:47:15 +0100306 s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300307
Andreas Färber922bb312013-07-24 02:03:39 +0200308 qdev_init_gpio_in(dev, pxa2xx_gpio_set, s->lines);
309 qdev_init_gpio_out(dev, s->handler, s->lines);
balrogc1713132007-04-30 01:26:42 +0000310}
311
312/*
313 * Registers a callback to notify on GPLR reads. This normally
314 * shouldn't be needed but it is used for the hack on Spitz machines.
315 */
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300316void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
balrog38641a52007-11-17 14:07:13 +0000317{
Andreas Färber922bb312013-07-24 02:03:39 +0200318 PXA2xxGPIOInfo *s = PXA2XX_GPIO(dev);
319
balrogc1713132007-04-30 01:26:42 +0000320 s->read_notify = handler;
balrogc1713132007-04-30 01:26:42 +0000321}
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300322
323static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
324 .name = "pxa2xx-gpio",
325 .version_id = 1,
326 .minimum_version_id = 1,
Juan Quintela8f1e8842014-05-13 16:09:35 +0100327 .fields = (VMStateField[]) {
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300328 VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
329 VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
330 VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
331 VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
332 VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
333 VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
334 VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
Peter Maydell166fa992014-06-29 18:38:40 +0100335 VMSTATE_UINT32_ARRAY(prev_level, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300336 VMSTATE_END_OF_LIST(),
337 },
338};
339
Anthony Liguori999e12b2012-01-24 13:12:29 -0600340static Property pxa2xx_gpio_properties[] = {
341 DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
342 DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
343 DEFINE_PROP_END_OF_LIST(),
344};
345
346static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
347{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600348 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600349
Anthony Liguori39bffca2011-12-07 21:34:16 -0600350 dc->desc = "PXA2xx GPIO controller";
Marc-André Lureau4f67d302020-01-10 19:30:32 +0400351 device_class_set_props(dc, pxa2xx_gpio_properties);
Peter Maydell166fa992014-06-29 18:38:40 +0100352 dc->vmsd = &vmstate_pxa2xx_gpio_regs;
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100353 dc->realize = pxa2xx_gpio_realize;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600354}
355
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100356static const TypeInfo pxa2xx_gpio_info = {
Andreas Färber922bb312013-07-24 02:03:39 +0200357 .name = TYPE_PXA2XX_GPIO,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600358 .parent = TYPE_SYS_BUS_DEVICE,
359 .instance_size = sizeof(PXA2xxGPIOInfo),
xiaoqiang zhaof79a7ff2016-10-24 16:26:55 +0100360 .instance_init = pxa2xx_gpio_initfn,
Anthony Liguori39bffca2011-12-07 21:34:16 -0600361 .class_init = pxa2xx_gpio_class_init,
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300362};
363
Andreas Färber83f7d432012-02-09 15:20:55 +0100364static void pxa2xx_gpio_register_types(void)
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300365{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600366 type_register_static(&pxa2xx_gpio_info);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300367}
Andreas Färber83f7d432012-02-09 15:20:55 +0100368
369type_init(pxa2xx_gpio_register_types)