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balrogc1713132007-04-30 01:26:42 +00001/*
2 * Intel XScale PXA255/270 GPIO controller emulation.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010010#include "hw/hw.h"
11#include "hw/sysbus.h"
12#include "hw/pxa.h"
balrogc1713132007-04-30 01:26:42 +000013
14#define PXA2XX_GPIO_BANKS 4
15
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030016typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
Paul Brookbc24a222009-05-10 01:44:56 +010017struct PXA2xxGPIOInfo {
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030018 SysBusDevice busdev;
Benoît Canet55a8b802011-10-30 14:50:11 +010019 MemoryRegion iomem;
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030020 qemu_irq irq0, irq1, irqX;
balrogc1713132007-04-30 01:26:42 +000021 int lines;
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030022 int ncpu;
Andreas Färber95d42bb2012-05-04 00:23:14 +020023 ARMCPU *cpu;
balrogc1713132007-04-30 01:26:42 +000024
25 /* XXX: GNU C vectors are more suitable */
26 uint32_t ilevel[PXA2XX_GPIO_BANKS];
27 uint32_t olevel[PXA2XX_GPIO_BANKS];
28 uint32_t dir[PXA2XX_GPIO_BANKS];
29 uint32_t rising[PXA2XX_GPIO_BANKS];
30 uint32_t falling[PXA2XX_GPIO_BANKS];
31 uint32_t status[PXA2XX_GPIO_BANKS];
balrog2b76bdc2007-10-04 19:41:17 +000032 uint32_t gpsr[PXA2XX_GPIO_BANKS];
balrogc1713132007-04-30 01:26:42 +000033 uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
34
35 uint32_t prev_level[PXA2XX_GPIO_BANKS];
balrog38641a52007-11-17 14:07:13 +000036 qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
37 qemu_irq read_notify;
balrogc1713132007-04-30 01:26:42 +000038};
39
40static struct {
41 enum {
42 GPIO_NONE,
43 GPLR,
44 GPSR,
45 GPCR,
46 GPDR,
47 GRER,
48 GFER,
49 GEDR,
50 GAFR_L,
51 GAFR_U,
52 } reg;
53 int bank;
54} pxa2xx_gpio_regs[0x200] = {
55 [0 ... 0x1ff] = { GPIO_NONE, 0 },
56#define PXA2XX_REG(reg, a0, a1, a2, a3) \
ths5fafdf22007-09-16 21:08:06 +000057 [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
balrogc1713132007-04-30 01:26:42 +000058
59 PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
60 PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
61 PXA2XX_REG(GPCR, 0x024, 0x028, 0x02c, 0x124)
62 PXA2XX_REG(GPDR, 0x00c, 0x010, 0x014, 0x10c)
63 PXA2XX_REG(GRER, 0x030, 0x034, 0x038, 0x130)
64 PXA2XX_REG(GFER, 0x03c, 0x040, 0x044, 0x13c)
65 PXA2XX_REG(GEDR, 0x048, 0x04c, 0x050, 0x148)
66 PXA2XX_REG(GAFR_L, 0x054, 0x05c, 0x064, 0x06c)
67 PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
68};
69
Paul Brookbc24a222009-05-10 01:44:56 +010070static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
balrogc1713132007-04-30 01:26:42 +000071{
72 if (s->status[0] & (1 << 0))
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030073 qemu_irq_raise(s->irq0);
balrogc1713132007-04-30 01:26:42 +000074 else
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030075 qemu_irq_lower(s->irq0);
balrogc1713132007-04-30 01:26:42 +000076
77 if (s->status[0] & (1 << 1))
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030078 qemu_irq_raise(s->irq1);
balrogc1713132007-04-30 01:26:42 +000079 else
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030080 qemu_irq_lower(s->irq1);
balrogc1713132007-04-30 01:26:42 +000081
82 if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030083 qemu_irq_raise(s->irqX);
balrogc1713132007-04-30 01:26:42 +000084 else
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +030085 qemu_irq_lower(s->irqX);
balrogc1713132007-04-30 01:26:42 +000086}
87
88/* Bitmap of pins used as standby and sleep wake-up sources. */
balrog38641a52007-11-17 14:07:13 +000089static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
balrogc1713132007-04-30 01:26:42 +000090 0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
91};
92
balrog38641a52007-11-17 14:07:13 +000093static void pxa2xx_gpio_set(void *opaque, int line, int level)
balrogc1713132007-04-30 01:26:42 +000094{
Paul Brookbc24a222009-05-10 01:44:56 +010095 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
Andreas Färber259186a2013-01-17 18:51:17 +010096 CPUState *cpu = CPU(s->cpu);
balrogc1713132007-04-30 01:26:42 +000097 int bank;
98 uint32_t mask;
99
100 if (line >= s->lines) {
101 printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
102 return;
103 }
104
105 bank = line >> 5;
106 mask = 1 << (line & 31);
107
108 if (level) {
109 s->status[bank] |= s->rising[bank] & mask &
110 ~s->ilevel[bank] & ~s->dir[bank];
111 s->ilevel[bank] |= mask;
112 } else {
113 s->status[bank] |= s->falling[bank] & mask &
114 s->ilevel[bank] & ~s->dir[bank];
115 s->ilevel[bank] &= ~mask;
116 }
117
118 if (s->status[bank] & mask)
119 pxa2xx_gpio_irq_update(s);
120
121 /* Wake-up GPIOs */
Andreas Färber259186a2013-01-17 18:51:17 +0100122 if (cpu->halted && (mask & ~s->dir[bank] & pxa2xx_gpio_wake[bank])) {
Andreas Färberc3affe52013-01-18 15:03:43 +0100123 cpu_interrupt(cpu, CPU_INTERRUPT_EXITTB);
Andreas Färber95d42bb2012-05-04 00:23:14 +0200124 }
balrogc1713132007-04-30 01:26:42 +0000125}
126
Paul Brookbc24a222009-05-10 01:44:56 +0100127static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
balrogc1713132007-04-30 01:26:42 +0000128 uint32_t level, diff;
129 int i, bit, line;
130 for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
131 level = s->olevel[i] & s->dir[i];
132
133 for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
134 bit = ffs(diff) - 1;
135 line = bit + 32 * i;
balrog38641a52007-11-17 14:07:13 +0000136 qemu_set_irq(s->handler[line], (level >> bit) & 1);
balrogc1713132007-04-30 01:26:42 +0000137 }
138
139 s->prev_level[i] = level;
140 }
141}
142
Avi Kivitya8170e52012-10-23 12:30:10 +0200143static uint64_t pxa2xx_gpio_read(void *opaque, hwaddr offset,
Benoît Canet55a8b802011-10-30 14:50:11 +0100144 unsigned size)
balrogc1713132007-04-30 01:26:42 +0000145{
Paul Brookbc24a222009-05-10 01:44:56 +0100146 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
balrogc1713132007-04-30 01:26:42 +0000147 uint32_t ret;
148 int bank;
balrogc1713132007-04-30 01:26:42 +0000149 if (offset >= 0x200)
150 return 0;
151
152 bank = pxa2xx_gpio_regs[offset].bank;
153 switch (pxa2xx_gpio_regs[offset].reg) {
154 case GPDR: /* GPIO Pin-Direction registers */
155 return s->dir[bank];
156
balrog2b76bdc2007-10-04 19:41:17 +0000157 case GPSR: /* GPIO Pin-Output Set registers */
158 printf("%s: Read from a write-only register " REG_FMT "\n",
159 __FUNCTION__, offset);
160 return s->gpsr[bank]; /* Return last written value. */
161
balroge1dad5a2007-11-17 18:43:47 +0000162 case GPCR: /* GPIO Pin-Output Clear registers */
163 printf("%s: Read from a write-only register " REG_FMT "\n",
164 __FUNCTION__, offset);
165 return 31337; /* Specified as unpredictable in the docs. */
166
balrogc1713132007-04-30 01:26:42 +0000167 case GRER: /* GPIO Rising-Edge Detect Enable registers */
168 return s->rising[bank];
169
170 case GFER: /* GPIO Falling-Edge Detect Enable registers */
171 return s->falling[bank];
172
173 case GAFR_L: /* GPIO Alternate Function registers */
174 return s->gafr[bank * 2];
175
176 case GAFR_U: /* GPIO Alternate Function registers */
177 return s->gafr[bank * 2 + 1];
178
179 case GPLR: /* GPIO Pin-Level registers */
180 ret = (s->olevel[bank] & s->dir[bank]) |
181 (s->ilevel[bank] & ~s->dir[bank]);
balrog38641a52007-11-17 14:07:13 +0000182 qemu_irq_raise(s->read_notify);
balrogc1713132007-04-30 01:26:42 +0000183 return ret;
184
185 case GEDR: /* GPIO Edge Detect Status registers */
186 return s->status[bank];
187
188 default:
Paul Brook2ac71172009-05-08 02:35:15 +0100189 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
balrogc1713132007-04-30 01:26:42 +0000190 }
191
192 return 0;
193}
194
Avi Kivitya8170e52012-10-23 12:30:10 +0200195static void pxa2xx_gpio_write(void *opaque, hwaddr offset,
Benoît Canet55a8b802011-10-30 14:50:11 +0100196 uint64_t value, unsigned size)
balrogc1713132007-04-30 01:26:42 +0000197{
Paul Brookbc24a222009-05-10 01:44:56 +0100198 PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
balrogc1713132007-04-30 01:26:42 +0000199 int bank;
balrogc1713132007-04-30 01:26:42 +0000200 if (offset >= 0x200)
201 return;
202
203 bank = pxa2xx_gpio_regs[offset].bank;
204 switch (pxa2xx_gpio_regs[offset].reg) {
205 case GPDR: /* GPIO Pin-Direction registers */
206 s->dir[bank] = value;
207 pxa2xx_gpio_handler_update(s);
208 break;
209
210 case GPSR: /* GPIO Pin-Output Set registers */
211 s->olevel[bank] |= value;
212 pxa2xx_gpio_handler_update(s);
balrog2b76bdc2007-10-04 19:41:17 +0000213 s->gpsr[bank] = value;
balrogc1713132007-04-30 01:26:42 +0000214 break;
215
216 case GPCR: /* GPIO Pin-Output Clear registers */
217 s->olevel[bank] &= ~value;
218 pxa2xx_gpio_handler_update(s);
219 break;
220
221 case GRER: /* GPIO Rising-Edge Detect Enable registers */
222 s->rising[bank] = value;
223 break;
224
225 case GFER: /* GPIO Falling-Edge Detect Enable registers */
226 s->falling[bank] = value;
227 break;
228
229 case GAFR_L: /* GPIO Alternate Function registers */
230 s->gafr[bank * 2] = value;
231 break;
232
233 case GAFR_U: /* GPIO Alternate Function registers */
234 s->gafr[bank * 2 + 1] = value;
235 break;
236
237 case GEDR: /* GPIO Edge Detect Status registers */
238 s->status[bank] &= ~value;
239 pxa2xx_gpio_irq_update(s);
240 break;
241
242 default:
Paul Brook2ac71172009-05-08 02:35:15 +0100243 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
balrogc1713132007-04-30 01:26:42 +0000244 }
245}
246
Benoît Canet55a8b802011-10-30 14:50:11 +0100247static const MemoryRegionOps pxa_gpio_ops = {
248 .read = pxa2xx_gpio_read,
249 .write = pxa2xx_gpio_write,
250 .endianness = DEVICE_NATIVE_ENDIAN,
balrogc1713132007-04-30 01:26:42 +0000251};
252
Avi Kivitya8170e52012-10-23 12:30:10 +0200253DeviceState *pxa2xx_gpio_init(hwaddr base,
Andreas Färber55e5c282012-12-17 06:18:02 +0100254 ARMCPU *cpu, DeviceState *pic, int lines)
balrogc1713132007-04-30 01:26:42 +0000255{
Andreas Färber55e5c282012-12-17 06:18:02 +0100256 CPUState *cs = CPU(cpu);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300257 DeviceState *dev;
258
259 dev = qdev_create(NULL, "pxa2xx-gpio");
260 qdev_prop_set_int32(dev, "lines", lines);
Andreas Färber55e5c282012-12-17 06:18:02 +0100261 qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300262 qdev_init_nofail(dev);
263
Andreas Färber1356b982013-01-20 02:47:33 +0100264 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
265 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
Dmitry Eremin-Solenikove1f8c722011-02-25 12:13:38 +0100266 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
Andreas Färber1356b982013-01-20 02:47:33 +0100267 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1,
Dmitry Eremin-Solenikove1f8c722011-02-25 12:13:38 +0100268 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
Andreas Färber1356b982013-01-20 02:47:33 +0100269 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2,
Dmitry Eremin-Solenikove1f8c722011-02-25 12:13:38 +0100270 qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300271
272 return dev;
273}
274
275static int pxa2xx_gpio_initfn(SysBusDevice *dev)
276{
Paul Brookbc24a222009-05-10 01:44:56 +0100277 PXA2xxGPIOInfo *s;
balrogc1713132007-04-30 01:26:42 +0000278
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300279 s = FROM_SYSBUS(PXA2xxGPIOInfo, dev);
280
Andreas Färber38d8f5c2012-12-17 19:47:15 +0100281 s->cpu = ARM_CPU(qemu_get_cpu(s->ncpu));
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300282
283 qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines);
284 qdev_init_gpio_out(&dev->qdev, s->handler, s->lines);
balrogc1713132007-04-30 01:26:42 +0000285
Benoît Canet55a8b802011-10-30 14:50:11 +0100286 memory_region_init_io(&s->iomem, &pxa_gpio_ops, s, "pxa2xx-gpio", 0x1000);
Avi Kivity750ecd42011-11-27 11:38:10 +0200287 sysbus_init_mmio(dev, &s->iomem);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300288 sysbus_init_irq(dev, &s->irq0);
289 sysbus_init_irq(dev, &s->irq1);
290 sysbus_init_irq(dev, &s->irqX);
balrogaa941b92007-05-24 18:50:09 +0000291
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300292 return 0;
balrogc1713132007-04-30 01:26:42 +0000293}
294
295/*
296 * Registers a callback to notify on GPLR reads. This normally
297 * shouldn't be needed but it is used for the hack on Spitz machines.
298 */
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300299void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
balrog38641a52007-11-17 14:07:13 +0000300{
Andreas Färber1356b982013-01-20 02:47:33 +0100301 PXA2xxGPIOInfo *s = FROM_SYSBUS(PXA2xxGPIOInfo, SYS_BUS_DEVICE(dev));
balrogc1713132007-04-30 01:26:42 +0000302 s->read_notify = handler;
balrogc1713132007-04-30 01:26:42 +0000303}
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300304
305static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
306 .name = "pxa2xx-gpio",
307 .version_id = 1,
308 .minimum_version_id = 1,
309 .minimum_version_id_old = 1,
310 .fields = (VMStateField []) {
311 VMSTATE_INT32(lines, PXA2xxGPIOInfo),
312 VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
313 VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
314 VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
315 VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
316 VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
317 VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
318 VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
319 VMSTATE_END_OF_LIST(),
320 },
321};
322
Anthony Liguori999e12b2012-01-24 13:12:29 -0600323static Property pxa2xx_gpio_properties[] = {
324 DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
325 DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
326 DEFINE_PROP_END_OF_LIST(),
327};
328
329static void pxa2xx_gpio_class_init(ObjectClass *klass, void *data)
330{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600331 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600332 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
333
334 k->init = pxa2xx_gpio_initfn;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600335 dc->desc = "PXA2xx GPIO controller";
336 dc->props = pxa2xx_gpio_properties;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600337}
338
Andreas Färber8c43a6f2013-01-10 16:19:07 +0100339static const TypeInfo pxa2xx_gpio_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -0600340 .name = "pxa2xx-gpio",
341 .parent = TYPE_SYS_BUS_DEVICE,
342 .instance_size = sizeof(PXA2xxGPIOInfo),
343 .class_init = pxa2xx_gpio_class_init,
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300344};
345
Andreas Färber83f7d432012-02-09 15:20:55 +0100346static void pxa2xx_gpio_register_types(void)
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300347{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600348 type_register_static(&pxa2xx_gpio_info);
Dmitry Eremin-Solenikov0bb53332011-01-21 19:57:50 +0300349}
Andreas Färber83f7d432012-02-09 15:20:55 +0100350
351type_init(pxa2xx_gpio_register_types)