blob: 3e495a1b12d4645408b86d56cb62b762dc3dd432 [file] [log] [blame]
bellard9a64fbe2004-01-04 22:58:38 +00001/*
bellard3fc6c082005-07-02 20:59:34 +00002 * PowerPC emulation helpers for qemu.
ths5fafdf22007-09-16 21:08:06 +00003 *
j_mayer76a66252007-03-07 08:32:30 +00004 * Copyright (c) 2003-2007 Jocelyn Mayer
bellard9a64fbe2004-01-04 22:58:38 +00005 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
aurel32fad6cb12009-01-04 22:05:52 +000018 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
bellard9a64fbe2004-01-04 22:58:38 +000019 */
bellard9a64fbe2004-01-04 22:58:38 +000020#include "exec.h"
j_mayer603fccc2007-10-28 12:54:53 +000021#include "host-utils.h"
pbrooka7812ae2008-11-17 14:43:54 +000022#include "helper.h"
bellard9a64fbe2004-01-04 22:58:38 +000023
j_mayer0411a972007-10-25 21:35:50 +000024#include "helper_regs.h"
j_mayer0487d6a2007-03-20 22:11:31 +000025
bellardfdabc362005-07-04 22:17:05 +000026//#define DEBUG_OP
27//#define DEBUG_EXCEPTIONS
j_mayer76a66252007-03-07 08:32:30 +000028//#define DEBUG_SOFTWARE_TLB
bellardfdabc362005-07-04 22:17:05 +000029
bellard9a64fbe2004-01-04 22:58:38 +000030/*****************************************************************************/
31/* Exceptions processing helpers */
bellard9a64fbe2004-01-04 22:58:38 +000032
aurel3264adab32008-11-22 10:09:17 +000033void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
bellard9a64fbe2004-01-04 22:58:38 +000034{
aurel32e06fcd72008-12-11 22:42:14 +000035#if 0
36 printf("Raise exception %3x code : %d\n", exception, error_code);
37#endif
38 env->exception_index = exception;
39 env->error_code = error_code;
40 cpu_loop_exit();
j_mayer76a66252007-03-07 08:32:30 +000041}
bellard9fddaa02004-05-21 12:59:32 +000042
aurel32e06fcd72008-12-11 22:42:14 +000043void helper_raise_exception (uint32_t exception)
bellard9fddaa02004-05-21 12:59:32 +000044{
aurel32e06fcd72008-12-11 22:42:14 +000045 helper_raise_exception_err(exception, 0);
bellard9a64fbe2004-01-04 22:58:38 +000046}
47
48/*****************************************************************************/
j_mayer76a66252007-03-07 08:32:30 +000049/* Registers load and stores */
pbrooka7812ae2008-11-17 14:43:54 +000050target_ulong helper_load_cr (void)
j_mayer76a66252007-03-07 08:32:30 +000051{
aurel32e1571902008-10-21 11:31:14 +000052 return (env->crf[0] << 28) |
53 (env->crf[1] << 24) |
54 (env->crf[2] << 20) |
55 (env->crf[3] << 16) |
56 (env->crf[4] << 12) |
57 (env->crf[5] << 8) |
58 (env->crf[6] << 4) |
59 (env->crf[7] << 0);
j_mayer76a66252007-03-07 08:32:30 +000060}
61
aurel32e1571902008-10-21 11:31:14 +000062void helper_store_cr (target_ulong val, uint32_t mask)
j_mayer76a66252007-03-07 08:32:30 +000063{
64 int i, sh;
65
j_mayer36081602007-09-17 08:21:54 +000066 for (i = 0, sh = 7; i < 8; i++, sh--) {
j_mayer76a66252007-03-07 08:32:30 +000067 if (mask & (1 << sh))
aurel32e1571902008-10-21 11:31:14 +000068 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
j_mayer76a66252007-03-07 08:32:30 +000069 }
70}
71
aurel3245d827d2008-12-07 13:40:29 +000072/*****************************************************************************/
73/* SPR accesses */
74void helper_load_dump_spr (uint32_t sprn)
j_mayera4967752007-04-16 07:10:48 +000075{
j_mayer6b800552007-04-24 07:36:03 +000076 if (loglevel != 0) {
j_mayera4967752007-04-16 07:10:48 +000077 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
78 sprn, sprn, env->spr[sprn]);
79 }
j_mayera4967752007-04-16 07:10:48 +000080}
81
aurel3245d827d2008-12-07 13:40:29 +000082void helper_store_dump_spr (uint32_t sprn)
j_mayera4967752007-04-16 07:10:48 +000083{
j_mayer6b800552007-04-24 07:36:03 +000084 if (loglevel != 0) {
aurel3245d827d2008-12-07 13:40:29 +000085 fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n",
86 sprn, sprn, env->spr[sprn]);
j_mayera4967752007-04-16 07:10:48 +000087 }
j_mayera4967752007-04-16 07:10:48 +000088}
89
aurel3245d827d2008-12-07 13:40:29 +000090target_ulong helper_load_tbl (void)
91{
92 return cpu_ppc_load_tbl(env);
93}
94
95target_ulong helper_load_tbu (void)
96{
97 return cpu_ppc_load_tbu(env);
98}
99
100target_ulong helper_load_atbl (void)
101{
102 return cpu_ppc_load_atbl(env);
103}
104
105target_ulong helper_load_atbu (void)
106{
107 return cpu_ppc_load_atbu(env);
108}
109
110target_ulong helper_load_601_rtcl (void)
111{
112 return cpu_ppc601_load_rtcl(env);
113}
114
115target_ulong helper_load_601_rtcu (void)
116{
117 return cpu_ppc601_load_rtcu(env);
118}
119
120#if !defined(CONFIG_USER_ONLY)
121#if defined (TARGET_PPC64)
122void helper_store_asr (target_ulong val)
123{
124 ppc_store_asr(env, val);
125}
126#endif
127
128void helper_store_sdr1 (target_ulong val)
129{
130 ppc_store_sdr1(env, val);
131}
132
133void helper_store_tbl (target_ulong val)
134{
135 cpu_ppc_store_tbl(env, val);
136}
137
138void helper_store_tbu (target_ulong val)
139{
140 cpu_ppc_store_tbu(env, val);
141}
142
143void helper_store_atbl (target_ulong val)
144{
145 cpu_ppc_store_atbl(env, val);
146}
147
148void helper_store_atbu (target_ulong val)
149{
150 cpu_ppc_store_atbu(env, val);
151}
152
153void helper_store_601_rtcl (target_ulong val)
154{
155 cpu_ppc601_store_rtcl(env, val);
156}
157
158void helper_store_601_rtcu (target_ulong val)
159{
160 cpu_ppc601_store_rtcu(env, val);
161}
162
163target_ulong helper_load_decr (void)
164{
165 return cpu_ppc_load_decr(env);
166}
167
168void helper_store_decr (target_ulong val)
169{
170 cpu_ppc_store_decr(env, val);
171}
172
173void helper_store_hid0_601 (target_ulong val)
174{
175 target_ulong hid0;
176
177 hid0 = env->spr[SPR_HID0];
178 if ((val ^ hid0) & 0x00000008) {
179 /* Change current endianness */
180 env->hflags &= ~(1 << MSR_LE);
181 env->hflags_nmsr &= ~(1 << MSR_LE);
182 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
183 env->hflags |= env->hflags_nmsr;
184 if (loglevel != 0) {
185 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
186 __func__, val & 0x8 ? 'l' : 'b', env->hflags);
187 }
188 }
189 env->spr[SPR_HID0] = (uint32_t)val;
190}
191
192void helper_store_403_pbr (uint32_t num, target_ulong value)
193{
194 if (likely(env->pb[num] != value)) {
195 env->pb[num] = value;
196 /* Should be optimized */
197 tlb_flush(env, 1);
198 }
199}
200
201target_ulong helper_load_40x_pit (void)
202{
203 return load_40x_pit(env);
204}
205
206void helper_store_40x_pit (target_ulong val)
207{
208 store_40x_pit(env, val);
209}
210
211void helper_store_40x_dbcr0 (target_ulong val)
212{
213 store_40x_dbcr0(env, val);
214}
215
216void helper_store_40x_sler (target_ulong val)
217{
218 store_40x_sler(env, val);
219}
220
221void helper_store_booke_tcr (target_ulong val)
222{
223 store_booke_tcr(env, val);
224}
225
226void helper_store_booke_tsr (target_ulong val)
227{
228 store_booke_tsr(env, val);
229}
230
231void helper_store_ibatu (uint32_t nr, target_ulong val)
232{
233 ppc_store_ibatu(env, nr, val);
234}
235
236void helper_store_ibatl (uint32_t nr, target_ulong val)
237{
238 ppc_store_ibatl(env, nr, val);
239}
240
241void helper_store_dbatu (uint32_t nr, target_ulong val)
242{
243 ppc_store_dbatu(env, nr, val);
244}
245
246void helper_store_dbatl (uint32_t nr, target_ulong val)
247{
248 ppc_store_dbatl(env, nr, val);
249}
250
251void helper_store_601_batl (uint32_t nr, target_ulong val)
252{
253 ppc_store_ibatl_601(env, nr, val);
254}
255
256void helper_store_601_batu (uint32_t nr, target_ulong val)
257{
258 ppc_store_ibatu_601(env, nr, val);
259}
260#endif
261
j_mayer76a66252007-03-07 08:32:30 +0000262/*****************************************************************************/
aurel32ff4a62c2008-11-30 16:23:56 +0000263/* Memory load and stores */
264
aurel3276db3ba2008-12-08 18:11:21 +0000265static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
aurel32ff4a62c2008-11-30 16:23:56 +0000266{
267#if defined(TARGET_PPC64)
aurel3276db3ba2008-12-08 18:11:21 +0000268 if (!msr_sf)
269 return (uint32_t)(addr + arg);
aurel32ff4a62c2008-11-30 16:23:56 +0000270 else
271#endif
aurel3276db3ba2008-12-08 18:11:21 +0000272 return addr + arg;
aurel32ff4a62c2008-11-30 16:23:56 +0000273}
274
275void helper_lmw (target_ulong addr, uint32_t reg)
276{
aurel3276db3ba2008-12-08 18:11:21 +0000277 for (; reg < 32; reg++) {
aurel32ff4a62c2008-11-30 16:23:56 +0000278 if (msr_le)
aurel3276db3ba2008-12-08 18:11:21 +0000279 env->gpr[reg] = bswap32(ldl(addr));
aurel32ff4a62c2008-11-30 16:23:56 +0000280 else
aurel3276db3ba2008-12-08 18:11:21 +0000281 env->gpr[reg] = ldl(addr);
282 addr = addr_add(addr, 4);
aurel32ff4a62c2008-11-30 16:23:56 +0000283 }
284}
285
286void helper_stmw (target_ulong addr, uint32_t reg)
287{
aurel3276db3ba2008-12-08 18:11:21 +0000288 for (; reg < 32; reg++) {
aurel32ff4a62c2008-11-30 16:23:56 +0000289 if (msr_le)
aurel3276db3ba2008-12-08 18:11:21 +0000290 stl(addr, bswap32((uint32_t)env->gpr[reg]));
aurel32ff4a62c2008-11-30 16:23:56 +0000291 else
aurel3276db3ba2008-12-08 18:11:21 +0000292 stl(addr, (uint32_t)env->gpr[reg]);
293 addr = addr_add(addr, 4);
aurel32ff4a62c2008-11-30 16:23:56 +0000294 }
295}
296
aurel32dfbc7992008-11-30 16:24:21 +0000297void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
298{
299 int sh;
aurel3276db3ba2008-12-08 18:11:21 +0000300 for (; nb > 3; nb -= 4) {
301 env->gpr[reg] = ldl(addr);
aurel32dfbc7992008-11-30 16:24:21 +0000302 reg = (reg + 1) % 32;
aurel3276db3ba2008-12-08 18:11:21 +0000303 addr = addr_add(addr, 4);
aurel32dfbc7992008-11-30 16:24:21 +0000304 }
305 if (unlikely(nb > 0)) {
306 env->gpr[reg] = 0;
aurel3276db3ba2008-12-08 18:11:21 +0000307 for (sh = 24; nb > 0; nb--, sh -= 8) {
308 env->gpr[reg] |= ldub(addr) << sh;
309 addr = addr_add(addr, 1);
aurel32dfbc7992008-11-30 16:24:21 +0000310 }
311 }
312}
313/* PPC32 specification says we must generate an exception if
314 * rA is in the range of registers to be loaded.
315 * In an other hand, IBM says this is valid, but rA won't be loaded.
316 * For now, I'll follow the spec...
317 */
318void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
319{
320 if (likely(xer_bc != 0)) {
321 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
322 (reg < rb && (reg + xer_bc) > rb))) {
aurel32e06fcd72008-12-11 22:42:14 +0000323 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
324 POWERPC_EXCP_INVAL |
325 POWERPC_EXCP_INVAL_LSWX);
aurel32dfbc7992008-11-30 16:24:21 +0000326 } else {
327 helper_lsw(addr, xer_bc, reg);
328 }
329 }
330}
331
332void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
333{
334 int sh;
aurel3276db3ba2008-12-08 18:11:21 +0000335 for (; nb > 3; nb -= 4) {
336 stl(addr, env->gpr[reg]);
aurel32dfbc7992008-11-30 16:24:21 +0000337 reg = (reg + 1) % 32;
aurel3276db3ba2008-12-08 18:11:21 +0000338 addr = addr_add(addr, 4);
aurel32dfbc7992008-11-30 16:24:21 +0000339 }
340 if (unlikely(nb > 0)) {
aurel32a16b45e2008-12-29 09:46:58 +0000341 for (sh = 24; nb > 0; nb--, sh -= 8) {
aurel3276db3ba2008-12-08 18:11:21 +0000342 stb(addr, (env->gpr[reg] >> sh) & 0xFF);
aurel32a16b45e2008-12-29 09:46:58 +0000343 addr = addr_add(addr, 1);
344 }
aurel32dfbc7992008-11-30 16:24:21 +0000345 }
346}
347
aurel32799a8c82008-11-30 16:24:05 +0000348static void do_dcbz(target_ulong addr, int dcache_line_size)
349{
aurel3276db3ba2008-12-08 18:11:21 +0000350 addr &= ~(dcache_line_size - 1);
aurel32799a8c82008-11-30 16:24:05 +0000351 int i;
aurel32799a8c82008-11-30 16:24:05 +0000352 for (i = 0 ; i < dcache_line_size ; i += 4) {
aurel32dcc532c2008-11-30 17:54:21 +0000353 stl(addr + i , 0);
aurel32799a8c82008-11-30 16:24:05 +0000354 }
aurel3276db3ba2008-12-08 18:11:21 +0000355 if (env->reserve == addr)
aurel32799a8c82008-11-30 16:24:05 +0000356 env->reserve = (target_ulong)-1ULL;
357}
358
359void helper_dcbz(target_ulong addr)
360{
361 do_dcbz(addr, env->dcache_line_size);
362}
363
364void helper_dcbz_970(target_ulong addr)
365{
366 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
367 do_dcbz(addr, 32);
368 else
369 do_dcbz(addr, env->dcache_line_size);
370}
371
aurel3237d269d2008-11-30 16:24:13 +0000372void helper_icbi(target_ulong addr)
373{
374 uint32_t tmp;
375
aurel3276db3ba2008-12-08 18:11:21 +0000376 addr &= ~(env->dcache_line_size - 1);
aurel3237d269d2008-11-30 16:24:13 +0000377 /* Invalidate one cache line :
378 * PowerPC specification says this is to be treated like a load
379 * (not a fetch) by the MMU. To be sure it will be so,
380 * do the load "by hand".
381 */
aurel32dcc532c2008-11-30 17:54:21 +0000382 tmp = ldl(addr);
aurel3237d269d2008-11-30 16:24:13 +0000383 tb_invalidate_page_range(addr, addr + env->icache_line_size);
384}
385
aurel32bdb4b682008-11-30 16:24:30 +0000386// XXX: to be tested
387target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
388{
389 int i, c, d;
aurel32bdb4b682008-11-30 16:24:30 +0000390 d = 24;
391 for (i = 0; i < xer_bc; i++) {
aurel3276db3ba2008-12-08 18:11:21 +0000392 c = ldub(addr);
393 addr = addr_add(addr, 1);
aurel32bdb4b682008-11-30 16:24:30 +0000394 /* ra (if not 0) and rb are never modified */
395 if (likely(reg != rb && (ra == 0 || reg != ra))) {
396 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
397 }
398 if (unlikely(c == xer_cmp))
399 break;
400 if (likely(d != 0)) {
401 d -= 8;
402 } else {
403 d = 24;
404 reg++;
405 reg = reg & 0x1F;
406 }
407 }
408 return i;
409}
410
aurel32ff4a62c2008-11-30 16:23:56 +0000411/*****************************************************************************/
bellardfdabc362005-07-04 22:17:05 +0000412/* Fixed point operations helpers */
j_mayerd9bce9d2007-03-17 14:02:15 +0000413#if defined(TARGET_PPC64)
bellardfdabc362005-07-04 22:17:05 +0000414
aurel3274637402008-11-01 00:54:12 +0000415/* multiply high word */
416uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
bellardfdabc362005-07-04 22:17:05 +0000417{
aurel3274637402008-11-01 00:54:12 +0000418 uint64_t tl, th;
419
420 muls64(&tl, &th, arg1, arg2);
421 return th;
bellardfdabc362005-07-04 22:17:05 +0000422}
423
aurel3274637402008-11-01 00:54:12 +0000424/* multiply high word unsigned */
425uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
bellardfdabc362005-07-04 22:17:05 +0000426{
aurel3274637402008-11-01 00:54:12 +0000427 uint64_t tl, th;
bellardfdabc362005-07-04 22:17:05 +0000428
aurel3274637402008-11-01 00:54:12 +0000429 mulu64(&tl, &th, arg1, arg2);
430 return th;
bellardfdabc362005-07-04 22:17:05 +0000431}
432
aurel3274637402008-11-01 00:54:12 +0000433uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
j_mayerd9bce9d2007-03-17 14:02:15 +0000434{
435 int64_t th;
436 uint64_t tl;
437
aurel3274637402008-11-01 00:54:12 +0000438 muls64(&tl, (uint64_t *)&th, arg1, arg2);
j_mayer88ad9202007-10-25 23:36:08 +0000439 /* If th != 0 && th != -1, then we had an overflow */
j_mayer6f2d8972007-11-12 00:04:48 +0000440 if (likely((uint64_t)(th + 1) <= 1)) {
aurel323d7b4172008-10-21 11:28:46 +0000441 env->xer &= ~(1 << XER_OV);
j_mayerd9bce9d2007-03-17 14:02:15 +0000442 } else {
aurel323d7b4172008-10-21 11:28:46 +0000443 env->xer |= (1 << XER_OV) | (1 << XER_SO);
j_mayerd9bce9d2007-03-17 14:02:15 +0000444 }
aurel3274637402008-11-01 00:54:12 +0000445 return (int64_t)tl;
j_mayerd9bce9d2007-03-17 14:02:15 +0000446}
447#endif
448
aurel3226d67362008-10-21 11:31:27 +0000449target_ulong helper_cntlzw (target_ulong t)
j_mayer603fccc2007-10-28 12:54:53 +0000450{
aurel3226d67362008-10-21 11:31:27 +0000451 return clz32(t);
j_mayer603fccc2007-10-28 12:54:53 +0000452}
453
454#if defined(TARGET_PPC64)
aurel3226d67362008-10-21 11:31:27 +0000455target_ulong helper_cntlzd (target_ulong t)
j_mayer603fccc2007-10-28 12:54:53 +0000456{
aurel3226d67362008-10-21 11:31:27 +0000457 return clz64(t);
j_mayer603fccc2007-10-28 12:54:53 +0000458}
459#endif
460
bellard9a64fbe2004-01-04 22:58:38 +0000461/* shift right arithmetic helper */
aurel3226d67362008-10-21 11:31:27 +0000462target_ulong helper_sraw (target_ulong value, target_ulong shift)
bellard9a64fbe2004-01-04 22:58:38 +0000463{
464 int32_t ret;
465
aurel3226d67362008-10-21 11:31:27 +0000466 if (likely(!(shift & 0x20))) {
467 if (likely((uint32_t)shift != 0)) {
468 shift &= 0x1f;
469 ret = (int32_t)value >> shift;
470 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
aurel323d7b4172008-10-21 11:28:46 +0000471 env->xer &= ~(1 << XER_CA);
bellardfdabc362005-07-04 22:17:05 +0000472 } else {
aurel323d7b4172008-10-21 11:28:46 +0000473 env->xer |= (1 << XER_CA);
bellardfdabc362005-07-04 22:17:05 +0000474 }
475 } else {
aurel3226d67362008-10-21 11:31:27 +0000476 ret = (int32_t)value;
aurel323d7b4172008-10-21 11:28:46 +0000477 env->xer &= ~(1 << XER_CA);
bellardfdabc362005-07-04 22:17:05 +0000478 }
bellard9a64fbe2004-01-04 22:58:38 +0000479 } else {
aurel3226d67362008-10-21 11:31:27 +0000480 ret = (int32_t)value >> 31;
481 if (ret) {
aurel323d7b4172008-10-21 11:28:46 +0000482 env->xer |= (1 << XER_CA);
aurel3226d67362008-10-21 11:31:27 +0000483 } else {
484 env->xer &= ~(1 << XER_CA);
j_mayer76a66252007-03-07 08:32:30 +0000485 }
bellardfdabc362005-07-04 22:17:05 +0000486 }
aurel3226d67362008-10-21 11:31:27 +0000487 return (target_long)ret;
bellard9a64fbe2004-01-04 22:58:38 +0000488}
489
j_mayerd9bce9d2007-03-17 14:02:15 +0000490#if defined(TARGET_PPC64)
aurel3226d67362008-10-21 11:31:27 +0000491target_ulong helper_srad (target_ulong value, target_ulong shift)
j_mayerd9bce9d2007-03-17 14:02:15 +0000492{
493 int64_t ret;
494
aurel3226d67362008-10-21 11:31:27 +0000495 if (likely(!(shift & 0x40))) {
496 if (likely((uint64_t)shift != 0)) {
497 shift &= 0x3f;
498 ret = (int64_t)value >> shift;
499 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
aurel323d7b4172008-10-21 11:28:46 +0000500 env->xer &= ~(1 << XER_CA);
j_mayerd9bce9d2007-03-17 14:02:15 +0000501 } else {
aurel323d7b4172008-10-21 11:28:46 +0000502 env->xer |= (1 << XER_CA);
j_mayerd9bce9d2007-03-17 14:02:15 +0000503 }
504 } else {
aurel3226d67362008-10-21 11:31:27 +0000505 ret = (int64_t)value;
aurel323d7b4172008-10-21 11:28:46 +0000506 env->xer &= ~(1 << XER_CA);
j_mayerd9bce9d2007-03-17 14:02:15 +0000507 }
508 } else {
aurel3226d67362008-10-21 11:31:27 +0000509 ret = (int64_t)value >> 63;
510 if (ret) {
aurel323d7b4172008-10-21 11:28:46 +0000511 env->xer |= (1 << XER_CA);
aurel3226d67362008-10-21 11:31:27 +0000512 } else {
513 env->xer &= ~(1 << XER_CA);
j_mayerd9bce9d2007-03-17 14:02:15 +0000514 }
515 }
aurel3226d67362008-10-21 11:31:27 +0000516 return ret;
j_mayerd9bce9d2007-03-17 14:02:15 +0000517}
518#endif
519
aurel3226d67362008-10-21 11:31:27 +0000520target_ulong helper_popcntb (target_ulong val)
j_mayerd9bce9d2007-03-17 14:02:15 +0000521{
aurel326176a262008-11-01 00:54:33 +0000522 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
523 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
524 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
525 return val;
j_mayerd9bce9d2007-03-17 14:02:15 +0000526}
527
528#if defined(TARGET_PPC64)
aurel3226d67362008-10-21 11:31:27 +0000529target_ulong helper_popcntb_64 (target_ulong val)
j_mayerd9bce9d2007-03-17 14:02:15 +0000530{
aurel326176a262008-11-01 00:54:33 +0000531 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
532 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
533 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
534 return val;
j_mayerd9bce9d2007-03-17 14:02:15 +0000535}
536#endif
537
bellardfdabc362005-07-04 22:17:05 +0000538/*****************************************************************************/
bellard9a64fbe2004-01-04 22:58:38 +0000539/* Floating point operations helpers */
aurel32a0d7d5a2008-11-23 16:30:50 +0000540uint64_t helper_float32_to_float64(uint32_t arg)
541{
542 CPU_FloatU f;
543 CPU_DoubleU d;
544 f.l = arg;
545 d.d = float32_to_float64(f.f, &env->fp_status);
546 return d.ll;
547}
548
549uint32_t helper_float64_to_float32(uint64_t arg)
550{
551 CPU_FloatU f;
552 CPU_DoubleU d;
553 d.ll = arg;
554 f.f = float64_to_float32(d.d, &env->fp_status);
555 return f.l;
556}
557
aurel320ca9d382008-03-13 19:19:16 +0000558static always_inline int isden (float64 d)
j_mayer7c580442007-10-27 17:54:30 +0000559{
aurel320ca9d382008-03-13 19:19:16 +0000560 CPU_DoubleU u;
j_mayer7c580442007-10-27 17:54:30 +0000561
aurel320ca9d382008-03-13 19:19:16 +0000562 u.d = d;
j_mayer7c580442007-10-27 17:54:30 +0000563
aurel320ca9d382008-03-13 19:19:16 +0000564 return ((u.ll >> 52) & 0x7FF) == 0;
j_mayer7c580442007-10-27 17:54:30 +0000565}
566
aurel32af129062008-11-19 16:10:23 +0000567uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
j_mayer7c580442007-10-27 17:54:30 +0000568{
aurel32af129062008-11-19 16:10:23 +0000569 CPU_DoubleU farg;
j_mayer7c580442007-10-27 17:54:30 +0000570 int isneg;
aurel32af129062008-11-19 16:10:23 +0000571 int ret;
572 farg.ll = arg;
aurel32f23c3462008-12-15 17:14:27 +0000573 isneg = float64_is_neg(farg.d);
aurel32af129062008-11-19 16:10:23 +0000574 if (unlikely(float64_is_nan(farg.d))) {
575 if (float64_is_signaling_nan(farg.d)) {
j_mayer7c580442007-10-27 17:54:30 +0000576 /* Signaling NaN: flags are undefined */
aurel32af129062008-11-19 16:10:23 +0000577 ret = 0x00;
j_mayer7c580442007-10-27 17:54:30 +0000578 } else {
579 /* Quiet NaN */
aurel32af129062008-11-19 16:10:23 +0000580 ret = 0x11;
j_mayer7c580442007-10-27 17:54:30 +0000581 }
aurel32f23c3462008-12-15 17:14:27 +0000582 } else if (unlikely(float64_is_infinity(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +0000583 /* +/- infinity */
584 if (isneg)
aurel32af129062008-11-19 16:10:23 +0000585 ret = 0x09;
j_mayer7c580442007-10-27 17:54:30 +0000586 else
aurel32af129062008-11-19 16:10:23 +0000587 ret = 0x05;
j_mayer7c580442007-10-27 17:54:30 +0000588 } else {
aurel32f23c3462008-12-15 17:14:27 +0000589 if (float64_is_zero(farg.d)) {
j_mayer7c580442007-10-27 17:54:30 +0000590 /* +/- zero */
591 if (isneg)
aurel32af129062008-11-19 16:10:23 +0000592 ret = 0x12;
j_mayer7c580442007-10-27 17:54:30 +0000593 else
aurel32af129062008-11-19 16:10:23 +0000594 ret = 0x02;
j_mayer7c580442007-10-27 17:54:30 +0000595 } else {
aurel32af129062008-11-19 16:10:23 +0000596 if (isden(farg.d)) {
j_mayer7c580442007-10-27 17:54:30 +0000597 /* Denormalized numbers */
aurel32af129062008-11-19 16:10:23 +0000598 ret = 0x10;
j_mayer7c580442007-10-27 17:54:30 +0000599 } else {
600 /* Normalized numbers */
aurel32af129062008-11-19 16:10:23 +0000601 ret = 0x00;
j_mayer7c580442007-10-27 17:54:30 +0000602 }
603 if (isneg) {
aurel32af129062008-11-19 16:10:23 +0000604 ret |= 0x08;
j_mayer7c580442007-10-27 17:54:30 +0000605 } else {
aurel32af129062008-11-19 16:10:23 +0000606 ret |= 0x04;
j_mayer7c580442007-10-27 17:54:30 +0000607 }
608 }
609 }
610 if (set_fprf) {
611 /* We update FPSCR_FPRF */
612 env->fpscr &= ~(0x1F << FPSCR_FPRF);
aurel32af129062008-11-19 16:10:23 +0000613 env->fpscr |= ret << FPSCR_FPRF;
j_mayer7c580442007-10-27 17:54:30 +0000614 }
615 /* We just need fpcc to update Rc1 */
aurel32af129062008-11-19 16:10:23 +0000616 return ret & 0xF;
j_mayer7c580442007-10-27 17:54:30 +0000617}
618
619/* Floating-point invalid operations exception */
aurel32af129062008-11-19 16:10:23 +0000620static always_inline uint64_t fload_invalid_op_excp (int op)
j_mayer7c580442007-10-27 17:54:30 +0000621{
aurel32af129062008-11-19 16:10:23 +0000622 uint64_t ret = 0;
j_mayer7c580442007-10-27 17:54:30 +0000623 int ve;
624
625 ve = fpscr_ve;
aurel32e0147e42008-12-15 17:13:55 +0000626 switch (op) {
627 case POWERPC_EXCP_FP_VXSNAN:
j_mayer7c580442007-10-27 17:54:30 +0000628 env->fpscr |= 1 << FPSCR_VXSNAN;
aurel32e0147e42008-12-15 17:13:55 +0000629 break;
630 case POWERPC_EXCP_FP_VXSOFT:
j_mayer7c580442007-10-27 17:54:30 +0000631 env->fpscr |= 1 << FPSCR_VXSOFT;
aurel32e0147e42008-12-15 17:13:55 +0000632 break;
j_mayer7c580442007-10-27 17:54:30 +0000633 case POWERPC_EXCP_FP_VXISI:
634 /* Magnitude subtraction of infinities */
635 env->fpscr |= 1 << FPSCR_VXISI;
636 goto update_arith;
637 case POWERPC_EXCP_FP_VXIDI:
638 /* Division of infinity by infinity */
639 env->fpscr |= 1 << FPSCR_VXIDI;
640 goto update_arith;
641 case POWERPC_EXCP_FP_VXZDZ:
642 /* Division of zero by zero */
643 env->fpscr |= 1 << FPSCR_VXZDZ;
644 goto update_arith;
645 case POWERPC_EXCP_FP_VXIMZ:
646 /* Multiplication of zero by infinity */
647 env->fpscr |= 1 << FPSCR_VXIMZ;
648 goto update_arith;
649 case POWERPC_EXCP_FP_VXVC:
650 /* Ordered comparison of NaN */
651 env->fpscr |= 1 << FPSCR_VXVC;
652 env->fpscr &= ~(0xF << FPSCR_FPCC);
653 env->fpscr |= 0x11 << FPSCR_FPCC;
654 /* We must update the target FPR before raising the exception */
655 if (ve != 0) {
656 env->exception_index = POWERPC_EXCP_PROGRAM;
657 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
658 /* Update the floating-point enabled exception summary */
659 env->fpscr |= 1 << FPSCR_FEX;
660 /* Exception is differed */
661 ve = 0;
662 }
663 break;
664 case POWERPC_EXCP_FP_VXSQRT:
665 /* Square root of a negative number */
666 env->fpscr |= 1 << FPSCR_VXSQRT;
667 update_arith:
668 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
669 if (ve == 0) {
670 /* Set the result to quiet NaN */
aurel32e0147e42008-12-15 17:13:55 +0000671 ret = 0xFFF8000000000000ULL;
j_mayer7c580442007-10-27 17:54:30 +0000672 env->fpscr &= ~(0xF << FPSCR_FPCC);
673 env->fpscr |= 0x11 << FPSCR_FPCC;
674 }
675 break;
676 case POWERPC_EXCP_FP_VXCVI:
677 /* Invalid conversion */
678 env->fpscr |= 1 << FPSCR_VXCVI;
679 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
680 if (ve == 0) {
681 /* Set the result to quiet NaN */
aurel32e0147e42008-12-15 17:13:55 +0000682 ret = 0xFFF8000000000000ULL;
j_mayer7c580442007-10-27 17:54:30 +0000683 env->fpscr &= ~(0xF << FPSCR_FPCC);
684 env->fpscr |= 0x11 << FPSCR_FPCC;
685 }
686 break;
687 }
688 /* Update the floating-point invalid operation summary */
689 env->fpscr |= 1 << FPSCR_VX;
690 /* Update the floating-point exception summary */
691 env->fpscr |= 1 << FPSCR_FX;
692 if (ve != 0) {
693 /* Update the floating-point enabled exception summary */
694 env->fpscr |= 1 << FPSCR_FEX;
695 if (msr_fe0 != 0 || msr_fe1 != 0)
aurel32e06fcd72008-12-11 22:42:14 +0000696 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
j_mayer7c580442007-10-27 17:54:30 +0000697 }
aurel32af129062008-11-19 16:10:23 +0000698 return ret;
j_mayer7c580442007-10-27 17:54:30 +0000699}
700
aurel32e33e94f2008-12-18 22:44:21 +0000701static always_inline void float_zero_divide_excp (void)
j_mayer7c580442007-10-27 17:54:30 +0000702{
j_mayer7c580442007-10-27 17:54:30 +0000703 env->fpscr |= 1 << FPSCR_ZX;
704 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
705 /* Update the floating-point exception summary */
706 env->fpscr |= 1 << FPSCR_FX;
707 if (fpscr_ze != 0) {
708 /* Update the floating-point enabled exception summary */
709 env->fpscr |= 1 << FPSCR_FEX;
710 if (msr_fe0 != 0 || msr_fe1 != 0) {
aurel32e06fcd72008-12-11 22:42:14 +0000711 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
712 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
j_mayer7c580442007-10-27 17:54:30 +0000713 }
j_mayer7c580442007-10-27 17:54:30 +0000714 }
715}
716
717static always_inline void float_overflow_excp (void)
718{
719 env->fpscr |= 1 << FPSCR_OX;
720 /* Update the floating-point exception summary */
721 env->fpscr |= 1 << FPSCR_FX;
722 if (fpscr_oe != 0) {
723 /* XXX: should adjust the result */
724 /* Update the floating-point enabled exception summary */
725 env->fpscr |= 1 << FPSCR_FEX;
726 /* We must update the target FPR before raising the exception */
727 env->exception_index = POWERPC_EXCP_PROGRAM;
728 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
729 } else {
730 env->fpscr |= 1 << FPSCR_XX;
731 env->fpscr |= 1 << FPSCR_FI;
732 }
733}
734
735static always_inline void float_underflow_excp (void)
736{
737 env->fpscr |= 1 << FPSCR_UX;
738 /* Update the floating-point exception summary */
739 env->fpscr |= 1 << FPSCR_FX;
740 if (fpscr_ue != 0) {
741 /* XXX: should adjust the result */
742 /* Update the floating-point enabled exception summary */
743 env->fpscr |= 1 << FPSCR_FEX;
744 /* We must update the target FPR before raising the exception */
745 env->exception_index = POWERPC_EXCP_PROGRAM;
746 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
747 }
748}
749
750static always_inline void float_inexact_excp (void)
751{
752 env->fpscr |= 1 << FPSCR_XX;
753 /* Update the floating-point exception summary */
754 env->fpscr |= 1 << FPSCR_FX;
755 if (fpscr_xe != 0) {
756 /* Update the floating-point enabled exception summary */
757 env->fpscr |= 1 << FPSCR_FEX;
758 /* We must update the target FPR before raising the exception */
759 env->exception_index = POWERPC_EXCP_PROGRAM;
760 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
761 }
762}
763
764static always_inline void fpscr_set_rounding_mode (void)
765{
766 int rnd_type;
767
768 /* Set rounding mode */
769 switch (fpscr_rn) {
770 case 0:
771 /* Best approximation (round to nearest) */
772 rnd_type = float_round_nearest_even;
773 break;
774 case 1:
775 /* Smaller magnitude (round toward zero) */
776 rnd_type = float_round_to_zero;
777 break;
778 case 2:
779 /* Round toward +infinite */
780 rnd_type = float_round_up;
781 break;
782 default:
783 case 3:
784 /* Round toward -infinite */
785 rnd_type = float_round_down;
786 break;
787 }
788 set_float_rounding_mode(rnd_type, &env->fp_status);
789}
790
aurel326e35d522008-12-14 18:40:58 +0000791void helper_fpscr_clrbit (uint32_t bit)
792{
793 int prev;
794
795 prev = (env->fpscr >> bit) & 1;
796 env->fpscr &= ~(1 << bit);
797 if (prev == 1) {
798 switch (bit) {
799 case FPSCR_RN1:
800 case FPSCR_RN:
801 fpscr_set_rounding_mode();
802 break;
803 default:
804 break;
805 }
806 }
807}
808
aurel32af129062008-11-19 16:10:23 +0000809void helper_fpscr_setbit (uint32_t bit)
j_mayer7c580442007-10-27 17:54:30 +0000810{
811 int prev;
812
813 prev = (env->fpscr >> bit) & 1;
814 env->fpscr |= 1 << bit;
815 if (prev == 0) {
816 switch (bit) {
817 case FPSCR_VX:
818 env->fpscr |= 1 << FPSCR_FX;
819 if (fpscr_ve)
820 goto raise_ve;
821 case FPSCR_OX:
822 env->fpscr |= 1 << FPSCR_FX;
823 if (fpscr_oe)
824 goto raise_oe;
825 break;
826 case FPSCR_UX:
827 env->fpscr |= 1 << FPSCR_FX;
828 if (fpscr_ue)
829 goto raise_ue;
830 break;
831 case FPSCR_ZX:
832 env->fpscr |= 1 << FPSCR_FX;
833 if (fpscr_ze)
834 goto raise_ze;
835 break;
836 case FPSCR_XX:
837 env->fpscr |= 1 << FPSCR_FX;
838 if (fpscr_xe)
839 goto raise_xe;
840 break;
841 case FPSCR_VXSNAN:
842 case FPSCR_VXISI:
843 case FPSCR_VXIDI:
844 case FPSCR_VXZDZ:
845 case FPSCR_VXIMZ:
846 case FPSCR_VXVC:
847 case FPSCR_VXSOFT:
848 case FPSCR_VXSQRT:
849 case FPSCR_VXCVI:
850 env->fpscr |= 1 << FPSCR_VX;
851 env->fpscr |= 1 << FPSCR_FX;
852 if (fpscr_ve != 0)
853 goto raise_ve;
854 break;
855 case FPSCR_VE:
856 if (fpscr_vx != 0) {
857 raise_ve:
858 env->error_code = POWERPC_EXCP_FP;
859 if (fpscr_vxsnan)
860 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
861 if (fpscr_vxisi)
862 env->error_code |= POWERPC_EXCP_FP_VXISI;
863 if (fpscr_vxidi)
864 env->error_code |= POWERPC_EXCP_FP_VXIDI;
865 if (fpscr_vxzdz)
866 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
867 if (fpscr_vximz)
868 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
869 if (fpscr_vxvc)
870 env->error_code |= POWERPC_EXCP_FP_VXVC;
871 if (fpscr_vxsoft)
872 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
873 if (fpscr_vxsqrt)
874 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
875 if (fpscr_vxcvi)
876 env->error_code |= POWERPC_EXCP_FP_VXCVI;
877 goto raise_excp;
878 }
879 break;
880 case FPSCR_OE:
881 if (fpscr_ox != 0) {
882 raise_oe:
883 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
884 goto raise_excp;
885 }
886 break;
887 case FPSCR_UE:
888 if (fpscr_ux != 0) {
889 raise_ue:
890 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
891 goto raise_excp;
892 }
893 break;
894 case FPSCR_ZE:
895 if (fpscr_zx != 0) {
896 raise_ze:
897 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
898 goto raise_excp;
899 }
900 break;
901 case FPSCR_XE:
902 if (fpscr_xx != 0) {
903 raise_xe:
904 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
905 goto raise_excp;
906 }
907 break;
908 case FPSCR_RN1:
909 case FPSCR_RN:
910 fpscr_set_rounding_mode();
911 break;
912 default:
913 break;
914 raise_excp:
915 /* Update the floating-point enabled exception summary */
916 env->fpscr |= 1 << FPSCR_FEX;
917 /* We have to update Rc1 before raising the exception */
918 env->exception_index = POWERPC_EXCP_PROGRAM;
919 break;
920 }
921 }
922}
923
aurel32af129062008-11-19 16:10:23 +0000924void helper_store_fpscr (uint64_t arg, uint32_t mask)
j_mayer7c580442007-10-27 17:54:30 +0000925{
926 /*
927 * We use only the 32 LSB of the incoming fpr
928 */
j_mayer7c580442007-10-27 17:54:30 +0000929 uint32_t prev, new;
930 int i;
931
j_mayer7c580442007-10-27 17:54:30 +0000932 prev = env->fpscr;
aurel32af129062008-11-19 16:10:23 +0000933 new = (uint32_t)arg;
aurel3227ee5df2008-12-15 00:30:28 +0000934 new &= ~0x60000000;
935 new |= prev & 0x60000000;
936 for (i = 0; i < 8; i++) {
j_mayer7c580442007-10-27 17:54:30 +0000937 if (mask & (1 << i)) {
938 env->fpscr &= ~(0xF << (4 * i));
939 env->fpscr |= new & (0xF << (4 * i));
940 }
941 }
942 /* Update VX and FEX */
943 if (fpscr_ix != 0)
944 env->fpscr |= 1 << FPSCR_VX;
aurel3255670252008-03-10 00:09:28 +0000945 else
946 env->fpscr &= ~(1 << FPSCR_VX);
j_mayer7c580442007-10-27 17:54:30 +0000947 if ((fpscr_ex & fpscr_eex) != 0) {
948 env->fpscr |= 1 << FPSCR_FEX;
949 env->exception_index = POWERPC_EXCP_PROGRAM;
950 /* XXX: we should compute it properly */
951 env->error_code = POWERPC_EXCP_FP;
952 }
aurel3255670252008-03-10 00:09:28 +0000953 else
954 env->fpscr &= ~(1 << FPSCR_FEX);
j_mayer7c580442007-10-27 17:54:30 +0000955 fpscr_set_rounding_mode();
956}
j_mayer7c580442007-10-27 17:54:30 +0000957
aurel32af129062008-11-19 16:10:23 +0000958void helper_float_check_status (void)
j_mayer7c580442007-10-27 17:54:30 +0000959{
aurel32af129062008-11-19 16:10:23 +0000960#ifdef CONFIG_SOFTFLOAT
j_mayer7c580442007-10-27 17:54:30 +0000961 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
962 (env->error_code & POWERPC_EXCP_FP)) {
963 /* Differred floating-point exception after target FPR update */
964 if (msr_fe0 != 0 || msr_fe1 != 0)
aurel32e06fcd72008-12-11 22:42:14 +0000965 helper_raise_exception_err(env->exception_index, env->error_code);
aurel32be94c952008-12-13 12:13:33 +0000966 } else {
967 int status = get_float_exception_flags(&env->fp_status);
aurel32e33e94f2008-12-18 22:44:21 +0000968 if (status & float_flag_divbyzero) {
969 float_zero_divide_excp();
970 } else if (status & float_flag_overflow) {
aurel32be94c952008-12-13 12:13:33 +0000971 float_overflow_excp();
972 } else if (status & float_flag_underflow) {
973 float_underflow_excp();
974 } else if (status & float_flag_inexact) {
975 float_inexact_excp();
976 }
j_mayer7c580442007-10-27 17:54:30 +0000977 }
aurel32af129062008-11-19 16:10:23 +0000978#else
979 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
980 (env->error_code & POWERPC_EXCP_FP)) {
981 /* Differred floating-point exception after target FPR update */
982 if (msr_fe0 != 0 || msr_fe1 != 0)
aurel32e06fcd72008-12-11 22:42:14 +0000983 helper_raise_exception_err(env->exception_index, env->error_code);
aurel32af129062008-11-19 16:10:23 +0000984 }
aurel32af129062008-11-19 16:10:23 +0000985#endif
986}
987
988#ifdef CONFIG_SOFTFLOAT
989void helper_reset_fpstatus (void)
990{
aurel32be94c952008-12-13 12:13:33 +0000991 set_float_exception_flags(0, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +0000992}
993#endif
994
aurel32af129062008-11-19 16:10:23 +0000995/* fadd - fadd. */
996uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
997{
998 CPU_DoubleU farg1, farg2;
999
1000 farg1.ll = arg1;
1001 farg2.ll = arg2;
aurel321cdb9c32008-04-07 21:24:25 +00001002#if USE_PRECISE_EMULATION
aurel32af129062008-11-19 16:10:23 +00001003 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1004 float64_is_signaling_nan(farg2.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001005 /* sNaN addition */
aurel32af129062008-11-19 16:10:23 +00001006 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel3217218d12008-12-15 17:14:35 +00001007 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
1008 float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001009 /* Magnitude subtraction of infinities */
aurel32cf1cf212008-12-13 11:46:36 +00001010 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
aurel3217218d12008-12-15 17:14:35 +00001011 } else {
1012 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001013 }
aurel32af129062008-11-19 16:10:23 +00001014#else
1015 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1016#endif
1017 return farg1.ll;
j_mayer7c580442007-10-27 17:54:30 +00001018}
1019
aurel32af129062008-11-19 16:10:23 +00001020/* fsub - fsub. */
1021uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
j_mayer7c580442007-10-27 17:54:30 +00001022{
aurel32af129062008-11-19 16:10:23 +00001023 CPU_DoubleU farg1, farg2;
1024
1025 farg1.ll = arg1;
1026 farg2.ll = arg2;
1027#if USE_PRECISE_EMULATION
1028{
1029 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1030 float64_is_signaling_nan(farg2.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001031 /* sNaN subtraction */
aurel32af129062008-11-19 16:10:23 +00001032 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel3217218d12008-12-15 17:14:35 +00001033 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
1034 float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001035 /* Magnitude subtraction of infinities */
aurel32af129062008-11-19 16:10:23 +00001036 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
aurel3217218d12008-12-15 17:14:35 +00001037 } else {
1038 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001039 }
1040}
aurel32af129062008-11-19 16:10:23 +00001041#else
1042 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1043#endif
1044 return farg1.ll;
1045}
j_mayer7c580442007-10-27 17:54:30 +00001046
aurel32af129062008-11-19 16:10:23 +00001047/* fmul - fmul. */
1048uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
j_mayer7c580442007-10-27 17:54:30 +00001049{
aurel32af129062008-11-19 16:10:23 +00001050 CPU_DoubleU farg1, farg2;
1051
1052 farg1.ll = arg1;
1053 farg2.ll = arg2;
1054#if USE_PRECISE_EMULATION
1055 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1056 float64_is_signaling_nan(farg2.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001057 /* sNaN multiplication */
aurel32af129062008-11-19 16:10:23 +00001058 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32f23c3462008-12-15 17:14:27 +00001059 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1060 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
j_mayer7c580442007-10-27 17:54:30 +00001061 /* Multiplication of zero by infinity */
aurel32af129062008-11-19 16:10:23 +00001062 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
j_mayer7c580442007-10-27 17:54:30 +00001063 } else {
aurel32af129062008-11-19 16:10:23 +00001064 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001065 }
aurel32af129062008-11-19 16:10:23 +00001066#else
1067 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1068#endif
1069 return farg1.ll;
1070}
j_mayer7c580442007-10-27 17:54:30 +00001071
aurel32af129062008-11-19 16:10:23 +00001072/* fdiv - fdiv. */
1073uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
j_mayer7c580442007-10-27 17:54:30 +00001074{
aurel32af129062008-11-19 16:10:23 +00001075 CPU_DoubleU farg1, farg2;
1076
1077 farg1.ll = arg1;
1078 farg2.ll = arg2;
1079#if USE_PRECISE_EMULATION
1080 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1081 float64_is_signaling_nan(farg2.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001082 /* sNaN division */
aurel32af129062008-11-19 16:10:23 +00001083 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32f23c3462008-12-15 17:14:27 +00001084 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001085 /* Division of infinity by infinity */
aurel32af129062008-11-19 16:10:23 +00001086 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
aurel32e33e94f2008-12-18 22:44:21 +00001087 } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) {
1088 /* Division of zero by zero */
1089 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
j_mayer7c580442007-10-27 17:54:30 +00001090 } else {
aurel32af129062008-11-19 16:10:23 +00001091 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001092 }
aurel32af129062008-11-19 16:10:23 +00001093#else
1094 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1095#endif
1096 return farg1.ll;
j_mayer7c580442007-10-27 17:54:30 +00001097}
j_mayer7c580442007-10-27 17:54:30 +00001098
aurel32af129062008-11-19 16:10:23 +00001099/* fabs */
1100uint64_t helper_fabs (uint64_t arg)
bellard9a64fbe2004-01-04 22:58:38 +00001101{
aurel32af129062008-11-19 16:10:23 +00001102 CPU_DoubleU farg;
bellard9a64fbe2004-01-04 22:58:38 +00001103
aurel32af129062008-11-19 16:10:23 +00001104 farg.ll = arg;
1105 farg.d = float64_abs(farg.d);
1106 return farg.ll;
1107}
1108
1109/* fnabs */
1110uint64_t helper_fnabs (uint64_t arg)
1111{
1112 CPU_DoubleU farg;
1113
1114 farg.ll = arg;
1115 farg.d = float64_abs(farg.d);
1116 farg.d = float64_chs(farg.d);
1117 return farg.ll;
1118}
1119
1120/* fneg */
1121uint64_t helper_fneg (uint64_t arg)
1122{
1123 CPU_DoubleU farg;
1124
1125 farg.ll = arg;
1126 farg.d = float64_chs(farg.d);
1127 return farg.ll;
1128}
1129
1130/* fctiw - fctiw. */
1131uint64_t helper_fctiw (uint64_t arg)
1132{
1133 CPU_DoubleU farg;
1134 farg.ll = arg;
1135
1136 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001137 /* sNaN conversion */
aurel32af129062008-11-19 16:10:23 +00001138 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
aurel32f23c3462008-12-15 17:14:27 +00001139 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001140 /* qNan / infinity conversion */
aurel32af129062008-11-19 16:10:23 +00001141 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
j_mayer7c580442007-10-27 17:54:30 +00001142 } else {
aurel32af129062008-11-19 16:10:23 +00001143 farg.ll = float64_to_int32(farg.d, &env->fp_status);
aurel321cdb9c32008-04-07 21:24:25 +00001144#if USE_PRECISE_EMULATION
j_mayer7c580442007-10-27 17:54:30 +00001145 /* XXX: higher bits are not supposed to be significant.
1146 * to make tests easier, return the same as a real PowerPC 750
1147 */
aurel32af129062008-11-19 16:10:23 +00001148 farg.ll |= 0xFFF80000ULL << 32;
j_mayere864cab2007-03-22 22:17:08 +00001149#endif
j_mayer7c580442007-10-27 17:54:30 +00001150 }
aurel32af129062008-11-19 16:10:23 +00001151 return farg.ll;
bellard9a64fbe2004-01-04 22:58:38 +00001152}
1153
aurel32af129062008-11-19 16:10:23 +00001154/* fctiwz - fctiwz. */
1155uint64_t helper_fctiwz (uint64_t arg)
bellard9a64fbe2004-01-04 22:58:38 +00001156{
aurel32af129062008-11-19 16:10:23 +00001157 CPU_DoubleU farg;
1158 farg.ll = arg;
bellard9a64fbe2004-01-04 22:58:38 +00001159
aurel32af129062008-11-19 16:10:23 +00001160 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001161 /* sNaN conversion */
aurel32af129062008-11-19 16:10:23 +00001162 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
aurel32f23c3462008-12-15 17:14:27 +00001163 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001164 /* qNan / infinity conversion */
aurel32af129062008-11-19 16:10:23 +00001165 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
j_mayer7c580442007-10-27 17:54:30 +00001166 } else {
aurel32af129062008-11-19 16:10:23 +00001167 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
aurel321cdb9c32008-04-07 21:24:25 +00001168#if USE_PRECISE_EMULATION
j_mayer7c580442007-10-27 17:54:30 +00001169 /* XXX: higher bits are not supposed to be significant.
1170 * to make tests easier, return the same as a real PowerPC 750
1171 */
aurel32af129062008-11-19 16:10:23 +00001172 farg.ll |= 0xFFF80000ULL << 32;
j_mayere864cab2007-03-22 22:17:08 +00001173#endif
j_mayer7c580442007-10-27 17:54:30 +00001174 }
aurel32af129062008-11-19 16:10:23 +00001175 return farg.ll;
bellard9a64fbe2004-01-04 22:58:38 +00001176}
1177
j_mayer426613d2007-03-23 09:45:27 +00001178#if defined(TARGET_PPC64)
aurel32af129062008-11-19 16:10:23 +00001179/* fcfid - fcfid. */
1180uint64_t helper_fcfid (uint64_t arg)
j_mayer426613d2007-03-23 09:45:27 +00001181{
aurel32af129062008-11-19 16:10:23 +00001182 CPU_DoubleU farg;
1183 farg.d = int64_to_float64(arg, &env->fp_status);
1184 return farg.ll;
j_mayer426613d2007-03-23 09:45:27 +00001185}
1186
aurel32af129062008-11-19 16:10:23 +00001187/* fctid - fctid. */
1188uint64_t helper_fctid (uint64_t arg)
j_mayer426613d2007-03-23 09:45:27 +00001189{
aurel32af129062008-11-19 16:10:23 +00001190 CPU_DoubleU farg;
1191 farg.ll = arg;
j_mayer426613d2007-03-23 09:45:27 +00001192
aurel32af129062008-11-19 16:10:23 +00001193 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001194 /* sNaN conversion */
aurel32af129062008-11-19 16:10:23 +00001195 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
aurel32f23c3462008-12-15 17:14:27 +00001196 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001197 /* qNan / infinity conversion */
aurel32af129062008-11-19 16:10:23 +00001198 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
j_mayer7c580442007-10-27 17:54:30 +00001199 } else {
aurel32af129062008-11-19 16:10:23 +00001200 farg.ll = float64_to_int64(farg.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001201 }
aurel32af129062008-11-19 16:10:23 +00001202 return farg.ll;
j_mayer426613d2007-03-23 09:45:27 +00001203}
1204
aurel32af129062008-11-19 16:10:23 +00001205/* fctidz - fctidz. */
1206uint64_t helper_fctidz (uint64_t arg)
j_mayer426613d2007-03-23 09:45:27 +00001207{
aurel32af129062008-11-19 16:10:23 +00001208 CPU_DoubleU farg;
1209 farg.ll = arg;
j_mayer426613d2007-03-23 09:45:27 +00001210
aurel32af129062008-11-19 16:10:23 +00001211 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001212 /* sNaN conversion */
aurel32af129062008-11-19 16:10:23 +00001213 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
aurel32f23c3462008-12-15 17:14:27 +00001214 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001215 /* qNan / infinity conversion */
aurel32af129062008-11-19 16:10:23 +00001216 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
j_mayer7c580442007-10-27 17:54:30 +00001217 } else {
aurel32af129062008-11-19 16:10:23 +00001218 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001219 }
aurel32af129062008-11-19 16:10:23 +00001220 return farg.ll;
j_mayer426613d2007-03-23 09:45:27 +00001221}
1222
1223#endif
1224
aurel32af129062008-11-19 16:10:23 +00001225static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
j_mayerd7e4b872007-09-30 01:11:48 +00001226{
aurel32af129062008-11-19 16:10:23 +00001227 CPU_DoubleU farg;
1228 farg.ll = arg;
1229
1230 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001231 /* sNaN round */
aurel32af129062008-11-19 16:10:23 +00001232 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
aurel32f23c3462008-12-15 17:14:27 +00001233 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001234 /* qNan / infinity round */
aurel32af129062008-11-19 16:10:23 +00001235 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
j_mayer7c580442007-10-27 17:54:30 +00001236 } else {
1237 set_float_rounding_mode(rounding_mode, &env->fp_status);
aurel32af129062008-11-19 16:10:23 +00001238 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001239 /* Restore rounding mode from FPSCR */
1240 fpscr_set_rounding_mode();
1241 }
aurel32af129062008-11-19 16:10:23 +00001242 return farg.ll;
j_mayerd7e4b872007-09-30 01:11:48 +00001243}
1244
aurel32af129062008-11-19 16:10:23 +00001245uint64_t helper_frin (uint64_t arg)
j_mayerd7e4b872007-09-30 01:11:48 +00001246{
aurel32af129062008-11-19 16:10:23 +00001247 return do_fri(arg, float_round_nearest_even);
j_mayerd7e4b872007-09-30 01:11:48 +00001248}
1249
aurel32af129062008-11-19 16:10:23 +00001250uint64_t helper_friz (uint64_t arg)
j_mayerd7e4b872007-09-30 01:11:48 +00001251{
aurel32af129062008-11-19 16:10:23 +00001252 return do_fri(arg, float_round_to_zero);
j_mayerd7e4b872007-09-30 01:11:48 +00001253}
1254
aurel32af129062008-11-19 16:10:23 +00001255uint64_t helper_frip (uint64_t arg)
j_mayerd7e4b872007-09-30 01:11:48 +00001256{
aurel32af129062008-11-19 16:10:23 +00001257 return do_fri(arg, float_round_up);
j_mayerd7e4b872007-09-30 01:11:48 +00001258}
1259
aurel32af129062008-11-19 16:10:23 +00001260uint64_t helper_frim (uint64_t arg)
j_mayerd7e4b872007-09-30 01:11:48 +00001261{
aurel32af129062008-11-19 16:10:23 +00001262 return do_fri(arg, float_round_down);
j_mayerd7e4b872007-09-30 01:11:48 +00001263}
1264
aurel32af129062008-11-19 16:10:23 +00001265/* fmadd - fmadd. */
1266uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1267{
1268 CPU_DoubleU farg1, farg2, farg3;
1269
1270 farg1.ll = arg1;
1271 farg2.ll = arg2;
1272 farg3.ll = arg3;
aurel321cdb9c32008-04-07 21:24:25 +00001273#if USE_PRECISE_EMULATION
aurel32af129062008-11-19 16:10:23 +00001274 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1275 float64_is_signaling_nan(farg2.d) ||
1276 float64_is_signaling_nan(farg3.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001277 /* sNaN operation */
aurel32af129062008-11-19 16:10:23 +00001278 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32da1e7ac2008-12-15 17:14:43 +00001279 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1280 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1281 /* Multiplication of zero by infinity */
1282 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
j_mayer7c580442007-10-27 17:54:30 +00001283 } else {
j_mayere864cab2007-03-22 22:17:08 +00001284#ifdef FLOAT128
j_mayer7c580442007-10-27 17:54:30 +00001285 /* This is the way the PowerPC specification defines it */
1286 float128 ft0_128, ft1_128;
j_mayere864cab2007-03-22 22:17:08 +00001287
aurel32af129062008-11-19 16:10:23 +00001288 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1289 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001290 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
aurel32da1e7ac2008-12-15 17:14:43 +00001291 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1292 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
1293 /* Magnitude subtraction of infinities */
1294 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1295 } else {
1296 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1297 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1298 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1299 }
j_mayere864cab2007-03-22 22:17:08 +00001300#else
j_mayer7c580442007-10-27 17:54:30 +00001301 /* This is OK on x86 hosts */
aurel32af129062008-11-19 16:10:23 +00001302 farg1.d = (farg1.d * farg2.d) + farg3.d;
j_mayere864cab2007-03-22 22:17:08 +00001303#endif
j_mayer7c580442007-10-27 17:54:30 +00001304 }
aurel32af129062008-11-19 16:10:23 +00001305#else
1306 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1307 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1308#endif
1309 return farg1.ll;
j_mayere864cab2007-03-22 22:17:08 +00001310}
1311
aurel32af129062008-11-19 16:10:23 +00001312/* fmsub - fmsub. */
1313uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
j_mayere864cab2007-03-22 22:17:08 +00001314{
aurel32af129062008-11-19 16:10:23 +00001315 CPU_DoubleU farg1, farg2, farg3;
1316
1317 farg1.ll = arg1;
1318 farg2.ll = arg2;
1319 farg3.ll = arg3;
1320#if USE_PRECISE_EMULATION
1321 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1322 float64_is_signaling_nan(farg2.d) ||
1323 float64_is_signaling_nan(farg3.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001324 /* sNaN operation */
aurel32af129062008-11-19 16:10:23 +00001325 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32da1e7ac2008-12-15 17:14:43 +00001326 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1327 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1328 /* Multiplication of zero by infinity */
1329 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
j_mayer7c580442007-10-27 17:54:30 +00001330 } else {
j_mayere864cab2007-03-22 22:17:08 +00001331#ifdef FLOAT128
j_mayer7c580442007-10-27 17:54:30 +00001332 /* This is the way the PowerPC specification defines it */
1333 float128 ft0_128, ft1_128;
j_mayere864cab2007-03-22 22:17:08 +00001334
aurel32af129062008-11-19 16:10:23 +00001335 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1336 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001337 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
aurel32da1e7ac2008-12-15 17:14:43 +00001338 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1339 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
1340 /* Magnitude subtraction of infinities */
1341 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1342 } else {
1343 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1344 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1345 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1346 }
j_mayere864cab2007-03-22 22:17:08 +00001347#else
j_mayer7c580442007-10-27 17:54:30 +00001348 /* This is OK on x86 hosts */
aurel32af129062008-11-19 16:10:23 +00001349 farg1.d = (farg1.d * farg2.d) - farg3.d;
j_mayere864cab2007-03-22 22:17:08 +00001350#endif
j_mayer7c580442007-10-27 17:54:30 +00001351 }
aurel32af129062008-11-19 16:10:23 +00001352#else
1353 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1354 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1355#endif
1356 return farg1.ll;
j_mayere864cab2007-03-22 22:17:08 +00001357}
j_mayere864cab2007-03-22 22:17:08 +00001358
aurel32af129062008-11-19 16:10:23 +00001359/* fnmadd - fnmadd. */
1360uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
bellard4b3686f2004-05-23 22:18:12 +00001361{
aurel32af129062008-11-19 16:10:23 +00001362 CPU_DoubleU farg1, farg2, farg3;
1363
1364 farg1.ll = arg1;
1365 farg2.ll = arg2;
1366 farg3.ll = arg3;
1367
1368 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1369 float64_is_signaling_nan(farg2.d) ||
1370 float64_is_signaling_nan(farg3.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001371 /* sNaN operation */
aurel32af129062008-11-19 16:10:23 +00001372 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32da1e7ac2008-12-15 17:14:43 +00001373 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1374 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1375 /* Multiplication of zero by infinity */
1376 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
j_mayer7c580442007-10-27 17:54:30 +00001377 } else {
aurel321cdb9c32008-04-07 21:24:25 +00001378#if USE_PRECISE_EMULATION
j_mayere864cab2007-03-22 22:17:08 +00001379#ifdef FLOAT128
j_mayer7c580442007-10-27 17:54:30 +00001380 /* This is the way the PowerPC specification defines it */
1381 float128 ft0_128, ft1_128;
j_mayere864cab2007-03-22 22:17:08 +00001382
aurel32af129062008-11-19 16:10:23 +00001383 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1384 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001385 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
aurel32da1e7ac2008-12-15 17:14:43 +00001386 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1387 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
1388 /* Magnitude subtraction of infinities */
1389 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1390 } else {
1391 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1392 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1393 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1394 }
j_mayere864cab2007-03-22 22:17:08 +00001395#else
j_mayer7c580442007-10-27 17:54:30 +00001396 /* This is OK on x86 hosts */
aurel32af129062008-11-19 16:10:23 +00001397 farg1.d = (farg1.d * farg2.d) + farg3.d;
j_mayere864cab2007-03-22 22:17:08 +00001398#endif
1399#else
aurel32af129062008-11-19 16:10:23 +00001400 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1401 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
j_mayere864cab2007-03-22 22:17:08 +00001402#endif
aurel32a44d2ce2008-12-13 11:46:27 +00001403 if (likely(!float64_is_nan(farg1.d)))
aurel32af129062008-11-19 16:10:23 +00001404 farg1.d = float64_chs(farg1.d);
j_mayer7c580442007-10-27 17:54:30 +00001405 }
aurel32af129062008-11-19 16:10:23 +00001406 return farg1.ll;
bellard4b3686f2004-05-23 22:18:12 +00001407}
1408
aurel32af129062008-11-19 16:10:23 +00001409/* fnmsub - fnmsub. */
1410uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
bellard4b3686f2004-05-23 22:18:12 +00001411{
aurel32af129062008-11-19 16:10:23 +00001412 CPU_DoubleU farg1, farg2, farg3;
1413
1414 farg1.ll = arg1;
1415 farg2.ll = arg2;
1416 farg3.ll = arg3;
1417
1418 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1419 float64_is_signaling_nan(farg2.d) ||
1420 float64_is_signaling_nan(farg3.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001421 /* sNaN operation */
aurel32af129062008-11-19 16:10:23 +00001422 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32da1e7ac2008-12-15 17:14:43 +00001423 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1424 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1425 /* Multiplication of zero by infinity */
1426 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
j_mayer7c580442007-10-27 17:54:30 +00001427 } else {
aurel321cdb9c32008-04-07 21:24:25 +00001428#if USE_PRECISE_EMULATION
j_mayere864cab2007-03-22 22:17:08 +00001429#ifdef FLOAT128
j_mayer7c580442007-10-27 17:54:30 +00001430 /* This is the way the PowerPC specification defines it */
1431 float128 ft0_128, ft1_128;
j_mayere864cab2007-03-22 22:17:08 +00001432
aurel32af129062008-11-19 16:10:23 +00001433 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1434 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001435 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
aurel32da1e7ac2008-12-15 17:14:43 +00001436 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1437 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
1438 /* Magnitude subtraction of infinities */
1439 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1440 } else {
1441 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1442 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1443 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1444 }
j_mayere864cab2007-03-22 22:17:08 +00001445#else
j_mayer7c580442007-10-27 17:54:30 +00001446 /* This is OK on x86 hosts */
aurel32af129062008-11-19 16:10:23 +00001447 farg1.d = (farg1.d * farg2.d) - farg3.d;
j_mayere864cab2007-03-22 22:17:08 +00001448#endif
1449#else
aurel32af129062008-11-19 16:10:23 +00001450 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1451 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
j_mayere864cab2007-03-22 22:17:08 +00001452#endif
aurel32a44d2ce2008-12-13 11:46:27 +00001453 if (likely(!float64_is_nan(farg1.d)))
aurel32af129062008-11-19 16:10:23 +00001454 farg1.d = float64_chs(farg1.d);
j_mayer7c580442007-10-27 17:54:30 +00001455 }
aurel32af129062008-11-19 16:10:23 +00001456 return farg1.ll;
bellard1ef59d02004-04-26 19:48:05 +00001457}
1458
aurel32af129062008-11-19 16:10:23 +00001459/* frsp - frsp. */
1460uint64_t helper_frsp (uint64_t arg)
1461{
1462 CPU_DoubleU farg;
aurel326ad193e2008-12-15 01:00:17 +00001463 float32 f32;
aurel32af129062008-11-19 16:10:23 +00001464 farg.ll = arg;
1465
aurel321cdb9c32008-04-07 21:24:25 +00001466#if USE_PRECISE_EMULATION
aurel32af129062008-11-19 16:10:23 +00001467 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001468 /* sNaN square root */
aurel32af129062008-11-19 16:10:23 +00001469 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
j_mayer7c580442007-10-27 17:54:30 +00001470 } else {
aurel326ad193e2008-12-15 01:00:17 +00001471 f32 = float64_to_float32(farg.d, &env->fp_status);
1472 farg.d = float32_to_float64(f32, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001473 }
aurel32af129062008-11-19 16:10:23 +00001474#else
aurel326ad193e2008-12-15 01:00:17 +00001475 f32 = float64_to_float32(farg.d, &env->fp_status);
1476 farg.d = float32_to_float64(f32, &env->fp_status);
aurel32af129062008-11-19 16:10:23 +00001477#endif
1478 return farg.ll;
j_mayer7c580442007-10-27 17:54:30 +00001479}
j_mayer7c580442007-10-27 17:54:30 +00001480
aurel32af129062008-11-19 16:10:23 +00001481/* fsqrt - fsqrt. */
1482uint64_t helper_fsqrt (uint64_t arg)
bellard9a64fbe2004-01-04 22:58:38 +00001483{
aurel32af129062008-11-19 16:10:23 +00001484 CPU_DoubleU farg;
1485 farg.ll = arg;
1486
1487 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001488 /* sNaN square root */
aurel32af129062008-11-19 16:10:23 +00001489 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32f23c3462008-12-15 17:14:27 +00001490 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001491 /* Square root of a negative nonzero number */
aurel32af129062008-11-19 16:10:23 +00001492 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
j_mayer7c580442007-10-27 17:54:30 +00001493 } else {
aurel32af129062008-11-19 16:10:23 +00001494 farg.d = float64_sqrt(farg.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001495 }
aurel32af129062008-11-19 16:10:23 +00001496 return farg.ll;
bellard9a64fbe2004-01-04 22:58:38 +00001497}
1498
aurel32af129062008-11-19 16:10:23 +00001499/* fre - fre. */
1500uint64_t helper_fre (uint64_t arg)
j_mayerd7e4b872007-09-30 01:11:48 +00001501{
aurel3205b93602008-12-15 17:13:48 +00001502 CPU_DoubleU fone, farg;
aurel3201feec02008-12-16 10:44:29 +00001503 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
aurel32af129062008-11-19 16:10:23 +00001504 farg.ll = arg;
j_mayerd7e4b872007-09-30 01:11:48 +00001505
aurel32af129062008-11-19 16:10:23 +00001506 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001507 /* sNaN reciprocal */
aurel32af129062008-11-19 16:10:23 +00001508 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
j_mayerd7e4b872007-09-30 01:11:48 +00001509 } else {
aurel326c01bf62008-12-18 22:42:23 +00001510 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
j_mayerd7e4b872007-09-30 01:11:48 +00001511 }
aurel32af129062008-11-19 16:10:23 +00001512 return farg.d;
j_mayerd7e4b872007-09-30 01:11:48 +00001513}
1514
aurel32af129062008-11-19 16:10:23 +00001515/* fres - fres. */
1516uint64_t helper_fres (uint64_t arg)
bellard9a64fbe2004-01-04 22:58:38 +00001517{
aurel3205b93602008-12-15 17:13:48 +00001518 CPU_DoubleU fone, farg;
aurel326c01bf62008-12-18 22:42:23 +00001519 float32 f32;
aurel3201feec02008-12-16 10:44:29 +00001520 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
aurel32af129062008-11-19 16:10:23 +00001521 farg.ll = arg;
bellard4ecc3192005-03-13 17:01:22 +00001522
aurel32af129062008-11-19 16:10:23 +00001523 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001524 /* sNaN reciprocal */
aurel32af129062008-11-19 16:10:23 +00001525 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
bellard4ecc3192005-03-13 17:01:22 +00001526 } else {
aurel326c01bf62008-12-18 22:42:23 +00001527 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1528 f32 = float64_to_float32(farg.d, &env->fp_status);
1529 farg.d = float32_to_float64(f32, &env->fp_status);
bellard4ecc3192005-03-13 17:01:22 +00001530 }
aurel32af129062008-11-19 16:10:23 +00001531 return farg.ll;
bellard9a64fbe2004-01-04 22:58:38 +00001532}
1533
aurel32af129062008-11-19 16:10:23 +00001534/* frsqrte - frsqrte. */
1535uint64_t helper_frsqrte (uint64_t arg)
bellard9a64fbe2004-01-04 22:58:38 +00001536{
aurel3205b93602008-12-15 17:13:48 +00001537 CPU_DoubleU fone, farg;
aurel326c01bf62008-12-18 22:42:23 +00001538 float32 f32;
aurel3201feec02008-12-16 10:44:29 +00001539 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
aurel32af129062008-11-19 16:10:23 +00001540 farg.ll = arg;
bellard4ecc3192005-03-13 17:01:22 +00001541
aurel32af129062008-11-19 16:10:23 +00001542 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001543 /* sNaN reciprocal square root */
aurel32af129062008-11-19 16:10:23 +00001544 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32f23c3462008-12-15 17:14:27 +00001545 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001546 /* Reciprocal square root of a negative nonzero number */
aurel32af129062008-11-19 16:10:23 +00001547 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
bellard4ecc3192005-03-13 17:01:22 +00001548 } else {
aurel326c01bf62008-12-18 22:42:23 +00001549 farg.d = float64_sqrt(farg.d, &env->fp_status);
1550 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1551 f32 = float64_to_float32(farg.d, &env->fp_status);
1552 farg.d = float32_to_float64(f32, &env->fp_status);
bellard4ecc3192005-03-13 17:01:22 +00001553 }
aurel32af129062008-11-19 16:10:23 +00001554 return farg.ll;
bellard9a64fbe2004-01-04 22:58:38 +00001555}
1556
aurel32af129062008-11-19 16:10:23 +00001557/* fsel - fsel. */
1558uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
bellard9a64fbe2004-01-04 22:58:38 +00001559{
aurel326ad73652008-12-14 11:12:10 +00001560 CPU_DoubleU farg1;
aurel32af129062008-11-19 16:10:23 +00001561
1562 farg1.ll = arg1;
aurel32af129062008-11-19 16:10:23 +00001563
aurel32572c8952008-12-29 09:47:11 +00001564 if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) && !float64_is_nan(farg1.d))
aurel326ad73652008-12-14 11:12:10 +00001565 return arg2;
bellard4ecc3192005-03-13 17:01:22 +00001566 else
aurel326ad73652008-12-14 11:12:10 +00001567 return arg3;
bellard9a64fbe2004-01-04 22:58:38 +00001568}
1569
aurel329a819372008-12-14 19:34:09 +00001570void helper_fcmpu (uint64_t arg1, uint64_t arg2, uint32_t crfD)
bellard9a64fbe2004-01-04 22:58:38 +00001571{
aurel32af129062008-11-19 16:10:23 +00001572 CPU_DoubleU farg1, farg2;
aurel32e1571902008-10-21 11:31:14 +00001573 uint32_t ret = 0;
aurel32af129062008-11-19 16:10:23 +00001574 farg1.ll = arg1;
1575 farg2.ll = arg2;
aurel32e1571902008-10-21 11:31:14 +00001576
aurel32af129062008-11-19 16:10:23 +00001577 if (unlikely(float64_is_nan(farg1.d) ||
1578 float64_is_nan(farg2.d))) {
aurel329a819372008-12-14 19:34:09 +00001579 ret = 0x01UL;
1580 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1581 ret = 0x08UL;
1582 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1583 ret = 0x04UL;
1584 } else {
1585 ret = 0x02UL;
1586 }
1587
1588 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1589 env->fpscr |= ret << FPSCR_FPRF;
1590 env->crf[crfD] = ret;
1591 if (unlikely(ret == 0x01UL
1592 && (float64_is_signaling_nan(farg1.d) ||
1593 float64_is_signaling_nan(farg2.d)))) {
1594 /* sNaN comparison */
1595 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1596 }
1597}
1598
1599void helper_fcmpo (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1600{
1601 CPU_DoubleU farg1, farg2;
1602 uint32_t ret = 0;
1603 farg1.ll = arg1;
1604 farg2.ll = arg2;
1605
1606 if (unlikely(float64_is_nan(farg1.d) ||
1607 float64_is_nan(farg2.d))) {
1608 ret = 0x01UL;
1609 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1610 ret = 0x08UL;
1611 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1612 ret = 0x04UL;
1613 } else {
1614 ret = 0x02UL;
1615 }
1616
1617 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1618 env->fpscr |= ret << FPSCR_FPRF;
1619 env->crf[crfD] = ret;
1620 if (unlikely (ret == 0x01UL)) {
aurel32af129062008-11-19 16:10:23 +00001621 if (float64_is_signaling_nan(farg1.d) ||
1622 float64_is_signaling_nan(farg2.d)) {
j_mayer7c580442007-10-27 17:54:30 +00001623 /* sNaN comparison */
1624 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1625 POWERPC_EXCP_FP_VXVC);
1626 } else {
1627 /* qNaN comparison */
1628 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1629 }
bellard9a64fbe2004-01-04 22:58:38 +00001630 }
bellard9a64fbe2004-01-04 22:58:38 +00001631}
1632
j_mayer76a66252007-03-07 08:32:30 +00001633#if !defined (CONFIG_USER_ONLY)
aurel326527f6e2008-12-06 13:03:35 +00001634void helper_store_msr (target_ulong val)
j_mayer0411a972007-10-25 21:35:50 +00001635{
aurel326527f6e2008-12-06 13:03:35 +00001636 val = hreg_store_msr(env, val, 0);
1637 if (val != 0) {
j_mayer0411a972007-10-25 21:35:50 +00001638 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
aurel32e06fcd72008-12-11 22:42:14 +00001639 helper_raise_exception(val);
j_mayer0411a972007-10-25 21:35:50 +00001640 }
1641}
1642
aurel32d72a19f2008-11-30 16:24:55 +00001643static always_inline void do_rfi (target_ulong nip, target_ulong msr,
j_mayer0411a972007-10-25 21:35:50 +00001644 target_ulong msrm, int keep_msrh)
bellard9a64fbe2004-01-04 22:58:38 +00001645{
j_mayer426613d2007-03-23 09:45:27 +00001646#if defined(TARGET_PPC64)
j_mayer0411a972007-10-25 21:35:50 +00001647 if (msr & (1ULL << MSR_SF)) {
1648 nip = (uint64_t)nip;
1649 msr &= (uint64_t)msrm;
j_mayera42bd6c2007-03-30 10:22:46 +00001650 } else {
j_mayer0411a972007-10-25 21:35:50 +00001651 nip = (uint32_t)nip;
1652 msr = (uint32_t)(msr & msrm);
1653 if (keep_msrh)
1654 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
j_mayera42bd6c2007-03-30 10:22:46 +00001655 }
j_mayer426613d2007-03-23 09:45:27 +00001656#else
j_mayer0411a972007-10-25 21:35:50 +00001657 nip = (uint32_t)nip;
1658 msr &= (uint32_t)msrm;
j_mayer426613d2007-03-23 09:45:27 +00001659#endif
j_mayer0411a972007-10-25 21:35:50 +00001660 /* XXX: beware: this is false if VLE is supported */
1661 env->nip = nip & ~((target_ulong)0x00000003);
j_mayera4f30712007-11-17 21:14:09 +00001662 hreg_store_msr(env, msr, 1);
j_mayerd9bce9d2007-03-17 14:02:15 +00001663#if defined (DEBUG_OP)
j_mayer0411a972007-10-25 21:35:50 +00001664 cpu_dump_rfi(env->nip, env->msr);
j_mayerd9bce9d2007-03-17 14:02:15 +00001665#endif
j_mayer0411a972007-10-25 21:35:50 +00001666 /* No need to raise an exception here,
1667 * as rfi is always the last insn of a TB
1668 */
j_mayerd9bce9d2007-03-17 14:02:15 +00001669 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1670}
1671
aurel32d72a19f2008-11-30 16:24:55 +00001672void helper_rfi (void)
j_mayer0411a972007-10-25 21:35:50 +00001673{
aurel32d72a19f2008-11-30 16:24:55 +00001674 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1675 ~((target_ulong)0xFFFF0000), 1);
j_mayer0411a972007-10-25 21:35:50 +00001676}
1677
j_mayerd9bce9d2007-03-17 14:02:15 +00001678#if defined(TARGET_PPC64)
aurel32d72a19f2008-11-30 16:24:55 +00001679void helper_rfid (void)
j_mayer426613d2007-03-23 09:45:27 +00001680{
aurel32d72a19f2008-11-30 16:24:55 +00001681 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1682 ~((target_ulong)0xFFFF0000), 0);
bellard9a64fbe2004-01-04 22:58:38 +00001683}
j_mayer78636672007-11-16 14:11:28 +00001684
aurel32d72a19f2008-11-30 16:24:55 +00001685void helper_hrfid (void)
j_mayerbe147d02007-09-30 13:03:23 +00001686{
aurel32d72a19f2008-11-30 16:24:55 +00001687 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1688 ~((target_ulong)0xFFFF0000), 0);
j_mayerbe147d02007-09-30 13:03:23 +00001689}
1690#endif
j_mayerd9bce9d2007-03-17 14:02:15 +00001691#endif
bellard9a64fbe2004-01-04 22:58:38 +00001692
aurel32cab3bee2008-11-24 11:28:19 +00001693void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
bellard9a64fbe2004-01-04 22:58:38 +00001694{
aurel32cab3bee2008-11-24 11:28:19 +00001695 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1696 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1697 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1698 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1699 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
aurel32e06fcd72008-12-11 22:42:14 +00001700 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
j_mayera42bd6c2007-03-30 10:22:46 +00001701 }
bellard9a64fbe2004-01-04 22:58:38 +00001702}
1703
j_mayerd9bce9d2007-03-17 14:02:15 +00001704#if defined(TARGET_PPC64)
aurel32cab3bee2008-11-24 11:28:19 +00001705void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
j_mayerd9bce9d2007-03-17 14:02:15 +00001706{
aurel32cab3bee2008-11-24 11:28:19 +00001707 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1708 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1709 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1710 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1711 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
aurel32e06fcd72008-12-11 22:42:14 +00001712 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
j_mayerd9bce9d2007-03-17 14:02:15 +00001713}
1714#endif
1715
bellardfdabc362005-07-04 22:17:05 +00001716/*****************************************************************************/
j_mayer76a66252007-03-07 08:32:30 +00001717/* PowerPC 601 specific instructions (POWER bridge) */
bellard9a64fbe2004-01-04 22:58:38 +00001718
aurel3222e0e172008-12-06 12:19:14 +00001719target_ulong helper_clcs (uint32_t arg)
bellard9a64fbe2004-01-04 22:58:38 +00001720{
aurel3222e0e172008-12-06 12:19:14 +00001721 switch (arg) {
j_mayer76a66252007-03-07 08:32:30 +00001722 case 0x0CUL:
1723 /* Instruction cache line size */
aurel3222e0e172008-12-06 12:19:14 +00001724 return env->icache_line_size;
j_mayer76a66252007-03-07 08:32:30 +00001725 break;
1726 case 0x0DUL:
1727 /* Data cache line size */
aurel3222e0e172008-12-06 12:19:14 +00001728 return env->dcache_line_size;
j_mayer76a66252007-03-07 08:32:30 +00001729 break;
1730 case 0x0EUL:
1731 /* Minimum cache line size */
aurel3222e0e172008-12-06 12:19:14 +00001732 return (env->icache_line_size < env->dcache_line_size) ?
1733 env->icache_line_size : env->dcache_line_size;
j_mayer76a66252007-03-07 08:32:30 +00001734 break;
1735 case 0x0FUL:
1736 /* Maximum cache line size */
aurel3222e0e172008-12-06 12:19:14 +00001737 return (env->icache_line_size > env->dcache_line_size) ?
1738 env->icache_line_size : env->dcache_line_size;
j_mayer76a66252007-03-07 08:32:30 +00001739 break;
1740 default:
1741 /* Undefined */
aurel3222e0e172008-12-06 12:19:14 +00001742 return 0;
j_mayer76a66252007-03-07 08:32:30 +00001743 break;
1744 }
1745}
1746
aurel3222e0e172008-12-06 12:19:14 +00001747target_ulong helper_div (target_ulong arg1, target_ulong arg2)
j_mayer76a66252007-03-07 08:32:30 +00001748{
aurel3222e0e172008-12-06 12:19:14 +00001749 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
j_mayer76a66252007-03-07 08:32:30 +00001750
aurel3222e0e172008-12-06 12:19:14 +00001751 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1752 (int32_t)arg2 == 0) {
j_mayer76a66252007-03-07 08:32:30 +00001753 env->spr[SPR_MQ] = 0;
aurel3222e0e172008-12-06 12:19:14 +00001754 return INT32_MIN;
j_mayer76a66252007-03-07 08:32:30 +00001755 } else {
aurel3222e0e172008-12-06 12:19:14 +00001756 env->spr[SPR_MQ] = tmp % arg2;
1757 return tmp / (int32_t)arg2;
j_mayer76a66252007-03-07 08:32:30 +00001758 }
1759}
1760
aurel3222e0e172008-12-06 12:19:14 +00001761target_ulong helper_divo (target_ulong arg1, target_ulong arg2)
j_mayer76a66252007-03-07 08:32:30 +00001762{
aurel3222e0e172008-12-06 12:19:14 +00001763 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
j_mayer76a66252007-03-07 08:32:30 +00001764
aurel3222e0e172008-12-06 12:19:14 +00001765 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1766 (int32_t)arg2 == 0) {
aurel323d7b4172008-10-21 11:28:46 +00001767 env->xer |= (1 << XER_OV) | (1 << XER_SO);
aurel3222e0e172008-12-06 12:19:14 +00001768 env->spr[SPR_MQ] = 0;
1769 return INT32_MIN;
j_mayer76a66252007-03-07 08:32:30 +00001770 } else {
aurel3222e0e172008-12-06 12:19:14 +00001771 env->spr[SPR_MQ] = tmp % arg2;
1772 tmp /= (int32_t)arg2;
1773 if ((int32_t)tmp != tmp) {
aurel323d7b4172008-10-21 11:28:46 +00001774 env->xer |= (1 << XER_OV) | (1 << XER_SO);
j_mayer76a66252007-03-07 08:32:30 +00001775 } else {
aurel323d7b4172008-10-21 11:28:46 +00001776 env->xer &= ~(1 << XER_OV);
j_mayer76a66252007-03-07 08:32:30 +00001777 }
aurel3222e0e172008-12-06 12:19:14 +00001778 return tmp;
j_mayer76a66252007-03-07 08:32:30 +00001779 }
1780}
1781
aurel3222e0e172008-12-06 12:19:14 +00001782target_ulong helper_divs (target_ulong arg1, target_ulong arg2)
j_mayer76a66252007-03-07 08:32:30 +00001783{
aurel3222e0e172008-12-06 12:19:14 +00001784 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1785 (int32_t)arg2 == 0) {
j_mayer76a66252007-03-07 08:32:30 +00001786 env->spr[SPR_MQ] = 0;
aurel3222e0e172008-12-06 12:19:14 +00001787 return INT32_MIN;
j_mayer76a66252007-03-07 08:32:30 +00001788 } else {
aurel3222e0e172008-12-06 12:19:14 +00001789 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1790 return (int32_t)arg1 / (int32_t)arg2;
j_mayer76a66252007-03-07 08:32:30 +00001791 }
1792}
1793
aurel3222e0e172008-12-06 12:19:14 +00001794target_ulong helper_divso (target_ulong arg1, target_ulong arg2)
j_mayer76a66252007-03-07 08:32:30 +00001795{
aurel3222e0e172008-12-06 12:19:14 +00001796 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1797 (int32_t)arg2 == 0) {
1798 env->xer |= (1 << XER_OV) | (1 << XER_SO);
j_mayer76a66252007-03-07 08:32:30 +00001799 env->spr[SPR_MQ] = 0;
aurel3222e0e172008-12-06 12:19:14 +00001800 return INT32_MIN;
j_mayer76a66252007-03-07 08:32:30 +00001801 } else {
aurel323d7b4172008-10-21 11:28:46 +00001802 env->xer &= ~(1 << XER_OV);
aurel3222e0e172008-12-06 12:19:14 +00001803 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1804 return (int32_t)arg1 / (int32_t)arg2;
j_mayer76a66252007-03-07 08:32:30 +00001805 }
1806}
1807
1808#if !defined (CONFIG_USER_ONLY)
aurel3222e0e172008-12-06 12:19:14 +00001809target_ulong helper_rac (target_ulong addr)
j_mayer76a66252007-03-07 08:32:30 +00001810{
j_mayer76a66252007-03-07 08:32:30 +00001811 mmu_ctx_t ctx;
j_mayerfaadf502007-11-03 13:37:12 +00001812 int nb_BATs;
aurel3222e0e172008-12-06 12:19:14 +00001813 target_ulong ret = 0;
j_mayer76a66252007-03-07 08:32:30 +00001814
1815 /* We don't have to generate many instances of this instruction,
1816 * as rac is supervisor only.
1817 */
j_mayerfaadf502007-11-03 13:37:12 +00001818 /* XXX: FIX THIS: Pretend we have no BAT */
1819 nb_BATs = env->nb_BATs;
1820 env->nb_BATs = 0;
aurel3222e0e172008-12-06 12:19:14 +00001821 if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0)
1822 ret = ctx.raddr;
j_mayerfaadf502007-11-03 13:37:12 +00001823 env->nb_BATs = nb_BATs;
aurel3222e0e172008-12-06 12:19:14 +00001824 return ret;
bellard9a64fbe2004-01-04 22:58:38 +00001825}
1826
aurel32d72a19f2008-11-30 16:24:55 +00001827void helper_rfsvc (void)
j_mayer76a66252007-03-07 08:32:30 +00001828{
aurel32d72a19f2008-11-30 16:24:55 +00001829 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
j_mayer76a66252007-03-07 08:32:30 +00001830}
j_mayer76a66252007-03-07 08:32:30 +00001831#endif
1832
1833/*****************************************************************************/
1834/* 602 specific instructions */
1835/* mfrom is the most crazy instruction ever seen, imho ! */
1836/* Real implementation uses a ROM table. Do the same */
aurel325e9ae182008-12-13 12:30:21 +00001837/* Extremly decomposed:
1838 * -arg / 256
1839 * return 256 * log10(10 + 1.0) + 0.5
1840 */
aurel32db9a16a2008-12-08 18:11:50 +00001841#if !defined (CONFIG_USER_ONLY)
aurel32cf02a652008-11-30 16:23:35 +00001842target_ulong helper_602_mfrom (target_ulong arg)
j_mayer76a66252007-03-07 08:32:30 +00001843{
aurel32cf02a652008-11-30 16:23:35 +00001844 if (likely(arg < 602)) {
j_mayer76a66252007-03-07 08:32:30 +00001845#include "mfrom_table.c"
aurel3245d827d2008-12-07 13:40:29 +00001846 return mfrom_ROM_table[arg];
j_mayer76a66252007-03-07 08:32:30 +00001847 } else {
aurel32cf02a652008-11-30 16:23:35 +00001848 return 0;
j_mayer76a66252007-03-07 08:32:30 +00001849 }
1850}
aurel32db9a16a2008-12-08 18:11:50 +00001851#endif
j_mayer76a66252007-03-07 08:32:30 +00001852
1853/*****************************************************************************/
1854/* Embedded PowerPC specific helpers */
j_mayer76a66252007-03-07 08:32:30 +00001855
j_mayera750fc02007-09-26 23:54:22 +00001856/* XXX: to be improved to check access rights when in user-mode */
aurel3206dca6a2008-12-06 16:37:18 +00001857target_ulong helper_load_dcr (target_ulong dcrn)
j_mayera750fc02007-09-26 23:54:22 +00001858{
aurel3206dca6a2008-12-06 16:37:18 +00001859 target_ulong val = 0;
j_mayera750fc02007-09-26 23:54:22 +00001860
1861 if (unlikely(env->dcr_env == NULL)) {
1862 if (loglevel != 0) {
1863 fprintf(logfile, "No DCR environment\n");
1864 }
aurel32e06fcd72008-12-11 22:42:14 +00001865 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1866 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
aurel3206dca6a2008-12-06 16:37:18 +00001867 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
j_mayera750fc02007-09-26 23:54:22 +00001868 if (loglevel != 0) {
aurel3245d827d2008-12-07 13:40:29 +00001869 fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
j_mayera750fc02007-09-26 23:54:22 +00001870 }
aurel32e06fcd72008-12-11 22:42:14 +00001871 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1872 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
j_mayera750fc02007-09-26 23:54:22 +00001873 }
aurel3206dca6a2008-12-06 16:37:18 +00001874 return val;
j_mayera750fc02007-09-26 23:54:22 +00001875}
1876
aurel3206dca6a2008-12-06 16:37:18 +00001877void helper_store_dcr (target_ulong dcrn, target_ulong val)
j_mayera750fc02007-09-26 23:54:22 +00001878{
1879 if (unlikely(env->dcr_env == NULL)) {
1880 if (loglevel != 0) {
1881 fprintf(logfile, "No DCR environment\n");
1882 }
aurel32e06fcd72008-12-11 22:42:14 +00001883 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1884 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
aurel3206dca6a2008-12-06 16:37:18 +00001885 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
j_mayera750fc02007-09-26 23:54:22 +00001886 if (loglevel != 0) {
aurel3245d827d2008-12-07 13:40:29 +00001887 fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
j_mayera750fc02007-09-26 23:54:22 +00001888 }
aurel32e06fcd72008-12-11 22:42:14 +00001889 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1890 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
j_mayera750fc02007-09-26 23:54:22 +00001891 }
1892}
1893
j_mayer76a66252007-03-07 08:32:30 +00001894#if !defined(CONFIG_USER_ONLY)
aurel32d72a19f2008-11-30 16:24:55 +00001895void helper_40x_rfci (void)
j_mayer76a66252007-03-07 08:32:30 +00001896{
aurel32d72a19f2008-11-30 16:24:55 +00001897 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1898 ~((target_ulong)0xFFFF0000), 0);
j_mayer76a66252007-03-07 08:32:30 +00001899}
1900
aurel32d72a19f2008-11-30 16:24:55 +00001901void helper_rfci (void)
j_mayera42bd6c2007-03-30 10:22:46 +00001902{
aurel32d72a19f2008-11-30 16:24:55 +00001903 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1904 ~((target_ulong)0x3FFF0000), 0);
j_mayera42bd6c2007-03-30 10:22:46 +00001905}
1906
aurel32d72a19f2008-11-30 16:24:55 +00001907void helper_rfdi (void)
j_mayera42bd6c2007-03-30 10:22:46 +00001908{
aurel32d72a19f2008-11-30 16:24:55 +00001909 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1910 ~((target_ulong)0x3FFF0000), 0);
j_mayera42bd6c2007-03-30 10:22:46 +00001911}
1912
aurel32d72a19f2008-11-30 16:24:55 +00001913void helper_rfmci (void)
j_mayera42bd6c2007-03-30 10:22:46 +00001914{
aurel32d72a19f2008-11-30 16:24:55 +00001915 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1916 ~((target_ulong)0x3FFF0000), 0);
j_mayera42bd6c2007-03-30 10:22:46 +00001917}
j_mayer76a66252007-03-07 08:32:30 +00001918#endif
1919
1920/* 440 specific */
aurel32ef0d51a2008-11-30 17:26:29 +00001921target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
j_mayer76a66252007-03-07 08:32:30 +00001922{
1923 target_ulong mask;
1924 int i;
1925
1926 i = 1;
1927 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
aurel32ef0d51a2008-11-30 17:26:29 +00001928 if ((high & mask) == 0) {
1929 if (update_Rc) {
1930 env->crf[0] = 0x4;
1931 }
j_mayer76a66252007-03-07 08:32:30 +00001932 goto done;
aurel32ef0d51a2008-11-30 17:26:29 +00001933 }
j_mayer76a66252007-03-07 08:32:30 +00001934 i++;
1935 }
1936 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
aurel32ef0d51a2008-11-30 17:26:29 +00001937 if ((low & mask) == 0) {
1938 if (update_Rc) {
1939 env->crf[0] = 0x8;
1940 }
1941 goto done;
1942 }
j_mayer76a66252007-03-07 08:32:30 +00001943 i++;
1944 }
aurel32ef0d51a2008-11-30 17:26:29 +00001945 if (update_Rc) {
1946 env->crf[0] = 0x2;
1947 }
j_mayer76a66252007-03-07 08:32:30 +00001948 done:
aurel32ef0d51a2008-11-30 17:26:29 +00001949 env->xer = (env->xer & ~0x7F) | i;
1950 if (update_Rc) {
1951 env->crf[0] |= xer_so;
1952 }
1953 return i;
j_mayer76a66252007-03-07 08:32:30 +00001954}
1955
aurel321c978562008-11-23 10:54:04 +00001956/*****************************************************************************/
aurel32d6a46fe2009-01-03 13:31:19 +00001957/* Altivec extension helpers */
1958#if defined(WORDS_BIGENDIAN)
1959#define HI_IDX 0
1960#define LO_IDX 1
1961#else
1962#define HI_IDX 1
1963#define LO_IDX 0
1964#endif
1965
1966#if defined(WORDS_BIGENDIAN)
1967#define VECTOR_FOR_INORDER_I(index, element) \
1968 for (index = 0; index < ARRAY_SIZE(r->element); index++)
1969#else
1970#define VECTOR_FOR_INORDER_I(index, element) \
1971 for (index = ARRAY_SIZE(r->element)-1; index >= 0; index--)
1972#endif
1973
aurel327872c512009-01-03 13:31:40 +00001974#define VARITH_DO(name, op, element) \
1975void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
1976{ \
1977 int i; \
1978 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
1979 r->element[i] = a->element[i] op b->element[i]; \
1980 } \
1981}
1982#define VARITH(suffix, element) \
1983 VARITH_DO(add##suffix, +, element) \
1984 VARITH_DO(sub##suffix, -, element)
1985VARITH(ubm, u8)
1986VARITH(uhm, u16)
1987VARITH(uwm, u32)
1988#undef VARITH_DO
1989#undef VARITH
1990
aurel32fab3cbe2009-01-03 13:31:49 +00001991#define VAVG_DO(name, element, etype) \
1992 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
1993 { \
1994 int i; \
1995 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
1996 etype x = (etype)a->element[i] + (etype)b->element[i] + 1; \
1997 r->element[i] = x >> 1; \
1998 } \
1999 }
2000
2001#define VAVG(type, signed_element, signed_type, unsigned_element, unsigned_type) \
2002 VAVG_DO(avgs##type, signed_element, signed_type) \
2003 VAVG_DO(avgu##type, unsigned_element, unsigned_type)
2004VAVG(b, s8, int16_t, u8, uint16_t)
2005VAVG(h, s16, int32_t, u16, uint32_t)
2006VAVG(w, s32, int64_t, u32, uint64_t)
2007#undef VAVG_DO
2008#undef VAVG
2009
aurel32e4039332009-01-03 13:31:58 +00002010#define VMINMAX_DO(name, compare, element) \
2011 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2012 { \
2013 int i; \
2014 for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
2015 if (a->element[i] compare b->element[i]) { \
2016 r->element[i] = b->element[i]; \
2017 } else { \
2018 r->element[i] = a->element[i]; \
2019 } \
2020 } \
2021 }
2022#define VMINMAX(suffix, element) \
2023 VMINMAX_DO(min##suffix, >, element) \
2024 VMINMAX_DO(max##suffix, <, element)
2025VMINMAX(sb, s8)
2026VMINMAX(sh, s16)
2027VMINMAX(sw, s32)
2028VMINMAX(ub, u8)
2029VMINMAX(uh, u16)
2030VMINMAX(uw, u32)
2031#undef VMINMAX_DO
2032#undef VMINMAX
2033
aurel323b430042009-01-04 22:08:38 +00002034#define VMRG_DO(name, element, highp) \
2035 void helper_v##name (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
2036 { \
2037 ppc_avr_t result; \
2038 int i; \
2039 size_t n_elems = ARRAY_SIZE(r->element); \
2040 for (i = 0; i < n_elems/2; i++) { \
2041 if (highp) { \
2042 result.element[i*2+HI_IDX] = a->element[i]; \
2043 result.element[i*2+LO_IDX] = b->element[i]; \
2044 } else { \
2045 result.element[n_elems - i*2 - (1+HI_IDX)] = b->element[n_elems - i - 1]; \
2046 result.element[n_elems - i*2 - (1+LO_IDX)] = a->element[n_elems - i - 1]; \
2047 } \
2048 } \
2049 *r = result; \
2050 }
2051#if defined(WORDS_BIGENDIAN)
2052#define MRGHI 0
2053#define MRGL0 1
2054#else
2055#define MRGHI 1
2056#define MRGLO 0
2057#endif
2058#define VMRG(suffix, element) \
2059 VMRG_DO(mrgl##suffix, element, MRGHI) \
2060 VMRG_DO(mrgh##suffix, element, MRGLO)
2061VMRG(b, u8)
2062VMRG(h, u16)
2063VMRG(w, u32)
2064#undef VMRG_DO
2065#undef VMRG
2066#undef MRGHI
2067#undef MRGLO
2068
aurel32d6a46fe2009-01-03 13:31:19 +00002069#undef VECTOR_FOR_INORDER_I
2070#undef HI_IDX
2071#undef LO_IDX
2072
2073/*****************************************************************************/
j_mayer0487d6a2007-03-20 22:11:31 +00002074/* SPE extension helpers */
2075/* Use a table to make this quicker */
2076static uint8_t hbrev[16] = {
2077 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
2078 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
2079};
2080
j_mayerb068d6a2007-10-07 17:13:44 +00002081static always_inline uint8_t byte_reverse (uint8_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002082{
2083 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
2084}
2085
j_mayerb068d6a2007-10-07 17:13:44 +00002086static always_inline uint32_t word_reverse (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002087{
2088 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
2089 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
2090}
2091
j_mayer3cd7d1d2007-11-12 01:56:18 +00002092#define MASKBITS 16 // Random value - to be fixed (implementation dependant)
aurel3257951c22008-11-10 11:10:23 +00002093target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
j_mayer0487d6a2007-03-20 22:11:31 +00002094{
2095 uint32_t a, b, d, mask;
2096
j_mayer3cd7d1d2007-11-12 01:56:18 +00002097 mask = UINT32_MAX >> (32 - MASKBITS);
aurel3257951c22008-11-10 11:10:23 +00002098 a = arg1 & mask;
2099 b = arg2 & mask;
j_mayer3cd7d1d2007-11-12 01:56:18 +00002100 d = word_reverse(1 + word_reverse(a | ~b));
aurel3257951c22008-11-10 11:10:23 +00002101 return (arg1 & ~mask) | (d & b);
j_mayer0487d6a2007-03-20 22:11:31 +00002102}
2103
aurel3257951c22008-11-10 11:10:23 +00002104uint32_t helper_cntlsw32 (uint32_t val)
2105{
2106 if (val & 0x80000000)
2107 return clz32(~val);
2108 else
2109 return clz32(val);
2110}
2111
2112uint32_t helper_cntlzw32 (uint32_t val)
2113{
2114 return clz32(val);
j_mayer0487d6a2007-03-20 22:11:31 +00002115}
2116
aurel321c978562008-11-23 10:54:04 +00002117/* Single-precision floating-point conversions */
2118static always_inline uint32_t efscfsi (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002119{
aurel320ca9d382008-03-13 19:19:16 +00002120 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002121
2122 u.f = int32_to_float32(val, &env->spe_status);
2123
aurel320ca9d382008-03-13 19:19:16 +00002124 return u.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002125}
2126
aurel321c978562008-11-23 10:54:04 +00002127static always_inline uint32_t efscfui (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002128{
aurel320ca9d382008-03-13 19:19:16 +00002129 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002130
2131 u.f = uint32_to_float32(val, &env->spe_status);
2132
aurel320ca9d382008-03-13 19:19:16 +00002133 return u.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002134}
2135
aurel321c978562008-11-23 10:54:04 +00002136static always_inline int32_t efsctsi (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002137{
aurel320ca9d382008-03-13 19:19:16 +00002138 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002139
aurel320ca9d382008-03-13 19:19:16 +00002140 u.l = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002141 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002142 if (unlikely(float32_is_nan(u.f)))
j_mayer0487d6a2007-03-20 22:11:31 +00002143 return 0;
2144
2145 return float32_to_int32(u.f, &env->spe_status);
2146}
2147
aurel321c978562008-11-23 10:54:04 +00002148static always_inline uint32_t efsctui (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002149{
aurel320ca9d382008-03-13 19:19:16 +00002150 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002151
aurel320ca9d382008-03-13 19:19:16 +00002152 u.l = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002153 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002154 if (unlikely(float32_is_nan(u.f)))
j_mayer0487d6a2007-03-20 22:11:31 +00002155 return 0;
2156
2157 return float32_to_uint32(u.f, &env->spe_status);
2158}
2159
aurel321c978562008-11-23 10:54:04 +00002160static always_inline uint32_t efsctsiz (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002161{
aurel320ca9d382008-03-13 19:19:16 +00002162 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002163
aurel320ca9d382008-03-13 19:19:16 +00002164 u.l = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002165 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002166 if (unlikely(float32_is_nan(u.f)))
j_mayer0487d6a2007-03-20 22:11:31 +00002167 return 0;
2168
2169 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2170}
2171
aurel321c978562008-11-23 10:54:04 +00002172static always_inline uint32_t efsctuiz (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002173{
aurel320ca9d382008-03-13 19:19:16 +00002174 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002175
aurel320ca9d382008-03-13 19:19:16 +00002176 u.l = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002177 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002178 if (unlikely(float32_is_nan(u.f)))
j_mayer0487d6a2007-03-20 22:11:31 +00002179 return 0;
2180
2181 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2182}
2183
aurel321c978562008-11-23 10:54:04 +00002184static always_inline uint32_t efscfsf (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002185{
aurel320ca9d382008-03-13 19:19:16 +00002186 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002187 float32 tmp;
2188
2189 u.f = int32_to_float32(val, &env->spe_status);
2190 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2191 u.f = float32_div(u.f, tmp, &env->spe_status);
2192
aurel320ca9d382008-03-13 19:19:16 +00002193 return u.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002194}
2195
aurel321c978562008-11-23 10:54:04 +00002196static always_inline uint32_t efscfuf (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002197{
aurel320ca9d382008-03-13 19:19:16 +00002198 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002199 float32 tmp;
2200
2201 u.f = uint32_to_float32(val, &env->spe_status);
2202 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2203 u.f = float32_div(u.f, tmp, &env->spe_status);
2204
aurel320ca9d382008-03-13 19:19:16 +00002205 return u.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002206}
2207
aurel321c978562008-11-23 10:54:04 +00002208static always_inline uint32_t efsctsf (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002209{
aurel320ca9d382008-03-13 19:19:16 +00002210 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002211 float32 tmp;
2212
aurel320ca9d382008-03-13 19:19:16 +00002213 u.l = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002214 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002215 if (unlikely(float32_is_nan(u.f)))
j_mayer0487d6a2007-03-20 22:11:31 +00002216 return 0;
2217 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2218 u.f = float32_mul(u.f, tmp, &env->spe_status);
2219
2220 return float32_to_int32(u.f, &env->spe_status);
2221}
2222
aurel321c978562008-11-23 10:54:04 +00002223static always_inline uint32_t efsctuf (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002224{
aurel320ca9d382008-03-13 19:19:16 +00002225 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002226 float32 tmp;
2227
aurel320ca9d382008-03-13 19:19:16 +00002228 u.l = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002229 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002230 if (unlikely(float32_is_nan(u.f)))
j_mayer0487d6a2007-03-20 22:11:31 +00002231 return 0;
2232 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2233 u.f = float32_mul(u.f, tmp, &env->spe_status);
2234
2235 return float32_to_uint32(u.f, &env->spe_status);
2236}
2237
aurel321c978562008-11-23 10:54:04 +00002238#define HELPER_SPE_SINGLE_CONV(name) \
2239uint32_t helper_e##name (uint32_t val) \
2240{ \
2241 return e##name(val); \
2242}
2243/* efscfsi */
2244HELPER_SPE_SINGLE_CONV(fscfsi);
2245/* efscfui */
2246HELPER_SPE_SINGLE_CONV(fscfui);
2247/* efscfuf */
2248HELPER_SPE_SINGLE_CONV(fscfuf);
2249/* efscfsf */
2250HELPER_SPE_SINGLE_CONV(fscfsf);
2251/* efsctsi */
2252HELPER_SPE_SINGLE_CONV(fsctsi);
2253/* efsctui */
2254HELPER_SPE_SINGLE_CONV(fsctui);
2255/* efsctsiz */
2256HELPER_SPE_SINGLE_CONV(fsctsiz);
2257/* efsctuiz */
2258HELPER_SPE_SINGLE_CONV(fsctuiz);
2259/* efsctsf */
2260HELPER_SPE_SINGLE_CONV(fsctsf);
2261/* efsctuf */
2262HELPER_SPE_SINGLE_CONV(fsctuf);
2263
2264#define HELPER_SPE_VECTOR_CONV(name) \
2265uint64_t helper_ev##name (uint64_t val) \
2266{ \
2267 return ((uint64_t)e##name(val >> 32) << 32) | \
2268 (uint64_t)e##name(val); \
2269}
2270/* evfscfsi */
2271HELPER_SPE_VECTOR_CONV(fscfsi);
2272/* evfscfui */
2273HELPER_SPE_VECTOR_CONV(fscfui);
2274/* evfscfuf */
2275HELPER_SPE_VECTOR_CONV(fscfuf);
2276/* evfscfsf */
2277HELPER_SPE_VECTOR_CONV(fscfsf);
2278/* evfsctsi */
2279HELPER_SPE_VECTOR_CONV(fsctsi);
2280/* evfsctui */
2281HELPER_SPE_VECTOR_CONV(fsctui);
2282/* evfsctsiz */
2283HELPER_SPE_VECTOR_CONV(fsctsiz);
2284/* evfsctuiz */
2285HELPER_SPE_VECTOR_CONV(fsctuiz);
2286/* evfsctsf */
2287HELPER_SPE_VECTOR_CONV(fsctsf);
2288/* evfsctuf */
2289HELPER_SPE_VECTOR_CONV(fsctuf);
2290
2291/* Single-precision floating-point arithmetic */
2292static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002293{
aurel321c978562008-11-23 10:54:04 +00002294 CPU_FloatU u1, u2;
2295 u1.l = op1;
2296 u2.l = op2;
2297 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2298 return u1.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002299}
2300
aurel321c978562008-11-23 10:54:04 +00002301static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002302{
aurel321c978562008-11-23 10:54:04 +00002303 CPU_FloatU u1, u2;
2304 u1.l = op1;
2305 u2.l = op2;
2306 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2307 return u1.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002308}
2309
aurel321c978562008-11-23 10:54:04 +00002310static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002311{
aurel321c978562008-11-23 10:54:04 +00002312 CPU_FloatU u1, u2;
2313 u1.l = op1;
2314 u2.l = op2;
2315 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2316 return u1.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002317}
2318
aurel321c978562008-11-23 10:54:04 +00002319static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002320{
aurel321c978562008-11-23 10:54:04 +00002321 CPU_FloatU u1, u2;
2322 u1.l = op1;
2323 u2.l = op2;
2324 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2325 return u1.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002326}
2327
aurel321c978562008-11-23 10:54:04 +00002328#define HELPER_SPE_SINGLE_ARITH(name) \
2329uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2330{ \
2331 return e##name(op1, op2); \
2332}
2333/* efsadd */
2334HELPER_SPE_SINGLE_ARITH(fsadd);
2335/* efssub */
2336HELPER_SPE_SINGLE_ARITH(fssub);
2337/* efsmul */
2338HELPER_SPE_SINGLE_ARITH(fsmul);
2339/* efsdiv */
2340HELPER_SPE_SINGLE_ARITH(fsdiv);
2341
2342#define HELPER_SPE_VECTOR_ARITH(name) \
2343uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2344{ \
2345 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2346 (uint64_t)e##name(op1, op2); \
2347}
2348/* evfsadd */
2349HELPER_SPE_VECTOR_ARITH(fsadd);
2350/* evfssub */
2351HELPER_SPE_VECTOR_ARITH(fssub);
2352/* evfsmul */
2353HELPER_SPE_VECTOR_ARITH(fsmul);
2354/* evfsdiv */
2355HELPER_SPE_VECTOR_ARITH(fsdiv);
2356
2357/* Single-precision floating-point comparisons */
2358static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002359{
aurel321c978562008-11-23 10:54:04 +00002360 CPU_FloatU u1, u2;
2361 u1.l = op1;
2362 u2.l = op2;
2363 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
j_mayer0487d6a2007-03-20 22:11:31 +00002364}
2365
aurel321c978562008-11-23 10:54:04 +00002366static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002367{
aurel321c978562008-11-23 10:54:04 +00002368 CPU_FloatU u1, u2;
2369 u1.l = op1;
2370 u2.l = op2;
2371 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
j_mayer0487d6a2007-03-20 22:11:31 +00002372}
2373
aurel321c978562008-11-23 10:54:04 +00002374static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002375{
aurel321c978562008-11-23 10:54:04 +00002376 CPU_FloatU u1, u2;
2377 u1.l = op1;
2378 u2.l = op2;
2379 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
j_mayer0487d6a2007-03-20 22:11:31 +00002380}
2381
aurel321c978562008-11-23 10:54:04 +00002382static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002383{
2384 /* XXX: TODO: test special values (NaN, infinites, ...) */
aurel321c978562008-11-23 10:54:04 +00002385 return efststlt(op1, op2);
j_mayer0487d6a2007-03-20 22:11:31 +00002386}
2387
aurel321c978562008-11-23 10:54:04 +00002388static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002389{
2390 /* XXX: TODO: test special values (NaN, infinites, ...) */
aurel321c978562008-11-23 10:54:04 +00002391 return efststgt(op1, op2);
j_mayer0487d6a2007-03-20 22:11:31 +00002392}
2393
aurel321c978562008-11-23 10:54:04 +00002394static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002395{
2396 /* XXX: TODO: test special values (NaN, infinites, ...) */
aurel321c978562008-11-23 10:54:04 +00002397 return efststeq(op1, op2);
j_mayer0487d6a2007-03-20 22:11:31 +00002398}
2399
aurel321c978562008-11-23 10:54:04 +00002400#define HELPER_SINGLE_SPE_CMP(name) \
2401uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2402{ \
2403 return e##name(op1, op2) << 2; \
2404}
2405/* efststlt */
2406HELPER_SINGLE_SPE_CMP(fststlt);
2407/* efststgt */
2408HELPER_SINGLE_SPE_CMP(fststgt);
2409/* efststeq */
2410HELPER_SINGLE_SPE_CMP(fststeq);
2411/* efscmplt */
2412HELPER_SINGLE_SPE_CMP(fscmplt);
2413/* efscmpgt */
2414HELPER_SINGLE_SPE_CMP(fscmpgt);
2415/* efscmpeq */
2416HELPER_SINGLE_SPE_CMP(fscmpeq);
2417
2418static always_inline uint32_t evcmp_merge (int t0, int t1)
j_mayer0487d6a2007-03-20 22:11:31 +00002419{
aurel321c978562008-11-23 10:54:04 +00002420 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
j_mayer0487d6a2007-03-20 22:11:31 +00002421}
2422
aurel321c978562008-11-23 10:54:04 +00002423#define HELPER_VECTOR_SPE_CMP(name) \
2424uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2425{ \
2426 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2427}
2428/* evfststlt */
2429HELPER_VECTOR_SPE_CMP(fststlt);
2430/* evfststgt */
2431HELPER_VECTOR_SPE_CMP(fststgt);
2432/* evfststeq */
2433HELPER_VECTOR_SPE_CMP(fststeq);
2434/* evfscmplt */
2435HELPER_VECTOR_SPE_CMP(fscmplt);
2436/* evfscmpgt */
2437HELPER_VECTOR_SPE_CMP(fscmpgt);
2438/* evfscmpeq */
2439HELPER_VECTOR_SPE_CMP(fscmpeq);
2440
2441/* Double-precision floating-point conversion */
2442uint64_t helper_efdcfsi (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002443{
aurel321c978562008-11-23 10:54:04 +00002444 CPU_DoubleU u;
2445
2446 u.d = int32_to_float64(val, &env->spe_status);
2447
2448 return u.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002449}
2450
aurel321c978562008-11-23 10:54:04 +00002451uint64_t helper_efdcfsid (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002452{
aurel320ca9d382008-03-13 19:19:16 +00002453 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002454
aurel320ca9d382008-03-13 19:19:16 +00002455 u.d = int64_to_float64(val, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002456
aurel320ca9d382008-03-13 19:19:16 +00002457 return u.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002458}
2459
aurel321c978562008-11-23 10:54:04 +00002460uint64_t helper_efdcfui (uint32_t val)
2461{
2462 CPU_DoubleU u;
2463
2464 u.d = uint32_to_float64(val, &env->spe_status);
2465
2466 return u.ll;
2467}
2468
2469uint64_t helper_efdcfuid (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002470{
aurel320ca9d382008-03-13 19:19:16 +00002471 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002472
aurel320ca9d382008-03-13 19:19:16 +00002473 u.d = uint64_to_float64(val, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002474
aurel320ca9d382008-03-13 19:19:16 +00002475 return u.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002476}
2477
aurel321c978562008-11-23 10:54:04 +00002478uint32_t helper_efdctsi (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002479{
aurel320ca9d382008-03-13 19:19:16 +00002480 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002481
aurel320ca9d382008-03-13 19:19:16 +00002482 u.ll = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002483 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002484 if (unlikely(float64_is_nan(u.d)))
j_mayer0487d6a2007-03-20 22:11:31 +00002485 return 0;
2486
aurel321c978562008-11-23 10:54:04 +00002487 return float64_to_int32(u.d, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002488}
2489
aurel321c978562008-11-23 10:54:04 +00002490uint32_t helper_efdctui (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002491{
aurel320ca9d382008-03-13 19:19:16 +00002492 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002493
aurel320ca9d382008-03-13 19:19:16 +00002494 u.ll = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002495 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002496 if (unlikely(float64_is_nan(u.d)))
j_mayer0487d6a2007-03-20 22:11:31 +00002497 return 0;
2498
aurel321c978562008-11-23 10:54:04 +00002499 return float64_to_uint32(u.d, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002500}
2501
aurel321c978562008-11-23 10:54:04 +00002502uint32_t helper_efdctsiz (uint64_t val)
2503{
2504 CPU_DoubleU u;
2505
2506 u.ll = val;
2507 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002508 if (unlikely(float64_is_nan(u.d)))
aurel321c978562008-11-23 10:54:04 +00002509 return 0;
2510
2511 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2512}
2513
2514uint64_t helper_efdctsidz (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002515{
aurel320ca9d382008-03-13 19:19:16 +00002516 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002517
aurel320ca9d382008-03-13 19:19:16 +00002518 u.ll = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002519 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002520 if (unlikely(float64_is_nan(u.d)))
j_mayer0487d6a2007-03-20 22:11:31 +00002521 return 0;
2522
aurel320ca9d382008-03-13 19:19:16 +00002523 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002524}
2525
aurel321c978562008-11-23 10:54:04 +00002526uint32_t helper_efdctuiz (uint64_t val)
2527{
2528 CPU_DoubleU u;
2529
2530 u.ll = val;
2531 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002532 if (unlikely(float64_is_nan(u.d)))
aurel321c978562008-11-23 10:54:04 +00002533 return 0;
2534
2535 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2536}
2537
2538uint64_t helper_efdctuidz (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002539{
aurel320ca9d382008-03-13 19:19:16 +00002540 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002541
aurel320ca9d382008-03-13 19:19:16 +00002542 u.ll = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002543 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002544 if (unlikely(float64_is_nan(u.d)))
j_mayer0487d6a2007-03-20 22:11:31 +00002545 return 0;
2546
aurel320ca9d382008-03-13 19:19:16 +00002547 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002548}
2549
aurel321c978562008-11-23 10:54:04 +00002550uint64_t helper_efdcfsf (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002551{
aurel320ca9d382008-03-13 19:19:16 +00002552 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002553 float64 tmp;
2554
aurel320ca9d382008-03-13 19:19:16 +00002555 u.d = int32_to_float64(val, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002556 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
aurel320ca9d382008-03-13 19:19:16 +00002557 u.d = float64_div(u.d, tmp, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002558
aurel320ca9d382008-03-13 19:19:16 +00002559 return u.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002560}
2561
aurel321c978562008-11-23 10:54:04 +00002562uint64_t helper_efdcfuf (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002563{
aurel320ca9d382008-03-13 19:19:16 +00002564 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002565 float64 tmp;
2566
aurel320ca9d382008-03-13 19:19:16 +00002567 u.d = uint32_to_float64(val, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002568 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
aurel320ca9d382008-03-13 19:19:16 +00002569 u.d = float64_div(u.d, tmp, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002570
aurel320ca9d382008-03-13 19:19:16 +00002571 return u.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002572}
2573
aurel321c978562008-11-23 10:54:04 +00002574uint32_t helper_efdctsf (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002575{
aurel320ca9d382008-03-13 19:19:16 +00002576 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002577 float64 tmp;
2578
aurel320ca9d382008-03-13 19:19:16 +00002579 u.ll = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002580 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002581 if (unlikely(float64_is_nan(u.d)))
j_mayer0487d6a2007-03-20 22:11:31 +00002582 return 0;
2583 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
aurel320ca9d382008-03-13 19:19:16 +00002584 u.d = float64_mul(u.d, tmp, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002585
aurel320ca9d382008-03-13 19:19:16 +00002586 return float64_to_int32(u.d, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002587}
2588
aurel321c978562008-11-23 10:54:04 +00002589uint32_t helper_efdctuf (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002590{
aurel320ca9d382008-03-13 19:19:16 +00002591 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002592 float64 tmp;
2593
aurel320ca9d382008-03-13 19:19:16 +00002594 u.ll = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002595 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002596 if (unlikely(float64_is_nan(u.d)))
j_mayer0487d6a2007-03-20 22:11:31 +00002597 return 0;
2598 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
aurel320ca9d382008-03-13 19:19:16 +00002599 u.d = float64_mul(u.d, tmp, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002600
aurel320ca9d382008-03-13 19:19:16 +00002601 return float64_to_uint32(u.d, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002602}
2603
aurel321c978562008-11-23 10:54:04 +00002604uint32_t helper_efscfd (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002605{
aurel320ca9d382008-03-13 19:19:16 +00002606 CPU_DoubleU u1;
2607 CPU_FloatU u2;
j_mayer0487d6a2007-03-20 22:11:31 +00002608
aurel320ca9d382008-03-13 19:19:16 +00002609 u1.ll = val;
2610 u2.f = float64_to_float32(u1.d, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002611
aurel320ca9d382008-03-13 19:19:16 +00002612 return u2.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002613}
2614
aurel321c978562008-11-23 10:54:04 +00002615uint64_t helper_efdcfs (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002616{
aurel320ca9d382008-03-13 19:19:16 +00002617 CPU_DoubleU u2;
2618 CPU_FloatU u1;
j_mayer0487d6a2007-03-20 22:11:31 +00002619
aurel320ca9d382008-03-13 19:19:16 +00002620 u1.l = val;
2621 u2.d = float32_to_float64(u1.f, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002622
aurel320ca9d382008-03-13 19:19:16 +00002623 return u2.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002624}
2625
aurel321c978562008-11-23 10:54:04 +00002626/* Double precision fixed-point arithmetic */
2627uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002628{
aurel321c978562008-11-23 10:54:04 +00002629 CPU_DoubleU u1, u2;
2630 u1.ll = op1;
2631 u2.ll = op2;
2632 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2633 return u1.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002634}
2635
aurel321c978562008-11-23 10:54:04 +00002636uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002637{
aurel321c978562008-11-23 10:54:04 +00002638 CPU_DoubleU u1, u2;
2639 u1.ll = op1;
2640 u2.ll = op2;
2641 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2642 return u1.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002643}
2644
aurel321c978562008-11-23 10:54:04 +00002645uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
2646{
2647 CPU_DoubleU u1, u2;
2648 u1.ll = op1;
2649 u2.ll = op2;
2650 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2651 return u1.ll;
2652}
j_mayer0487d6a2007-03-20 22:11:31 +00002653
aurel321c978562008-11-23 10:54:04 +00002654uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
2655{
2656 CPU_DoubleU u1, u2;
2657 u1.ll = op1;
2658 u2.ll = op2;
2659 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2660 return u1.ll;
2661}
2662
2663/* Double precision floating point helpers */
2664uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
2665{
2666 CPU_DoubleU u1, u2;
2667 u1.ll = op1;
2668 u2.ll = op2;
2669 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2670}
2671
2672uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
2673{
2674 CPU_DoubleU u1, u2;
2675 u1.ll = op1;
2676 u2.ll = op2;
2677 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
2678}
2679
2680uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
2681{
2682 CPU_DoubleU u1, u2;
2683 u1.ll = op1;
2684 u2.ll = op2;
2685 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2686}
2687
2688uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002689{
2690 /* XXX: TODO: test special values (NaN, infinites, ...) */
aurel321c978562008-11-23 10:54:04 +00002691 return helper_efdtstlt(op1, op2);
j_mayer0487d6a2007-03-20 22:11:31 +00002692}
2693
aurel321c978562008-11-23 10:54:04 +00002694uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002695{
2696 /* XXX: TODO: test special values (NaN, infinites, ...) */
aurel321c978562008-11-23 10:54:04 +00002697 return helper_efdtstgt(op1, op2);
j_mayer0487d6a2007-03-20 22:11:31 +00002698}
2699
aurel321c978562008-11-23 10:54:04 +00002700uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002701{
2702 /* XXX: TODO: test special values (NaN, infinites, ...) */
aurel321c978562008-11-23 10:54:04 +00002703 return helper_efdtsteq(op1, op2);
j_mayer0487d6a2007-03-20 22:11:31 +00002704}
2705
bellardfdabc362005-07-04 22:17:05 +00002706/*****************************************************************************/
2707/* Softmmu support */
2708#if !defined (CONFIG_USER_ONLY)
2709
2710#define MMUSUFFIX _mmu
bellardfdabc362005-07-04 22:17:05 +00002711
2712#define SHIFT 0
2713#include "softmmu_template.h"
2714
2715#define SHIFT 1
2716#include "softmmu_template.h"
2717
2718#define SHIFT 2
2719#include "softmmu_template.h"
2720
2721#define SHIFT 3
2722#include "softmmu_template.h"
2723
2724/* try to fill the TLB and return an exception if error. If retaddr is
2725 NULL, it means that the function was called in C code (i.e. not
2726 from generated code or from helper.c) */
2727/* XXX: fix it to restore all registers */
j_mayer6ebbf392007-10-14 07:07:08 +00002728void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
bellardfdabc362005-07-04 22:17:05 +00002729{
2730 TranslationBlock *tb;
2731 CPUState *saved_env;
bellard44f86252007-11-11 12:35:55 +00002732 unsigned long pc;
bellardfdabc362005-07-04 22:17:05 +00002733 int ret;
2734
2735 /* XXX: hack to restore env in all cases, even if not called from
2736 generated code */
2737 saved_env = env;
2738 env = cpu_single_env;
j_mayer6ebbf392007-10-14 07:07:08 +00002739 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
j_mayer76a66252007-03-07 08:32:30 +00002740 if (unlikely(ret != 0)) {
bellardfdabc362005-07-04 22:17:05 +00002741 if (likely(retaddr)) {
2742 /* now we have a real cpu fault */
bellard44f86252007-11-11 12:35:55 +00002743 pc = (unsigned long)retaddr;
bellardfdabc362005-07-04 22:17:05 +00002744 tb = tb_find_pc(pc);
2745 if (likely(tb)) {
2746 /* the PC is inside the translated code. It means that we have
2747 a virtual CPU fault */
2748 cpu_restore_state(tb, env, pc, NULL);
j_mayer76a66252007-03-07 08:32:30 +00002749 }
bellardfdabc362005-07-04 22:17:05 +00002750 }
aurel32e06fcd72008-12-11 22:42:14 +00002751 helper_raise_exception_err(env->exception_index, env->error_code);
bellardfdabc362005-07-04 22:17:05 +00002752 }
2753 env = saved_env;
2754}
bellardfdabc362005-07-04 22:17:05 +00002755
aurel3274d37792008-12-06 21:46:17 +00002756/* Segment registers load and store */
2757target_ulong helper_load_sr (target_ulong sr_num)
2758{
2759 return env->sr[sr_num];
2760}
2761
2762void helper_store_sr (target_ulong sr_num, target_ulong val)
2763{
aurel3245d827d2008-12-07 13:40:29 +00002764 ppc_store_sr(env, sr_num, val);
aurel3274d37792008-12-06 21:46:17 +00002765}
2766
2767/* SLB management */
2768#if defined(TARGET_PPC64)
2769target_ulong helper_load_slb (target_ulong slb_nr)
2770{
2771 return ppc_load_slb(env, slb_nr);
2772}
2773
2774void helper_store_slb (target_ulong slb_nr, target_ulong rs)
2775{
2776 ppc_store_slb(env, slb_nr, rs);
2777}
2778
2779void helper_slbia (void)
2780{
2781 ppc_slb_invalidate_all(env);
2782}
2783
2784void helper_slbie (target_ulong addr)
2785{
2786 ppc_slb_invalidate_one(env, addr);
2787}
2788
2789#endif /* defined(TARGET_PPC64) */
2790
2791/* TLB management */
2792void helper_tlbia (void)
2793{
2794 ppc_tlb_invalidate_all(env);
2795}
2796
2797void helper_tlbie (target_ulong addr)
2798{
2799 ppc_tlb_invalidate_one(env, addr);
2800}
2801
j_mayer76a66252007-03-07 08:32:30 +00002802/* Software driven TLBs management */
2803/* PowerPC 602/603 software TLB load instructions helpers */
aurel3274d37792008-12-06 21:46:17 +00002804static void do_6xx_tlb (target_ulong new_EPN, int is_code)
j_mayer76a66252007-03-07 08:32:30 +00002805{
2806 target_ulong RPN, CMP, EPN;
2807 int way;
j_mayerd9bce9d2007-03-17 14:02:15 +00002808
j_mayer76a66252007-03-07 08:32:30 +00002809 RPN = env->spr[SPR_RPA];
2810 if (is_code) {
2811 CMP = env->spr[SPR_ICMP];
2812 EPN = env->spr[SPR_IMISS];
2813 } else {
2814 CMP = env->spr[SPR_DCMP];
2815 EPN = env->spr[SPR_DMISS];
2816 }
2817 way = (env->spr[SPR_SRR1] >> 17) & 1;
2818#if defined (DEBUG_SOFTWARE_TLB)
2819 if (loglevel != 0) {
aurel320e698052008-12-08 18:11:42 +00002820 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
j_mayer6b542af2007-11-24 02:03:55 +00002821 " PTE1 " ADDRX " way %d\n",
aurel320e698052008-12-08 18:11:42 +00002822 __func__, new_EPN, EPN, CMP, RPN, way);
j_mayer76a66252007-03-07 08:32:30 +00002823 }
2824#endif
2825 /* Store this TLB */
aurel320f3955e2008-11-30 16:22:56 +00002826 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
j_mayerd9bce9d2007-03-17 14:02:15 +00002827 way, is_code, CMP, RPN);
j_mayer76a66252007-03-07 08:32:30 +00002828}
2829
aurel3274d37792008-12-06 21:46:17 +00002830void helper_6xx_tlbd (target_ulong EPN)
aurel320f3955e2008-11-30 16:22:56 +00002831{
aurel3274d37792008-12-06 21:46:17 +00002832 do_6xx_tlb(EPN, 0);
aurel320f3955e2008-11-30 16:22:56 +00002833}
2834
aurel3274d37792008-12-06 21:46:17 +00002835void helper_6xx_tlbi (target_ulong EPN)
aurel320f3955e2008-11-30 16:22:56 +00002836{
aurel3274d37792008-12-06 21:46:17 +00002837 do_6xx_tlb(EPN, 1);
aurel320f3955e2008-11-30 16:22:56 +00002838}
2839
2840/* PowerPC 74xx software TLB load instructions helpers */
aurel3274d37792008-12-06 21:46:17 +00002841static void do_74xx_tlb (target_ulong new_EPN, int is_code)
j_mayer7dbe11a2007-10-01 05:16:57 +00002842{
2843 target_ulong RPN, CMP, EPN;
2844 int way;
2845
2846 RPN = env->spr[SPR_PTELO];
2847 CMP = env->spr[SPR_PTEHI];
2848 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2849 way = env->spr[SPR_TLBMISS] & 0x3;
2850#if defined (DEBUG_SOFTWARE_TLB)
2851 if (loglevel != 0) {
aurel320e698052008-12-08 18:11:42 +00002852 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
j_mayer6b542af2007-11-24 02:03:55 +00002853 " PTE1 " ADDRX " way %d\n",
aurel320e698052008-12-08 18:11:42 +00002854 __func__, new_EPN, EPN, CMP, RPN, way);
j_mayer7dbe11a2007-10-01 05:16:57 +00002855 }
2856#endif
2857 /* Store this TLB */
aurel320f3955e2008-11-30 16:22:56 +00002858 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
j_mayer7dbe11a2007-10-01 05:16:57 +00002859 way, is_code, CMP, RPN);
2860}
2861
aurel3274d37792008-12-06 21:46:17 +00002862void helper_74xx_tlbd (target_ulong EPN)
aurel320f3955e2008-11-30 16:22:56 +00002863{
aurel3274d37792008-12-06 21:46:17 +00002864 do_74xx_tlb(EPN, 0);
aurel320f3955e2008-11-30 16:22:56 +00002865}
2866
aurel3274d37792008-12-06 21:46:17 +00002867void helper_74xx_tlbi (target_ulong EPN)
aurel320f3955e2008-11-30 16:22:56 +00002868{
aurel3274d37792008-12-06 21:46:17 +00002869 do_74xx_tlb(EPN, 1);
aurel320f3955e2008-11-30 16:22:56 +00002870}
2871
j_mayera11b8152007-10-28 00:55:05 +00002872static always_inline target_ulong booke_tlb_to_page_size (int size)
j_mayera8dea122007-03-31 11:33:48 +00002873{
2874 return 1024 << (2 * size);
2875}
2876
j_mayera11b8152007-10-28 00:55:05 +00002877static always_inline int booke_page_size_to_tlb (target_ulong page_size)
j_mayera8dea122007-03-31 11:33:48 +00002878{
2879 int size;
2880
2881 switch (page_size) {
2882 case 0x00000400UL:
2883 size = 0x0;
2884 break;
2885 case 0x00001000UL:
2886 size = 0x1;
2887 break;
2888 case 0x00004000UL:
2889 size = 0x2;
2890 break;
2891 case 0x00010000UL:
2892 size = 0x3;
2893 break;
2894 case 0x00040000UL:
2895 size = 0x4;
2896 break;
2897 case 0x00100000UL:
2898 size = 0x5;
2899 break;
2900 case 0x00400000UL:
2901 size = 0x6;
2902 break;
2903 case 0x01000000UL:
2904 size = 0x7;
2905 break;
2906 case 0x04000000UL:
2907 size = 0x8;
2908 break;
2909 case 0x10000000UL:
2910 size = 0x9;
2911 break;
2912 case 0x40000000UL:
2913 size = 0xA;
2914 break;
2915#if defined (TARGET_PPC64)
2916 case 0x000100000000ULL:
2917 size = 0xB;
2918 break;
2919 case 0x000400000000ULL:
2920 size = 0xC;
2921 break;
2922 case 0x001000000000ULL:
2923 size = 0xD;
2924 break;
2925 case 0x004000000000ULL:
2926 size = 0xE;
2927 break;
2928 case 0x010000000000ULL:
2929 size = 0xF;
2930 break;
2931#endif
2932 default:
2933 size = -1;
2934 break;
2935 }
2936
2937 return size;
2938}
2939
j_mayer76a66252007-03-07 08:32:30 +00002940/* Helpers for 4xx TLB management */
aurel3274d37792008-12-06 21:46:17 +00002941target_ulong helper_4xx_tlbre_lo (target_ulong entry)
j_mayer76a66252007-03-07 08:32:30 +00002942{
j_mayera8dea122007-03-31 11:33:48 +00002943 ppcemb_tlb_t *tlb;
aurel3274d37792008-12-06 21:46:17 +00002944 target_ulong ret;
j_mayera8dea122007-03-31 11:33:48 +00002945 int size;
j_mayer76a66252007-03-07 08:32:30 +00002946
aurel3274d37792008-12-06 21:46:17 +00002947 entry &= 0x3F;
2948 tlb = &env->tlb[entry].tlbe;
2949 ret = tlb->EPN;
j_mayera8dea122007-03-31 11:33:48 +00002950 if (tlb->prot & PAGE_VALID)
aurel3274d37792008-12-06 21:46:17 +00002951 ret |= 0x400;
j_mayera8dea122007-03-31 11:33:48 +00002952 size = booke_page_size_to_tlb(tlb->size);
2953 if (size < 0 || size > 0x7)
2954 size = 1;
aurel3274d37792008-12-06 21:46:17 +00002955 ret |= size << 7;
j_mayera8dea122007-03-31 11:33:48 +00002956 env->spr[SPR_40x_PID] = tlb->PID;
aurel3274d37792008-12-06 21:46:17 +00002957 return ret;
j_mayer76a66252007-03-07 08:32:30 +00002958}
2959
aurel3274d37792008-12-06 21:46:17 +00002960target_ulong helper_4xx_tlbre_hi (target_ulong entry)
j_mayer76a66252007-03-07 08:32:30 +00002961{
j_mayera8dea122007-03-31 11:33:48 +00002962 ppcemb_tlb_t *tlb;
aurel3274d37792008-12-06 21:46:17 +00002963 target_ulong ret;
j_mayer76a66252007-03-07 08:32:30 +00002964
aurel3274d37792008-12-06 21:46:17 +00002965 entry &= 0x3F;
2966 tlb = &env->tlb[entry].tlbe;
2967 ret = tlb->RPN;
j_mayera8dea122007-03-31 11:33:48 +00002968 if (tlb->prot & PAGE_EXEC)
aurel3274d37792008-12-06 21:46:17 +00002969 ret |= 0x200;
j_mayera8dea122007-03-31 11:33:48 +00002970 if (tlb->prot & PAGE_WRITE)
aurel3274d37792008-12-06 21:46:17 +00002971 ret |= 0x100;
2972 return ret;
j_mayer76a66252007-03-07 08:32:30 +00002973}
2974
aurel3274d37792008-12-06 21:46:17 +00002975void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
j_mayer76a66252007-03-07 08:32:30 +00002976{
j_mayera8dea122007-03-31 11:33:48 +00002977 ppcemb_tlb_t *tlb;
j_mayer76a66252007-03-07 08:32:30 +00002978 target_ulong page, end;
2979
j_mayerc55e9ae2007-04-16 09:21:46 +00002980#if defined (DEBUG_SOFTWARE_TLB)
j_mayer6b800552007-04-24 07:36:03 +00002981 if (loglevel != 0) {
aurel320e698052008-12-08 18:11:42 +00002982 fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
j_mayerc55e9ae2007-04-16 09:21:46 +00002983 }
2984#endif
aurel3274d37792008-12-06 21:46:17 +00002985 entry &= 0x3F;
2986 tlb = &env->tlb[entry].tlbe;
j_mayer76a66252007-03-07 08:32:30 +00002987 /* Invalidate previous TLB (if it's valid) */
2988 if (tlb->prot & PAGE_VALID) {
2989 end = tlb->EPN + tlb->size;
j_mayerc55e9ae2007-04-16 09:21:46 +00002990#if defined (DEBUG_SOFTWARE_TLB)
j_mayer6b800552007-04-24 07:36:03 +00002991 if (loglevel != 0) {
j_mayerc55e9ae2007-04-16 09:21:46 +00002992 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
aurel3274d37792008-12-06 21:46:17 +00002993 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
j_mayerc55e9ae2007-04-16 09:21:46 +00002994 }
2995#endif
j_mayer76a66252007-03-07 08:32:30 +00002996 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2997 tlb_flush_page(env, page);
2998 }
aurel3274d37792008-12-06 21:46:17 +00002999 tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7);
j_mayerc294fc52007-04-24 06:44:14 +00003000 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
3001 * If this ever occurs, one should use the ppcemb target instead
3002 * of the ppc or ppc64 one
3003 */
aurel3274d37792008-12-06 21:46:17 +00003004 if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
j_mayer71c8b8f2007-09-19 05:46:03 +00003005 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
3006 "are not supported (%d)\n",
aurel3274d37792008-12-06 21:46:17 +00003007 tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
j_mayerc294fc52007-04-24 06:44:14 +00003008 }
aurel3274d37792008-12-06 21:46:17 +00003009 tlb->EPN = val & ~(tlb->size - 1);
3010 if (val & 0x40)
j_mayer76a66252007-03-07 08:32:30 +00003011 tlb->prot |= PAGE_VALID;
3012 else
3013 tlb->prot &= ~PAGE_VALID;
aurel3274d37792008-12-06 21:46:17 +00003014 if (val & 0x20) {
j_mayerc294fc52007-04-24 06:44:14 +00003015 /* XXX: TO BE FIXED */
3016 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
3017 }
j_mayerc55e9ae2007-04-16 09:21:46 +00003018 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
aurel3274d37792008-12-06 21:46:17 +00003019 tlb->attr = val & 0xFF;
j_mayerc55e9ae2007-04-16 09:21:46 +00003020#if defined (DEBUG_SOFTWARE_TLB)
j_mayerc294fc52007-04-24 06:44:14 +00003021 if (loglevel != 0) {
3022 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
j_mayerc55e9ae2007-04-16 09:21:46 +00003023 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
aurel320e698052008-12-08 18:11:42 +00003024 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
j_mayerc55e9ae2007-04-16 09:21:46 +00003025 tlb->prot & PAGE_READ ? 'r' : '-',
3026 tlb->prot & PAGE_WRITE ? 'w' : '-',
3027 tlb->prot & PAGE_EXEC ? 'x' : '-',
3028 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3029 }
3030#endif
j_mayer76a66252007-03-07 08:32:30 +00003031 /* Invalidate new TLB (if valid) */
3032 if (tlb->prot & PAGE_VALID) {
3033 end = tlb->EPN + tlb->size;
j_mayerc55e9ae2007-04-16 09:21:46 +00003034#if defined (DEBUG_SOFTWARE_TLB)
j_mayer6b800552007-04-24 07:36:03 +00003035 if (loglevel != 0) {
j_mayerc55e9ae2007-04-16 09:21:46 +00003036 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
aurel320e698052008-12-08 18:11:42 +00003037 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
j_mayerc55e9ae2007-04-16 09:21:46 +00003038 }
3039#endif
j_mayer76a66252007-03-07 08:32:30 +00003040 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
3041 tlb_flush_page(env, page);
3042 }
j_mayer76a66252007-03-07 08:32:30 +00003043}
3044
aurel3274d37792008-12-06 21:46:17 +00003045void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
j_mayer76a66252007-03-07 08:32:30 +00003046{
j_mayera8dea122007-03-31 11:33:48 +00003047 ppcemb_tlb_t *tlb;
j_mayer76a66252007-03-07 08:32:30 +00003048
j_mayerc55e9ae2007-04-16 09:21:46 +00003049#if defined (DEBUG_SOFTWARE_TLB)
j_mayer6b800552007-04-24 07:36:03 +00003050 if (loglevel != 0) {
aurel320e698052008-12-08 18:11:42 +00003051 fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
j_mayerc55e9ae2007-04-16 09:21:46 +00003052 }
3053#endif
aurel3274d37792008-12-06 21:46:17 +00003054 entry &= 0x3F;
3055 tlb = &env->tlb[entry].tlbe;
3056 tlb->RPN = val & 0xFFFFFC00;
j_mayer76a66252007-03-07 08:32:30 +00003057 tlb->prot = PAGE_READ;
aurel3274d37792008-12-06 21:46:17 +00003058 if (val & 0x200)
j_mayer76a66252007-03-07 08:32:30 +00003059 tlb->prot |= PAGE_EXEC;
aurel3274d37792008-12-06 21:46:17 +00003060 if (val & 0x100)
j_mayer76a66252007-03-07 08:32:30 +00003061 tlb->prot |= PAGE_WRITE;
j_mayerc55e9ae2007-04-16 09:21:46 +00003062#if defined (DEBUG_SOFTWARE_TLB)
j_mayer6b800552007-04-24 07:36:03 +00003063 if (loglevel != 0) {
3064 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
j_mayerc55e9ae2007-04-16 09:21:46 +00003065 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
aurel3274d37792008-12-06 21:46:17 +00003066 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
j_mayerc55e9ae2007-04-16 09:21:46 +00003067 tlb->prot & PAGE_READ ? 'r' : '-',
3068 tlb->prot & PAGE_WRITE ? 'w' : '-',
3069 tlb->prot & PAGE_EXEC ? 'x' : '-',
3070 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
3071 }
3072#endif
j_mayer76a66252007-03-07 08:32:30 +00003073}
j_mayer5eb79952007-09-19 05:44:04 +00003074
aurel3274d37792008-12-06 21:46:17 +00003075target_ulong helper_4xx_tlbsx (target_ulong address)
3076{
3077 return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
3078}
3079
j_mayera4bb6c32007-09-21 05:28:33 +00003080/* PowerPC 440 TLB management */
aurel3274d37792008-12-06 21:46:17 +00003081void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
j_mayer5eb79952007-09-19 05:44:04 +00003082{
3083 ppcemb_tlb_t *tlb;
j_mayera4bb6c32007-09-21 05:28:33 +00003084 target_ulong EPN, RPN, size;
j_mayer5eb79952007-09-19 05:44:04 +00003085 int do_flush_tlbs;
3086
3087#if defined (DEBUG_SOFTWARE_TLB)
3088 if (loglevel != 0) {
aurel320e698052008-12-08 18:11:42 +00003089 fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
3090 __func__, word, (int)entry, value);
j_mayer5eb79952007-09-19 05:44:04 +00003091 }
3092#endif
3093 do_flush_tlbs = 0;
aurel3274d37792008-12-06 21:46:17 +00003094 entry &= 0x3F;
3095 tlb = &env->tlb[entry].tlbe;
j_mayera4bb6c32007-09-21 05:28:33 +00003096 switch (word) {
3097 default:
3098 /* Just here to please gcc */
3099 case 0:
aurel3274d37792008-12-06 21:46:17 +00003100 EPN = value & 0xFFFFFC00;
j_mayera4bb6c32007-09-21 05:28:33 +00003101 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
j_mayer5eb79952007-09-19 05:44:04 +00003102 do_flush_tlbs = 1;
j_mayera4bb6c32007-09-21 05:28:33 +00003103 tlb->EPN = EPN;
aurel3274d37792008-12-06 21:46:17 +00003104 size = booke_tlb_to_page_size((value >> 4) & 0xF);
j_mayera4bb6c32007-09-21 05:28:33 +00003105 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
3106 do_flush_tlbs = 1;
3107 tlb->size = size;
3108 tlb->attr &= ~0x1;
aurel3274d37792008-12-06 21:46:17 +00003109 tlb->attr |= (value >> 8) & 1;
3110 if (value & 0x200) {
j_mayera4bb6c32007-09-21 05:28:33 +00003111 tlb->prot |= PAGE_VALID;
3112 } else {
3113 if (tlb->prot & PAGE_VALID) {
3114 tlb->prot &= ~PAGE_VALID;
3115 do_flush_tlbs = 1;
3116 }
j_mayer5eb79952007-09-19 05:44:04 +00003117 }
j_mayera4bb6c32007-09-21 05:28:33 +00003118 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3119 if (do_flush_tlbs)
3120 tlb_flush(env, 1);
3121 break;
3122 case 1:
aurel3274d37792008-12-06 21:46:17 +00003123 RPN = value & 0xFFFFFC0F;
j_mayera4bb6c32007-09-21 05:28:33 +00003124 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3125 tlb_flush(env, 1);
3126 tlb->RPN = RPN;
3127 break;
3128 case 2:
aurel3274d37792008-12-06 21:46:17 +00003129 tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
j_mayera4bb6c32007-09-21 05:28:33 +00003130 tlb->prot = tlb->prot & PAGE_VALID;
aurel3274d37792008-12-06 21:46:17 +00003131 if (value & 0x1)
j_mayera4bb6c32007-09-21 05:28:33 +00003132 tlb->prot |= PAGE_READ << 4;
aurel3274d37792008-12-06 21:46:17 +00003133 if (value & 0x2)
j_mayera4bb6c32007-09-21 05:28:33 +00003134 tlb->prot |= PAGE_WRITE << 4;
aurel3274d37792008-12-06 21:46:17 +00003135 if (value & 0x4)
j_mayera4bb6c32007-09-21 05:28:33 +00003136 tlb->prot |= PAGE_EXEC << 4;
aurel3274d37792008-12-06 21:46:17 +00003137 if (value & 0x8)
j_mayera4bb6c32007-09-21 05:28:33 +00003138 tlb->prot |= PAGE_READ;
aurel3274d37792008-12-06 21:46:17 +00003139 if (value & 0x10)
j_mayera4bb6c32007-09-21 05:28:33 +00003140 tlb->prot |= PAGE_WRITE;
aurel3274d37792008-12-06 21:46:17 +00003141 if (value & 0x20)
j_mayera4bb6c32007-09-21 05:28:33 +00003142 tlb->prot |= PAGE_EXEC;
3143 break;
j_mayer5eb79952007-09-19 05:44:04 +00003144 }
j_mayer5eb79952007-09-19 05:44:04 +00003145}
3146
aurel3274d37792008-12-06 21:46:17 +00003147target_ulong helper_440_tlbre (uint32_t word, target_ulong entry)
j_mayer5eb79952007-09-19 05:44:04 +00003148{
3149 ppcemb_tlb_t *tlb;
aurel3274d37792008-12-06 21:46:17 +00003150 target_ulong ret;
j_mayer5eb79952007-09-19 05:44:04 +00003151 int size;
3152
aurel3274d37792008-12-06 21:46:17 +00003153 entry &= 0x3F;
3154 tlb = &env->tlb[entry].tlbe;
j_mayera4bb6c32007-09-21 05:28:33 +00003155 switch (word) {
3156 default:
3157 /* Just here to please gcc */
3158 case 0:
aurel3274d37792008-12-06 21:46:17 +00003159 ret = tlb->EPN;
j_mayera4bb6c32007-09-21 05:28:33 +00003160 size = booke_page_size_to_tlb(tlb->size);
3161 if (size < 0 || size > 0xF)
3162 size = 1;
aurel3274d37792008-12-06 21:46:17 +00003163 ret |= size << 4;
j_mayera4bb6c32007-09-21 05:28:33 +00003164 if (tlb->attr & 0x1)
aurel3274d37792008-12-06 21:46:17 +00003165 ret |= 0x100;
j_mayera4bb6c32007-09-21 05:28:33 +00003166 if (tlb->prot & PAGE_VALID)
aurel3274d37792008-12-06 21:46:17 +00003167 ret |= 0x200;
j_mayera4bb6c32007-09-21 05:28:33 +00003168 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3169 env->spr[SPR_440_MMUCR] |= tlb->PID;
3170 break;
3171 case 1:
aurel3274d37792008-12-06 21:46:17 +00003172 ret = tlb->RPN;
j_mayera4bb6c32007-09-21 05:28:33 +00003173 break;
3174 case 2:
aurel3274d37792008-12-06 21:46:17 +00003175 ret = tlb->attr & ~0x1;
j_mayera4bb6c32007-09-21 05:28:33 +00003176 if (tlb->prot & (PAGE_READ << 4))
aurel3274d37792008-12-06 21:46:17 +00003177 ret |= 0x1;
j_mayera4bb6c32007-09-21 05:28:33 +00003178 if (tlb->prot & (PAGE_WRITE << 4))
aurel3274d37792008-12-06 21:46:17 +00003179 ret |= 0x2;
j_mayera4bb6c32007-09-21 05:28:33 +00003180 if (tlb->prot & (PAGE_EXEC << 4))
aurel3274d37792008-12-06 21:46:17 +00003181 ret |= 0x4;
j_mayera4bb6c32007-09-21 05:28:33 +00003182 if (tlb->prot & PAGE_READ)
aurel3274d37792008-12-06 21:46:17 +00003183 ret |= 0x8;
j_mayera4bb6c32007-09-21 05:28:33 +00003184 if (tlb->prot & PAGE_WRITE)
aurel3274d37792008-12-06 21:46:17 +00003185 ret |= 0x10;
j_mayera4bb6c32007-09-21 05:28:33 +00003186 if (tlb->prot & PAGE_EXEC)
aurel3274d37792008-12-06 21:46:17 +00003187 ret |= 0x20;
j_mayera4bb6c32007-09-21 05:28:33 +00003188 break;
3189 }
aurel3274d37792008-12-06 21:46:17 +00003190 return ret;
j_mayer5eb79952007-09-19 05:44:04 +00003191}
aurel3274d37792008-12-06 21:46:17 +00003192
3193target_ulong helper_440_tlbsx (target_ulong address)
3194{
3195 return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
3196}
3197
j_mayer76a66252007-03-07 08:32:30 +00003198#endif /* !CONFIG_USER_ONLY */