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bellard9a64fbe2004-01-04 22:58:38 +00001/*
bellard3fc6c082005-07-02 20:59:34 +00002 * PowerPC emulation helpers for qemu.
ths5fafdf22007-09-16 21:08:06 +00003 *
j_mayer76a66252007-03-07 08:32:30 +00004 * Copyright (c) 2003-2007 Jocelyn Mayer
bellard9a64fbe2004-01-04 22:58:38 +00005 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
bellard9a64fbe2004-01-04 22:58:38 +000020#include "exec.h"
j_mayer603fccc2007-10-28 12:54:53 +000021#include "host-utils.h"
pbrooka7812ae2008-11-17 14:43:54 +000022#include "helper.h"
bellard9a64fbe2004-01-04 22:58:38 +000023
j_mayer0411a972007-10-25 21:35:50 +000024#include "helper_regs.h"
j_mayer0487d6a2007-03-20 22:11:31 +000025
bellardfdabc362005-07-04 22:17:05 +000026//#define DEBUG_OP
27//#define DEBUG_EXCEPTIONS
j_mayer76a66252007-03-07 08:32:30 +000028//#define DEBUG_SOFTWARE_TLB
bellardfdabc362005-07-04 22:17:05 +000029
bellard9a64fbe2004-01-04 22:58:38 +000030/*****************************************************************************/
31/* Exceptions processing helpers */
bellard9a64fbe2004-01-04 22:58:38 +000032
aurel3264adab32008-11-22 10:09:17 +000033void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
bellard9a64fbe2004-01-04 22:58:38 +000034{
aurel32e06fcd72008-12-11 22:42:14 +000035#if 0
36 printf("Raise exception %3x code : %d\n", exception, error_code);
37#endif
38 env->exception_index = exception;
39 env->error_code = error_code;
40 cpu_loop_exit();
j_mayer76a66252007-03-07 08:32:30 +000041}
bellard9fddaa02004-05-21 12:59:32 +000042
aurel32e06fcd72008-12-11 22:42:14 +000043void helper_raise_exception (uint32_t exception)
bellard9fddaa02004-05-21 12:59:32 +000044{
aurel32e06fcd72008-12-11 22:42:14 +000045 helper_raise_exception_err(exception, 0);
bellard9a64fbe2004-01-04 22:58:38 +000046}
47
48/*****************************************************************************/
j_mayer76a66252007-03-07 08:32:30 +000049/* Registers load and stores */
pbrooka7812ae2008-11-17 14:43:54 +000050target_ulong helper_load_cr (void)
j_mayer76a66252007-03-07 08:32:30 +000051{
aurel32e1571902008-10-21 11:31:14 +000052 return (env->crf[0] << 28) |
53 (env->crf[1] << 24) |
54 (env->crf[2] << 20) |
55 (env->crf[3] << 16) |
56 (env->crf[4] << 12) |
57 (env->crf[5] << 8) |
58 (env->crf[6] << 4) |
59 (env->crf[7] << 0);
j_mayer76a66252007-03-07 08:32:30 +000060}
61
aurel32e1571902008-10-21 11:31:14 +000062void helper_store_cr (target_ulong val, uint32_t mask)
j_mayer76a66252007-03-07 08:32:30 +000063{
64 int i, sh;
65
j_mayer36081602007-09-17 08:21:54 +000066 for (i = 0, sh = 7; i < 8; i++, sh--) {
j_mayer76a66252007-03-07 08:32:30 +000067 if (mask & (1 << sh))
aurel32e1571902008-10-21 11:31:14 +000068 env->crf[i] = (val >> (sh * 4)) & 0xFUL;
j_mayer76a66252007-03-07 08:32:30 +000069 }
70}
71
aurel3245d827d2008-12-07 13:40:29 +000072/*****************************************************************************/
73/* SPR accesses */
74void helper_load_dump_spr (uint32_t sprn)
j_mayera4967752007-04-16 07:10:48 +000075{
j_mayer6b800552007-04-24 07:36:03 +000076 if (loglevel != 0) {
j_mayera4967752007-04-16 07:10:48 +000077 fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
78 sprn, sprn, env->spr[sprn]);
79 }
j_mayera4967752007-04-16 07:10:48 +000080}
81
aurel3245d827d2008-12-07 13:40:29 +000082void helper_store_dump_spr (uint32_t sprn)
j_mayera4967752007-04-16 07:10:48 +000083{
j_mayer6b800552007-04-24 07:36:03 +000084 if (loglevel != 0) {
aurel3245d827d2008-12-07 13:40:29 +000085 fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n",
86 sprn, sprn, env->spr[sprn]);
j_mayera4967752007-04-16 07:10:48 +000087 }
j_mayera4967752007-04-16 07:10:48 +000088}
89
aurel3245d827d2008-12-07 13:40:29 +000090target_ulong helper_load_tbl (void)
91{
92 return cpu_ppc_load_tbl(env);
93}
94
95target_ulong helper_load_tbu (void)
96{
97 return cpu_ppc_load_tbu(env);
98}
99
100target_ulong helper_load_atbl (void)
101{
102 return cpu_ppc_load_atbl(env);
103}
104
105target_ulong helper_load_atbu (void)
106{
107 return cpu_ppc_load_atbu(env);
108}
109
110target_ulong helper_load_601_rtcl (void)
111{
112 return cpu_ppc601_load_rtcl(env);
113}
114
115target_ulong helper_load_601_rtcu (void)
116{
117 return cpu_ppc601_load_rtcu(env);
118}
119
120#if !defined(CONFIG_USER_ONLY)
121#if defined (TARGET_PPC64)
122void helper_store_asr (target_ulong val)
123{
124 ppc_store_asr(env, val);
125}
126#endif
127
128void helper_store_sdr1 (target_ulong val)
129{
130 ppc_store_sdr1(env, val);
131}
132
133void helper_store_tbl (target_ulong val)
134{
135 cpu_ppc_store_tbl(env, val);
136}
137
138void helper_store_tbu (target_ulong val)
139{
140 cpu_ppc_store_tbu(env, val);
141}
142
143void helper_store_atbl (target_ulong val)
144{
145 cpu_ppc_store_atbl(env, val);
146}
147
148void helper_store_atbu (target_ulong val)
149{
150 cpu_ppc_store_atbu(env, val);
151}
152
153void helper_store_601_rtcl (target_ulong val)
154{
155 cpu_ppc601_store_rtcl(env, val);
156}
157
158void helper_store_601_rtcu (target_ulong val)
159{
160 cpu_ppc601_store_rtcu(env, val);
161}
162
163target_ulong helper_load_decr (void)
164{
165 return cpu_ppc_load_decr(env);
166}
167
168void helper_store_decr (target_ulong val)
169{
170 cpu_ppc_store_decr(env, val);
171}
172
173void helper_store_hid0_601 (target_ulong val)
174{
175 target_ulong hid0;
176
177 hid0 = env->spr[SPR_HID0];
178 if ((val ^ hid0) & 0x00000008) {
179 /* Change current endianness */
180 env->hflags &= ~(1 << MSR_LE);
181 env->hflags_nmsr &= ~(1 << MSR_LE);
182 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
183 env->hflags |= env->hflags_nmsr;
184 if (loglevel != 0) {
185 fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
186 __func__, val & 0x8 ? 'l' : 'b', env->hflags);
187 }
188 }
189 env->spr[SPR_HID0] = (uint32_t)val;
190}
191
192void helper_store_403_pbr (uint32_t num, target_ulong value)
193{
194 if (likely(env->pb[num] != value)) {
195 env->pb[num] = value;
196 /* Should be optimized */
197 tlb_flush(env, 1);
198 }
199}
200
201target_ulong helper_load_40x_pit (void)
202{
203 return load_40x_pit(env);
204}
205
206void helper_store_40x_pit (target_ulong val)
207{
208 store_40x_pit(env, val);
209}
210
211void helper_store_40x_dbcr0 (target_ulong val)
212{
213 store_40x_dbcr0(env, val);
214}
215
216void helper_store_40x_sler (target_ulong val)
217{
218 store_40x_sler(env, val);
219}
220
221void helper_store_booke_tcr (target_ulong val)
222{
223 store_booke_tcr(env, val);
224}
225
226void helper_store_booke_tsr (target_ulong val)
227{
228 store_booke_tsr(env, val);
229}
230
231void helper_store_ibatu (uint32_t nr, target_ulong val)
232{
233 ppc_store_ibatu(env, nr, val);
234}
235
236void helper_store_ibatl (uint32_t nr, target_ulong val)
237{
238 ppc_store_ibatl(env, nr, val);
239}
240
241void helper_store_dbatu (uint32_t nr, target_ulong val)
242{
243 ppc_store_dbatu(env, nr, val);
244}
245
246void helper_store_dbatl (uint32_t nr, target_ulong val)
247{
248 ppc_store_dbatl(env, nr, val);
249}
250
251void helper_store_601_batl (uint32_t nr, target_ulong val)
252{
253 ppc_store_ibatl_601(env, nr, val);
254}
255
256void helper_store_601_batu (uint32_t nr, target_ulong val)
257{
258 ppc_store_ibatu_601(env, nr, val);
259}
260#endif
261
j_mayer76a66252007-03-07 08:32:30 +0000262/*****************************************************************************/
aurel32ff4a62c2008-11-30 16:23:56 +0000263/* Memory load and stores */
264
aurel3276db3ba2008-12-08 18:11:21 +0000265static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
aurel32ff4a62c2008-11-30 16:23:56 +0000266{
267#if defined(TARGET_PPC64)
aurel3276db3ba2008-12-08 18:11:21 +0000268 if (!msr_sf)
269 return (uint32_t)(addr + arg);
aurel32ff4a62c2008-11-30 16:23:56 +0000270 else
271#endif
aurel3276db3ba2008-12-08 18:11:21 +0000272 return addr + arg;
aurel32ff4a62c2008-11-30 16:23:56 +0000273}
274
275void helper_lmw (target_ulong addr, uint32_t reg)
276{
aurel3276db3ba2008-12-08 18:11:21 +0000277 for (; reg < 32; reg++) {
aurel32ff4a62c2008-11-30 16:23:56 +0000278 if (msr_le)
aurel3276db3ba2008-12-08 18:11:21 +0000279 env->gpr[reg] = bswap32(ldl(addr));
aurel32ff4a62c2008-11-30 16:23:56 +0000280 else
aurel3276db3ba2008-12-08 18:11:21 +0000281 env->gpr[reg] = ldl(addr);
282 addr = addr_add(addr, 4);
aurel32ff4a62c2008-11-30 16:23:56 +0000283 }
284}
285
286void helper_stmw (target_ulong addr, uint32_t reg)
287{
aurel3276db3ba2008-12-08 18:11:21 +0000288 for (; reg < 32; reg++) {
aurel32ff4a62c2008-11-30 16:23:56 +0000289 if (msr_le)
aurel3276db3ba2008-12-08 18:11:21 +0000290 stl(addr, bswap32((uint32_t)env->gpr[reg]));
aurel32ff4a62c2008-11-30 16:23:56 +0000291 else
aurel3276db3ba2008-12-08 18:11:21 +0000292 stl(addr, (uint32_t)env->gpr[reg]);
293 addr = addr_add(addr, 4);
aurel32ff4a62c2008-11-30 16:23:56 +0000294 }
295}
296
aurel32dfbc7992008-11-30 16:24:21 +0000297void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
298{
299 int sh;
aurel3276db3ba2008-12-08 18:11:21 +0000300 for (; nb > 3; nb -= 4) {
301 env->gpr[reg] = ldl(addr);
aurel32dfbc7992008-11-30 16:24:21 +0000302 reg = (reg + 1) % 32;
aurel3276db3ba2008-12-08 18:11:21 +0000303 addr = addr_add(addr, 4);
aurel32dfbc7992008-11-30 16:24:21 +0000304 }
305 if (unlikely(nb > 0)) {
306 env->gpr[reg] = 0;
aurel3276db3ba2008-12-08 18:11:21 +0000307 for (sh = 24; nb > 0; nb--, sh -= 8) {
308 env->gpr[reg] |= ldub(addr) << sh;
309 addr = addr_add(addr, 1);
aurel32dfbc7992008-11-30 16:24:21 +0000310 }
311 }
312}
313/* PPC32 specification says we must generate an exception if
314 * rA is in the range of registers to be loaded.
315 * In an other hand, IBM says this is valid, but rA won't be loaded.
316 * For now, I'll follow the spec...
317 */
318void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
319{
320 if (likely(xer_bc != 0)) {
321 if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
322 (reg < rb && (reg + xer_bc) > rb))) {
aurel32e06fcd72008-12-11 22:42:14 +0000323 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
324 POWERPC_EXCP_INVAL |
325 POWERPC_EXCP_INVAL_LSWX);
aurel32dfbc7992008-11-30 16:24:21 +0000326 } else {
327 helper_lsw(addr, xer_bc, reg);
328 }
329 }
330}
331
332void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
333{
334 int sh;
aurel3276db3ba2008-12-08 18:11:21 +0000335 for (; nb > 3; nb -= 4) {
336 stl(addr, env->gpr[reg]);
aurel32dfbc7992008-11-30 16:24:21 +0000337 reg = (reg + 1) % 32;
aurel3276db3ba2008-12-08 18:11:21 +0000338 addr = addr_add(addr, 4);
aurel32dfbc7992008-11-30 16:24:21 +0000339 }
340 if (unlikely(nb > 0)) {
aurel3276db3ba2008-12-08 18:11:21 +0000341 for (sh = 24; nb > 0; nb--, sh -= 8)
342 stb(addr, (env->gpr[reg] >> sh) & 0xFF);
343 addr = addr_add(addr, 1);
aurel32dfbc7992008-11-30 16:24:21 +0000344 }
345}
346
aurel32799a8c82008-11-30 16:24:05 +0000347static void do_dcbz(target_ulong addr, int dcache_line_size)
348{
aurel3276db3ba2008-12-08 18:11:21 +0000349 addr &= ~(dcache_line_size - 1);
aurel32799a8c82008-11-30 16:24:05 +0000350 int i;
aurel32799a8c82008-11-30 16:24:05 +0000351 for (i = 0 ; i < dcache_line_size ; i += 4) {
aurel32dcc532c2008-11-30 17:54:21 +0000352 stl(addr + i , 0);
aurel32799a8c82008-11-30 16:24:05 +0000353 }
aurel3276db3ba2008-12-08 18:11:21 +0000354 if (env->reserve == addr)
aurel32799a8c82008-11-30 16:24:05 +0000355 env->reserve = (target_ulong)-1ULL;
356}
357
358void helper_dcbz(target_ulong addr)
359{
360 do_dcbz(addr, env->dcache_line_size);
361}
362
363void helper_dcbz_970(target_ulong addr)
364{
365 if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
366 do_dcbz(addr, 32);
367 else
368 do_dcbz(addr, env->dcache_line_size);
369}
370
aurel3237d269d2008-11-30 16:24:13 +0000371void helper_icbi(target_ulong addr)
372{
373 uint32_t tmp;
374
aurel3276db3ba2008-12-08 18:11:21 +0000375 addr &= ~(env->dcache_line_size - 1);
aurel3237d269d2008-11-30 16:24:13 +0000376 /* Invalidate one cache line :
377 * PowerPC specification says this is to be treated like a load
378 * (not a fetch) by the MMU. To be sure it will be so,
379 * do the load "by hand".
380 */
aurel32dcc532c2008-11-30 17:54:21 +0000381 tmp = ldl(addr);
aurel3237d269d2008-11-30 16:24:13 +0000382 tb_invalidate_page_range(addr, addr + env->icache_line_size);
383}
384
aurel32bdb4b682008-11-30 16:24:30 +0000385// XXX: to be tested
386target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
387{
388 int i, c, d;
aurel32bdb4b682008-11-30 16:24:30 +0000389 d = 24;
390 for (i = 0; i < xer_bc; i++) {
aurel3276db3ba2008-12-08 18:11:21 +0000391 c = ldub(addr);
392 addr = addr_add(addr, 1);
aurel32bdb4b682008-11-30 16:24:30 +0000393 /* ra (if not 0) and rb are never modified */
394 if (likely(reg != rb && (ra == 0 || reg != ra))) {
395 env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
396 }
397 if (unlikely(c == xer_cmp))
398 break;
399 if (likely(d != 0)) {
400 d -= 8;
401 } else {
402 d = 24;
403 reg++;
404 reg = reg & 0x1F;
405 }
406 }
407 return i;
408}
409
aurel32ff4a62c2008-11-30 16:23:56 +0000410/*****************************************************************************/
bellardfdabc362005-07-04 22:17:05 +0000411/* Fixed point operations helpers */
j_mayerd9bce9d2007-03-17 14:02:15 +0000412#if defined(TARGET_PPC64)
bellardfdabc362005-07-04 22:17:05 +0000413
aurel3274637402008-11-01 00:54:12 +0000414/* multiply high word */
415uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
bellardfdabc362005-07-04 22:17:05 +0000416{
aurel3274637402008-11-01 00:54:12 +0000417 uint64_t tl, th;
418
419 muls64(&tl, &th, arg1, arg2);
420 return th;
bellardfdabc362005-07-04 22:17:05 +0000421}
422
aurel3274637402008-11-01 00:54:12 +0000423/* multiply high word unsigned */
424uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
bellardfdabc362005-07-04 22:17:05 +0000425{
aurel3274637402008-11-01 00:54:12 +0000426 uint64_t tl, th;
bellardfdabc362005-07-04 22:17:05 +0000427
aurel3274637402008-11-01 00:54:12 +0000428 mulu64(&tl, &th, arg1, arg2);
429 return th;
bellardfdabc362005-07-04 22:17:05 +0000430}
431
aurel3274637402008-11-01 00:54:12 +0000432uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
j_mayerd9bce9d2007-03-17 14:02:15 +0000433{
434 int64_t th;
435 uint64_t tl;
436
aurel3274637402008-11-01 00:54:12 +0000437 muls64(&tl, (uint64_t *)&th, arg1, arg2);
j_mayer88ad9202007-10-25 23:36:08 +0000438 /* If th != 0 && th != -1, then we had an overflow */
j_mayer6f2d8972007-11-12 00:04:48 +0000439 if (likely((uint64_t)(th + 1) <= 1)) {
aurel323d7b4172008-10-21 11:28:46 +0000440 env->xer &= ~(1 << XER_OV);
j_mayerd9bce9d2007-03-17 14:02:15 +0000441 } else {
aurel323d7b4172008-10-21 11:28:46 +0000442 env->xer |= (1 << XER_OV) | (1 << XER_SO);
j_mayerd9bce9d2007-03-17 14:02:15 +0000443 }
aurel3274637402008-11-01 00:54:12 +0000444 return (int64_t)tl;
j_mayerd9bce9d2007-03-17 14:02:15 +0000445}
446#endif
447
aurel3226d67362008-10-21 11:31:27 +0000448target_ulong helper_cntlzw (target_ulong t)
j_mayer603fccc2007-10-28 12:54:53 +0000449{
aurel3226d67362008-10-21 11:31:27 +0000450 return clz32(t);
j_mayer603fccc2007-10-28 12:54:53 +0000451}
452
453#if defined(TARGET_PPC64)
aurel3226d67362008-10-21 11:31:27 +0000454target_ulong helper_cntlzd (target_ulong t)
j_mayer603fccc2007-10-28 12:54:53 +0000455{
aurel3226d67362008-10-21 11:31:27 +0000456 return clz64(t);
j_mayer603fccc2007-10-28 12:54:53 +0000457}
458#endif
459
bellard9a64fbe2004-01-04 22:58:38 +0000460/* shift right arithmetic helper */
aurel3226d67362008-10-21 11:31:27 +0000461target_ulong helper_sraw (target_ulong value, target_ulong shift)
bellard9a64fbe2004-01-04 22:58:38 +0000462{
463 int32_t ret;
464
aurel3226d67362008-10-21 11:31:27 +0000465 if (likely(!(shift & 0x20))) {
466 if (likely((uint32_t)shift != 0)) {
467 shift &= 0x1f;
468 ret = (int32_t)value >> shift;
469 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
aurel323d7b4172008-10-21 11:28:46 +0000470 env->xer &= ~(1 << XER_CA);
bellardfdabc362005-07-04 22:17:05 +0000471 } else {
aurel323d7b4172008-10-21 11:28:46 +0000472 env->xer |= (1 << XER_CA);
bellardfdabc362005-07-04 22:17:05 +0000473 }
474 } else {
aurel3226d67362008-10-21 11:31:27 +0000475 ret = (int32_t)value;
aurel323d7b4172008-10-21 11:28:46 +0000476 env->xer &= ~(1 << XER_CA);
bellardfdabc362005-07-04 22:17:05 +0000477 }
bellard9a64fbe2004-01-04 22:58:38 +0000478 } else {
aurel3226d67362008-10-21 11:31:27 +0000479 ret = (int32_t)value >> 31;
480 if (ret) {
aurel323d7b4172008-10-21 11:28:46 +0000481 env->xer |= (1 << XER_CA);
aurel3226d67362008-10-21 11:31:27 +0000482 } else {
483 env->xer &= ~(1 << XER_CA);
j_mayer76a66252007-03-07 08:32:30 +0000484 }
bellardfdabc362005-07-04 22:17:05 +0000485 }
aurel3226d67362008-10-21 11:31:27 +0000486 return (target_long)ret;
bellard9a64fbe2004-01-04 22:58:38 +0000487}
488
j_mayerd9bce9d2007-03-17 14:02:15 +0000489#if defined(TARGET_PPC64)
aurel3226d67362008-10-21 11:31:27 +0000490target_ulong helper_srad (target_ulong value, target_ulong shift)
j_mayerd9bce9d2007-03-17 14:02:15 +0000491{
492 int64_t ret;
493
aurel3226d67362008-10-21 11:31:27 +0000494 if (likely(!(shift & 0x40))) {
495 if (likely((uint64_t)shift != 0)) {
496 shift &= 0x3f;
497 ret = (int64_t)value >> shift;
498 if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
aurel323d7b4172008-10-21 11:28:46 +0000499 env->xer &= ~(1 << XER_CA);
j_mayerd9bce9d2007-03-17 14:02:15 +0000500 } else {
aurel323d7b4172008-10-21 11:28:46 +0000501 env->xer |= (1 << XER_CA);
j_mayerd9bce9d2007-03-17 14:02:15 +0000502 }
503 } else {
aurel3226d67362008-10-21 11:31:27 +0000504 ret = (int64_t)value;
aurel323d7b4172008-10-21 11:28:46 +0000505 env->xer &= ~(1 << XER_CA);
j_mayerd9bce9d2007-03-17 14:02:15 +0000506 }
507 } else {
aurel3226d67362008-10-21 11:31:27 +0000508 ret = (int64_t)value >> 63;
509 if (ret) {
aurel323d7b4172008-10-21 11:28:46 +0000510 env->xer |= (1 << XER_CA);
aurel3226d67362008-10-21 11:31:27 +0000511 } else {
512 env->xer &= ~(1 << XER_CA);
j_mayerd9bce9d2007-03-17 14:02:15 +0000513 }
514 }
aurel3226d67362008-10-21 11:31:27 +0000515 return ret;
j_mayerd9bce9d2007-03-17 14:02:15 +0000516}
517#endif
518
aurel3226d67362008-10-21 11:31:27 +0000519target_ulong helper_popcntb (target_ulong val)
j_mayerd9bce9d2007-03-17 14:02:15 +0000520{
aurel326176a262008-11-01 00:54:33 +0000521 val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
522 val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
523 val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
524 return val;
j_mayerd9bce9d2007-03-17 14:02:15 +0000525}
526
527#if defined(TARGET_PPC64)
aurel3226d67362008-10-21 11:31:27 +0000528target_ulong helper_popcntb_64 (target_ulong val)
j_mayerd9bce9d2007-03-17 14:02:15 +0000529{
aurel326176a262008-11-01 00:54:33 +0000530 val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
531 val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
532 val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
533 return val;
j_mayerd9bce9d2007-03-17 14:02:15 +0000534}
535#endif
536
bellardfdabc362005-07-04 22:17:05 +0000537/*****************************************************************************/
bellard9a64fbe2004-01-04 22:58:38 +0000538/* Floating point operations helpers */
aurel32a0d7d5a2008-11-23 16:30:50 +0000539uint64_t helper_float32_to_float64(uint32_t arg)
540{
541 CPU_FloatU f;
542 CPU_DoubleU d;
543 f.l = arg;
544 d.d = float32_to_float64(f.f, &env->fp_status);
545 return d.ll;
546}
547
548uint32_t helper_float64_to_float32(uint64_t arg)
549{
550 CPU_FloatU f;
551 CPU_DoubleU d;
552 d.ll = arg;
553 f.f = float64_to_float32(d.d, &env->fp_status);
554 return f.l;
555}
556
aurel320ca9d382008-03-13 19:19:16 +0000557static always_inline int isden (float64 d)
j_mayer7c580442007-10-27 17:54:30 +0000558{
aurel320ca9d382008-03-13 19:19:16 +0000559 CPU_DoubleU u;
j_mayer7c580442007-10-27 17:54:30 +0000560
aurel320ca9d382008-03-13 19:19:16 +0000561 u.d = d;
j_mayer7c580442007-10-27 17:54:30 +0000562
aurel320ca9d382008-03-13 19:19:16 +0000563 return ((u.ll >> 52) & 0x7FF) == 0;
j_mayer7c580442007-10-27 17:54:30 +0000564}
565
aurel32af129062008-11-19 16:10:23 +0000566uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
j_mayer7c580442007-10-27 17:54:30 +0000567{
aurel32af129062008-11-19 16:10:23 +0000568 CPU_DoubleU farg;
j_mayer7c580442007-10-27 17:54:30 +0000569 int isneg;
aurel32af129062008-11-19 16:10:23 +0000570 int ret;
571 farg.ll = arg;
aurel32f23c3462008-12-15 17:14:27 +0000572 isneg = float64_is_neg(farg.d);
aurel32af129062008-11-19 16:10:23 +0000573 if (unlikely(float64_is_nan(farg.d))) {
574 if (float64_is_signaling_nan(farg.d)) {
j_mayer7c580442007-10-27 17:54:30 +0000575 /* Signaling NaN: flags are undefined */
aurel32af129062008-11-19 16:10:23 +0000576 ret = 0x00;
j_mayer7c580442007-10-27 17:54:30 +0000577 } else {
578 /* Quiet NaN */
aurel32af129062008-11-19 16:10:23 +0000579 ret = 0x11;
j_mayer7c580442007-10-27 17:54:30 +0000580 }
aurel32f23c3462008-12-15 17:14:27 +0000581 } else if (unlikely(float64_is_infinity(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +0000582 /* +/- infinity */
583 if (isneg)
aurel32af129062008-11-19 16:10:23 +0000584 ret = 0x09;
j_mayer7c580442007-10-27 17:54:30 +0000585 else
aurel32af129062008-11-19 16:10:23 +0000586 ret = 0x05;
j_mayer7c580442007-10-27 17:54:30 +0000587 } else {
aurel32f23c3462008-12-15 17:14:27 +0000588 if (float64_is_zero(farg.d)) {
j_mayer7c580442007-10-27 17:54:30 +0000589 /* +/- zero */
590 if (isneg)
aurel32af129062008-11-19 16:10:23 +0000591 ret = 0x12;
j_mayer7c580442007-10-27 17:54:30 +0000592 else
aurel32af129062008-11-19 16:10:23 +0000593 ret = 0x02;
j_mayer7c580442007-10-27 17:54:30 +0000594 } else {
aurel32af129062008-11-19 16:10:23 +0000595 if (isden(farg.d)) {
j_mayer7c580442007-10-27 17:54:30 +0000596 /* Denormalized numbers */
aurel32af129062008-11-19 16:10:23 +0000597 ret = 0x10;
j_mayer7c580442007-10-27 17:54:30 +0000598 } else {
599 /* Normalized numbers */
aurel32af129062008-11-19 16:10:23 +0000600 ret = 0x00;
j_mayer7c580442007-10-27 17:54:30 +0000601 }
602 if (isneg) {
aurel32af129062008-11-19 16:10:23 +0000603 ret |= 0x08;
j_mayer7c580442007-10-27 17:54:30 +0000604 } else {
aurel32af129062008-11-19 16:10:23 +0000605 ret |= 0x04;
j_mayer7c580442007-10-27 17:54:30 +0000606 }
607 }
608 }
609 if (set_fprf) {
610 /* We update FPSCR_FPRF */
611 env->fpscr &= ~(0x1F << FPSCR_FPRF);
aurel32af129062008-11-19 16:10:23 +0000612 env->fpscr |= ret << FPSCR_FPRF;
j_mayer7c580442007-10-27 17:54:30 +0000613 }
614 /* We just need fpcc to update Rc1 */
aurel32af129062008-11-19 16:10:23 +0000615 return ret & 0xF;
j_mayer7c580442007-10-27 17:54:30 +0000616}
617
618/* Floating-point invalid operations exception */
aurel32af129062008-11-19 16:10:23 +0000619static always_inline uint64_t fload_invalid_op_excp (int op)
j_mayer7c580442007-10-27 17:54:30 +0000620{
aurel32af129062008-11-19 16:10:23 +0000621 uint64_t ret = 0;
j_mayer7c580442007-10-27 17:54:30 +0000622 int ve;
623
624 ve = fpscr_ve;
aurel32e0147e42008-12-15 17:13:55 +0000625 switch (op) {
626 case POWERPC_EXCP_FP_VXSNAN:
j_mayer7c580442007-10-27 17:54:30 +0000627 env->fpscr |= 1 << FPSCR_VXSNAN;
aurel32e0147e42008-12-15 17:13:55 +0000628 break;
629 case POWERPC_EXCP_FP_VXSOFT:
j_mayer7c580442007-10-27 17:54:30 +0000630 env->fpscr |= 1 << FPSCR_VXSOFT;
aurel32e0147e42008-12-15 17:13:55 +0000631 break;
j_mayer7c580442007-10-27 17:54:30 +0000632 case POWERPC_EXCP_FP_VXISI:
633 /* Magnitude subtraction of infinities */
634 env->fpscr |= 1 << FPSCR_VXISI;
635 goto update_arith;
636 case POWERPC_EXCP_FP_VXIDI:
637 /* Division of infinity by infinity */
638 env->fpscr |= 1 << FPSCR_VXIDI;
639 goto update_arith;
640 case POWERPC_EXCP_FP_VXZDZ:
641 /* Division of zero by zero */
642 env->fpscr |= 1 << FPSCR_VXZDZ;
643 goto update_arith;
644 case POWERPC_EXCP_FP_VXIMZ:
645 /* Multiplication of zero by infinity */
646 env->fpscr |= 1 << FPSCR_VXIMZ;
647 goto update_arith;
648 case POWERPC_EXCP_FP_VXVC:
649 /* Ordered comparison of NaN */
650 env->fpscr |= 1 << FPSCR_VXVC;
651 env->fpscr &= ~(0xF << FPSCR_FPCC);
652 env->fpscr |= 0x11 << FPSCR_FPCC;
653 /* We must update the target FPR before raising the exception */
654 if (ve != 0) {
655 env->exception_index = POWERPC_EXCP_PROGRAM;
656 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
657 /* Update the floating-point enabled exception summary */
658 env->fpscr |= 1 << FPSCR_FEX;
659 /* Exception is differed */
660 ve = 0;
661 }
662 break;
663 case POWERPC_EXCP_FP_VXSQRT:
664 /* Square root of a negative number */
665 env->fpscr |= 1 << FPSCR_VXSQRT;
666 update_arith:
667 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
668 if (ve == 0) {
669 /* Set the result to quiet NaN */
aurel32e0147e42008-12-15 17:13:55 +0000670 ret = 0xFFF8000000000000ULL;
j_mayer7c580442007-10-27 17:54:30 +0000671 env->fpscr &= ~(0xF << FPSCR_FPCC);
672 env->fpscr |= 0x11 << FPSCR_FPCC;
673 }
674 break;
675 case POWERPC_EXCP_FP_VXCVI:
676 /* Invalid conversion */
677 env->fpscr |= 1 << FPSCR_VXCVI;
678 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
679 if (ve == 0) {
680 /* Set the result to quiet NaN */
aurel32e0147e42008-12-15 17:13:55 +0000681 ret = 0xFFF8000000000000ULL;
j_mayer7c580442007-10-27 17:54:30 +0000682 env->fpscr &= ~(0xF << FPSCR_FPCC);
683 env->fpscr |= 0x11 << FPSCR_FPCC;
684 }
685 break;
686 }
687 /* Update the floating-point invalid operation summary */
688 env->fpscr |= 1 << FPSCR_VX;
689 /* Update the floating-point exception summary */
690 env->fpscr |= 1 << FPSCR_FX;
691 if (ve != 0) {
692 /* Update the floating-point enabled exception summary */
693 env->fpscr |= 1 << FPSCR_FEX;
694 if (msr_fe0 != 0 || msr_fe1 != 0)
aurel32e06fcd72008-12-11 22:42:14 +0000695 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
j_mayer7c580442007-10-27 17:54:30 +0000696 }
aurel32af129062008-11-19 16:10:23 +0000697 return ret;
j_mayer7c580442007-10-27 17:54:30 +0000698}
699
aurel32e33e94f2008-12-18 22:44:21 +0000700static always_inline void float_zero_divide_excp (void)
j_mayer7c580442007-10-27 17:54:30 +0000701{
j_mayer7c580442007-10-27 17:54:30 +0000702 env->fpscr |= 1 << FPSCR_ZX;
703 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
704 /* Update the floating-point exception summary */
705 env->fpscr |= 1 << FPSCR_FX;
706 if (fpscr_ze != 0) {
707 /* Update the floating-point enabled exception summary */
708 env->fpscr |= 1 << FPSCR_FEX;
709 if (msr_fe0 != 0 || msr_fe1 != 0) {
aurel32e06fcd72008-12-11 22:42:14 +0000710 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
711 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
j_mayer7c580442007-10-27 17:54:30 +0000712 }
j_mayer7c580442007-10-27 17:54:30 +0000713 }
714}
715
716static always_inline void float_overflow_excp (void)
717{
718 env->fpscr |= 1 << FPSCR_OX;
719 /* Update the floating-point exception summary */
720 env->fpscr |= 1 << FPSCR_FX;
721 if (fpscr_oe != 0) {
722 /* XXX: should adjust the result */
723 /* Update the floating-point enabled exception summary */
724 env->fpscr |= 1 << FPSCR_FEX;
725 /* We must update the target FPR before raising the exception */
726 env->exception_index = POWERPC_EXCP_PROGRAM;
727 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
728 } else {
729 env->fpscr |= 1 << FPSCR_XX;
730 env->fpscr |= 1 << FPSCR_FI;
731 }
732}
733
734static always_inline void float_underflow_excp (void)
735{
736 env->fpscr |= 1 << FPSCR_UX;
737 /* Update the floating-point exception summary */
738 env->fpscr |= 1 << FPSCR_FX;
739 if (fpscr_ue != 0) {
740 /* XXX: should adjust the result */
741 /* Update the floating-point enabled exception summary */
742 env->fpscr |= 1 << FPSCR_FEX;
743 /* We must update the target FPR before raising the exception */
744 env->exception_index = POWERPC_EXCP_PROGRAM;
745 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
746 }
747}
748
749static always_inline void float_inexact_excp (void)
750{
751 env->fpscr |= 1 << FPSCR_XX;
752 /* Update the floating-point exception summary */
753 env->fpscr |= 1 << FPSCR_FX;
754 if (fpscr_xe != 0) {
755 /* Update the floating-point enabled exception summary */
756 env->fpscr |= 1 << FPSCR_FEX;
757 /* We must update the target FPR before raising the exception */
758 env->exception_index = POWERPC_EXCP_PROGRAM;
759 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
760 }
761}
762
763static always_inline void fpscr_set_rounding_mode (void)
764{
765 int rnd_type;
766
767 /* Set rounding mode */
768 switch (fpscr_rn) {
769 case 0:
770 /* Best approximation (round to nearest) */
771 rnd_type = float_round_nearest_even;
772 break;
773 case 1:
774 /* Smaller magnitude (round toward zero) */
775 rnd_type = float_round_to_zero;
776 break;
777 case 2:
778 /* Round toward +infinite */
779 rnd_type = float_round_up;
780 break;
781 default:
782 case 3:
783 /* Round toward -infinite */
784 rnd_type = float_round_down;
785 break;
786 }
787 set_float_rounding_mode(rnd_type, &env->fp_status);
788}
789
aurel326e35d522008-12-14 18:40:58 +0000790void helper_fpscr_clrbit (uint32_t bit)
791{
792 int prev;
793
794 prev = (env->fpscr >> bit) & 1;
795 env->fpscr &= ~(1 << bit);
796 if (prev == 1) {
797 switch (bit) {
798 case FPSCR_RN1:
799 case FPSCR_RN:
800 fpscr_set_rounding_mode();
801 break;
802 default:
803 break;
804 }
805 }
806}
807
aurel32af129062008-11-19 16:10:23 +0000808void helper_fpscr_setbit (uint32_t bit)
j_mayer7c580442007-10-27 17:54:30 +0000809{
810 int prev;
811
812 prev = (env->fpscr >> bit) & 1;
813 env->fpscr |= 1 << bit;
814 if (prev == 0) {
815 switch (bit) {
816 case FPSCR_VX:
817 env->fpscr |= 1 << FPSCR_FX;
818 if (fpscr_ve)
819 goto raise_ve;
820 case FPSCR_OX:
821 env->fpscr |= 1 << FPSCR_FX;
822 if (fpscr_oe)
823 goto raise_oe;
824 break;
825 case FPSCR_UX:
826 env->fpscr |= 1 << FPSCR_FX;
827 if (fpscr_ue)
828 goto raise_ue;
829 break;
830 case FPSCR_ZX:
831 env->fpscr |= 1 << FPSCR_FX;
832 if (fpscr_ze)
833 goto raise_ze;
834 break;
835 case FPSCR_XX:
836 env->fpscr |= 1 << FPSCR_FX;
837 if (fpscr_xe)
838 goto raise_xe;
839 break;
840 case FPSCR_VXSNAN:
841 case FPSCR_VXISI:
842 case FPSCR_VXIDI:
843 case FPSCR_VXZDZ:
844 case FPSCR_VXIMZ:
845 case FPSCR_VXVC:
846 case FPSCR_VXSOFT:
847 case FPSCR_VXSQRT:
848 case FPSCR_VXCVI:
849 env->fpscr |= 1 << FPSCR_VX;
850 env->fpscr |= 1 << FPSCR_FX;
851 if (fpscr_ve != 0)
852 goto raise_ve;
853 break;
854 case FPSCR_VE:
855 if (fpscr_vx != 0) {
856 raise_ve:
857 env->error_code = POWERPC_EXCP_FP;
858 if (fpscr_vxsnan)
859 env->error_code |= POWERPC_EXCP_FP_VXSNAN;
860 if (fpscr_vxisi)
861 env->error_code |= POWERPC_EXCP_FP_VXISI;
862 if (fpscr_vxidi)
863 env->error_code |= POWERPC_EXCP_FP_VXIDI;
864 if (fpscr_vxzdz)
865 env->error_code |= POWERPC_EXCP_FP_VXZDZ;
866 if (fpscr_vximz)
867 env->error_code |= POWERPC_EXCP_FP_VXIMZ;
868 if (fpscr_vxvc)
869 env->error_code |= POWERPC_EXCP_FP_VXVC;
870 if (fpscr_vxsoft)
871 env->error_code |= POWERPC_EXCP_FP_VXSOFT;
872 if (fpscr_vxsqrt)
873 env->error_code |= POWERPC_EXCP_FP_VXSQRT;
874 if (fpscr_vxcvi)
875 env->error_code |= POWERPC_EXCP_FP_VXCVI;
876 goto raise_excp;
877 }
878 break;
879 case FPSCR_OE:
880 if (fpscr_ox != 0) {
881 raise_oe:
882 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
883 goto raise_excp;
884 }
885 break;
886 case FPSCR_UE:
887 if (fpscr_ux != 0) {
888 raise_ue:
889 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
890 goto raise_excp;
891 }
892 break;
893 case FPSCR_ZE:
894 if (fpscr_zx != 0) {
895 raise_ze:
896 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
897 goto raise_excp;
898 }
899 break;
900 case FPSCR_XE:
901 if (fpscr_xx != 0) {
902 raise_xe:
903 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
904 goto raise_excp;
905 }
906 break;
907 case FPSCR_RN1:
908 case FPSCR_RN:
909 fpscr_set_rounding_mode();
910 break;
911 default:
912 break;
913 raise_excp:
914 /* Update the floating-point enabled exception summary */
915 env->fpscr |= 1 << FPSCR_FEX;
916 /* We have to update Rc1 before raising the exception */
917 env->exception_index = POWERPC_EXCP_PROGRAM;
918 break;
919 }
920 }
921}
922
aurel32af129062008-11-19 16:10:23 +0000923void helper_store_fpscr (uint64_t arg, uint32_t mask)
j_mayer7c580442007-10-27 17:54:30 +0000924{
925 /*
926 * We use only the 32 LSB of the incoming fpr
927 */
j_mayer7c580442007-10-27 17:54:30 +0000928 uint32_t prev, new;
929 int i;
930
j_mayer7c580442007-10-27 17:54:30 +0000931 prev = env->fpscr;
aurel32af129062008-11-19 16:10:23 +0000932 new = (uint32_t)arg;
aurel3227ee5df2008-12-15 00:30:28 +0000933 new &= ~0x60000000;
934 new |= prev & 0x60000000;
935 for (i = 0; i < 8; i++) {
j_mayer7c580442007-10-27 17:54:30 +0000936 if (mask & (1 << i)) {
937 env->fpscr &= ~(0xF << (4 * i));
938 env->fpscr |= new & (0xF << (4 * i));
939 }
940 }
941 /* Update VX and FEX */
942 if (fpscr_ix != 0)
943 env->fpscr |= 1 << FPSCR_VX;
aurel3255670252008-03-10 00:09:28 +0000944 else
945 env->fpscr &= ~(1 << FPSCR_VX);
j_mayer7c580442007-10-27 17:54:30 +0000946 if ((fpscr_ex & fpscr_eex) != 0) {
947 env->fpscr |= 1 << FPSCR_FEX;
948 env->exception_index = POWERPC_EXCP_PROGRAM;
949 /* XXX: we should compute it properly */
950 env->error_code = POWERPC_EXCP_FP;
951 }
aurel3255670252008-03-10 00:09:28 +0000952 else
953 env->fpscr &= ~(1 << FPSCR_FEX);
j_mayer7c580442007-10-27 17:54:30 +0000954 fpscr_set_rounding_mode();
955}
j_mayer7c580442007-10-27 17:54:30 +0000956
aurel32af129062008-11-19 16:10:23 +0000957void helper_float_check_status (void)
j_mayer7c580442007-10-27 17:54:30 +0000958{
aurel32af129062008-11-19 16:10:23 +0000959#ifdef CONFIG_SOFTFLOAT
j_mayer7c580442007-10-27 17:54:30 +0000960 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
961 (env->error_code & POWERPC_EXCP_FP)) {
962 /* Differred floating-point exception after target FPR update */
963 if (msr_fe0 != 0 || msr_fe1 != 0)
aurel32e06fcd72008-12-11 22:42:14 +0000964 helper_raise_exception_err(env->exception_index, env->error_code);
aurel32be94c952008-12-13 12:13:33 +0000965 } else {
966 int status = get_float_exception_flags(&env->fp_status);
aurel32e33e94f2008-12-18 22:44:21 +0000967 if (status & float_flag_divbyzero) {
968 float_zero_divide_excp();
969 } else if (status & float_flag_overflow) {
aurel32be94c952008-12-13 12:13:33 +0000970 float_overflow_excp();
971 } else if (status & float_flag_underflow) {
972 float_underflow_excp();
973 } else if (status & float_flag_inexact) {
974 float_inexact_excp();
975 }
j_mayer7c580442007-10-27 17:54:30 +0000976 }
aurel32af129062008-11-19 16:10:23 +0000977#else
978 if (env->exception_index == POWERPC_EXCP_PROGRAM &&
979 (env->error_code & POWERPC_EXCP_FP)) {
980 /* Differred floating-point exception after target FPR update */
981 if (msr_fe0 != 0 || msr_fe1 != 0)
aurel32e06fcd72008-12-11 22:42:14 +0000982 helper_raise_exception_err(env->exception_index, env->error_code);
aurel32af129062008-11-19 16:10:23 +0000983 }
aurel32af129062008-11-19 16:10:23 +0000984#endif
985}
986
987#ifdef CONFIG_SOFTFLOAT
988void helper_reset_fpstatus (void)
989{
aurel32be94c952008-12-13 12:13:33 +0000990 set_float_exception_flags(0, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +0000991}
992#endif
993
aurel32af129062008-11-19 16:10:23 +0000994/* fadd - fadd. */
995uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
996{
997 CPU_DoubleU farg1, farg2;
998
999 farg1.ll = arg1;
1000 farg2.ll = arg2;
aurel321cdb9c32008-04-07 21:24:25 +00001001#if USE_PRECISE_EMULATION
aurel32af129062008-11-19 16:10:23 +00001002 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1003 float64_is_signaling_nan(farg2.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001004 /* sNaN addition */
aurel32af129062008-11-19 16:10:23 +00001005 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel3217218d12008-12-15 17:14:35 +00001006 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
1007 float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001008 /* Magnitude subtraction of infinities */
aurel32cf1cf212008-12-13 11:46:36 +00001009 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
aurel3217218d12008-12-15 17:14:35 +00001010 } else {
1011 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001012 }
aurel32af129062008-11-19 16:10:23 +00001013#else
1014 farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
1015#endif
1016 return farg1.ll;
j_mayer7c580442007-10-27 17:54:30 +00001017}
1018
aurel32af129062008-11-19 16:10:23 +00001019/* fsub - fsub. */
1020uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
j_mayer7c580442007-10-27 17:54:30 +00001021{
aurel32af129062008-11-19 16:10:23 +00001022 CPU_DoubleU farg1, farg2;
1023
1024 farg1.ll = arg1;
1025 farg2.ll = arg2;
1026#if USE_PRECISE_EMULATION
1027{
1028 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1029 float64_is_signaling_nan(farg2.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001030 /* sNaN subtraction */
aurel32af129062008-11-19 16:10:23 +00001031 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel3217218d12008-12-15 17:14:35 +00001032 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
1033 float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001034 /* Magnitude subtraction of infinities */
aurel32af129062008-11-19 16:10:23 +00001035 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
aurel3217218d12008-12-15 17:14:35 +00001036 } else {
1037 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001038 }
1039}
aurel32af129062008-11-19 16:10:23 +00001040#else
1041 farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
1042#endif
1043 return farg1.ll;
1044}
j_mayer7c580442007-10-27 17:54:30 +00001045
aurel32af129062008-11-19 16:10:23 +00001046/* fmul - fmul. */
1047uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
j_mayer7c580442007-10-27 17:54:30 +00001048{
aurel32af129062008-11-19 16:10:23 +00001049 CPU_DoubleU farg1, farg2;
1050
1051 farg1.ll = arg1;
1052 farg2.ll = arg2;
1053#if USE_PRECISE_EMULATION
1054 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1055 float64_is_signaling_nan(farg2.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001056 /* sNaN multiplication */
aurel32af129062008-11-19 16:10:23 +00001057 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32f23c3462008-12-15 17:14:27 +00001058 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1059 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
j_mayer7c580442007-10-27 17:54:30 +00001060 /* Multiplication of zero by infinity */
aurel32af129062008-11-19 16:10:23 +00001061 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
j_mayer7c580442007-10-27 17:54:30 +00001062 } else {
aurel32af129062008-11-19 16:10:23 +00001063 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001064 }
aurel32af129062008-11-19 16:10:23 +00001065#else
1066 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1067#endif
1068 return farg1.ll;
1069}
j_mayer7c580442007-10-27 17:54:30 +00001070
aurel32af129062008-11-19 16:10:23 +00001071/* fdiv - fdiv. */
1072uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
j_mayer7c580442007-10-27 17:54:30 +00001073{
aurel32af129062008-11-19 16:10:23 +00001074 CPU_DoubleU farg1, farg2;
1075
1076 farg1.ll = arg1;
1077 farg2.ll = arg2;
1078#if USE_PRECISE_EMULATION
1079 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1080 float64_is_signaling_nan(farg2.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001081 /* sNaN division */
aurel32af129062008-11-19 16:10:23 +00001082 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32f23c3462008-12-15 17:14:27 +00001083 } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001084 /* Division of infinity by infinity */
aurel32af129062008-11-19 16:10:23 +00001085 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
aurel32e33e94f2008-12-18 22:44:21 +00001086 } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) {
1087 /* Division of zero by zero */
1088 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
j_mayer7c580442007-10-27 17:54:30 +00001089 } else {
aurel32af129062008-11-19 16:10:23 +00001090 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001091 }
aurel32af129062008-11-19 16:10:23 +00001092#else
1093 farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
1094#endif
1095 return farg1.ll;
j_mayer7c580442007-10-27 17:54:30 +00001096}
j_mayer7c580442007-10-27 17:54:30 +00001097
aurel32af129062008-11-19 16:10:23 +00001098/* fabs */
1099uint64_t helper_fabs (uint64_t arg)
bellard9a64fbe2004-01-04 22:58:38 +00001100{
aurel32af129062008-11-19 16:10:23 +00001101 CPU_DoubleU farg;
bellard9a64fbe2004-01-04 22:58:38 +00001102
aurel32af129062008-11-19 16:10:23 +00001103 farg.ll = arg;
1104 farg.d = float64_abs(farg.d);
1105 return farg.ll;
1106}
1107
1108/* fnabs */
1109uint64_t helper_fnabs (uint64_t arg)
1110{
1111 CPU_DoubleU farg;
1112
1113 farg.ll = arg;
1114 farg.d = float64_abs(farg.d);
1115 farg.d = float64_chs(farg.d);
1116 return farg.ll;
1117}
1118
1119/* fneg */
1120uint64_t helper_fneg (uint64_t arg)
1121{
1122 CPU_DoubleU farg;
1123
1124 farg.ll = arg;
1125 farg.d = float64_chs(farg.d);
1126 return farg.ll;
1127}
1128
1129/* fctiw - fctiw. */
1130uint64_t helper_fctiw (uint64_t arg)
1131{
1132 CPU_DoubleU farg;
1133 farg.ll = arg;
1134
1135 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001136 /* sNaN conversion */
aurel32af129062008-11-19 16:10:23 +00001137 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
aurel32f23c3462008-12-15 17:14:27 +00001138 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001139 /* qNan / infinity conversion */
aurel32af129062008-11-19 16:10:23 +00001140 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
j_mayer7c580442007-10-27 17:54:30 +00001141 } else {
aurel32af129062008-11-19 16:10:23 +00001142 farg.ll = float64_to_int32(farg.d, &env->fp_status);
aurel321cdb9c32008-04-07 21:24:25 +00001143#if USE_PRECISE_EMULATION
j_mayer7c580442007-10-27 17:54:30 +00001144 /* XXX: higher bits are not supposed to be significant.
1145 * to make tests easier, return the same as a real PowerPC 750
1146 */
aurel32af129062008-11-19 16:10:23 +00001147 farg.ll |= 0xFFF80000ULL << 32;
j_mayere864cab2007-03-22 22:17:08 +00001148#endif
j_mayer7c580442007-10-27 17:54:30 +00001149 }
aurel32af129062008-11-19 16:10:23 +00001150 return farg.ll;
bellard9a64fbe2004-01-04 22:58:38 +00001151}
1152
aurel32af129062008-11-19 16:10:23 +00001153/* fctiwz - fctiwz. */
1154uint64_t helper_fctiwz (uint64_t arg)
bellard9a64fbe2004-01-04 22:58:38 +00001155{
aurel32af129062008-11-19 16:10:23 +00001156 CPU_DoubleU farg;
1157 farg.ll = arg;
bellard9a64fbe2004-01-04 22:58:38 +00001158
aurel32af129062008-11-19 16:10:23 +00001159 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001160 /* sNaN conversion */
aurel32af129062008-11-19 16:10:23 +00001161 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
aurel32f23c3462008-12-15 17:14:27 +00001162 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001163 /* qNan / infinity conversion */
aurel32af129062008-11-19 16:10:23 +00001164 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
j_mayer7c580442007-10-27 17:54:30 +00001165 } else {
aurel32af129062008-11-19 16:10:23 +00001166 farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
aurel321cdb9c32008-04-07 21:24:25 +00001167#if USE_PRECISE_EMULATION
j_mayer7c580442007-10-27 17:54:30 +00001168 /* XXX: higher bits are not supposed to be significant.
1169 * to make tests easier, return the same as a real PowerPC 750
1170 */
aurel32af129062008-11-19 16:10:23 +00001171 farg.ll |= 0xFFF80000ULL << 32;
j_mayere864cab2007-03-22 22:17:08 +00001172#endif
j_mayer7c580442007-10-27 17:54:30 +00001173 }
aurel32af129062008-11-19 16:10:23 +00001174 return farg.ll;
bellard9a64fbe2004-01-04 22:58:38 +00001175}
1176
j_mayer426613d2007-03-23 09:45:27 +00001177#if defined(TARGET_PPC64)
aurel32af129062008-11-19 16:10:23 +00001178/* fcfid - fcfid. */
1179uint64_t helper_fcfid (uint64_t arg)
j_mayer426613d2007-03-23 09:45:27 +00001180{
aurel32af129062008-11-19 16:10:23 +00001181 CPU_DoubleU farg;
1182 farg.d = int64_to_float64(arg, &env->fp_status);
1183 return farg.ll;
j_mayer426613d2007-03-23 09:45:27 +00001184}
1185
aurel32af129062008-11-19 16:10:23 +00001186/* fctid - fctid. */
1187uint64_t helper_fctid (uint64_t arg)
j_mayer426613d2007-03-23 09:45:27 +00001188{
aurel32af129062008-11-19 16:10:23 +00001189 CPU_DoubleU farg;
1190 farg.ll = arg;
j_mayer426613d2007-03-23 09:45:27 +00001191
aurel32af129062008-11-19 16:10:23 +00001192 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001193 /* sNaN conversion */
aurel32af129062008-11-19 16:10:23 +00001194 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
aurel32f23c3462008-12-15 17:14:27 +00001195 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001196 /* qNan / infinity conversion */
aurel32af129062008-11-19 16:10:23 +00001197 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
j_mayer7c580442007-10-27 17:54:30 +00001198 } else {
aurel32af129062008-11-19 16:10:23 +00001199 farg.ll = float64_to_int64(farg.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001200 }
aurel32af129062008-11-19 16:10:23 +00001201 return farg.ll;
j_mayer426613d2007-03-23 09:45:27 +00001202}
1203
aurel32af129062008-11-19 16:10:23 +00001204/* fctidz - fctidz. */
1205uint64_t helper_fctidz (uint64_t arg)
j_mayer426613d2007-03-23 09:45:27 +00001206{
aurel32af129062008-11-19 16:10:23 +00001207 CPU_DoubleU farg;
1208 farg.ll = arg;
j_mayer426613d2007-03-23 09:45:27 +00001209
aurel32af129062008-11-19 16:10:23 +00001210 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001211 /* sNaN conversion */
aurel32af129062008-11-19 16:10:23 +00001212 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
aurel32f23c3462008-12-15 17:14:27 +00001213 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001214 /* qNan / infinity conversion */
aurel32af129062008-11-19 16:10:23 +00001215 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
j_mayer7c580442007-10-27 17:54:30 +00001216 } else {
aurel32af129062008-11-19 16:10:23 +00001217 farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001218 }
aurel32af129062008-11-19 16:10:23 +00001219 return farg.ll;
j_mayer426613d2007-03-23 09:45:27 +00001220}
1221
1222#endif
1223
aurel32af129062008-11-19 16:10:23 +00001224static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
j_mayerd7e4b872007-09-30 01:11:48 +00001225{
aurel32af129062008-11-19 16:10:23 +00001226 CPU_DoubleU farg;
1227 farg.ll = arg;
1228
1229 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001230 /* sNaN round */
aurel32af129062008-11-19 16:10:23 +00001231 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
aurel32f23c3462008-12-15 17:14:27 +00001232 } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001233 /* qNan / infinity round */
aurel32af129062008-11-19 16:10:23 +00001234 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
j_mayer7c580442007-10-27 17:54:30 +00001235 } else {
1236 set_float_rounding_mode(rounding_mode, &env->fp_status);
aurel32af129062008-11-19 16:10:23 +00001237 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001238 /* Restore rounding mode from FPSCR */
1239 fpscr_set_rounding_mode();
1240 }
aurel32af129062008-11-19 16:10:23 +00001241 return farg.ll;
j_mayerd7e4b872007-09-30 01:11:48 +00001242}
1243
aurel32af129062008-11-19 16:10:23 +00001244uint64_t helper_frin (uint64_t arg)
j_mayerd7e4b872007-09-30 01:11:48 +00001245{
aurel32af129062008-11-19 16:10:23 +00001246 return do_fri(arg, float_round_nearest_even);
j_mayerd7e4b872007-09-30 01:11:48 +00001247}
1248
aurel32af129062008-11-19 16:10:23 +00001249uint64_t helper_friz (uint64_t arg)
j_mayerd7e4b872007-09-30 01:11:48 +00001250{
aurel32af129062008-11-19 16:10:23 +00001251 return do_fri(arg, float_round_to_zero);
j_mayerd7e4b872007-09-30 01:11:48 +00001252}
1253
aurel32af129062008-11-19 16:10:23 +00001254uint64_t helper_frip (uint64_t arg)
j_mayerd7e4b872007-09-30 01:11:48 +00001255{
aurel32af129062008-11-19 16:10:23 +00001256 return do_fri(arg, float_round_up);
j_mayerd7e4b872007-09-30 01:11:48 +00001257}
1258
aurel32af129062008-11-19 16:10:23 +00001259uint64_t helper_frim (uint64_t arg)
j_mayerd7e4b872007-09-30 01:11:48 +00001260{
aurel32af129062008-11-19 16:10:23 +00001261 return do_fri(arg, float_round_down);
j_mayerd7e4b872007-09-30 01:11:48 +00001262}
1263
aurel32af129062008-11-19 16:10:23 +00001264/* fmadd - fmadd. */
1265uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
1266{
1267 CPU_DoubleU farg1, farg2, farg3;
1268
1269 farg1.ll = arg1;
1270 farg2.ll = arg2;
1271 farg3.ll = arg3;
aurel321cdb9c32008-04-07 21:24:25 +00001272#if USE_PRECISE_EMULATION
aurel32af129062008-11-19 16:10:23 +00001273 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1274 float64_is_signaling_nan(farg2.d) ||
1275 float64_is_signaling_nan(farg3.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001276 /* sNaN operation */
aurel32af129062008-11-19 16:10:23 +00001277 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32da1e7ac2008-12-15 17:14:43 +00001278 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1279 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1280 /* Multiplication of zero by infinity */
1281 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
j_mayer7c580442007-10-27 17:54:30 +00001282 } else {
j_mayere864cab2007-03-22 22:17:08 +00001283#ifdef FLOAT128
j_mayer7c580442007-10-27 17:54:30 +00001284 /* This is the way the PowerPC specification defines it */
1285 float128 ft0_128, ft1_128;
j_mayere864cab2007-03-22 22:17:08 +00001286
aurel32af129062008-11-19 16:10:23 +00001287 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1288 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001289 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
aurel32da1e7ac2008-12-15 17:14:43 +00001290 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1291 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
1292 /* Magnitude subtraction of infinities */
1293 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1294 } else {
1295 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1296 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1297 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1298 }
j_mayere864cab2007-03-22 22:17:08 +00001299#else
j_mayer7c580442007-10-27 17:54:30 +00001300 /* This is OK on x86 hosts */
aurel32af129062008-11-19 16:10:23 +00001301 farg1.d = (farg1.d * farg2.d) + farg3.d;
j_mayere864cab2007-03-22 22:17:08 +00001302#endif
j_mayer7c580442007-10-27 17:54:30 +00001303 }
aurel32af129062008-11-19 16:10:23 +00001304#else
1305 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1306 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
1307#endif
1308 return farg1.ll;
j_mayere864cab2007-03-22 22:17:08 +00001309}
1310
aurel32af129062008-11-19 16:10:23 +00001311/* fmsub - fmsub. */
1312uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
j_mayere864cab2007-03-22 22:17:08 +00001313{
aurel32af129062008-11-19 16:10:23 +00001314 CPU_DoubleU farg1, farg2, farg3;
1315
1316 farg1.ll = arg1;
1317 farg2.ll = arg2;
1318 farg3.ll = arg3;
1319#if USE_PRECISE_EMULATION
1320 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1321 float64_is_signaling_nan(farg2.d) ||
1322 float64_is_signaling_nan(farg3.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001323 /* sNaN operation */
aurel32af129062008-11-19 16:10:23 +00001324 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32da1e7ac2008-12-15 17:14:43 +00001325 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1326 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1327 /* Multiplication of zero by infinity */
1328 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
j_mayer7c580442007-10-27 17:54:30 +00001329 } else {
j_mayere864cab2007-03-22 22:17:08 +00001330#ifdef FLOAT128
j_mayer7c580442007-10-27 17:54:30 +00001331 /* This is the way the PowerPC specification defines it */
1332 float128 ft0_128, ft1_128;
j_mayere864cab2007-03-22 22:17:08 +00001333
aurel32af129062008-11-19 16:10:23 +00001334 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1335 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001336 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
aurel32da1e7ac2008-12-15 17:14:43 +00001337 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1338 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
1339 /* Magnitude subtraction of infinities */
1340 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1341 } else {
1342 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1343 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1344 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1345 }
j_mayere864cab2007-03-22 22:17:08 +00001346#else
j_mayer7c580442007-10-27 17:54:30 +00001347 /* This is OK on x86 hosts */
aurel32af129062008-11-19 16:10:23 +00001348 farg1.d = (farg1.d * farg2.d) - farg3.d;
j_mayere864cab2007-03-22 22:17:08 +00001349#endif
j_mayer7c580442007-10-27 17:54:30 +00001350 }
aurel32af129062008-11-19 16:10:23 +00001351#else
1352 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1353 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
1354#endif
1355 return farg1.ll;
j_mayere864cab2007-03-22 22:17:08 +00001356}
j_mayere864cab2007-03-22 22:17:08 +00001357
aurel32af129062008-11-19 16:10:23 +00001358/* fnmadd - fnmadd. */
1359uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
bellard4b3686f2004-05-23 22:18:12 +00001360{
aurel32af129062008-11-19 16:10:23 +00001361 CPU_DoubleU farg1, farg2, farg3;
1362
1363 farg1.ll = arg1;
1364 farg2.ll = arg2;
1365 farg3.ll = arg3;
1366
1367 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1368 float64_is_signaling_nan(farg2.d) ||
1369 float64_is_signaling_nan(farg3.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001370 /* sNaN operation */
aurel32af129062008-11-19 16:10:23 +00001371 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32da1e7ac2008-12-15 17:14:43 +00001372 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1373 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1374 /* Multiplication of zero by infinity */
1375 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
j_mayer7c580442007-10-27 17:54:30 +00001376 } else {
aurel321cdb9c32008-04-07 21:24:25 +00001377#if USE_PRECISE_EMULATION
j_mayere864cab2007-03-22 22:17:08 +00001378#ifdef FLOAT128
j_mayer7c580442007-10-27 17:54:30 +00001379 /* This is the way the PowerPC specification defines it */
1380 float128 ft0_128, ft1_128;
j_mayere864cab2007-03-22 22:17:08 +00001381
aurel32af129062008-11-19 16:10:23 +00001382 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1383 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001384 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
aurel32da1e7ac2008-12-15 17:14:43 +00001385 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1386 float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
1387 /* Magnitude subtraction of infinities */
1388 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1389 } else {
1390 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1391 ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
1392 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1393 }
j_mayere864cab2007-03-22 22:17:08 +00001394#else
j_mayer7c580442007-10-27 17:54:30 +00001395 /* This is OK on x86 hosts */
aurel32af129062008-11-19 16:10:23 +00001396 farg1.d = (farg1.d * farg2.d) + farg3.d;
j_mayere864cab2007-03-22 22:17:08 +00001397#endif
1398#else
aurel32af129062008-11-19 16:10:23 +00001399 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1400 farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
j_mayere864cab2007-03-22 22:17:08 +00001401#endif
aurel32a44d2ce2008-12-13 11:46:27 +00001402 if (likely(!float64_is_nan(farg1.d)))
aurel32af129062008-11-19 16:10:23 +00001403 farg1.d = float64_chs(farg1.d);
j_mayer7c580442007-10-27 17:54:30 +00001404 }
aurel32af129062008-11-19 16:10:23 +00001405 return farg1.ll;
bellard4b3686f2004-05-23 22:18:12 +00001406}
1407
aurel32af129062008-11-19 16:10:23 +00001408/* fnmsub - fnmsub. */
1409uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
bellard4b3686f2004-05-23 22:18:12 +00001410{
aurel32af129062008-11-19 16:10:23 +00001411 CPU_DoubleU farg1, farg2, farg3;
1412
1413 farg1.ll = arg1;
1414 farg2.ll = arg2;
1415 farg3.ll = arg3;
1416
1417 if (unlikely(float64_is_signaling_nan(farg1.d) ||
1418 float64_is_signaling_nan(farg2.d) ||
1419 float64_is_signaling_nan(farg3.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001420 /* sNaN operation */
aurel32af129062008-11-19 16:10:23 +00001421 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32da1e7ac2008-12-15 17:14:43 +00001422 } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
1423 (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
1424 /* Multiplication of zero by infinity */
1425 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
j_mayer7c580442007-10-27 17:54:30 +00001426 } else {
aurel321cdb9c32008-04-07 21:24:25 +00001427#if USE_PRECISE_EMULATION
j_mayere864cab2007-03-22 22:17:08 +00001428#ifdef FLOAT128
j_mayer7c580442007-10-27 17:54:30 +00001429 /* This is the way the PowerPC specification defines it */
1430 float128 ft0_128, ft1_128;
j_mayere864cab2007-03-22 22:17:08 +00001431
aurel32af129062008-11-19 16:10:23 +00001432 ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
1433 ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001434 ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
aurel32da1e7ac2008-12-15 17:14:43 +00001435 if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
1436 float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
1437 /* Magnitude subtraction of infinities */
1438 farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
1439 } else {
1440 ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
1441 ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
1442 farg1.d = float128_to_float64(ft0_128, &env->fp_status);
1443 }
j_mayere864cab2007-03-22 22:17:08 +00001444#else
j_mayer7c580442007-10-27 17:54:30 +00001445 /* This is OK on x86 hosts */
aurel32af129062008-11-19 16:10:23 +00001446 farg1.d = (farg1.d * farg2.d) - farg3.d;
j_mayere864cab2007-03-22 22:17:08 +00001447#endif
1448#else
aurel32af129062008-11-19 16:10:23 +00001449 farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
1450 farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
j_mayere864cab2007-03-22 22:17:08 +00001451#endif
aurel32a44d2ce2008-12-13 11:46:27 +00001452 if (likely(!float64_is_nan(farg1.d)))
aurel32af129062008-11-19 16:10:23 +00001453 farg1.d = float64_chs(farg1.d);
j_mayer7c580442007-10-27 17:54:30 +00001454 }
aurel32af129062008-11-19 16:10:23 +00001455 return farg1.ll;
bellard1ef59d02004-04-26 19:48:05 +00001456}
1457
aurel32af129062008-11-19 16:10:23 +00001458/* frsp - frsp. */
1459uint64_t helper_frsp (uint64_t arg)
1460{
1461 CPU_DoubleU farg;
aurel326ad193e2008-12-15 01:00:17 +00001462 float32 f32;
aurel32af129062008-11-19 16:10:23 +00001463 farg.ll = arg;
1464
aurel321cdb9c32008-04-07 21:24:25 +00001465#if USE_PRECISE_EMULATION
aurel32af129062008-11-19 16:10:23 +00001466 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001467 /* sNaN square root */
aurel32af129062008-11-19 16:10:23 +00001468 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
j_mayer7c580442007-10-27 17:54:30 +00001469 } else {
aurel326ad193e2008-12-15 01:00:17 +00001470 f32 = float64_to_float32(farg.d, &env->fp_status);
1471 farg.d = float32_to_float64(f32, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001472 }
aurel32af129062008-11-19 16:10:23 +00001473#else
aurel326ad193e2008-12-15 01:00:17 +00001474 f32 = float64_to_float32(farg.d, &env->fp_status);
1475 farg.d = float32_to_float64(f32, &env->fp_status);
aurel32af129062008-11-19 16:10:23 +00001476#endif
1477 return farg.ll;
j_mayer7c580442007-10-27 17:54:30 +00001478}
j_mayer7c580442007-10-27 17:54:30 +00001479
aurel32af129062008-11-19 16:10:23 +00001480/* fsqrt - fsqrt. */
1481uint64_t helper_fsqrt (uint64_t arg)
bellard9a64fbe2004-01-04 22:58:38 +00001482{
aurel32af129062008-11-19 16:10:23 +00001483 CPU_DoubleU farg;
1484 farg.ll = arg;
1485
1486 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001487 /* sNaN square root */
aurel32af129062008-11-19 16:10:23 +00001488 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32f23c3462008-12-15 17:14:27 +00001489 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001490 /* Square root of a negative nonzero number */
aurel32af129062008-11-19 16:10:23 +00001491 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
j_mayer7c580442007-10-27 17:54:30 +00001492 } else {
aurel32af129062008-11-19 16:10:23 +00001493 farg.d = float64_sqrt(farg.d, &env->fp_status);
j_mayer7c580442007-10-27 17:54:30 +00001494 }
aurel32af129062008-11-19 16:10:23 +00001495 return farg.ll;
bellard9a64fbe2004-01-04 22:58:38 +00001496}
1497
aurel32af129062008-11-19 16:10:23 +00001498/* fre - fre. */
1499uint64_t helper_fre (uint64_t arg)
j_mayerd7e4b872007-09-30 01:11:48 +00001500{
aurel3205b93602008-12-15 17:13:48 +00001501 CPU_DoubleU fone, farg;
aurel3201feec02008-12-16 10:44:29 +00001502 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
aurel32af129062008-11-19 16:10:23 +00001503 farg.ll = arg;
j_mayerd7e4b872007-09-30 01:11:48 +00001504
aurel32af129062008-11-19 16:10:23 +00001505 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001506 /* sNaN reciprocal */
aurel32af129062008-11-19 16:10:23 +00001507 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
j_mayerd7e4b872007-09-30 01:11:48 +00001508 } else {
aurel326c01bf62008-12-18 22:42:23 +00001509 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
j_mayerd7e4b872007-09-30 01:11:48 +00001510 }
aurel32af129062008-11-19 16:10:23 +00001511 return farg.d;
j_mayerd7e4b872007-09-30 01:11:48 +00001512}
1513
aurel32af129062008-11-19 16:10:23 +00001514/* fres - fres. */
1515uint64_t helper_fres (uint64_t arg)
bellard9a64fbe2004-01-04 22:58:38 +00001516{
aurel3205b93602008-12-15 17:13:48 +00001517 CPU_DoubleU fone, farg;
aurel326c01bf62008-12-18 22:42:23 +00001518 float32 f32;
aurel3201feec02008-12-16 10:44:29 +00001519 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
aurel32af129062008-11-19 16:10:23 +00001520 farg.ll = arg;
bellard4ecc3192005-03-13 17:01:22 +00001521
aurel32af129062008-11-19 16:10:23 +00001522 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001523 /* sNaN reciprocal */
aurel32af129062008-11-19 16:10:23 +00001524 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
bellard4ecc3192005-03-13 17:01:22 +00001525 } else {
aurel326c01bf62008-12-18 22:42:23 +00001526 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1527 f32 = float64_to_float32(farg.d, &env->fp_status);
1528 farg.d = float32_to_float64(f32, &env->fp_status);
bellard4ecc3192005-03-13 17:01:22 +00001529 }
aurel32af129062008-11-19 16:10:23 +00001530 return farg.ll;
bellard9a64fbe2004-01-04 22:58:38 +00001531}
1532
aurel32af129062008-11-19 16:10:23 +00001533/* frsqrte - frsqrte. */
1534uint64_t helper_frsqrte (uint64_t arg)
bellard9a64fbe2004-01-04 22:58:38 +00001535{
aurel3205b93602008-12-15 17:13:48 +00001536 CPU_DoubleU fone, farg;
aurel326c01bf62008-12-18 22:42:23 +00001537 float32 f32;
aurel3201feec02008-12-16 10:44:29 +00001538 fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
aurel32af129062008-11-19 16:10:23 +00001539 farg.ll = arg;
bellard4ecc3192005-03-13 17:01:22 +00001540
aurel32af129062008-11-19 16:10:23 +00001541 if (unlikely(float64_is_signaling_nan(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001542 /* sNaN reciprocal square root */
aurel32af129062008-11-19 16:10:23 +00001543 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
aurel32f23c3462008-12-15 17:14:27 +00001544 } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
j_mayer7c580442007-10-27 17:54:30 +00001545 /* Reciprocal square root of a negative nonzero number */
aurel32af129062008-11-19 16:10:23 +00001546 farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
bellard4ecc3192005-03-13 17:01:22 +00001547 } else {
aurel326c01bf62008-12-18 22:42:23 +00001548 farg.d = float64_sqrt(farg.d, &env->fp_status);
1549 farg.d = float64_div(fone.d, farg.d, &env->fp_status);
1550 f32 = float64_to_float32(farg.d, &env->fp_status);
1551 farg.d = float32_to_float64(f32, &env->fp_status);
bellard4ecc3192005-03-13 17:01:22 +00001552 }
aurel32af129062008-11-19 16:10:23 +00001553 return farg.ll;
bellard9a64fbe2004-01-04 22:58:38 +00001554}
1555
aurel32af129062008-11-19 16:10:23 +00001556/* fsel - fsel. */
1557uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
bellard9a64fbe2004-01-04 22:58:38 +00001558{
aurel326ad73652008-12-14 11:12:10 +00001559 CPU_DoubleU farg1;
aurel32af129062008-11-19 16:10:23 +00001560
1561 farg1.ll = arg1;
aurel32af129062008-11-19 16:10:23 +00001562
aurel32f23c3462008-12-15 17:14:27 +00001563 if (!float64_is_neg(farg1.d) || float64_is_zero(farg1.d))
aurel326ad73652008-12-14 11:12:10 +00001564 return arg2;
bellard4ecc3192005-03-13 17:01:22 +00001565 else
aurel326ad73652008-12-14 11:12:10 +00001566 return arg3;
bellard9a64fbe2004-01-04 22:58:38 +00001567}
1568
aurel329a819372008-12-14 19:34:09 +00001569void helper_fcmpu (uint64_t arg1, uint64_t arg2, uint32_t crfD)
bellard9a64fbe2004-01-04 22:58:38 +00001570{
aurel32af129062008-11-19 16:10:23 +00001571 CPU_DoubleU farg1, farg2;
aurel32e1571902008-10-21 11:31:14 +00001572 uint32_t ret = 0;
aurel32af129062008-11-19 16:10:23 +00001573 farg1.ll = arg1;
1574 farg2.ll = arg2;
aurel32e1571902008-10-21 11:31:14 +00001575
aurel32af129062008-11-19 16:10:23 +00001576 if (unlikely(float64_is_nan(farg1.d) ||
1577 float64_is_nan(farg2.d))) {
aurel329a819372008-12-14 19:34:09 +00001578 ret = 0x01UL;
1579 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1580 ret = 0x08UL;
1581 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1582 ret = 0x04UL;
1583 } else {
1584 ret = 0x02UL;
1585 }
1586
1587 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1588 env->fpscr |= ret << FPSCR_FPRF;
1589 env->crf[crfD] = ret;
1590 if (unlikely(ret == 0x01UL
1591 && (float64_is_signaling_nan(farg1.d) ||
1592 float64_is_signaling_nan(farg2.d)))) {
1593 /* sNaN comparison */
1594 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
1595 }
1596}
1597
1598void helper_fcmpo (uint64_t arg1, uint64_t arg2, uint32_t crfD)
1599{
1600 CPU_DoubleU farg1, farg2;
1601 uint32_t ret = 0;
1602 farg1.ll = arg1;
1603 farg2.ll = arg2;
1604
1605 if (unlikely(float64_is_nan(farg1.d) ||
1606 float64_is_nan(farg2.d))) {
1607 ret = 0x01UL;
1608 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1609 ret = 0x08UL;
1610 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1611 ret = 0x04UL;
1612 } else {
1613 ret = 0x02UL;
1614 }
1615
1616 env->fpscr &= ~(0x0F << FPSCR_FPRF);
1617 env->fpscr |= ret << FPSCR_FPRF;
1618 env->crf[crfD] = ret;
1619 if (unlikely (ret == 0x01UL)) {
aurel32af129062008-11-19 16:10:23 +00001620 if (float64_is_signaling_nan(farg1.d) ||
1621 float64_is_signaling_nan(farg2.d)) {
j_mayer7c580442007-10-27 17:54:30 +00001622 /* sNaN comparison */
1623 fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
1624 POWERPC_EXCP_FP_VXVC);
1625 } else {
1626 /* qNaN comparison */
1627 fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
1628 }
bellard9a64fbe2004-01-04 22:58:38 +00001629 }
bellard9a64fbe2004-01-04 22:58:38 +00001630}
1631
j_mayer76a66252007-03-07 08:32:30 +00001632#if !defined (CONFIG_USER_ONLY)
aurel326527f6e2008-12-06 13:03:35 +00001633void helper_store_msr (target_ulong val)
j_mayer0411a972007-10-25 21:35:50 +00001634{
aurel326527f6e2008-12-06 13:03:35 +00001635 val = hreg_store_msr(env, val, 0);
1636 if (val != 0) {
j_mayer0411a972007-10-25 21:35:50 +00001637 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
aurel32e06fcd72008-12-11 22:42:14 +00001638 helper_raise_exception(val);
j_mayer0411a972007-10-25 21:35:50 +00001639 }
1640}
1641
aurel32d72a19f2008-11-30 16:24:55 +00001642static always_inline void do_rfi (target_ulong nip, target_ulong msr,
j_mayer0411a972007-10-25 21:35:50 +00001643 target_ulong msrm, int keep_msrh)
bellard9a64fbe2004-01-04 22:58:38 +00001644{
j_mayer426613d2007-03-23 09:45:27 +00001645#if defined(TARGET_PPC64)
j_mayer0411a972007-10-25 21:35:50 +00001646 if (msr & (1ULL << MSR_SF)) {
1647 nip = (uint64_t)nip;
1648 msr &= (uint64_t)msrm;
j_mayera42bd6c2007-03-30 10:22:46 +00001649 } else {
j_mayer0411a972007-10-25 21:35:50 +00001650 nip = (uint32_t)nip;
1651 msr = (uint32_t)(msr & msrm);
1652 if (keep_msrh)
1653 msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
j_mayera42bd6c2007-03-30 10:22:46 +00001654 }
j_mayer426613d2007-03-23 09:45:27 +00001655#else
j_mayer0411a972007-10-25 21:35:50 +00001656 nip = (uint32_t)nip;
1657 msr &= (uint32_t)msrm;
j_mayer426613d2007-03-23 09:45:27 +00001658#endif
j_mayer0411a972007-10-25 21:35:50 +00001659 /* XXX: beware: this is false if VLE is supported */
1660 env->nip = nip & ~((target_ulong)0x00000003);
j_mayera4f30712007-11-17 21:14:09 +00001661 hreg_store_msr(env, msr, 1);
j_mayerd9bce9d2007-03-17 14:02:15 +00001662#if defined (DEBUG_OP)
j_mayer0411a972007-10-25 21:35:50 +00001663 cpu_dump_rfi(env->nip, env->msr);
j_mayerd9bce9d2007-03-17 14:02:15 +00001664#endif
j_mayer0411a972007-10-25 21:35:50 +00001665 /* No need to raise an exception here,
1666 * as rfi is always the last insn of a TB
1667 */
j_mayerd9bce9d2007-03-17 14:02:15 +00001668 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1669}
1670
aurel32d72a19f2008-11-30 16:24:55 +00001671void helper_rfi (void)
j_mayer0411a972007-10-25 21:35:50 +00001672{
aurel32d72a19f2008-11-30 16:24:55 +00001673 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1674 ~((target_ulong)0xFFFF0000), 1);
j_mayer0411a972007-10-25 21:35:50 +00001675}
1676
j_mayerd9bce9d2007-03-17 14:02:15 +00001677#if defined(TARGET_PPC64)
aurel32d72a19f2008-11-30 16:24:55 +00001678void helper_rfid (void)
j_mayer426613d2007-03-23 09:45:27 +00001679{
aurel32d72a19f2008-11-30 16:24:55 +00001680 do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
1681 ~((target_ulong)0xFFFF0000), 0);
bellard9a64fbe2004-01-04 22:58:38 +00001682}
j_mayer78636672007-11-16 14:11:28 +00001683
aurel32d72a19f2008-11-30 16:24:55 +00001684void helper_hrfid (void)
j_mayerbe147d02007-09-30 13:03:23 +00001685{
aurel32d72a19f2008-11-30 16:24:55 +00001686 do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
1687 ~((target_ulong)0xFFFF0000), 0);
j_mayerbe147d02007-09-30 13:03:23 +00001688}
1689#endif
j_mayerd9bce9d2007-03-17 14:02:15 +00001690#endif
bellard9a64fbe2004-01-04 22:58:38 +00001691
aurel32cab3bee2008-11-24 11:28:19 +00001692void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
bellard9a64fbe2004-01-04 22:58:38 +00001693{
aurel32cab3bee2008-11-24 11:28:19 +00001694 if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
1695 ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
1696 ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
1697 ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
1698 ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
aurel32e06fcd72008-12-11 22:42:14 +00001699 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
j_mayera42bd6c2007-03-30 10:22:46 +00001700 }
bellard9a64fbe2004-01-04 22:58:38 +00001701}
1702
j_mayerd9bce9d2007-03-17 14:02:15 +00001703#if defined(TARGET_PPC64)
aurel32cab3bee2008-11-24 11:28:19 +00001704void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
j_mayerd9bce9d2007-03-17 14:02:15 +00001705{
aurel32cab3bee2008-11-24 11:28:19 +00001706 if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
1707 ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
1708 ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
1709 ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
1710 ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
aurel32e06fcd72008-12-11 22:42:14 +00001711 helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
j_mayerd9bce9d2007-03-17 14:02:15 +00001712}
1713#endif
1714
bellardfdabc362005-07-04 22:17:05 +00001715/*****************************************************************************/
j_mayer76a66252007-03-07 08:32:30 +00001716/* PowerPC 601 specific instructions (POWER bridge) */
bellard9a64fbe2004-01-04 22:58:38 +00001717
aurel3222e0e172008-12-06 12:19:14 +00001718target_ulong helper_clcs (uint32_t arg)
bellard9a64fbe2004-01-04 22:58:38 +00001719{
aurel3222e0e172008-12-06 12:19:14 +00001720 switch (arg) {
j_mayer76a66252007-03-07 08:32:30 +00001721 case 0x0CUL:
1722 /* Instruction cache line size */
aurel3222e0e172008-12-06 12:19:14 +00001723 return env->icache_line_size;
j_mayer76a66252007-03-07 08:32:30 +00001724 break;
1725 case 0x0DUL:
1726 /* Data cache line size */
aurel3222e0e172008-12-06 12:19:14 +00001727 return env->dcache_line_size;
j_mayer76a66252007-03-07 08:32:30 +00001728 break;
1729 case 0x0EUL:
1730 /* Minimum cache line size */
aurel3222e0e172008-12-06 12:19:14 +00001731 return (env->icache_line_size < env->dcache_line_size) ?
1732 env->icache_line_size : env->dcache_line_size;
j_mayer76a66252007-03-07 08:32:30 +00001733 break;
1734 case 0x0FUL:
1735 /* Maximum cache line size */
aurel3222e0e172008-12-06 12:19:14 +00001736 return (env->icache_line_size > env->dcache_line_size) ?
1737 env->icache_line_size : env->dcache_line_size;
j_mayer76a66252007-03-07 08:32:30 +00001738 break;
1739 default:
1740 /* Undefined */
aurel3222e0e172008-12-06 12:19:14 +00001741 return 0;
j_mayer76a66252007-03-07 08:32:30 +00001742 break;
1743 }
1744}
1745
aurel3222e0e172008-12-06 12:19:14 +00001746target_ulong helper_div (target_ulong arg1, target_ulong arg2)
j_mayer76a66252007-03-07 08:32:30 +00001747{
aurel3222e0e172008-12-06 12:19:14 +00001748 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
j_mayer76a66252007-03-07 08:32:30 +00001749
aurel3222e0e172008-12-06 12:19:14 +00001750 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1751 (int32_t)arg2 == 0) {
j_mayer76a66252007-03-07 08:32:30 +00001752 env->spr[SPR_MQ] = 0;
aurel3222e0e172008-12-06 12:19:14 +00001753 return INT32_MIN;
j_mayer76a66252007-03-07 08:32:30 +00001754 } else {
aurel3222e0e172008-12-06 12:19:14 +00001755 env->spr[SPR_MQ] = tmp % arg2;
1756 return tmp / (int32_t)arg2;
j_mayer76a66252007-03-07 08:32:30 +00001757 }
1758}
1759
aurel3222e0e172008-12-06 12:19:14 +00001760target_ulong helper_divo (target_ulong arg1, target_ulong arg2)
j_mayer76a66252007-03-07 08:32:30 +00001761{
aurel3222e0e172008-12-06 12:19:14 +00001762 uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
j_mayer76a66252007-03-07 08:32:30 +00001763
aurel3222e0e172008-12-06 12:19:14 +00001764 if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1765 (int32_t)arg2 == 0) {
aurel323d7b4172008-10-21 11:28:46 +00001766 env->xer |= (1 << XER_OV) | (1 << XER_SO);
aurel3222e0e172008-12-06 12:19:14 +00001767 env->spr[SPR_MQ] = 0;
1768 return INT32_MIN;
j_mayer76a66252007-03-07 08:32:30 +00001769 } else {
aurel3222e0e172008-12-06 12:19:14 +00001770 env->spr[SPR_MQ] = tmp % arg2;
1771 tmp /= (int32_t)arg2;
1772 if ((int32_t)tmp != tmp) {
aurel323d7b4172008-10-21 11:28:46 +00001773 env->xer |= (1 << XER_OV) | (1 << XER_SO);
j_mayer76a66252007-03-07 08:32:30 +00001774 } else {
aurel323d7b4172008-10-21 11:28:46 +00001775 env->xer &= ~(1 << XER_OV);
j_mayer76a66252007-03-07 08:32:30 +00001776 }
aurel3222e0e172008-12-06 12:19:14 +00001777 return tmp;
j_mayer76a66252007-03-07 08:32:30 +00001778 }
1779}
1780
aurel3222e0e172008-12-06 12:19:14 +00001781target_ulong helper_divs (target_ulong arg1, target_ulong arg2)
j_mayer76a66252007-03-07 08:32:30 +00001782{
aurel3222e0e172008-12-06 12:19:14 +00001783 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1784 (int32_t)arg2 == 0) {
j_mayer76a66252007-03-07 08:32:30 +00001785 env->spr[SPR_MQ] = 0;
aurel3222e0e172008-12-06 12:19:14 +00001786 return INT32_MIN;
j_mayer76a66252007-03-07 08:32:30 +00001787 } else {
aurel3222e0e172008-12-06 12:19:14 +00001788 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1789 return (int32_t)arg1 / (int32_t)arg2;
j_mayer76a66252007-03-07 08:32:30 +00001790 }
1791}
1792
aurel3222e0e172008-12-06 12:19:14 +00001793target_ulong helper_divso (target_ulong arg1, target_ulong arg2)
j_mayer76a66252007-03-07 08:32:30 +00001794{
aurel3222e0e172008-12-06 12:19:14 +00001795 if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
1796 (int32_t)arg2 == 0) {
1797 env->xer |= (1 << XER_OV) | (1 << XER_SO);
j_mayer76a66252007-03-07 08:32:30 +00001798 env->spr[SPR_MQ] = 0;
aurel3222e0e172008-12-06 12:19:14 +00001799 return INT32_MIN;
j_mayer76a66252007-03-07 08:32:30 +00001800 } else {
aurel323d7b4172008-10-21 11:28:46 +00001801 env->xer &= ~(1 << XER_OV);
aurel3222e0e172008-12-06 12:19:14 +00001802 env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
1803 return (int32_t)arg1 / (int32_t)arg2;
j_mayer76a66252007-03-07 08:32:30 +00001804 }
1805}
1806
1807#if !defined (CONFIG_USER_ONLY)
aurel3222e0e172008-12-06 12:19:14 +00001808target_ulong helper_rac (target_ulong addr)
j_mayer76a66252007-03-07 08:32:30 +00001809{
j_mayer76a66252007-03-07 08:32:30 +00001810 mmu_ctx_t ctx;
j_mayerfaadf502007-11-03 13:37:12 +00001811 int nb_BATs;
aurel3222e0e172008-12-06 12:19:14 +00001812 target_ulong ret = 0;
j_mayer76a66252007-03-07 08:32:30 +00001813
1814 /* We don't have to generate many instances of this instruction,
1815 * as rac is supervisor only.
1816 */
j_mayerfaadf502007-11-03 13:37:12 +00001817 /* XXX: FIX THIS: Pretend we have no BAT */
1818 nb_BATs = env->nb_BATs;
1819 env->nb_BATs = 0;
aurel3222e0e172008-12-06 12:19:14 +00001820 if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0)
1821 ret = ctx.raddr;
j_mayerfaadf502007-11-03 13:37:12 +00001822 env->nb_BATs = nb_BATs;
aurel3222e0e172008-12-06 12:19:14 +00001823 return ret;
bellard9a64fbe2004-01-04 22:58:38 +00001824}
1825
aurel32d72a19f2008-11-30 16:24:55 +00001826void helper_rfsvc (void)
j_mayer76a66252007-03-07 08:32:30 +00001827{
aurel32d72a19f2008-11-30 16:24:55 +00001828 do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
j_mayer76a66252007-03-07 08:32:30 +00001829}
j_mayer76a66252007-03-07 08:32:30 +00001830#endif
1831
1832/*****************************************************************************/
1833/* 602 specific instructions */
1834/* mfrom is the most crazy instruction ever seen, imho ! */
1835/* Real implementation uses a ROM table. Do the same */
aurel325e9ae182008-12-13 12:30:21 +00001836/* Extremly decomposed:
1837 * -arg / 256
1838 * return 256 * log10(10 + 1.0) + 0.5
1839 */
aurel32db9a16a2008-12-08 18:11:50 +00001840#if !defined (CONFIG_USER_ONLY)
aurel32cf02a652008-11-30 16:23:35 +00001841target_ulong helper_602_mfrom (target_ulong arg)
j_mayer76a66252007-03-07 08:32:30 +00001842{
aurel32cf02a652008-11-30 16:23:35 +00001843 if (likely(arg < 602)) {
j_mayer76a66252007-03-07 08:32:30 +00001844#include "mfrom_table.c"
aurel3245d827d2008-12-07 13:40:29 +00001845 return mfrom_ROM_table[arg];
j_mayer76a66252007-03-07 08:32:30 +00001846 } else {
aurel32cf02a652008-11-30 16:23:35 +00001847 return 0;
j_mayer76a66252007-03-07 08:32:30 +00001848 }
1849}
aurel32db9a16a2008-12-08 18:11:50 +00001850#endif
j_mayer76a66252007-03-07 08:32:30 +00001851
1852/*****************************************************************************/
1853/* Embedded PowerPC specific helpers */
j_mayer76a66252007-03-07 08:32:30 +00001854
j_mayera750fc02007-09-26 23:54:22 +00001855/* XXX: to be improved to check access rights when in user-mode */
aurel3206dca6a2008-12-06 16:37:18 +00001856target_ulong helper_load_dcr (target_ulong dcrn)
j_mayera750fc02007-09-26 23:54:22 +00001857{
aurel3206dca6a2008-12-06 16:37:18 +00001858 target_ulong val = 0;
j_mayera750fc02007-09-26 23:54:22 +00001859
1860 if (unlikely(env->dcr_env == NULL)) {
1861 if (loglevel != 0) {
1862 fprintf(logfile, "No DCR environment\n");
1863 }
aurel32e06fcd72008-12-11 22:42:14 +00001864 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1865 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
aurel3206dca6a2008-12-06 16:37:18 +00001866 } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
j_mayera750fc02007-09-26 23:54:22 +00001867 if (loglevel != 0) {
aurel3245d827d2008-12-07 13:40:29 +00001868 fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
j_mayera750fc02007-09-26 23:54:22 +00001869 }
aurel32e06fcd72008-12-11 22:42:14 +00001870 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1871 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
j_mayera750fc02007-09-26 23:54:22 +00001872 }
aurel3206dca6a2008-12-06 16:37:18 +00001873 return val;
j_mayera750fc02007-09-26 23:54:22 +00001874}
1875
aurel3206dca6a2008-12-06 16:37:18 +00001876void helper_store_dcr (target_ulong dcrn, target_ulong val)
j_mayera750fc02007-09-26 23:54:22 +00001877{
1878 if (unlikely(env->dcr_env == NULL)) {
1879 if (loglevel != 0) {
1880 fprintf(logfile, "No DCR environment\n");
1881 }
aurel32e06fcd72008-12-11 22:42:14 +00001882 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1883 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
aurel3206dca6a2008-12-06 16:37:18 +00001884 } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
j_mayera750fc02007-09-26 23:54:22 +00001885 if (loglevel != 0) {
aurel3245d827d2008-12-07 13:40:29 +00001886 fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
j_mayera750fc02007-09-26 23:54:22 +00001887 }
aurel32e06fcd72008-12-11 22:42:14 +00001888 helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
1889 POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
j_mayera750fc02007-09-26 23:54:22 +00001890 }
1891}
1892
j_mayer76a66252007-03-07 08:32:30 +00001893#if !defined(CONFIG_USER_ONLY)
aurel32d72a19f2008-11-30 16:24:55 +00001894void helper_40x_rfci (void)
j_mayer76a66252007-03-07 08:32:30 +00001895{
aurel32d72a19f2008-11-30 16:24:55 +00001896 do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
1897 ~((target_ulong)0xFFFF0000), 0);
j_mayer76a66252007-03-07 08:32:30 +00001898}
1899
aurel32d72a19f2008-11-30 16:24:55 +00001900void helper_rfci (void)
j_mayera42bd6c2007-03-30 10:22:46 +00001901{
aurel32d72a19f2008-11-30 16:24:55 +00001902 do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
1903 ~((target_ulong)0x3FFF0000), 0);
j_mayera42bd6c2007-03-30 10:22:46 +00001904}
1905
aurel32d72a19f2008-11-30 16:24:55 +00001906void helper_rfdi (void)
j_mayera42bd6c2007-03-30 10:22:46 +00001907{
aurel32d72a19f2008-11-30 16:24:55 +00001908 do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
1909 ~((target_ulong)0x3FFF0000), 0);
j_mayera42bd6c2007-03-30 10:22:46 +00001910}
1911
aurel32d72a19f2008-11-30 16:24:55 +00001912void helper_rfmci (void)
j_mayera42bd6c2007-03-30 10:22:46 +00001913{
aurel32d72a19f2008-11-30 16:24:55 +00001914 do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
1915 ~((target_ulong)0x3FFF0000), 0);
j_mayera42bd6c2007-03-30 10:22:46 +00001916}
j_mayer76a66252007-03-07 08:32:30 +00001917#endif
1918
1919/* 440 specific */
aurel32ef0d51a2008-11-30 17:26:29 +00001920target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
j_mayer76a66252007-03-07 08:32:30 +00001921{
1922 target_ulong mask;
1923 int i;
1924
1925 i = 1;
1926 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
aurel32ef0d51a2008-11-30 17:26:29 +00001927 if ((high & mask) == 0) {
1928 if (update_Rc) {
1929 env->crf[0] = 0x4;
1930 }
j_mayer76a66252007-03-07 08:32:30 +00001931 goto done;
aurel32ef0d51a2008-11-30 17:26:29 +00001932 }
j_mayer76a66252007-03-07 08:32:30 +00001933 i++;
1934 }
1935 for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
aurel32ef0d51a2008-11-30 17:26:29 +00001936 if ((low & mask) == 0) {
1937 if (update_Rc) {
1938 env->crf[0] = 0x8;
1939 }
1940 goto done;
1941 }
j_mayer76a66252007-03-07 08:32:30 +00001942 i++;
1943 }
aurel32ef0d51a2008-11-30 17:26:29 +00001944 if (update_Rc) {
1945 env->crf[0] = 0x2;
1946 }
j_mayer76a66252007-03-07 08:32:30 +00001947 done:
aurel32ef0d51a2008-11-30 17:26:29 +00001948 env->xer = (env->xer & ~0x7F) | i;
1949 if (update_Rc) {
1950 env->crf[0] |= xer_so;
1951 }
1952 return i;
j_mayer76a66252007-03-07 08:32:30 +00001953}
1954
aurel321c978562008-11-23 10:54:04 +00001955/*****************************************************************************/
j_mayer0487d6a2007-03-20 22:11:31 +00001956/* SPE extension helpers */
1957/* Use a table to make this quicker */
1958static uint8_t hbrev[16] = {
1959 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
1960 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
1961};
1962
j_mayerb068d6a2007-10-07 17:13:44 +00001963static always_inline uint8_t byte_reverse (uint8_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00001964{
1965 return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
1966}
1967
j_mayerb068d6a2007-10-07 17:13:44 +00001968static always_inline uint32_t word_reverse (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00001969{
1970 return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
1971 (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
1972}
1973
j_mayer3cd7d1d2007-11-12 01:56:18 +00001974#define MASKBITS 16 // Random value - to be fixed (implementation dependant)
aurel3257951c22008-11-10 11:10:23 +00001975target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
j_mayer0487d6a2007-03-20 22:11:31 +00001976{
1977 uint32_t a, b, d, mask;
1978
j_mayer3cd7d1d2007-11-12 01:56:18 +00001979 mask = UINT32_MAX >> (32 - MASKBITS);
aurel3257951c22008-11-10 11:10:23 +00001980 a = arg1 & mask;
1981 b = arg2 & mask;
j_mayer3cd7d1d2007-11-12 01:56:18 +00001982 d = word_reverse(1 + word_reverse(a | ~b));
aurel3257951c22008-11-10 11:10:23 +00001983 return (arg1 & ~mask) | (d & b);
j_mayer0487d6a2007-03-20 22:11:31 +00001984}
1985
aurel3257951c22008-11-10 11:10:23 +00001986uint32_t helper_cntlsw32 (uint32_t val)
1987{
1988 if (val & 0x80000000)
1989 return clz32(~val);
1990 else
1991 return clz32(val);
1992}
1993
1994uint32_t helper_cntlzw32 (uint32_t val)
1995{
1996 return clz32(val);
j_mayer0487d6a2007-03-20 22:11:31 +00001997}
1998
aurel321c978562008-11-23 10:54:04 +00001999/* Single-precision floating-point conversions */
2000static always_inline uint32_t efscfsi (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002001{
aurel320ca9d382008-03-13 19:19:16 +00002002 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002003
2004 u.f = int32_to_float32(val, &env->spe_status);
2005
aurel320ca9d382008-03-13 19:19:16 +00002006 return u.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002007}
2008
aurel321c978562008-11-23 10:54:04 +00002009static always_inline uint32_t efscfui (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002010{
aurel320ca9d382008-03-13 19:19:16 +00002011 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002012
2013 u.f = uint32_to_float32(val, &env->spe_status);
2014
aurel320ca9d382008-03-13 19:19:16 +00002015 return u.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002016}
2017
aurel321c978562008-11-23 10:54:04 +00002018static always_inline int32_t efsctsi (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002019{
aurel320ca9d382008-03-13 19:19:16 +00002020 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002021
aurel320ca9d382008-03-13 19:19:16 +00002022 u.l = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002023 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002024 if (unlikely(float32_is_nan(u.f)))
j_mayer0487d6a2007-03-20 22:11:31 +00002025 return 0;
2026
2027 return float32_to_int32(u.f, &env->spe_status);
2028}
2029
aurel321c978562008-11-23 10:54:04 +00002030static always_inline uint32_t efsctui (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002031{
aurel320ca9d382008-03-13 19:19:16 +00002032 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002033
aurel320ca9d382008-03-13 19:19:16 +00002034 u.l = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002035 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002036 if (unlikely(float32_is_nan(u.f)))
j_mayer0487d6a2007-03-20 22:11:31 +00002037 return 0;
2038
2039 return float32_to_uint32(u.f, &env->spe_status);
2040}
2041
aurel321c978562008-11-23 10:54:04 +00002042static always_inline uint32_t efsctsiz (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002043{
aurel320ca9d382008-03-13 19:19:16 +00002044 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002045
aurel320ca9d382008-03-13 19:19:16 +00002046 u.l = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002047 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002048 if (unlikely(float32_is_nan(u.f)))
j_mayer0487d6a2007-03-20 22:11:31 +00002049 return 0;
2050
2051 return float32_to_int32_round_to_zero(u.f, &env->spe_status);
2052}
2053
aurel321c978562008-11-23 10:54:04 +00002054static always_inline uint32_t efsctuiz (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002055{
aurel320ca9d382008-03-13 19:19:16 +00002056 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002057
aurel320ca9d382008-03-13 19:19:16 +00002058 u.l = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002059 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002060 if (unlikely(float32_is_nan(u.f)))
j_mayer0487d6a2007-03-20 22:11:31 +00002061 return 0;
2062
2063 return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
2064}
2065
aurel321c978562008-11-23 10:54:04 +00002066static always_inline uint32_t efscfsf (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002067{
aurel320ca9d382008-03-13 19:19:16 +00002068 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002069 float32 tmp;
2070
2071 u.f = int32_to_float32(val, &env->spe_status);
2072 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2073 u.f = float32_div(u.f, tmp, &env->spe_status);
2074
aurel320ca9d382008-03-13 19:19:16 +00002075 return u.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002076}
2077
aurel321c978562008-11-23 10:54:04 +00002078static always_inline uint32_t efscfuf (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002079{
aurel320ca9d382008-03-13 19:19:16 +00002080 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002081 float32 tmp;
2082
2083 u.f = uint32_to_float32(val, &env->spe_status);
2084 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2085 u.f = float32_div(u.f, tmp, &env->spe_status);
2086
aurel320ca9d382008-03-13 19:19:16 +00002087 return u.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002088}
2089
aurel321c978562008-11-23 10:54:04 +00002090static always_inline uint32_t efsctsf (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002091{
aurel320ca9d382008-03-13 19:19:16 +00002092 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002093 float32 tmp;
2094
aurel320ca9d382008-03-13 19:19:16 +00002095 u.l = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002096 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002097 if (unlikely(float32_is_nan(u.f)))
j_mayer0487d6a2007-03-20 22:11:31 +00002098 return 0;
2099 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2100 u.f = float32_mul(u.f, tmp, &env->spe_status);
2101
2102 return float32_to_int32(u.f, &env->spe_status);
2103}
2104
aurel321c978562008-11-23 10:54:04 +00002105static always_inline uint32_t efsctuf (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002106{
aurel320ca9d382008-03-13 19:19:16 +00002107 CPU_FloatU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002108 float32 tmp;
2109
aurel320ca9d382008-03-13 19:19:16 +00002110 u.l = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002111 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002112 if (unlikely(float32_is_nan(u.f)))
j_mayer0487d6a2007-03-20 22:11:31 +00002113 return 0;
2114 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2115 u.f = float32_mul(u.f, tmp, &env->spe_status);
2116
2117 return float32_to_uint32(u.f, &env->spe_status);
2118}
2119
aurel321c978562008-11-23 10:54:04 +00002120#define HELPER_SPE_SINGLE_CONV(name) \
2121uint32_t helper_e##name (uint32_t val) \
2122{ \
2123 return e##name(val); \
2124}
2125/* efscfsi */
2126HELPER_SPE_SINGLE_CONV(fscfsi);
2127/* efscfui */
2128HELPER_SPE_SINGLE_CONV(fscfui);
2129/* efscfuf */
2130HELPER_SPE_SINGLE_CONV(fscfuf);
2131/* efscfsf */
2132HELPER_SPE_SINGLE_CONV(fscfsf);
2133/* efsctsi */
2134HELPER_SPE_SINGLE_CONV(fsctsi);
2135/* efsctui */
2136HELPER_SPE_SINGLE_CONV(fsctui);
2137/* efsctsiz */
2138HELPER_SPE_SINGLE_CONV(fsctsiz);
2139/* efsctuiz */
2140HELPER_SPE_SINGLE_CONV(fsctuiz);
2141/* efsctsf */
2142HELPER_SPE_SINGLE_CONV(fsctsf);
2143/* efsctuf */
2144HELPER_SPE_SINGLE_CONV(fsctuf);
2145
2146#define HELPER_SPE_VECTOR_CONV(name) \
2147uint64_t helper_ev##name (uint64_t val) \
2148{ \
2149 return ((uint64_t)e##name(val >> 32) << 32) | \
2150 (uint64_t)e##name(val); \
2151}
2152/* evfscfsi */
2153HELPER_SPE_VECTOR_CONV(fscfsi);
2154/* evfscfui */
2155HELPER_SPE_VECTOR_CONV(fscfui);
2156/* evfscfuf */
2157HELPER_SPE_VECTOR_CONV(fscfuf);
2158/* evfscfsf */
2159HELPER_SPE_VECTOR_CONV(fscfsf);
2160/* evfsctsi */
2161HELPER_SPE_VECTOR_CONV(fsctsi);
2162/* evfsctui */
2163HELPER_SPE_VECTOR_CONV(fsctui);
2164/* evfsctsiz */
2165HELPER_SPE_VECTOR_CONV(fsctsiz);
2166/* evfsctuiz */
2167HELPER_SPE_VECTOR_CONV(fsctuiz);
2168/* evfsctsf */
2169HELPER_SPE_VECTOR_CONV(fsctsf);
2170/* evfsctuf */
2171HELPER_SPE_VECTOR_CONV(fsctuf);
2172
2173/* Single-precision floating-point arithmetic */
2174static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002175{
aurel321c978562008-11-23 10:54:04 +00002176 CPU_FloatU u1, u2;
2177 u1.l = op1;
2178 u2.l = op2;
2179 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
2180 return u1.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002181}
2182
aurel321c978562008-11-23 10:54:04 +00002183static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002184{
aurel321c978562008-11-23 10:54:04 +00002185 CPU_FloatU u1, u2;
2186 u1.l = op1;
2187 u2.l = op2;
2188 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
2189 return u1.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002190}
2191
aurel321c978562008-11-23 10:54:04 +00002192static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002193{
aurel321c978562008-11-23 10:54:04 +00002194 CPU_FloatU u1, u2;
2195 u1.l = op1;
2196 u2.l = op2;
2197 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
2198 return u1.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002199}
2200
aurel321c978562008-11-23 10:54:04 +00002201static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002202{
aurel321c978562008-11-23 10:54:04 +00002203 CPU_FloatU u1, u2;
2204 u1.l = op1;
2205 u2.l = op2;
2206 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
2207 return u1.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002208}
2209
aurel321c978562008-11-23 10:54:04 +00002210#define HELPER_SPE_SINGLE_ARITH(name) \
2211uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2212{ \
2213 return e##name(op1, op2); \
2214}
2215/* efsadd */
2216HELPER_SPE_SINGLE_ARITH(fsadd);
2217/* efssub */
2218HELPER_SPE_SINGLE_ARITH(fssub);
2219/* efsmul */
2220HELPER_SPE_SINGLE_ARITH(fsmul);
2221/* efsdiv */
2222HELPER_SPE_SINGLE_ARITH(fsdiv);
2223
2224#define HELPER_SPE_VECTOR_ARITH(name) \
2225uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
2226{ \
2227 return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
2228 (uint64_t)e##name(op1, op2); \
2229}
2230/* evfsadd */
2231HELPER_SPE_VECTOR_ARITH(fsadd);
2232/* evfssub */
2233HELPER_SPE_VECTOR_ARITH(fssub);
2234/* evfsmul */
2235HELPER_SPE_VECTOR_ARITH(fsmul);
2236/* evfsdiv */
2237HELPER_SPE_VECTOR_ARITH(fsdiv);
2238
2239/* Single-precision floating-point comparisons */
2240static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002241{
aurel321c978562008-11-23 10:54:04 +00002242 CPU_FloatU u1, u2;
2243 u1.l = op1;
2244 u2.l = op2;
2245 return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
j_mayer0487d6a2007-03-20 22:11:31 +00002246}
2247
aurel321c978562008-11-23 10:54:04 +00002248static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002249{
aurel321c978562008-11-23 10:54:04 +00002250 CPU_FloatU u1, u2;
2251 u1.l = op1;
2252 u2.l = op2;
2253 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
j_mayer0487d6a2007-03-20 22:11:31 +00002254}
2255
aurel321c978562008-11-23 10:54:04 +00002256static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002257{
aurel321c978562008-11-23 10:54:04 +00002258 CPU_FloatU u1, u2;
2259 u1.l = op1;
2260 u2.l = op2;
2261 return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
j_mayer0487d6a2007-03-20 22:11:31 +00002262}
2263
aurel321c978562008-11-23 10:54:04 +00002264static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002265{
2266 /* XXX: TODO: test special values (NaN, infinites, ...) */
aurel321c978562008-11-23 10:54:04 +00002267 return efststlt(op1, op2);
j_mayer0487d6a2007-03-20 22:11:31 +00002268}
2269
aurel321c978562008-11-23 10:54:04 +00002270static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002271{
2272 /* XXX: TODO: test special values (NaN, infinites, ...) */
aurel321c978562008-11-23 10:54:04 +00002273 return efststgt(op1, op2);
j_mayer0487d6a2007-03-20 22:11:31 +00002274}
2275
aurel321c978562008-11-23 10:54:04 +00002276static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002277{
2278 /* XXX: TODO: test special values (NaN, infinites, ...) */
aurel321c978562008-11-23 10:54:04 +00002279 return efststeq(op1, op2);
j_mayer0487d6a2007-03-20 22:11:31 +00002280}
2281
aurel321c978562008-11-23 10:54:04 +00002282#define HELPER_SINGLE_SPE_CMP(name) \
2283uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
2284{ \
2285 return e##name(op1, op2) << 2; \
2286}
2287/* efststlt */
2288HELPER_SINGLE_SPE_CMP(fststlt);
2289/* efststgt */
2290HELPER_SINGLE_SPE_CMP(fststgt);
2291/* efststeq */
2292HELPER_SINGLE_SPE_CMP(fststeq);
2293/* efscmplt */
2294HELPER_SINGLE_SPE_CMP(fscmplt);
2295/* efscmpgt */
2296HELPER_SINGLE_SPE_CMP(fscmpgt);
2297/* efscmpeq */
2298HELPER_SINGLE_SPE_CMP(fscmpeq);
2299
2300static always_inline uint32_t evcmp_merge (int t0, int t1)
j_mayer0487d6a2007-03-20 22:11:31 +00002301{
aurel321c978562008-11-23 10:54:04 +00002302 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
j_mayer0487d6a2007-03-20 22:11:31 +00002303}
2304
aurel321c978562008-11-23 10:54:04 +00002305#define HELPER_VECTOR_SPE_CMP(name) \
2306uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
2307{ \
2308 return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
2309}
2310/* evfststlt */
2311HELPER_VECTOR_SPE_CMP(fststlt);
2312/* evfststgt */
2313HELPER_VECTOR_SPE_CMP(fststgt);
2314/* evfststeq */
2315HELPER_VECTOR_SPE_CMP(fststeq);
2316/* evfscmplt */
2317HELPER_VECTOR_SPE_CMP(fscmplt);
2318/* evfscmpgt */
2319HELPER_VECTOR_SPE_CMP(fscmpgt);
2320/* evfscmpeq */
2321HELPER_VECTOR_SPE_CMP(fscmpeq);
2322
2323/* Double-precision floating-point conversion */
2324uint64_t helper_efdcfsi (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002325{
aurel321c978562008-11-23 10:54:04 +00002326 CPU_DoubleU u;
2327
2328 u.d = int32_to_float64(val, &env->spe_status);
2329
2330 return u.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002331}
2332
aurel321c978562008-11-23 10:54:04 +00002333uint64_t helper_efdcfsid (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002334{
aurel320ca9d382008-03-13 19:19:16 +00002335 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002336
aurel320ca9d382008-03-13 19:19:16 +00002337 u.d = int64_to_float64(val, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002338
aurel320ca9d382008-03-13 19:19:16 +00002339 return u.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002340}
2341
aurel321c978562008-11-23 10:54:04 +00002342uint64_t helper_efdcfui (uint32_t val)
2343{
2344 CPU_DoubleU u;
2345
2346 u.d = uint32_to_float64(val, &env->spe_status);
2347
2348 return u.ll;
2349}
2350
2351uint64_t helper_efdcfuid (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002352{
aurel320ca9d382008-03-13 19:19:16 +00002353 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002354
aurel320ca9d382008-03-13 19:19:16 +00002355 u.d = uint64_to_float64(val, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002356
aurel320ca9d382008-03-13 19:19:16 +00002357 return u.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002358}
2359
aurel321c978562008-11-23 10:54:04 +00002360uint32_t helper_efdctsi (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002361{
aurel320ca9d382008-03-13 19:19:16 +00002362 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002363
aurel320ca9d382008-03-13 19:19:16 +00002364 u.ll = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002365 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002366 if (unlikely(float64_is_nan(u.d)))
j_mayer0487d6a2007-03-20 22:11:31 +00002367 return 0;
2368
aurel321c978562008-11-23 10:54:04 +00002369 return float64_to_int32(u.d, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002370}
2371
aurel321c978562008-11-23 10:54:04 +00002372uint32_t helper_efdctui (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002373{
aurel320ca9d382008-03-13 19:19:16 +00002374 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002375
aurel320ca9d382008-03-13 19:19:16 +00002376 u.ll = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002377 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002378 if (unlikely(float64_is_nan(u.d)))
j_mayer0487d6a2007-03-20 22:11:31 +00002379 return 0;
2380
aurel321c978562008-11-23 10:54:04 +00002381 return float64_to_uint32(u.d, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002382}
2383
aurel321c978562008-11-23 10:54:04 +00002384uint32_t helper_efdctsiz (uint64_t val)
2385{
2386 CPU_DoubleU u;
2387
2388 u.ll = val;
2389 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002390 if (unlikely(float64_is_nan(u.d)))
aurel321c978562008-11-23 10:54:04 +00002391 return 0;
2392
2393 return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2394}
2395
2396uint64_t helper_efdctsidz (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002397{
aurel320ca9d382008-03-13 19:19:16 +00002398 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002399
aurel320ca9d382008-03-13 19:19:16 +00002400 u.ll = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002401 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002402 if (unlikely(float64_is_nan(u.d)))
j_mayer0487d6a2007-03-20 22:11:31 +00002403 return 0;
2404
aurel320ca9d382008-03-13 19:19:16 +00002405 return float64_to_int64_round_to_zero(u.d, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002406}
2407
aurel321c978562008-11-23 10:54:04 +00002408uint32_t helper_efdctuiz (uint64_t val)
2409{
2410 CPU_DoubleU u;
2411
2412 u.ll = val;
2413 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002414 if (unlikely(float64_is_nan(u.d)))
aurel321c978562008-11-23 10:54:04 +00002415 return 0;
2416
2417 return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2418}
2419
2420uint64_t helper_efdctuidz (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002421{
aurel320ca9d382008-03-13 19:19:16 +00002422 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002423
aurel320ca9d382008-03-13 19:19:16 +00002424 u.ll = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002425 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002426 if (unlikely(float64_is_nan(u.d)))
j_mayer0487d6a2007-03-20 22:11:31 +00002427 return 0;
2428
aurel320ca9d382008-03-13 19:19:16 +00002429 return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002430}
2431
aurel321c978562008-11-23 10:54:04 +00002432uint64_t helper_efdcfsf (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002433{
aurel320ca9d382008-03-13 19:19:16 +00002434 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002435 float64 tmp;
2436
aurel320ca9d382008-03-13 19:19:16 +00002437 u.d = int32_to_float64(val, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002438 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
aurel320ca9d382008-03-13 19:19:16 +00002439 u.d = float64_div(u.d, tmp, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002440
aurel320ca9d382008-03-13 19:19:16 +00002441 return u.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002442}
2443
aurel321c978562008-11-23 10:54:04 +00002444uint64_t helper_efdcfuf (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002445{
aurel320ca9d382008-03-13 19:19:16 +00002446 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002447 float64 tmp;
2448
aurel320ca9d382008-03-13 19:19:16 +00002449 u.d = uint32_to_float64(val, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002450 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
aurel320ca9d382008-03-13 19:19:16 +00002451 u.d = float64_div(u.d, tmp, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002452
aurel320ca9d382008-03-13 19:19:16 +00002453 return u.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002454}
2455
aurel321c978562008-11-23 10:54:04 +00002456uint32_t helper_efdctsf (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002457{
aurel320ca9d382008-03-13 19:19:16 +00002458 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002459 float64 tmp;
2460
aurel320ca9d382008-03-13 19:19:16 +00002461 u.ll = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002462 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002463 if (unlikely(float64_is_nan(u.d)))
j_mayer0487d6a2007-03-20 22:11:31 +00002464 return 0;
2465 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
aurel320ca9d382008-03-13 19:19:16 +00002466 u.d = float64_mul(u.d, tmp, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002467
aurel320ca9d382008-03-13 19:19:16 +00002468 return float64_to_int32(u.d, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002469}
2470
aurel321c978562008-11-23 10:54:04 +00002471uint32_t helper_efdctuf (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002472{
aurel320ca9d382008-03-13 19:19:16 +00002473 CPU_DoubleU u;
j_mayer0487d6a2007-03-20 22:11:31 +00002474 float64 tmp;
2475
aurel320ca9d382008-03-13 19:19:16 +00002476 u.ll = val;
j_mayer0487d6a2007-03-20 22:11:31 +00002477 /* NaN are not treated the same way IEEE 754 does */
aurel32a44d2ce2008-12-13 11:46:27 +00002478 if (unlikely(float64_is_nan(u.d)))
j_mayer0487d6a2007-03-20 22:11:31 +00002479 return 0;
2480 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
aurel320ca9d382008-03-13 19:19:16 +00002481 u.d = float64_mul(u.d, tmp, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002482
aurel320ca9d382008-03-13 19:19:16 +00002483 return float64_to_uint32(u.d, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002484}
2485
aurel321c978562008-11-23 10:54:04 +00002486uint32_t helper_efscfd (uint64_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002487{
aurel320ca9d382008-03-13 19:19:16 +00002488 CPU_DoubleU u1;
2489 CPU_FloatU u2;
j_mayer0487d6a2007-03-20 22:11:31 +00002490
aurel320ca9d382008-03-13 19:19:16 +00002491 u1.ll = val;
2492 u2.f = float64_to_float32(u1.d, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002493
aurel320ca9d382008-03-13 19:19:16 +00002494 return u2.l;
j_mayer0487d6a2007-03-20 22:11:31 +00002495}
2496
aurel321c978562008-11-23 10:54:04 +00002497uint64_t helper_efdcfs (uint32_t val)
j_mayer0487d6a2007-03-20 22:11:31 +00002498{
aurel320ca9d382008-03-13 19:19:16 +00002499 CPU_DoubleU u2;
2500 CPU_FloatU u1;
j_mayer0487d6a2007-03-20 22:11:31 +00002501
aurel320ca9d382008-03-13 19:19:16 +00002502 u1.l = val;
2503 u2.d = float32_to_float64(u1.f, &env->spe_status);
j_mayer0487d6a2007-03-20 22:11:31 +00002504
aurel320ca9d382008-03-13 19:19:16 +00002505 return u2.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002506}
2507
aurel321c978562008-11-23 10:54:04 +00002508/* Double precision fixed-point arithmetic */
2509uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002510{
aurel321c978562008-11-23 10:54:04 +00002511 CPU_DoubleU u1, u2;
2512 u1.ll = op1;
2513 u2.ll = op2;
2514 u1.d = float64_add(u1.d, u2.d, &env->spe_status);
2515 return u1.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002516}
2517
aurel321c978562008-11-23 10:54:04 +00002518uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002519{
aurel321c978562008-11-23 10:54:04 +00002520 CPU_DoubleU u1, u2;
2521 u1.ll = op1;
2522 u2.ll = op2;
2523 u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
2524 return u1.ll;
j_mayer0487d6a2007-03-20 22:11:31 +00002525}
2526
aurel321c978562008-11-23 10:54:04 +00002527uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
2528{
2529 CPU_DoubleU u1, u2;
2530 u1.ll = op1;
2531 u2.ll = op2;
2532 u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
2533 return u1.ll;
2534}
j_mayer0487d6a2007-03-20 22:11:31 +00002535
aurel321c978562008-11-23 10:54:04 +00002536uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
2537{
2538 CPU_DoubleU u1, u2;
2539 u1.ll = op1;
2540 u2.ll = op2;
2541 u1.d = float64_div(u1.d, u2.d, &env->spe_status);
2542 return u1.ll;
2543}
2544
2545/* Double precision floating point helpers */
2546uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
2547{
2548 CPU_DoubleU u1, u2;
2549 u1.ll = op1;
2550 u2.ll = op2;
2551 return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2552}
2553
2554uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
2555{
2556 CPU_DoubleU u1, u2;
2557 u1.ll = op1;
2558 u2.ll = op2;
2559 return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
2560}
2561
2562uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
2563{
2564 CPU_DoubleU u1, u2;
2565 u1.ll = op1;
2566 u2.ll = op2;
2567 return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
2568}
2569
2570uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002571{
2572 /* XXX: TODO: test special values (NaN, infinites, ...) */
aurel321c978562008-11-23 10:54:04 +00002573 return helper_efdtstlt(op1, op2);
j_mayer0487d6a2007-03-20 22:11:31 +00002574}
2575
aurel321c978562008-11-23 10:54:04 +00002576uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002577{
2578 /* XXX: TODO: test special values (NaN, infinites, ...) */
aurel321c978562008-11-23 10:54:04 +00002579 return helper_efdtstgt(op1, op2);
j_mayer0487d6a2007-03-20 22:11:31 +00002580}
2581
aurel321c978562008-11-23 10:54:04 +00002582uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
j_mayer0487d6a2007-03-20 22:11:31 +00002583{
2584 /* XXX: TODO: test special values (NaN, infinites, ...) */
aurel321c978562008-11-23 10:54:04 +00002585 return helper_efdtsteq(op1, op2);
j_mayer0487d6a2007-03-20 22:11:31 +00002586}
2587
bellardfdabc362005-07-04 22:17:05 +00002588/*****************************************************************************/
2589/* Softmmu support */
2590#if !defined (CONFIG_USER_ONLY)
2591
2592#define MMUSUFFIX _mmu
bellardfdabc362005-07-04 22:17:05 +00002593
2594#define SHIFT 0
2595#include "softmmu_template.h"
2596
2597#define SHIFT 1
2598#include "softmmu_template.h"
2599
2600#define SHIFT 2
2601#include "softmmu_template.h"
2602
2603#define SHIFT 3
2604#include "softmmu_template.h"
2605
2606/* try to fill the TLB and return an exception if error. If retaddr is
2607 NULL, it means that the function was called in C code (i.e. not
2608 from generated code or from helper.c) */
2609/* XXX: fix it to restore all registers */
j_mayer6ebbf392007-10-14 07:07:08 +00002610void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
bellardfdabc362005-07-04 22:17:05 +00002611{
2612 TranslationBlock *tb;
2613 CPUState *saved_env;
bellard44f86252007-11-11 12:35:55 +00002614 unsigned long pc;
bellardfdabc362005-07-04 22:17:05 +00002615 int ret;
2616
2617 /* XXX: hack to restore env in all cases, even if not called from
2618 generated code */
2619 saved_env = env;
2620 env = cpu_single_env;
j_mayer6ebbf392007-10-14 07:07:08 +00002621 ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
j_mayer76a66252007-03-07 08:32:30 +00002622 if (unlikely(ret != 0)) {
bellardfdabc362005-07-04 22:17:05 +00002623 if (likely(retaddr)) {
2624 /* now we have a real cpu fault */
bellard44f86252007-11-11 12:35:55 +00002625 pc = (unsigned long)retaddr;
bellardfdabc362005-07-04 22:17:05 +00002626 tb = tb_find_pc(pc);
2627 if (likely(tb)) {
2628 /* the PC is inside the translated code. It means that we have
2629 a virtual CPU fault */
2630 cpu_restore_state(tb, env, pc, NULL);
j_mayer76a66252007-03-07 08:32:30 +00002631 }
bellardfdabc362005-07-04 22:17:05 +00002632 }
aurel32e06fcd72008-12-11 22:42:14 +00002633 helper_raise_exception_err(env->exception_index, env->error_code);
bellardfdabc362005-07-04 22:17:05 +00002634 }
2635 env = saved_env;
2636}
bellardfdabc362005-07-04 22:17:05 +00002637
aurel3274d37792008-12-06 21:46:17 +00002638/* Segment registers load and store */
2639target_ulong helper_load_sr (target_ulong sr_num)
2640{
2641 return env->sr[sr_num];
2642}
2643
2644void helper_store_sr (target_ulong sr_num, target_ulong val)
2645{
aurel3245d827d2008-12-07 13:40:29 +00002646 ppc_store_sr(env, sr_num, val);
aurel3274d37792008-12-06 21:46:17 +00002647}
2648
2649/* SLB management */
2650#if defined(TARGET_PPC64)
2651target_ulong helper_load_slb (target_ulong slb_nr)
2652{
2653 return ppc_load_slb(env, slb_nr);
2654}
2655
2656void helper_store_slb (target_ulong slb_nr, target_ulong rs)
2657{
2658 ppc_store_slb(env, slb_nr, rs);
2659}
2660
2661void helper_slbia (void)
2662{
2663 ppc_slb_invalidate_all(env);
2664}
2665
2666void helper_slbie (target_ulong addr)
2667{
2668 ppc_slb_invalidate_one(env, addr);
2669}
2670
2671#endif /* defined(TARGET_PPC64) */
2672
2673/* TLB management */
2674void helper_tlbia (void)
2675{
2676 ppc_tlb_invalidate_all(env);
2677}
2678
2679void helper_tlbie (target_ulong addr)
2680{
2681 ppc_tlb_invalidate_one(env, addr);
2682}
2683
j_mayer76a66252007-03-07 08:32:30 +00002684/* Software driven TLBs management */
2685/* PowerPC 602/603 software TLB load instructions helpers */
aurel3274d37792008-12-06 21:46:17 +00002686static void do_6xx_tlb (target_ulong new_EPN, int is_code)
j_mayer76a66252007-03-07 08:32:30 +00002687{
2688 target_ulong RPN, CMP, EPN;
2689 int way;
j_mayerd9bce9d2007-03-17 14:02:15 +00002690
j_mayer76a66252007-03-07 08:32:30 +00002691 RPN = env->spr[SPR_RPA];
2692 if (is_code) {
2693 CMP = env->spr[SPR_ICMP];
2694 EPN = env->spr[SPR_IMISS];
2695 } else {
2696 CMP = env->spr[SPR_DCMP];
2697 EPN = env->spr[SPR_DMISS];
2698 }
2699 way = (env->spr[SPR_SRR1] >> 17) & 1;
2700#if defined (DEBUG_SOFTWARE_TLB)
2701 if (loglevel != 0) {
aurel320e698052008-12-08 18:11:42 +00002702 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
j_mayer6b542af2007-11-24 02:03:55 +00002703 " PTE1 " ADDRX " way %d\n",
aurel320e698052008-12-08 18:11:42 +00002704 __func__, new_EPN, EPN, CMP, RPN, way);
j_mayer76a66252007-03-07 08:32:30 +00002705 }
2706#endif
2707 /* Store this TLB */
aurel320f3955e2008-11-30 16:22:56 +00002708 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
j_mayerd9bce9d2007-03-17 14:02:15 +00002709 way, is_code, CMP, RPN);
j_mayer76a66252007-03-07 08:32:30 +00002710}
2711
aurel3274d37792008-12-06 21:46:17 +00002712void helper_6xx_tlbd (target_ulong EPN)
aurel320f3955e2008-11-30 16:22:56 +00002713{
aurel3274d37792008-12-06 21:46:17 +00002714 do_6xx_tlb(EPN, 0);
aurel320f3955e2008-11-30 16:22:56 +00002715}
2716
aurel3274d37792008-12-06 21:46:17 +00002717void helper_6xx_tlbi (target_ulong EPN)
aurel320f3955e2008-11-30 16:22:56 +00002718{
aurel3274d37792008-12-06 21:46:17 +00002719 do_6xx_tlb(EPN, 1);
aurel320f3955e2008-11-30 16:22:56 +00002720}
2721
2722/* PowerPC 74xx software TLB load instructions helpers */
aurel3274d37792008-12-06 21:46:17 +00002723static void do_74xx_tlb (target_ulong new_EPN, int is_code)
j_mayer7dbe11a2007-10-01 05:16:57 +00002724{
2725 target_ulong RPN, CMP, EPN;
2726 int way;
2727
2728 RPN = env->spr[SPR_PTELO];
2729 CMP = env->spr[SPR_PTEHI];
2730 EPN = env->spr[SPR_TLBMISS] & ~0x3;
2731 way = env->spr[SPR_TLBMISS] & 0x3;
2732#if defined (DEBUG_SOFTWARE_TLB)
2733 if (loglevel != 0) {
aurel320e698052008-12-08 18:11:42 +00002734 fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
j_mayer6b542af2007-11-24 02:03:55 +00002735 " PTE1 " ADDRX " way %d\n",
aurel320e698052008-12-08 18:11:42 +00002736 __func__, new_EPN, EPN, CMP, RPN, way);
j_mayer7dbe11a2007-10-01 05:16:57 +00002737 }
2738#endif
2739 /* Store this TLB */
aurel320f3955e2008-11-30 16:22:56 +00002740 ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
j_mayer7dbe11a2007-10-01 05:16:57 +00002741 way, is_code, CMP, RPN);
2742}
2743
aurel3274d37792008-12-06 21:46:17 +00002744void helper_74xx_tlbd (target_ulong EPN)
aurel320f3955e2008-11-30 16:22:56 +00002745{
aurel3274d37792008-12-06 21:46:17 +00002746 do_74xx_tlb(EPN, 0);
aurel320f3955e2008-11-30 16:22:56 +00002747}
2748
aurel3274d37792008-12-06 21:46:17 +00002749void helper_74xx_tlbi (target_ulong EPN)
aurel320f3955e2008-11-30 16:22:56 +00002750{
aurel3274d37792008-12-06 21:46:17 +00002751 do_74xx_tlb(EPN, 1);
aurel320f3955e2008-11-30 16:22:56 +00002752}
2753
j_mayera11b8152007-10-28 00:55:05 +00002754static always_inline target_ulong booke_tlb_to_page_size (int size)
j_mayera8dea122007-03-31 11:33:48 +00002755{
2756 return 1024 << (2 * size);
2757}
2758
j_mayera11b8152007-10-28 00:55:05 +00002759static always_inline int booke_page_size_to_tlb (target_ulong page_size)
j_mayera8dea122007-03-31 11:33:48 +00002760{
2761 int size;
2762
2763 switch (page_size) {
2764 case 0x00000400UL:
2765 size = 0x0;
2766 break;
2767 case 0x00001000UL:
2768 size = 0x1;
2769 break;
2770 case 0x00004000UL:
2771 size = 0x2;
2772 break;
2773 case 0x00010000UL:
2774 size = 0x3;
2775 break;
2776 case 0x00040000UL:
2777 size = 0x4;
2778 break;
2779 case 0x00100000UL:
2780 size = 0x5;
2781 break;
2782 case 0x00400000UL:
2783 size = 0x6;
2784 break;
2785 case 0x01000000UL:
2786 size = 0x7;
2787 break;
2788 case 0x04000000UL:
2789 size = 0x8;
2790 break;
2791 case 0x10000000UL:
2792 size = 0x9;
2793 break;
2794 case 0x40000000UL:
2795 size = 0xA;
2796 break;
2797#if defined (TARGET_PPC64)
2798 case 0x000100000000ULL:
2799 size = 0xB;
2800 break;
2801 case 0x000400000000ULL:
2802 size = 0xC;
2803 break;
2804 case 0x001000000000ULL:
2805 size = 0xD;
2806 break;
2807 case 0x004000000000ULL:
2808 size = 0xE;
2809 break;
2810 case 0x010000000000ULL:
2811 size = 0xF;
2812 break;
2813#endif
2814 default:
2815 size = -1;
2816 break;
2817 }
2818
2819 return size;
2820}
2821
j_mayer76a66252007-03-07 08:32:30 +00002822/* Helpers for 4xx TLB management */
aurel3274d37792008-12-06 21:46:17 +00002823target_ulong helper_4xx_tlbre_lo (target_ulong entry)
j_mayer76a66252007-03-07 08:32:30 +00002824{
j_mayera8dea122007-03-31 11:33:48 +00002825 ppcemb_tlb_t *tlb;
aurel3274d37792008-12-06 21:46:17 +00002826 target_ulong ret;
j_mayera8dea122007-03-31 11:33:48 +00002827 int size;
j_mayer76a66252007-03-07 08:32:30 +00002828
aurel3274d37792008-12-06 21:46:17 +00002829 entry &= 0x3F;
2830 tlb = &env->tlb[entry].tlbe;
2831 ret = tlb->EPN;
j_mayera8dea122007-03-31 11:33:48 +00002832 if (tlb->prot & PAGE_VALID)
aurel3274d37792008-12-06 21:46:17 +00002833 ret |= 0x400;
j_mayera8dea122007-03-31 11:33:48 +00002834 size = booke_page_size_to_tlb(tlb->size);
2835 if (size < 0 || size > 0x7)
2836 size = 1;
aurel3274d37792008-12-06 21:46:17 +00002837 ret |= size << 7;
j_mayera8dea122007-03-31 11:33:48 +00002838 env->spr[SPR_40x_PID] = tlb->PID;
aurel3274d37792008-12-06 21:46:17 +00002839 return ret;
j_mayer76a66252007-03-07 08:32:30 +00002840}
2841
aurel3274d37792008-12-06 21:46:17 +00002842target_ulong helper_4xx_tlbre_hi (target_ulong entry)
j_mayer76a66252007-03-07 08:32:30 +00002843{
j_mayera8dea122007-03-31 11:33:48 +00002844 ppcemb_tlb_t *tlb;
aurel3274d37792008-12-06 21:46:17 +00002845 target_ulong ret;
j_mayer76a66252007-03-07 08:32:30 +00002846
aurel3274d37792008-12-06 21:46:17 +00002847 entry &= 0x3F;
2848 tlb = &env->tlb[entry].tlbe;
2849 ret = tlb->RPN;
j_mayera8dea122007-03-31 11:33:48 +00002850 if (tlb->prot & PAGE_EXEC)
aurel3274d37792008-12-06 21:46:17 +00002851 ret |= 0x200;
j_mayera8dea122007-03-31 11:33:48 +00002852 if (tlb->prot & PAGE_WRITE)
aurel3274d37792008-12-06 21:46:17 +00002853 ret |= 0x100;
2854 return ret;
j_mayer76a66252007-03-07 08:32:30 +00002855}
2856
aurel3274d37792008-12-06 21:46:17 +00002857void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
j_mayer76a66252007-03-07 08:32:30 +00002858{
j_mayera8dea122007-03-31 11:33:48 +00002859 ppcemb_tlb_t *tlb;
j_mayer76a66252007-03-07 08:32:30 +00002860 target_ulong page, end;
2861
j_mayerc55e9ae2007-04-16 09:21:46 +00002862#if defined (DEBUG_SOFTWARE_TLB)
j_mayer6b800552007-04-24 07:36:03 +00002863 if (loglevel != 0) {
aurel320e698052008-12-08 18:11:42 +00002864 fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
j_mayerc55e9ae2007-04-16 09:21:46 +00002865 }
2866#endif
aurel3274d37792008-12-06 21:46:17 +00002867 entry &= 0x3F;
2868 tlb = &env->tlb[entry].tlbe;
j_mayer76a66252007-03-07 08:32:30 +00002869 /* Invalidate previous TLB (if it's valid) */
2870 if (tlb->prot & PAGE_VALID) {
2871 end = tlb->EPN + tlb->size;
j_mayerc55e9ae2007-04-16 09:21:46 +00002872#if defined (DEBUG_SOFTWARE_TLB)
j_mayer6b800552007-04-24 07:36:03 +00002873 if (loglevel != 0) {
j_mayerc55e9ae2007-04-16 09:21:46 +00002874 fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
aurel3274d37792008-12-06 21:46:17 +00002875 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
j_mayerc55e9ae2007-04-16 09:21:46 +00002876 }
2877#endif
j_mayer76a66252007-03-07 08:32:30 +00002878 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2879 tlb_flush_page(env, page);
2880 }
aurel3274d37792008-12-06 21:46:17 +00002881 tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7);
j_mayerc294fc52007-04-24 06:44:14 +00002882 /* We cannot handle TLB size < TARGET_PAGE_SIZE.
2883 * If this ever occurs, one should use the ppcemb target instead
2884 * of the ppc or ppc64 one
2885 */
aurel3274d37792008-12-06 21:46:17 +00002886 if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
j_mayer71c8b8f2007-09-19 05:46:03 +00002887 cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
2888 "are not supported (%d)\n",
aurel3274d37792008-12-06 21:46:17 +00002889 tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
j_mayerc294fc52007-04-24 06:44:14 +00002890 }
aurel3274d37792008-12-06 21:46:17 +00002891 tlb->EPN = val & ~(tlb->size - 1);
2892 if (val & 0x40)
j_mayer76a66252007-03-07 08:32:30 +00002893 tlb->prot |= PAGE_VALID;
2894 else
2895 tlb->prot &= ~PAGE_VALID;
aurel3274d37792008-12-06 21:46:17 +00002896 if (val & 0x20) {
j_mayerc294fc52007-04-24 06:44:14 +00002897 /* XXX: TO BE FIXED */
2898 cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
2899 }
j_mayerc55e9ae2007-04-16 09:21:46 +00002900 tlb->PID = env->spr[SPR_40x_PID]; /* PID */
aurel3274d37792008-12-06 21:46:17 +00002901 tlb->attr = val & 0xFF;
j_mayerc55e9ae2007-04-16 09:21:46 +00002902#if defined (DEBUG_SOFTWARE_TLB)
j_mayerc294fc52007-04-24 06:44:14 +00002903 if (loglevel != 0) {
2904 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
j_mayerc55e9ae2007-04-16 09:21:46 +00002905 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
aurel320e698052008-12-08 18:11:42 +00002906 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
j_mayerc55e9ae2007-04-16 09:21:46 +00002907 tlb->prot & PAGE_READ ? 'r' : '-',
2908 tlb->prot & PAGE_WRITE ? 'w' : '-',
2909 tlb->prot & PAGE_EXEC ? 'x' : '-',
2910 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2911 }
2912#endif
j_mayer76a66252007-03-07 08:32:30 +00002913 /* Invalidate new TLB (if valid) */
2914 if (tlb->prot & PAGE_VALID) {
2915 end = tlb->EPN + tlb->size;
j_mayerc55e9ae2007-04-16 09:21:46 +00002916#if defined (DEBUG_SOFTWARE_TLB)
j_mayer6b800552007-04-24 07:36:03 +00002917 if (loglevel != 0) {
j_mayerc55e9ae2007-04-16 09:21:46 +00002918 fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
aurel320e698052008-12-08 18:11:42 +00002919 " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
j_mayerc55e9ae2007-04-16 09:21:46 +00002920 }
2921#endif
j_mayer76a66252007-03-07 08:32:30 +00002922 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
2923 tlb_flush_page(env, page);
2924 }
j_mayer76a66252007-03-07 08:32:30 +00002925}
2926
aurel3274d37792008-12-06 21:46:17 +00002927void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
j_mayer76a66252007-03-07 08:32:30 +00002928{
j_mayera8dea122007-03-31 11:33:48 +00002929 ppcemb_tlb_t *tlb;
j_mayer76a66252007-03-07 08:32:30 +00002930
j_mayerc55e9ae2007-04-16 09:21:46 +00002931#if defined (DEBUG_SOFTWARE_TLB)
j_mayer6b800552007-04-24 07:36:03 +00002932 if (loglevel != 0) {
aurel320e698052008-12-08 18:11:42 +00002933 fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
j_mayerc55e9ae2007-04-16 09:21:46 +00002934 }
2935#endif
aurel3274d37792008-12-06 21:46:17 +00002936 entry &= 0x3F;
2937 tlb = &env->tlb[entry].tlbe;
2938 tlb->RPN = val & 0xFFFFFC00;
j_mayer76a66252007-03-07 08:32:30 +00002939 tlb->prot = PAGE_READ;
aurel3274d37792008-12-06 21:46:17 +00002940 if (val & 0x200)
j_mayer76a66252007-03-07 08:32:30 +00002941 tlb->prot |= PAGE_EXEC;
aurel3274d37792008-12-06 21:46:17 +00002942 if (val & 0x100)
j_mayer76a66252007-03-07 08:32:30 +00002943 tlb->prot |= PAGE_WRITE;
j_mayerc55e9ae2007-04-16 09:21:46 +00002944#if defined (DEBUG_SOFTWARE_TLB)
j_mayer6b800552007-04-24 07:36:03 +00002945 if (loglevel != 0) {
2946 fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
j_mayerc55e9ae2007-04-16 09:21:46 +00002947 " size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
aurel3274d37792008-12-06 21:46:17 +00002948 (int)entry, tlb->RPN, tlb->EPN, tlb->size,
j_mayerc55e9ae2007-04-16 09:21:46 +00002949 tlb->prot & PAGE_READ ? 'r' : '-',
2950 tlb->prot & PAGE_WRITE ? 'w' : '-',
2951 tlb->prot & PAGE_EXEC ? 'x' : '-',
2952 tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
2953 }
2954#endif
j_mayer76a66252007-03-07 08:32:30 +00002955}
j_mayer5eb79952007-09-19 05:44:04 +00002956
aurel3274d37792008-12-06 21:46:17 +00002957target_ulong helper_4xx_tlbsx (target_ulong address)
2958{
2959 return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
2960}
2961
j_mayera4bb6c32007-09-21 05:28:33 +00002962/* PowerPC 440 TLB management */
aurel3274d37792008-12-06 21:46:17 +00002963void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
j_mayer5eb79952007-09-19 05:44:04 +00002964{
2965 ppcemb_tlb_t *tlb;
j_mayera4bb6c32007-09-21 05:28:33 +00002966 target_ulong EPN, RPN, size;
j_mayer5eb79952007-09-19 05:44:04 +00002967 int do_flush_tlbs;
2968
2969#if defined (DEBUG_SOFTWARE_TLB)
2970 if (loglevel != 0) {
aurel320e698052008-12-08 18:11:42 +00002971 fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
2972 __func__, word, (int)entry, value);
j_mayer5eb79952007-09-19 05:44:04 +00002973 }
2974#endif
2975 do_flush_tlbs = 0;
aurel3274d37792008-12-06 21:46:17 +00002976 entry &= 0x3F;
2977 tlb = &env->tlb[entry].tlbe;
j_mayera4bb6c32007-09-21 05:28:33 +00002978 switch (word) {
2979 default:
2980 /* Just here to please gcc */
2981 case 0:
aurel3274d37792008-12-06 21:46:17 +00002982 EPN = value & 0xFFFFFC00;
j_mayera4bb6c32007-09-21 05:28:33 +00002983 if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
j_mayer5eb79952007-09-19 05:44:04 +00002984 do_flush_tlbs = 1;
j_mayera4bb6c32007-09-21 05:28:33 +00002985 tlb->EPN = EPN;
aurel3274d37792008-12-06 21:46:17 +00002986 size = booke_tlb_to_page_size((value >> 4) & 0xF);
j_mayera4bb6c32007-09-21 05:28:33 +00002987 if ((tlb->prot & PAGE_VALID) && tlb->size < size)
2988 do_flush_tlbs = 1;
2989 tlb->size = size;
2990 tlb->attr &= ~0x1;
aurel3274d37792008-12-06 21:46:17 +00002991 tlb->attr |= (value >> 8) & 1;
2992 if (value & 0x200) {
j_mayera4bb6c32007-09-21 05:28:33 +00002993 tlb->prot |= PAGE_VALID;
2994 } else {
2995 if (tlb->prot & PAGE_VALID) {
2996 tlb->prot &= ~PAGE_VALID;
2997 do_flush_tlbs = 1;
2998 }
j_mayer5eb79952007-09-19 05:44:04 +00002999 }
j_mayera4bb6c32007-09-21 05:28:33 +00003000 tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
3001 if (do_flush_tlbs)
3002 tlb_flush(env, 1);
3003 break;
3004 case 1:
aurel3274d37792008-12-06 21:46:17 +00003005 RPN = value & 0xFFFFFC0F;
j_mayera4bb6c32007-09-21 05:28:33 +00003006 if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
3007 tlb_flush(env, 1);
3008 tlb->RPN = RPN;
3009 break;
3010 case 2:
aurel3274d37792008-12-06 21:46:17 +00003011 tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
j_mayera4bb6c32007-09-21 05:28:33 +00003012 tlb->prot = tlb->prot & PAGE_VALID;
aurel3274d37792008-12-06 21:46:17 +00003013 if (value & 0x1)
j_mayera4bb6c32007-09-21 05:28:33 +00003014 tlb->prot |= PAGE_READ << 4;
aurel3274d37792008-12-06 21:46:17 +00003015 if (value & 0x2)
j_mayera4bb6c32007-09-21 05:28:33 +00003016 tlb->prot |= PAGE_WRITE << 4;
aurel3274d37792008-12-06 21:46:17 +00003017 if (value & 0x4)
j_mayera4bb6c32007-09-21 05:28:33 +00003018 tlb->prot |= PAGE_EXEC << 4;
aurel3274d37792008-12-06 21:46:17 +00003019 if (value & 0x8)
j_mayera4bb6c32007-09-21 05:28:33 +00003020 tlb->prot |= PAGE_READ;
aurel3274d37792008-12-06 21:46:17 +00003021 if (value & 0x10)
j_mayera4bb6c32007-09-21 05:28:33 +00003022 tlb->prot |= PAGE_WRITE;
aurel3274d37792008-12-06 21:46:17 +00003023 if (value & 0x20)
j_mayera4bb6c32007-09-21 05:28:33 +00003024 tlb->prot |= PAGE_EXEC;
3025 break;
j_mayer5eb79952007-09-19 05:44:04 +00003026 }
j_mayer5eb79952007-09-19 05:44:04 +00003027}
3028
aurel3274d37792008-12-06 21:46:17 +00003029target_ulong helper_440_tlbre (uint32_t word, target_ulong entry)
j_mayer5eb79952007-09-19 05:44:04 +00003030{
3031 ppcemb_tlb_t *tlb;
aurel3274d37792008-12-06 21:46:17 +00003032 target_ulong ret;
j_mayer5eb79952007-09-19 05:44:04 +00003033 int size;
3034
aurel3274d37792008-12-06 21:46:17 +00003035 entry &= 0x3F;
3036 tlb = &env->tlb[entry].tlbe;
j_mayera4bb6c32007-09-21 05:28:33 +00003037 switch (word) {
3038 default:
3039 /* Just here to please gcc */
3040 case 0:
aurel3274d37792008-12-06 21:46:17 +00003041 ret = tlb->EPN;
j_mayera4bb6c32007-09-21 05:28:33 +00003042 size = booke_page_size_to_tlb(tlb->size);
3043 if (size < 0 || size > 0xF)
3044 size = 1;
aurel3274d37792008-12-06 21:46:17 +00003045 ret |= size << 4;
j_mayera4bb6c32007-09-21 05:28:33 +00003046 if (tlb->attr & 0x1)
aurel3274d37792008-12-06 21:46:17 +00003047 ret |= 0x100;
j_mayera4bb6c32007-09-21 05:28:33 +00003048 if (tlb->prot & PAGE_VALID)
aurel3274d37792008-12-06 21:46:17 +00003049 ret |= 0x200;
j_mayera4bb6c32007-09-21 05:28:33 +00003050 env->spr[SPR_440_MMUCR] &= ~0x000000FF;
3051 env->spr[SPR_440_MMUCR] |= tlb->PID;
3052 break;
3053 case 1:
aurel3274d37792008-12-06 21:46:17 +00003054 ret = tlb->RPN;
j_mayera4bb6c32007-09-21 05:28:33 +00003055 break;
3056 case 2:
aurel3274d37792008-12-06 21:46:17 +00003057 ret = tlb->attr & ~0x1;
j_mayera4bb6c32007-09-21 05:28:33 +00003058 if (tlb->prot & (PAGE_READ << 4))
aurel3274d37792008-12-06 21:46:17 +00003059 ret |= 0x1;
j_mayera4bb6c32007-09-21 05:28:33 +00003060 if (tlb->prot & (PAGE_WRITE << 4))
aurel3274d37792008-12-06 21:46:17 +00003061 ret |= 0x2;
j_mayera4bb6c32007-09-21 05:28:33 +00003062 if (tlb->prot & (PAGE_EXEC << 4))
aurel3274d37792008-12-06 21:46:17 +00003063 ret |= 0x4;
j_mayera4bb6c32007-09-21 05:28:33 +00003064 if (tlb->prot & PAGE_READ)
aurel3274d37792008-12-06 21:46:17 +00003065 ret |= 0x8;
j_mayera4bb6c32007-09-21 05:28:33 +00003066 if (tlb->prot & PAGE_WRITE)
aurel3274d37792008-12-06 21:46:17 +00003067 ret |= 0x10;
j_mayera4bb6c32007-09-21 05:28:33 +00003068 if (tlb->prot & PAGE_EXEC)
aurel3274d37792008-12-06 21:46:17 +00003069 ret |= 0x20;
j_mayera4bb6c32007-09-21 05:28:33 +00003070 break;
3071 }
aurel3274d37792008-12-06 21:46:17 +00003072 return ret;
j_mayer5eb79952007-09-19 05:44:04 +00003073}
aurel3274d37792008-12-06 21:46:17 +00003074
3075target_ulong helper_440_tlbsx (target_ulong address)
3076{
3077 return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
3078}
3079
j_mayer76a66252007-03-07 08:32:30 +00003080#endif /* !CONFIG_USER_ONLY */