blob: bef0d7d69a79bab6348b81d99787bab548935dfd [file] [log] [blame]
thsd34cab92007-04-02 01:10:46 +00001/*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Markus Armbruster0b8fa322019-05-23 16:35:07 +020024
Peter Maydell47df5152016-01-26 18:17:13 +000025#include "qemu/osdep.h"
Markus Armbruster0b8fa322019-05-23 16:35:07 +020026#include "qemu/module.h"
Philippe Mathieu-Daudéf0353b02018-06-25 09:42:06 -030027#include "qemu/units.h"
Markus Armbrusterda34e652016-03-14 09:01:28 +010028#include "qapi/error.h"
Philippe Mathieu-Daudéaa0fd162020-05-26 08:22:48 +020029#include "qemu/log.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010030#include "hw/loader.h"
Stefan Weilac860482013-11-10 14:20:16 +010031#include "trace.h"
Peter Lieven2f487a3d2014-03-17 18:38:58 +010032#include "ui/vnc.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010033#include "hw/pci/pci.h"
Markus Armbrustera27bd6c2019-08-12 07:23:51 +020034#include "hw/qdev-properties.h"
Markus Armbrusterd6454272019-08-12 07:23:45 +020035#include "migration/vmstate.h"
Eduardo Habkostdb1015e2020-09-03 16:43:22 -040036#include "qom/object.h"
thsd34cab92007-04-02 01:10:46 +000037
Jan Kiszkaca0508d2011-08-22 19:12:09 +020038#undef VERBOSE
thsd34cab92007-04-02 01:10:46 +000039#define HW_RECT_ACCEL
40#define HW_FILL_ACCEL
41#define HW_MOUSE_ACCEL
42
Paolo Bonzini47b43a12013-03-18 17:36:02 +010043#include "vga_int.h"
BALATON Zoltan5b9575c2012-11-03 12:47:08 +010044
45/* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */
thsd34cab92007-04-02 01:10:46 +000046
47struct vmsvga_state_s {
Avi Kivity4e12cd92009-05-03 22:25:16 +030048 VGACommonState vga;
thsd34cab92007-04-02 01:10:46 +000049
thsd34cab92007-04-02 01:10:46 +000050 int invalidated;
thsd34cab92007-04-02 01:10:46 +000051 int enable;
52 int config;
53 struct {
54 int id;
55 int x;
56 int y;
57 int on;
58 } cursor;
59
thsd34cab92007-04-02 01:10:46 +000060 int index;
61 int scratch_size;
62 uint32_t *scratch;
63 int new_width;
64 int new_height;
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +010065 int new_depth;
thsd34cab92007-04-02 01:10:46 +000066 uint32_t guest;
67 uint32_t svgaid;
thsd34cab92007-04-02 01:10:46 +000068 int syncing;
thsd34cab92007-04-02 01:10:46 +000069
Avi Kivityb1950432011-08-08 16:08:57 +030070 MemoryRegion fifo_ram;
Dave Airlief351d052009-12-18 08:08:06 +100071 uint8_t *fifo_ptr;
72 unsigned int fifo_size;
Dave Airlief351d052009-12-18 08:08:06 +100073
Gerd Hoffmann7e486f72016-05-30 09:09:20 +020074 uint32_t *fifo;
75 uint32_t fifo_min;
76 uint32_t fifo_max;
77 uint32_t fifo_next;
78 uint32_t fifo_stop;
thsd34cab92007-04-02 01:10:46 +000079
BALATON Zoltan0d793792012-11-03 12:47:08 +010080#define REDRAW_FIFO_LEN 512
thsd34cab92007-04-02 01:10:46 +000081 struct vmsvga_rect_s {
82 int x, y, w, h;
83 } redraw_fifo[REDRAW_FIFO_LEN];
84 int redraw_fifo_first, redraw_fifo_last;
85};
86
Peter Crosthwaite39d45982013-06-24 16:58:45 +100087#define TYPE_VMWARE_SVGA "vmware-svga"
88
Eduardo Habkost8110fa12020-08-31 17:07:33 -040089DECLARE_INSTANCE_CHECKER(struct pci_vmsvga_state_s, VMWARE_SVGA,
90 TYPE_VMWARE_SVGA)
Peter Crosthwaite39d45982013-06-24 16:58:45 +100091
thsd34cab92007-04-02 01:10:46 +000092struct pci_vmsvga_state_s {
Andreas Färberaf21c742013-06-30 15:01:36 +020093 /*< private >*/
94 PCIDevice parent_obj;
95 /*< public >*/
96
thsd34cab92007-04-02 01:10:46 +000097 struct vmsvga_state_s chip;
Avi Kivityb1950432011-08-08 16:08:57 +030098 MemoryRegion io_bar;
thsd34cab92007-04-02 01:10:46 +000099};
100
BALATON Zoltan0d793792012-11-03 12:47:08 +0100101#define SVGA_MAGIC 0x900000UL
102#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
103#define SVGA_ID_0 SVGA_MAKE_ID(0)
104#define SVGA_ID_1 SVGA_MAKE_ID(1)
105#define SVGA_ID_2 SVGA_MAKE_ID(2)
thsd34cab92007-04-02 01:10:46 +0000106
BALATON Zoltan0d793792012-11-03 12:47:08 +0100107#define SVGA_LEGACY_BASE_PORT 0x4560
108#define SVGA_INDEX_PORT 0x0
109#define SVGA_VALUE_PORT 0x1
110#define SVGA_BIOS_PORT 0x2
thsd34cab92007-04-02 01:10:46 +0000111
112#define SVGA_VERSION_2
113
114#ifdef SVGA_VERSION_2
BALATON Zoltan0d793792012-11-03 12:47:08 +0100115# define SVGA_ID SVGA_ID_2
116# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
117# define SVGA_IO_MUL 1
118# define SVGA_FIFO_SIZE 0x10000
119# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
thsd34cab92007-04-02 01:10:46 +0000120#else
BALATON Zoltan0d793792012-11-03 12:47:08 +0100121# define SVGA_ID SVGA_ID_1
122# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
123# define SVGA_IO_MUL 4
124# define SVGA_FIFO_SIZE 0x10000
125# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
thsd34cab92007-04-02 01:10:46 +0000126#endif
127
128enum {
129 /* ID 0, 1 and 2 registers */
130 SVGA_REG_ID = 0,
131 SVGA_REG_ENABLE = 1,
132 SVGA_REG_WIDTH = 2,
133 SVGA_REG_HEIGHT = 3,
134 SVGA_REG_MAX_WIDTH = 4,
135 SVGA_REG_MAX_HEIGHT = 5,
136 SVGA_REG_DEPTH = 6,
BALATON Zoltan0d793792012-11-03 12:47:08 +0100137 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
thsd34cab92007-04-02 01:10:46 +0000138 SVGA_REG_PSEUDOCOLOR = 8,
139 SVGA_REG_RED_MASK = 9,
140 SVGA_REG_GREEN_MASK = 10,
141 SVGA_REG_BLUE_MASK = 11,
142 SVGA_REG_BYTES_PER_LINE = 12,
143 SVGA_REG_FB_START = 13,
144 SVGA_REG_FB_OFFSET = 14,
145 SVGA_REG_VRAM_SIZE = 15,
146 SVGA_REG_FB_SIZE = 16,
147
148 /* ID 1 and 2 registers */
149 SVGA_REG_CAPABILITIES = 17,
BALATON Zoltan0d793792012-11-03 12:47:08 +0100150 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
thsd34cab92007-04-02 01:10:46 +0000151 SVGA_REG_MEM_SIZE = 19,
BALATON Zoltan0d793792012-11-03 12:47:08 +0100152 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
153 SVGA_REG_SYNC = 21, /* Write to force synchronization */
154 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
155 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
156 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
157 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
158 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
159 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
160 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
161 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
162 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
163 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
164 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
thsd34cab92007-04-02 01:10:46 +0000165
BALATON Zoltan0d793792012-11-03 12:47:08 +0100166 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
thsd34cab92007-04-02 01:10:46 +0000167 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
168 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
169};
170
BALATON Zoltan0d793792012-11-03 12:47:08 +0100171#define SVGA_CAP_NONE 0
172#define SVGA_CAP_RECT_FILL (1 << 0)
173#define SVGA_CAP_RECT_COPY (1 << 1)
174#define SVGA_CAP_RECT_PAT_FILL (1 << 2)
175#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
176#define SVGA_CAP_RASTER_OP (1 << 4)
177#define SVGA_CAP_CURSOR (1 << 5)
178#define SVGA_CAP_CURSOR_BYPASS (1 << 6)
179#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
180#define SVGA_CAP_8BIT_EMULATION (1 << 8)
181#define SVGA_CAP_ALPHA_CURSOR (1 << 9)
182#define SVGA_CAP_GLYPH (1 << 10)
183#define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
184#define SVGA_CAP_OFFSCREEN_1 (1 << 12)
185#define SVGA_CAP_ALPHA_BLEND (1 << 13)
186#define SVGA_CAP_3D (1 << 14)
187#define SVGA_CAP_EXTENDED_FIFO (1 << 15)
188#define SVGA_CAP_MULTIMON (1 << 16)
189#define SVGA_CAP_PITCHLOCK (1 << 17)
thsd34cab92007-04-02 01:10:46 +0000190
191/*
192 * FIFO offsets (seen as an array of 32-bit words)
193 */
194enum {
195 /*
196 * The original defined FIFO offsets
197 */
198 SVGA_FIFO_MIN = 0,
BALATON Zoltan0d793792012-11-03 12:47:08 +0100199 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
Gerd Hoffmann7e486f72016-05-30 09:09:20 +0200200 SVGA_FIFO_NEXT,
thsd34cab92007-04-02 01:10:46 +0000201 SVGA_FIFO_STOP,
202
203 /*
204 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
205 */
206 SVGA_FIFO_CAPABILITIES = 4,
207 SVGA_FIFO_FLAGS,
208 SVGA_FIFO_FENCE,
209 SVGA_FIFO_3D_HWVERSION,
210 SVGA_FIFO_PITCHLOCK,
211};
212
BALATON Zoltan0d793792012-11-03 12:47:08 +0100213#define SVGA_FIFO_CAP_NONE 0
214#define SVGA_FIFO_CAP_FENCE (1 << 0)
215#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
216#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
thsd34cab92007-04-02 01:10:46 +0000217
BALATON Zoltan0d793792012-11-03 12:47:08 +0100218#define SVGA_FIFO_FLAG_NONE 0
219#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
thsd34cab92007-04-02 01:10:46 +0000220
221/* These values can probably be changed arbitrarily. */
BALATON Zoltan0d793792012-11-03 12:47:08 +0100222#define SVGA_SCRATCH_SIZE 0x8000
Peter Lieven2f487a3d2014-03-17 18:38:58 +0100223#define SVGA_MAX_WIDTH ROUND_UP(2360, VNC_DIRTY_PIXELS_PER_BIT)
BALATON Zoltan0d793792012-11-03 12:47:08 +0100224#define SVGA_MAX_HEIGHT 1770
thsd34cab92007-04-02 01:10:46 +0000225
226#ifdef VERBOSE
BALATON Zoltan0d793792012-11-03 12:47:08 +0100227# define GUEST_OS_BASE 0x5001
thsd34cab92007-04-02 01:10:46 +0000228static const char *vmsvga_guest_id[] = {
balrogf707cfb2007-05-13 13:26:49 +0000229 [0x00] = "Dos",
230 [0x01] = "Windows 3.1",
231 [0x02] = "Windows 95",
232 [0x03] = "Windows 98",
233 [0x04] = "Windows ME",
234 [0x05] = "Windows NT",
235 [0x06] = "Windows 2000",
236 [0x07] = "Linux",
237 [0x08] = "OS/2",
blueswir1511d2b12009-03-07 15:32:56 +0000238 [0x09] = "an unknown OS",
balrogf707cfb2007-05-13 13:26:49 +0000239 [0x0a] = "BSD",
240 [0x0b] = "Whistler",
blueswir1511d2b12009-03-07 15:32:56 +0000241 [0x0c] = "an unknown OS",
242 [0x0d] = "an unknown OS",
243 [0x0e] = "an unknown OS",
244 [0x0f] = "an unknown OS",
245 [0x10] = "an unknown OS",
246 [0x11] = "an unknown OS",
247 [0x12] = "an unknown OS",
248 [0x13] = "an unknown OS",
249 [0x14] = "an unknown OS",
balrogf707cfb2007-05-13 13:26:49 +0000250 [0x15] = "Windows 2003",
thsd34cab92007-04-02 01:10:46 +0000251};
252#endif
253
254enum {
255 SVGA_CMD_INVALID_CMD = 0,
256 SVGA_CMD_UPDATE = 1,
257 SVGA_CMD_RECT_FILL = 2,
258 SVGA_CMD_RECT_COPY = 3,
259 SVGA_CMD_DEFINE_BITMAP = 4,
260 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
261 SVGA_CMD_DEFINE_PIXMAP = 6,
262 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
263 SVGA_CMD_RECT_BITMAP_FILL = 8,
264 SVGA_CMD_RECT_PIXMAP_FILL = 9,
265 SVGA_CMD_RECT_BITMAP_COPY = 10,
266 SVGA_CMD_RECT_PIXMAP_COPY = 11,
267 SVGA_CMD_FREE_OBJECT = 12,
268 SVGA_CMD_RECT_ROP_FILL = 13,
269 SVGA_CMD_RECT_ROP_COPY = 14,
270 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
271 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
272 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
273 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
274 SVGA_CMD_DEFINE_CURSOR = 19,
275 SVGA_CMD_DISPLAY_CURSOR = 20,
276 SVGA_CMD_MOVE_CURSOR = 21,
277 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
278 SVGA_CMD_DRAW_GLYPH = 23,
279 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
280 SVGA_CMD_UPDATE_VERBOSE = 25,
281 SVGA_CMD_SURFACE_FILL = 26,
282 SVGA_CMD_SURFACE_COPY = 27,
283 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
284 SVGA_CMD_FRONT_ROP_FILL = 29,
285 SVGA_CMD_FENCE = 30,
286};
287
288/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
289enum {
290 SVGA_CURSOR_ON_HIDE = 0,
291 SVGA_CURSOR_ON_SHOW = 1,
292 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
293 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
294};
295
Gerd Hoffmann07258902014-10-06 11:51:54 +0200296static inline bool vmsvga_verify_rect(DisplaySurface *surface,
297 const char *name,
298 int x, int y, int w, int h)
299{
300 if (x < 0) {
301 fprintf(stderr, "%s: x was < 0 (%d)\n", name, x);
302 return false;
303 }
304 if (x > SVGA_MAX_WIDTH) {
305 fprintf(stderr, "%s: x was > %d (%d)\n", name, SVGA_MAX_WIDTH, x);
306 return false;
307 }
308 if (w < 0) {
309 fprintf(stderr, "%s: w was < 0 (%d)\n", name, w);
310 return false;
311 }
312 if (w > SVGA_MAX_WIDTH) {
313 fprintf(stderr, "%s: w was > %d (%d)\n", name, SVGA_MAX_WIDTH, w);
314 return false;
315 }
316 if (x + w > surface_width(surface)) {
317 fprintf(stderr, "%s: width was > %d (x: %d, w: %d)\n",
318 name, surface_width(surface), x, w);
319 return false;
320 }
321
322 if (y < 0) {
323 fprintf(stderr, "%s: y was < 0 (%d)\n", name, y);
324 return false;
325 }
326 if (y > SVGA_MAX_HEIGHT) {
327 fprintf(stderr, "%s: y was > %d (%d)\n", name, SVGA_MAX_HEIGHT, y);
328 return false;
329 }
330 if (h < 0) {
331 fprintf(stderr, "%s: h was < 0 (%d)\n", name, h);
332 return false;
333 }
334 if (h > SVGA_MAX_HEIGHT) {
335 fprintf(stderr, "%s: h was > %d (%d)\n", name, SVGA_MAX_HEIGHT, h);
336 return false;
337 }
338 if (y + h > surface_height(surface)) {
339 fprintf(stderr, "%s: update height > %d (y: %d, h: %d)\n",
340 name, surface_height(surface), y, h);
341 return false;
342 }
343
344 return true;
345}
346
thsd34cab92007-04-02 01:10:46 +0000347static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
Gerd Hoffmann07258902014-10-06 11:51:54 +0200348 int x, int y, int w, int h)
thsd34cab92007-04-02 01:10:46 +0000349{
Gerd Hoffmannc78f7132013-03-05 15:24:14 +0100350 DisplaySurface *surface = qemu_console_surface(s->vga.con);
balroga8fbaf92008-03-06 20:43:34 +0000351 int line;
352 int bypl;
353 int width;
354 int start;
355 uint8_t *src;
356 uint8_t *dst;
357
Gerd Hoffmann1735fe12014-10-06 11:58:22 +0200358 if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) {
359 /* go for a fullscreen update as fallback */
Michael Tokarev8cb6bfb2013-01-25 21:23:24 +0400360 x = 0;
Michael Tokarev8cb6bfb2013-01-25 21:23:24 +0400361 y = 0;
Gerd Hoffmann1735fe12014-10-06 11:58:22 +0200362 w = surface_width(surface);
363 h = surface_height(surface);
balroga8fbaf92008-03-06 20:43:34 +0000364 }
365
Gerd Hoffmannc78f7132013-03-05 15:24:14 +0100366 bypl = surface_stride(surface);
367 width = surface_bytes_per_pixel(surface) * w;
368 start = surface_bytes_per_pixel(surface) * x + bypl * y;
Avi Kivity4e12cd92009-05-03 22:25:16 +0300369 src = s->vga.vram_ptr + start;
Gerd Hoffmannc78f7132013-03-05 15:24:14 +0100370 dst = surface_data(surface) + start;
thsd34cab92007-04-02 01:10:46 +0000371
BALATON Zoltan0d793792012-11-03 12:47:08 +0100372 for (line = h; line > 0; line--, src += bypl, dst += bypl) {
thsd34cab92007-04-02 01:10:46 +0000373 memcpy(dst, src, width);
BALATON Zoltan0d793792012-11-03 12:47:08 +0100374 }
Gerd Hoffmannc78f7132013-03-05 15:24:14 +0100375 dpy_gfx_update(s->vga.con, x, y, w, h);
thsd34cab92007-04-02 01:10:46 +0000376}
377
thsd34cab92007-04-02 01:10:46 +0000378static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
379 int x, int y, int w, int h)
380{
BALATON Zoltan0d793792012-11-03 12:47:08 +0100381 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++];
382
thsd34cab92007-04-02 01:10:46 +0000383 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
384 rect->x = x;
385 rect->y = y;
386 rect->w = w;
387 rect->h = h;
388}
thsd34cab92007-04-02 01:10:46 +0000389
390static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
391{
392 struct vmsvga_rect_s *rect;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100393
thsd34cab92007-04-02 01:10:46 +0000394 if (s->invalidated) {
395 s->redraw_fifo_first = s->redraw_fifo_last;
396 return;
397 }
398 /* Overlapping region updates can be optimised out here - if someone
399 * knows a smart algorithm to do that, please share. */
400 while (s->redraw_fifo_first != s->redraw_fifo_last) {
BALATON Zoltan0d793792012-11-03 12:47:08 +0100401 rect = &s->redraw_fifo[s->redraw_fifo_first++];
thsd34cab92007-04-02 01:10:46 +0000402 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
403 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
404 }
405}
406
407#ifdef HW_RECT_ACCEL
Gerd Hoffmann61b41b42014-10-06 11:58:51 +0200408static inline int vmsvga_copy_rect(struct vmsvga_state_s *s,
thsd34cab92007-04-02 01:10:46 +0000409 int x0, int y0, int x1, int y1, int w, int h)
410{
Gerd Hoffmannc78f7132013-03-05 15:24:14 +0100411 DisplaySurface *surface = qemu_console_surface(s->vga.con);
Avi Kivity4e12cd92009-05-03 22:25:16 +0300412 uint8_t *vram = s->vga.vram_ptr;
Gerd Hoffmannc78f7132013-03-05 15:24:14 +0100413 int bypl = surface_stride(surface);
414 int bypp = surface_bytes_per_pixel(surface);
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100415 int width = bypp * w;
thsd34cab92007-04-02 01:10:46 +0000416 int line = h;
417 uint8_t *ptr[2];
418
Gerd Hoffmann61b41b42014-10-06 11:58:51 +0200419 if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/src", x0, y0, w, h)) {
420 return -1;
421 }
422 if (!vmsvga_verify_rect(surface, "vmsvga_copy_rect/dst", x1, y1, w, h)) {
423 return -1;
424 }
425
Jan Kiszka8d121d42011-08-22 19:12:10 +0200426 if (y1 > y0) {
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100427 ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1);
428 ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1);
Jan Kiszka8d121d42011-08-22 19:12:10 +0200429 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) {
430 memmove(ptr[1], ptr[0], width);
431 }
432 } else {
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100433 ptr[0] = vram + bypp * x0 + bypl * y0;
434 ptr[1] = vram + bypp * x1 + bypl * y1;
Jan Kiszka8d121d42011-08-22 19:12:10 +0200435 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) {
436 memmove(ptr[1], ptr[0], width);
thsd34cab92007-04-02 01:10:46 +0000437 }
438 }
439
440 vmsvga_update_rect_delayed(s, x1, y1, w, h);
Gerd Hoffmann61b41b42014-10-06 11:58:51 +0200441 return 0;
thsd34cab92007-04-02 01:10:46 +0000442}
443#endif
444
445#ifdef HW_FILL_ACCEL
Gerd Hoffmannbd9ccd82014-10-06 11:59:51 +0200446static inline int vmsvga_fill_rect(struct vmsvga_state_s *s,
thsd34cab92007-04-02 01:10:46 +0000447 uint32_t c, int x, int y, int w, int h)
448{
Gerd Hoffmannc78f7132013-03-05 15:24:14 +0100449 DisplaySurface *surface = qemu_console_surface(s->vga.con);
450 int bypl = surface_stride(surface);
451 int width = surface_bytes_per_pixel(surface) * w;
thsd34cab92007-04-02 01:10:46 +0000452 int line = h;
453 int column;
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100454 uint8_t *fst;
thsd34cab92007-04-02 01:10:46 +0000455 uint8_t *dst;
456 uint8_t *src;
457 uint8_t col[4];
458
Gerd Hoffmannbd9ccd82014-10-06 11:59:51 +0200459 if (!vmsvga_verify_rect(surface, __func__, x, y, w, h)) {
460 return -1;
461 }
462
Jan Kiszka8d121d42011-08-22 19:12:10 +0200463 col[0] = c;
464 col[1] = c >> 8;
465 col[2] = c >> 16;
466 col[3] = c >> 24;
thsd34cab92007-04-02 01:10:46 +0000467
Gerd Hoffmannc78f7132013-03-05 15:24:14 +0100468 fst = s->vga.vram_ptr + surface_bytes_per_pixel(surface) * x + bypl * y;
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100469
Jan Kiszka8d121d42011-08-22 19:12:10 +0200470 if (line--) {
471 dst = fst;
472 src = col;
473 for (column = width; column > 0; column--) {
474 *(dst++) = *(src++);
Gerd Hoffmannc78f7132013-03-05 15:24:14 +0100475 if (src - col == surface_bytes_per_pixel(surface)) {
Jan Kiszka8d121d42011-08-22 19:12:10 +0200476 src = col;
thsd34cab92007-04-02 01:10:46 +0000477 }
Jan Kiszka8d121d42011-08-22 19:12:10 +0200478 }
479 dst = fst;
480 for (; line > 0; line--) {
481 dst += bypl;
482 memcpy(dst, fst, width);
thsd34cab92007-04-02 01:10:46 +0000483 }
484 }
485
486 vmsvga_update_rect_delayed(s, x, y, w, h);
Gerd Hoffmannbd9ccd82014-10-06 11:59:51 +0200487 return 0;
thsd34cab92007-04-02 01:10:46 +0000488}
489#endif
490
491struct vmsvga_cursor_definition_s {
Gerd Hoffmann5829b092015-09-29 09:58:05 +0200492 uint32_t width;
493 uint32_t height;
thsd34cab92007-04-02 01:10:46 +0000494 int id;
Gerd Hoffmann5829b092015-09-29 09:58:05 +0200495 uint32_t bpp;
thsd34cab92007-04-02 01:10:46 +0000496 int hot_x;
497 int hot_y;
498 uint32_t mask[1024];
Dave Airlie8095cb32009-12-18 08:08:11 +1000499 uint32_t image[4096];
thsd34cab92007-04-02 01:10:46 +0000500};
501
BALATON Zoltan0d793792012-11-03 12:47:08 +0100502#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
503#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
thsd34cab92007-04-02 01:10:46 +0000504
505#ifdef HW_MOUSE_ACCEL
506static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
507 struct vmsvga_cursor_definition_s *c)
508{
Gerd Hoffmannfbe6d7a2010-05-21 11:54:33 +0200509 QEMUCursor *qc;
510 int i, pixels;
511
512 qc = cursor_alloc(c->width, c->height);
513 qc->hot_x = c->hot_x;
514 qc->hot_y = c->hot_y;
515 switch (c->bpp) {
516 case 1:
BALATON Zoltan0d793792012-11-03 12:47:08 +0100517 cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image,
518 1, (void *)c->mask);
Gerd Hoffmannfbe6d7a2010-05-21 11:54:33 +0200519#ifdef DEBUG
520 cursor_print_ascii_art(qc, "vmware/mono");
521#endif
522 break;
523 case 32:
524 /* fill alpha channel from mask, set color to zero */
BALATON Zoltan0d793792012-11-03 12:47:08 +0100525 cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask,
526 1, (void *)c->mask);
Gerd Hoffmannfbe6d7a2010-05-21 11:54:33 +0200527 /* add in rgb values */
528 pixels = c->width * c->height;
529 for (i = 0; i < pixels; i++) {
530 qc->data[i] |= c->image[i] & 0xffffff;
531 }
532#ifdef DEBUG
533 cursor_print_ascii_art(qc, "vmware/32bit");
534#endif
535 break;
536 default:
537 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
BALATON Zoltan0d793792012-11-03 12:47:08 +0100538 __func__, c->bpp);
Gerd Hoffmannfbe6d7a2010-05-21 11:54:33 +0200539 cursor_put(qc);
540 qc = cursor_builtin_left_ptr();
541 }
thsd34cab92007-04-02 01:10:46 +0000542
Gerd Hoffmannc78f7132013-03-05 15:24:14 +0100543 dpy_cursor_define(s->vga.con, qc);
Gerd Hoffmannfbe6d7a2010-05-21 11:54:33 +0200544 cursor_put(qc);
thsd34cab92007-04-02 01:10:46 +0000545}
546#endif
547
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200548static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
thsd34cab92007-04-02 01:10:46 +0000549{
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200550 int num;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100551
552 if (!s->config || !s->enable) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200553 return 0;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100554 }
Gerd Hoffmann52136022016-05-30 09:09:18 +0200555
Gerd Hoffmann7e486f72016-05-30 09:09:20 +0200556 s->fifo_min = le32_to_cpu(s->fifo[SVGA_FIFO_MIN]);
557 s->fifo_max = le32_to_cpu(s->fifo[SVGA_FIFO_MAX]);
558 s->fifo_next = le32_to_cpu(s->fifo[SVGA_FIFO_NEXT]);
559 s->fifo_stop = le32_to_cpu(s->fifo[SVGA_FIFO_STOP]);
560
Gerd Hoffmann52136022016-05-30 09:09:18 +0200561 /* Check range and alignment. */
Gerd Hoffmann7e486f72016-05-30 09:09:20 +0200562 if ((s->fifo_min | s->fifo_max | s->fifo_next | s->fifo_stop) & 3) {
Gerd Hoffmann52136022016-05-30 09:09:18 +0200563 return 0;
564 }
Gerd Hoffmann7e486f72016-05-30 09:09:20 +0200565 if (s->fifo_min < sizeof(uint32_t) * 4) {
Gerd Hoffmann52136022016-05-30 09:09:18 +0200566 return 0;
567 }
Gerd Hoffmann7e486f72016-05-30 09:09:20 +0200568 if (s->fifo_max > SVGA_FIFO_SIZE ||
569 s->fifo_min >= SVGA_FIFO_SIZE ||
570 s->fifo_stop >= SVGA_FIFO_SIZE ||
571 s->fifo_next >= SVGA_FIFO_SIZE) {
Gerd Hoffmann52136022016-05-30 09:09:18 +0200572 return 0;
573 }
Philippe Mathieu-Daudéf0353b02018-06-25 09:42:06 -0300574 if (s->fifo_max < s->fifo_min + 10 * KiB) {
Gerd Hoffmann52136022016-05-30 09:09:18 +0200575 return 0;
576 }
577
Gerd Hoffmann7e486f72016-05-30 09:09:20 +0200578 num = s->fifo_next - s->fifo_stop;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100579 if (num < 0) {
Gerd Hoffmann7e486f72016-05-30 09:09:20 +0200580 num += s->fifo_max - s->fifo_min;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100581 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200582 return num >> 2;
thsd34cab92007-04-02 01:10:46 +0000583}
584
balrogff9cf2c2008-07-16 04:45:12 +0000585static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
thsd34cab92007-04-02 01:10:46 +0000586{
Gerd Hoffmann7e486f72016-05-30 09:09:20 +0200587 uint32_t cmd = s->fifo[s->fifo_stop >> 2];
BALATON Zoltan0d793792012-11-03 12:47:08 +0100588
Gerd Hoffmann7e486f72016-05-30 09:09:20 +0200589 s->fifo_stop += 4;
590 if (s->fifo_stop >= s->fifo_max) {
591 s->fifo_stop = s->fifo_min;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100592 }
Gerd Hoffmann7e486f72016-05-30 09:09:20 +0200593 s->fifo[SVGA_FIFO_STOP] = cpu_to_le32(s->fifo_stop);
thsd34cab92007-04-02 01:10:46 +0000594 return cmd;
595}
596
balrogff9cf2c2008-07-16 04:45:12 +0000597static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
598{
599 return le32_to_cpu(vmsvga_fifo_read_raw(s));
600}
601
thsd34cab92007-04-02 01:10:46 +0000602static void vmsvga_fifo_run(struct vmsvga_state_s *s)
603{
604 uint32_t cmd, colour;
Gerd Hoffmann4e68a0e2016-05-30 09:09:21 +0200605 int args, len, maxloop = 1024;
thsd34cab92007-04-02 01:10:46 +0000606 int x, y, dx, dy, width, height;
607 struct vmsvga_cursor_definition_s cursor;
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200608 uint32_t cmd_start;
609
610 len = vmsvga_fifo_length(s);
Gerd Hoffmann4e68a0e2016-05-30 09:09:21 +0200611 while (len > 0 && --maxloop > 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200612 /* May need to go back to the start of the command if incomplete */
Gerd Hoffmann7e486f72016-05-30 09:09:20 +0200613 cmd_start = s->fifo_stop;
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200614
thsd34cab92007-04-02 01:10:46 +0000615 switch (cmd = vmsvga_fifo_read(s)) {
616 case SVGA_CMD_UPDATE:
617 case SVGA_CMD_UPDATE_VERBOSE:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200618 len -= 5;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100619 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200620 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100621 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200622
thsd34cab92007-04-02 01:10:46 +0000623 x = vmsvga_fifo_read(s);
624 y = vmsvga_fifo_read(s);
625 width = vmsvga_fifo_read(s);
626 height = vmsvga_fifo_read(s);
627 vmsvga_update_rect_delayed(s, x, y, width, height);
628 break;
629
630 case SVGA_CMD_RECT_FILL:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200631 len -= 6;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100632 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200633 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100634 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200635
thsd34cab92007-04-02 01:10:46 +0000636 colour = vmsvga_fifo_read(s);
637 x = vmsvga_fifo_read(s);
638 y = vmsvga_fifo_read(s);
639 width = vmsvga_fifo_read(s);
640 height = vmsvga_fifo_read(s);
641#ifdef HW_FILL_ACCEL
Gerd Hoffmannbd9ccd82014-10-06 11:59:51 +0200642 if (vmsvga_fill_rect(s, colour, x, y, width, height) == 0) {
643 break;
644 }
645#endif
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200646 args = 0;
thsd34cab92007-04-02 01:10:46 +0000647 goto badcmd;
thsd34cab92007-04-02 01:10:46 +0000648
649 case SVGA_CMD_RECT_COPY:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200650 len -= 7;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100651 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200652 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100653 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200654
thsd34cab92007-04-02 01:10:46 +0000655 x = vmsvga_fifo_read(s);
656 y = vmsvga_fifo_read(s);
657 dx = vmsvga_fifo_read(s);
658 dy = vmsvga_fifo_read(s);
659 width = vmsvga_fifo_read(s);
660 height = vmsvga_fifo_read(s);
661#ifdef HW_RECT_ACCEL
Gerd Hoffmann61b41b42014-10-06 11:58:51 +0200662 if (vmsvga_copy_rect(s, x, y, dx, dy, width, height) == 0) {
663 break;
664 }
665#endif
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200666 args = 0;
thsd34cab92007-04-02 01:10:46 +0000667 goto badcmd;
thsd34cab92007-04-02 01:10:46 +0000668
669 case SVGA_CMD_DEFINE_CURSOR:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200670 len -= 8;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100671 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200672 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100673 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200674
thsd34cab92007-04-02 01:10:46 +0000675 cursor.id = vmsvga_fifo_read(s);
676 cursor.hot_x = vmsvga_fifo_read(s);
677 cursor.hot_y = vmsvga_fifo_read(s);
678 cursor.width = x = vmsvga_fifo_read(s);
679 cursor.height = y = vmsvga_fifo_read(s);
680 vmsvga_fifo_read(s);
681 cursor.bpp = vmsvga_fifo_read(s);
Roland Dreierf2d928d2010-01-05 20:43:34 -0800682
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200683 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
Prasad J Pandit167d97a2016-09-08 18:15:54 +0530684 if (cursor.width > 256
685 || cursor.height > 256
686 || cursor.bpp > 32
Philippe Mathieu-Daudécf7040e2017-07-18 03:09:58 -0300687 || SVGA_BITMAP_SIZE(x, y) > ARRAY_SIZE(cursor.mask)
Prasad J Pandit167d97a2016-09-08 18:15:54 +0530688 || SVGA_PIXMAP_SIZE(x, y, cursor.bpp)
Philippe Mathieu-Daudécf7040e2017-07-18 03:09:58 -0300689 > ARRAY_SIZE(cursor.image)) {
Andrzej Zaborowski9f810be2010-09-10 02:30:04 +0200690 goto badcmd;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100691 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200692
693 len -= args;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100694 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200695 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100696 }
Roland Dreierf2d928d2010-01-05 20:43:34 -0800697
BALATON Zoltan0d793792012-11-03 12:47:08 +0100698 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) {
balrogff9cf2c2008-07-16 04:45:12 +0000699 cursor.mask[args] = vmsvga_fifo_read_raw(s);
BALATON Zoltan0d793792012-11-03 12:47:08 +0100700 }
701 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) {
balrogff9cf2c2008-07-16 04:45:12 +0000702 cursor.image[args] = vmsvga_fifo_read_raw(s);
BALATON Zoltan0d793792012-11-03 12:47:08 +0100703 }
thsd34cab92007-04-02 01:10:46 +0000704#ifdef HW_MOUSE_ACCEL
705 vmsvga_cursor_define(s, &cursor);
706 break;
707#else
708 args = 0;
709 goto badcmd;
710#endif
711
712 /*
713 * Other commands that we at least know the number of arguments
714 * for so we can avoid FIFO desync if driver uses them illegally.
715 */
716 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200717 len -= 6;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100718 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200719 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100720 }
thsd34cab92007-04-02 01:10:46 +0000721 vmsvga_fifo_read(s);
722 vmsvga_fifo_read(s);
723 vmsvga_fifo_read(s);
724 x = vmsvga_fifo_read(s);
725 y = vmsvga_fifo_read(s);
726 args = x * y;
727 goto badcmd;
728 case SVGA_CMD_RECT_ROP_FILL:
729 args = 6;
730 goto badcmd;
731 case SVGA_CMD_RECT_ROP_COPY:
732 args = 7;
733 goto badcmd;
734 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200735 len -= 4;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100736 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200737 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100738 }
thsd34cab92007-04-02 01:10:46 +0000739 vmsvga_fifo_read(s);
740 vmsvga_fifo_read(s);
741 args = 7 + (vmsvga_fifo_read(s) >> 2);
742 goto badcmd;
743 case SVGA_CMD_SURFACE_ALPHA_BLEND:
744 args = 12;
745 goto badcmd;
746
747 /*
748 * Other commands that are not listed as depending on any
749 * CAPABILITIES bits, but are not described in the README either.
750 */
751 case SVGA_CMD_SURFACE_FILL:
752 case SVGA_CMD_SURFACE_COPY:
753 case SVGA_CMD_FRONT_ROP_FILL:
754 case SVGA_CMD_FENCE:
755 case SVGA_CMD_INVALID_CMD:
756 break; /* Nop */
757
758 default:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200759 args = 0;
thsd34cab92007-04-02 01:10:46 +0000760 badcmd:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200761 len -= args;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100762 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200763 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100764 }
765 while (args--) {
thsd34cab92007-04-02 01:10:46 +0000766 vmsvga_fifo_read(s);
BALATON Zoltan0d793792012-11-03 12:47:08 +0100767 }
thsd34cab92007-04-02 01:10:46 +0000768 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
BALATON Zoltan0d793792012-11-03 12:47:08 +0100769 __func__, cmd);
thsd34cab92007-04-02 01:10:46 +0000770 break;
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200771
772 rewind:
Gerd Hoffmann7e486f72016-05-30 09:09:20 +0200773 s->fifo_stop = cmd_start;
774 s->fifo[SVGA_FIFO_STOP] = cpu_to_le32(s->fifo_stop);
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200775 break;
thsd34cab92007-04-02 01:10:46 +0000776 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200777 }
thsd34cab92007-04-02 01:10:46 +0000778
779 s->syncing = 0;
780}
781
782static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
783{
Juan Quintela467d44b2009-10-14 17:49:08 +0200784 struct vmsvga_state_s *s = opaque;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100785
thsd34cab92007-04-02 01:10:46 +0000786 return s->index;
787}
788
789static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
790{
Juan Quintela467d44b2009-10-14 17:49:08 +0200791 struct vmsvga_state_s *s = opaque;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100792
thsd34cab92007-04-02 01:10:46 +0000793 s->index = index;
794}
795
796static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
797{
798 uint32_t caps;
Juan Quintela467d44b2009-10-14 17:49:08 +0200799 struct vmsvga_state_s *s = opaque;
Gerd Hoffmannc78f7132013-03-05 15:24:14 +0100800 DisplaySurface *surface = qemu_console_surface(s->vga.con);
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +0100801 PixelFormat pf;
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100802 uint32_t ret;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100803
thsd34cab92007-04-02 01:10:46 +0000804 switch (s->index) {
805 case SVGA_REG_ID:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100806 ret = s->svgaid;
807 break;
thsd34cab92007-04-02 01:10:46 +0000808
809 case SVGA_REG_ENABLE:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100810 ret = s->enable;
811 break;
thsd34cab92007-04-02 01:10:46 +0000812
813 case SVGA_REG_WIDTH:
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +0100814 ret = s->new_width ? s->new_width : surface_width(surface);
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100815 break;
thsd34cab92007-04-02 01:10:46 +0000816
817 case SVGA_REG_HEIGHT:
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +0100818 ret = s->new_height ? s->new_height : surface_height(surface);
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100819 break;
thsd34cab92007-04-02 01:10:46 +0000820
821 case SVGA_REG_MAX_WIDTH:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100822 ret = SVGA_MAX_WIDTH;
823 break;
thsd34cab92007-04-02 01:10:46 +0000824
825 case SVGA_REG_MAX_HEIGHT:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100826 ret = SVGA_MAX_HEIGHT;
827 break;
thsd34cab92007-04-02 01:10:46 +0000828
829 case SVGA_REG_DEPTH:
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +0100830 ret = (s->new_depth == 32) ? 24 : s->new_depth;
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100831 break;
thsd34cab92007-04-02 01:10:46 +0000832
833 case SVGA_REG_BITS_PER_PIXEL:
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +0100834 case SVGA_REG_HOST_BITS_PER_PIXEL:
835 ret = s->new_depth;
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100836 break;
thsd34cab92007-04-02 01:10:46 +0000837
838 case SVGA_REG_PSEUDOCOLOR:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100839 ret = 0x0;
840 break;
thsd34cab92007-04-02 01:10:46 +0000841
842 case SVGA_REG_RED_MASK:
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +0100843 pf = qemu_default_pixelformat(s->new_depth);
844 ret = pf.rmask;
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100845 break;
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100846
thsd34cab92007-04-02 01:10:46 +0000847 case SVGA_REG_GREEN_MASK:
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +0100848 pf = qemu_default_pixelformat(s->new_depth);
849 ret = pf.gmask;
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100850 break;
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100851
thsd34cab92007-04-02 01:10:46 +0000852 case SVGA_REG_BLUE_MASK:
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +0100853 pf = qemu_default_pixelformat(s->new_depth);
854 ret = pf.bmask;
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100855 break;
thsd34cab92007-04-02 01:10:46 +0000856
857 case SVGA_REG_BYTES_PER_LINE:
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +0100858 if (s->new_width) {
859 ret = (s->new_depth * s->new_width) / 8;
860 } else {
861 ret = surface_stride(surface);
862 }
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100863 break;
thsd34cab92007-04-02 01:10:46 +0000864
Avi Kivity7b619b92011-08-08 16:08:56 +0300865 case SVGA_REG_FB_START: {
866 struct pci_vmsvga_state_s *pci_vmsvga
867 = container_of(s, struct pci_vmsvga_state_s, chip);
Andreas Färberaf21c742013-06-30 15:01:36 +0200868 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 1);
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100869 break;
Avi Kivity7b619b92011-08-08 16:08:56 +0300870 }
thsd34cab92007-04-02 01:10:46 +0000871
872 case SVGA_REG_FB_OFFSET:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100873 ret = 0x0;
874 break;
thsd34cab92007-04-02 01:10:46 +0000875
876 case SVGA_REG_VRAM_SIZE:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100877 ret = s->vga.vram_size; /* No physical VRAM besides the framebuffer */
878 break;
thsd34cab92007-04-02 01:10:46 +0000879
880 case SVGA_REG_FB_SIZE:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100881 ret = s->vga.vram_size;
882 break;
thsd34cab92007-04-02 01:10:46 +0000883
884 case SVGA_REG_CAPABILITIES:
885 caps = SVGA_CAP_NONE;
886#ifdef HW_RECT_ACCEL
887 caps |= SVGA_CAP_RECT_COPY;
888#endif
889#ifdef HW_FILL_ACCEL
890 caps |= SVGA_CAP_RECT_FILL;
891#endif
892#ifdef HW_MOUSE_ACCEL
Gerd Hoffmannc78f7132013-03-05 15:24:14 +0100893 if (dpy_cursor_define_supported(s->vga.con)) {
thsd34cab92007-04-02 01:10:46 +0000894 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
895 SVGA_CAP_CURSOR_BYPASS;
Gerd Hoffmannbf2fde72012-09-12 07:56:45 +0200896 }
thsd34cab92007-04-02 01:10:46 +0000897#endif
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100898 ret = caps;
899 break;
thsd34cab92007-04-02 01:10:46 +0000900
Avi Kivityb1950432011-08-08 16:08:57 +0300901 case SVGA_REG_MEM_START: {
902 struct pci_vmsvga_state_s *pci_vmsvga
903 = container_of(s, struct pci_vmsvga_state_s, chip);
Andreas Färberaf21c742013-06-30 15:01:36 +0200904 ret = pci_get_bar_addr(PCI_DEVICE(pci_vmsvga), 2);
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100905 break;
Avi Kivityb1950432011-08-08 16:08:57 +0300906 }
thsd34cab92007-04-02 01:10:46 +0000907
908 case SVGA_REG_MEM_SIZE:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100909 ret = s->fifo_size;
910 break;
thsd34cab92007-04-02 01:10:46 +0000911
912 case SVGA_REG_CONFIG_DONE:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100913 ret = s->config;
914 break;
thsd34cab92007-04-02 01:10:46 +0000915
916 case SVGA_REG_SYNC:
917 case SVGA_REG_BUSY:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100918 ret = s->syncing;
919 break;
thsd34cab92007-04-02 01:10:46 +0000920
921 case SVGA_REG_GUEST_ID:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100922 ret = s->guest;
923 break;
thsd34cab92007-04-02 01:10:46 +0000924
925 case SVGA_REG_CURSOR_ID:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100926 ret = s->cursor.id;
927 break;
thsd34cab92007-04-02 01:10:46 +0000928
929 case SVGA_REG_CURSOR_X:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100930 ret = s->cursor.x;
931 break;
thsd34cab92007-04-02 01:10:46 +0000932
933 case SVGA_REG_CURSOR_Y:
Nicolas Owense2bb4ae2014-06-08 22:19:17 -0700934 ret = s->cursor.y;
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100935 break;
thsd34cab92007-04-02 01:10:46 +0000936
937 case SVGA_REG_CURSOR_ON:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100938 ret = s->cursor.on;
939 break;
thsd34cab92007-04-02 01:10:46 +0000940
thsd34cab92007-04-02 01:10:46 +0000941 case SVGA_REG_SCRATCH_SIZE:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100942 ret = s->scratch_size;
943 break;
thsd34cab92007-04-02 01:10:46 +0000944
945 case SVGA_REG_MEM_REGS:
946 case SVGA_REG_NUM_DISPLAYS:
947 case SVGA_REG_PITCHLOCK:
948 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100949 ret = 0;
950 break;
thsd34cab92007-04-02 01:10:46 +0000951
952 default:
953 if (s->index >= SVGA_SCRATCH_BASE &&
BALATON Zoltan0d793792012-11-03 12:47:08 +0100954 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100955 ret = s->scratch[s->index - SVGA_SCRATCH_BASE];
956 break;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100957 }
Philippe Mathieu-Daudéaa0fd162020-05-26 08:22:48 +0200958 qemu_log_mask(LOG_GUEST_ERROR,
959 "%s: Bad register %02x\n", __func__, s->index);
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100960 ret = 0;
961 break;
thsd34cab92007-04-02 01:10:46 +0000962 }
963
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100964 if (s->index >= SVGA_SCRATCH_BASE) {
965 trace_vmware_scratch_read(s->index, ret);
966 } else if (s->index >= SVGA_PALETTE_BASE) {
967 trace_vmware_palette_read(s->index, ret);
968 } else {
969 trace_vmware_value_read(s->index, ret);
970 }
971 return ret;
thsd34cab92007-04-02 01:10:46 +0000972}
973
974static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
975{
Juan Quintela467d44b2009-10-14 17:49:08 +0200976 struct vmsvga_state_s *s = opaque;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100977
Gerd Hoffmann7a6404c2013-03-25 09:53:35 +0100978 if (s->index >= SVGA_SCRATCH_BASE) {
979 trace_vmware_scratch_write(s->index, value);
980 } else if (s->index >= SVGA_PALETTE_BASE) {
981 trace_vmware_palette_write(s->index, value);
982 } else {
983 trace_vmware_value_write(s->index, value);
984 }
thsd34cab92007-04-02 01:10:46 +0000985 switch (s->index) {
986 case SVGA_REG_ID:
BALATON Zoltan0d793792012-11-03 12:47:08 +0100987 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) {
thsd34cab92007-04-02 01:10:46 +0000988 s->svgaid = value;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100989 }
thsd34cab92007-04-02 01:10:46 +0000990 break;
991
992 case SVGA_REG_ENABLE:
BALATON Zoltanb51d7b22012-11-03 12:47:08 +0100993 s->enable = !!value;
thsd34cab92007-04-02 01:10:46 +0000994 s->invalidated = 1;
Gerd Hoffmann380cd052013-03-13 14:04:18 +0100995 s->vga.hw_ops->invalidate(&s->vga);
BALATON Zoltanb51d7b22012-11-03 12:47:08 +0100996 if (s->enable && s->config) {
Andrzej Zaborowski9f810be2010-09-10 02:30:04 +0200997 vga_dirty_log_stop(&s->vga);
998 } else {
999 vga_dirty_log_start(&s->vga);
1000 }
thsd34cab92007-04-02 01:10:46 +00001001 break;
1002
1003 case SVGA_REG_WIDTH:
BALATON Zoltanaa32b382012-11-03 12:47:08 +01001004 if (value <= SVGA_MAX_WIDTH) {
1005 s->new_width = value;
1006 s->invalidated = 1;
1007 } else {
Philippe Mathieu-Daudéaa0fd162020-05-26 08:22:48 +02001008 qemu_log_mask(LOG_GUEST_ERROR,
1009 "%s: Bad width: %i\n", __func__, value);
BALATON Zoltanaa32b382012-11-03 12:47:08 +01001010 }
thsd34cab92007-04-02 01:10:46 +00001011 break;
1012
1013 case SVGA_REG_HEIGHT:
BALATON Zoltanaa32b382012-11-03 12:47:08 +01001014 if (value <= SVGA_MAX_HEIGHT) {
1015 s->new_height = value;
1016 s->invalidated = 1;
1017 } else {
Philippe Mathieu-Daudéaa0fd162020-05-26 08:22:48 +02001018 qemu_log_mask(LOG_GUEST_ERROR,
1019 "%s: Bad height: %i\n", __func__, value);
BALATON Zoltanaa32b382012-11-03 12:47:08 +01001020 }
thsd34cab92007-04-02 01:10:46 +00001021 break;
1022
thsd34cab92007-04-02 01:10:46 +00001023 case SVGA_REG_BITS_PER_PIXEL:
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +01001024 if (value != 32) {
Philippe Mathieu-Daudéaa0fd162020-05-26 08:22:48 +02001025 qemu_log_mask(LOG_GUEST_ERROR,
1026 "%s: Bad bits per pixel: %i bits\n", __func__, value);
thsd34cab92007-04-02 01:10:46 +00001027 s->config = 0;
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +01001028 s->invalidated = 1;
thsd34cab92007-04-02 01:10:46 +00001029 }
1030 break;
1031
1032 case SVGA_REG_CONFIG_DONE:
1033 if (value) {
Dave Airlief351d052009-12-18 08:08:06 +10001034 s->fifo = (uint32_t *) s->fifo_ptr;
BALATON Zoltanb51d7b22012-11-03 12:47:08 +01001035 vga_dirty_log_stop(&s->vga);
thsd34cab92007-04-02 01:10:46 +00001036 }
balrogf707cfb2007-05-13 13:26:49 +00001037 s->config = !!value;
thsd34cab92007-04-02 01:10:46 +00001038 break;
1039
1040 case SVGA_REG_SYNC:
1041 s->syncing = 1;
1042 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
1043 break;
1044
1045 case SVGA_REG_GUEST_ID:
1046 s->guest = value;
1047#ifdef VERBOSE
1048 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
BALATON Zoltan0d793792012-11-03 12:47:08 +01001049 ARRAY_SIZE(vmsvga_guest_id)) {
1050 printf("%s: guest runs %s.\n", __func__,
1051 vmsvga_guest_id[value - GUEST_OS_BASE]);
1052 }
thsd34cab92007-04-02 01:10:46 +00001053#endif
1054 break;
1055
1056 case SVGA_REG_CURSOR_ID:
1057 s->cursor.id = value;
1058 break;
1059
1060 case SVGA_REG_CURSOR_X:
1061 s->cursor.x = value;
1062 break;
1063
1064 case SVGA_REG_CURSOR_Y:
1065 s->cursor.y = value;
1066 break;
1067
1068 case SVGA_REG_CURSOR_ON:
1069 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
1070 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
1071#ifdef HW_MOUSE_ACCEL
Gerd Hoffmannbf2fde72012-09-12 07:56:45 +02001072 if (value <= SVGA_CURSOR_ON_SHOW) {
Gerd Hoffmannc78f7132013-03-05 15:24:14 +01001073 dpy_mouse_set(s->vga.con, s->cursor.x, s->cursor.y, s->cursor.on);
Gerd Hoffmannbf2fde72012-09-12 07:56:45 +02001074 }
thsd34cab92007-04-02 01:10:46 +00001075#endif
1076 break;
1077
BALATON Zoltan5b9575c2012-11-03 12:47:08 +01001078 case SVGA_REG_DEPTH:
thsd34cab92007-04-02 01:10:46 +00001079 case SVGA_REG_MEM_REGS:
1080 case SVGA_REG_NUM_DISPLAYS:
1081 case SVGA_REG_PITCHLOCK:
1082 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
1083 break;
1084
1085 default:
1086 if (s->index >= SVGA_SCRATCH_BASE &&
1087 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
1088 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
1089 break;
1090 }
Philippe Mathieu-Daudéaa0fd162020-05-26 08:22:48 +02001091 qemu_log_mask(LOG_GUEST_ERROR,
1092 "%s: Bad register %02x\n", __func__, s->index);
thsd34cab92007-04-02 01:10:46 +00001093 }
1094}
1095
1096static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
1097{
BALATON Zoltan0d793792012-11-03 12:47:08 +01001098 printf("%s: what are we supposed to return?\n", __func__);
thsd34cab92007-04-02 01:10:46 +00001099 return 0xcafe;
1100}
1101
1102static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
1103{
BALATON Zoltan0d793792012-11-03 12:47:08 +01001104 printf("%s: what are we supposed to do with (%08x)?\n", __func__, data);
thsd34cab92007-04-02 01:10:46 +00001105}
1106
BALATON Zoltanaa32b382012-11-03 12:47:08 +01001107static inline void vmsvga_check_size(struct vmsvga_state_s *s)
thsd34cab92007-04-02 01:10:46 +00001108{
Gerd Hoffmannc78f7132013-03-05 15:24:14 +01001109 DisplaySurface *surface = qemu_console_surface(s->vga.con);
1110
1111 if (s->new_width != surface_width(surface) ||
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +01001112 s->new_height != surface_height(surface) ||
1113 s->new_depth != surface_bits_per_pixel(surface)) {
1114 int stride = (s->new_depth * s->new_width) / 8;
Gerd Hoffmann30f1e662014-06-18 11:03:15 +02001115 pixman_format_code_t format =
1116 qemu_default_pixman_format(s->new_depth, true);
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +01001117 trace_vmware_setmode(s->new_width, s->new_height, s->new_depth);
1118 surface = qemu_create_displaysurface_from(s->new_width, s->new_height,
Gerd Hoffmann30f1e662014-06-18 11:03:15 +02001119 format, stride,
1120 s->vga.vram_ptr);
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +01001121 dpy_gfx_replace_surface(s->vga.con, surface);
thsd34cab92007-04-02 01:10:46 +00001122 s->invalidated = 1;
1123 }
1124}
1125
1126static void vmsvga_update_display(void *opaque)
1127{
Juan Quintela467d44b2009-10-14 17:49:08 +02001128 struct vmsvga_state_s *s = opaque;
BALATON Zoltanb51d7b22012-11-03 12:47:08 +01001129
Gerd Hoffmann104bd1d2017-04-21 11:16:31 +02001130 if (!s->enable || !s->config) {
1131 /* in standard vga mode */
Gerd Hoffmann380cd052013-03-13 14:04:18 +01001132 s->vga.hw_ops->gfx_update(&s->vga);
thsd34cab92007-04-02 01:10:46 +00001133 return;
1134 }
1135
BALATON Zoltanaa32b382012-11-03 12:47:08 +01001136 vmsvga_check_size(s);
thsd34cab92007-04-02 01:10:46 +00001137
1138 vmsvga_fifo_run(s);
1139 vmsvga_update_rect_flush(s);
1140
Gerd Hoffmann104bd1d2017-04-21 11:16:31 +02001141 if (s->invalidated) {
thsd34cab92007-04-02 01:10:46 +00001142 s->invalidated = 0;
Gerd Hoffmann91155f82018-08-10 15:28:56 +02001143 dpy_gfx_update_full(s->vga.con);
BALATON Zoltanb51d7b22012-11-03 12:47:08 +01001144 }
thsd34cab92007-04-02 01:10:46 +00001145}
1146
Jan Kiszka8a9501b2011-08-22 19:12:08 +02001147static void vmsvga_reset(DeviceState *dev)
thsd34cab92007-04-02 01:10:46 +00001148{
Peter Crosthwaite39d45982013-06-24 16:58:45 +10001149 struct pci_vmsvga_state_s *pci = VMWARE_SVGA(dev);
Jan Kiszka8a9501b2011-08-22 19:12:08 +02001150 struct vmsvga_state_s *s = &pci->chip;
1151
thsd34cab92007-04-02 01:10:46 +00001152 s->index = 0;
1153 s->enable = 0;
1154 s->config = 0;
thsd34cab92007-04-02 01:10:46 +00001155 s->svgaid = SVGA_ID;
thsd34cab92007-04-02 01:10:46 +00001156 s->cursor.on = 0;
1157 s->redraw_fifo_first = 0;
1158 s->redraw_fifo_last = 0;
thsd34cab92007-04-02 01:10:46 +00001159 s->syncing = 0;
Anthony Liguorib5cc6e32009-12-18 08:08:10 +10001160
1161 vga_dirty_log_start(&s->vga);
thsd34cab92007-04-02 01:10:46 +00001162}
1163
1164static void vmsvga_invalidate_display(void *opaque)
1165{
Juan Quintela467d44b2009-10-14 17:49:08 +02001166 struct vmsvga_state_s *s = opaque;
thsd34cab92007-04-02 01:10:46 +00001167 if (!s->enable) {
Gerd Hoffmann380cd052013-03-13 14:04:18 +01001168 s->vga.hw_ops->invalidate(&s->vga);
thsd34cab92007-04-02 01:10:46 +00001169 return;
1170 }
1171
1172 s->invalidated = 1;
1173}
1174
Anthony Liguoric227f092009-10-01 16:12:16 -05001175static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
balrog4d3b6f62008-02-10 16:33:14 +00001176{
Juan Quintela467d44b2009-10-14 17:49:08 +02001177 struct vmsvga_state_s *s = opaque;
balrog4d3b6f62008-02-10 16:33:14 +00001178
Gerd Hoffmann380cd052013-03-13 14:04:18 +01001179 if (s->vga.hw_ops->text_update) {
1180 s->vga.hw_ops->text_update(&s->vga, chardata);
BALATON Zoltan0d793792012-11-03 12:47:08 +01001181 }
balrog4d3b6f62008-02-10 16:33:14 +00001182}
1183
Juan Quintelabacbe282009-10-14 19:30:22 +02001184static int vmsvga_post_load(void *opaque, int version_id)
thsd34cab92007-04-02 01:10:46 +00001185{
Juan Quintelabacbe282009-10-14 19:30:22 +02001186 struct vmsvga_state_s *s = opaque;
thsd34cab92007-04-02 01:10:46 +00001187
1188 s->invalidated = 1;
BALATON Zoltan0d793792012-11-03 12:47:08 +01001189 if (s->config) {
Dave Airlief351d052009-12-18 08:08:06 +10001190 s->fifo = (uint32_t *) s->fifo_ptr;
BALATON Zoltan0d793792012-11-03 12:47:08 +01001191 }
thsd34cab92007-04-02 01:10:46 +00001192 return 0;
1193}
1194
Blue Swirld05ac8f2009-12-04 20:44:44 +00001195static const VMStateDescription vmstate_vmware_vga_internal = {
Juan Quintelabacbe282009-10-14 19:30:22 +02001196 .name = "vmware_vga_internal",
1197 .version_id = 0,
1198 .minimum_version_id = 0,
Juan Quintelabacbe282009-10-14 19:30:22 +02001199 .post_load = vmsvga_post_load,
Juan Quintelad49805a2014-04-16 15:32:32 +02001200 .fields = (VMStateField[]) {
Halil Pasicd2164ad2017-06-23 16:48:23 +02001201 VMSTATE_INT32_EQUAL(new_depth, struct vmsvga_state_s, NULL),
Juan Quintelabacbe282009-10-14 19:30:22 +02001202 VMSTATE_INT32(enable, struct vmsvga_state_s),
1203 VMSTATE_INT32(config, struct vmsvga_state_s),
1204 VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1205 VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1206 VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1207 VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1208 VMSTATE_INT32(index, struct vmsvga_state_s),
1209 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1210 scratch_size, 0, vmstate_info_uint32, uint32_t),
1211 VMSTATE_INT32(new_width, struct vmsvga_state_s),
1212 VMSTATE_INT32(new_height, struct vmsvga_state_s),
1213 VMSTATE_UINT32(guest, struct vmsvga_state_s),
1214 VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1215 VMSTATE_INT32(syncing, struct vmsvga_state_s),
BALATON Zoltan5b9575c2012-11-03 12:47:08 +01001216 VMSTATE_UNUSED(4), /* was fb_size */
Juan Quintelabacbe282009-10-14 19:30:22 +02001217 VMSTATE_END_OF_LIST()
1218 }
1219};
1220
Blue Swirld05ac8f2009-12-04 20:44:44 +00001221static const VMStateDescription vmstate_vmware_vga = {
Juan Quintelabacbe282009-10-14 19:30:22 +02001222 .name = "vmware_vga",
1223 .version_id = 0,
1224 .minimum_version_id = 0,
Juan Quintelad49805a2014-04-16 15:32:32 +02001225 .fields = (VMStateField[]) {
Andreas Färberaf21c742013-06-30 15:01:36 +02001226 VMSTATE_PCI_DEVICE(parent_obj, struct pci_vmsvga_state_s),
Juan Quintelabacbe282009-10-14 19:30:22 +02001227 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1228 vmstate_vmware_vga_internal, struct vmsvga_state_s),
1229 VMSTATE_END_OF_LIST()
1230 }
1231};
1232
Gerd Hoffmann380cd052013-03-13 14:04:18 +01001233static const GraphicHwOps vmsvga_ops = {
1234 .invalidate = vmsvga_invalidate_display,
1235 .gfx_update = vmsvga_update_display,
1236 .text_update = vmsvga_text_update,
1237};
1238
Gerd Hoffmannaa2beaa2013-04-17 10:21:27 +02001239static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s,
Richard Henderson0a039dc2011-08-16 08:27:39 -07001240 MemoryRegion *address_space, MemoryRegion *io)
thsd34cab92007-04-02 01:10:46 +00001241{
thsd34cab92007-04-02 01:10:46 +00001242 s->scratch_size = SVGA_SCRATCH_SIZE;
Anthony Liguori7267c092011-08-20 22:09:37 -05001243 s->scratch = g_malloc(s->scratch_size * 4);
thsd34cab92007-04-02 01:10:46 +00001244
Gerd Hoffmann56437062014-01-24 15:35:21 +01001245 s->vga.con = graphic_console_init(dev, 0, &vmsvga_ops, s);
Andrzej Zaborowski4445b0a2009-08-23 19:00:58 +02001246
Dave Airlief351d052009-12-18 08:08:06 +10001247 s->fifo_size = SVGA_FIFO_SIZE;
Peter Maydell98a99ce2017-07-07 15:42:53 +01001248 memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size,
Markus Armbrusterf8ed85a2015-09-11 16:51:43 +02001249 &error_fatal);
Avi Kivityb1950432011-08-08 16:08:57 +03001250 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
Dave Airlief351d052009-12-18 08:08:06 +10001251
Gerd Hoffmann1fcfdc42018-07-02 18:33:44 +02001252 vga_common_init(&s->vga, OBJECT(dev));
Paolo Bonzini712f0cc2013-06-06 21:21:13 -04001253 vga_init(&s->vga, OBJECT(dev), address_space, io, true);
Alex Williamson0be71e32010-06-25 11:09:07 -06001254 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
Gerd Hoffmanneb2f9b02013-03-25 11:44:21 +01001255 s->new_depth = 32;
thsd34cab92007-04-02 01:10:46 +00001256}
1257
BALATON Zoltanaa32b382012-11-03 12:47:08 +01001258static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size)
balrog1492a3c2008-01-14 01:52:52 +00001259{
Avi Kivityb1950432011-08-08 16:08:57 +03001260 struct vmsvga_state_s *s = opaque;
balrog1492a3c2008-01-14 01:52:52 +00001261
Avi Kivityb1950432011-08-08 16:08:57 +03001262 switch (addr) {
1263 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr);
1264 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr);
1265 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr);
1266 default: return -1u;
1267 }
balrog1492a3c2008-01-14 01:52:52 +00001268}
1269
Avi Kivitya8170e52012-10-23 12:30:10 +02001270static void vmsvga_io_write(void *opaque, hwaddr addr,
Avi Kivityb1950432011-08-08 16:08:57 +03001271 uint64_t data, unsigned size)
balrog3016d802008-03-06 20:28:49 +00001272{
Avi Kivityb1950432011-08-08 16:08:57 +03001273 struct vmsvga_state_s *s = opaque;
balrog3016d802008-03-06 20:28:49 +00001274
Avi Kivityb1950432011-08-08 16:08:57 +03001275 switch (addr) {
1276 case SVGA_IO_MUL * SVGA_INDEX_PORT:
Blue Swirl0ed8b6f2012-07-08 06:56:53 +00001277 vmsvga_index_write(s, addr, data);
1278 break;
Avi Kivityb1950432011-08-08 16:08:57 +03001279 case SVGA_IO_MUL * SVGA_VALUE_PORT:
Blue Swirl0ed8b6f2012-07-08 06:56:53 +00001280 vmsvga_value_write(s, addr, data);
1281 break;
Avi Kivityb1950432011-08-08 16:08:57 +03001282 case SVGA_IO_MUL * SVGA_BIOS_PORT:
Blue Swirl0ed8b6f2012-07-08 06:56:53 +00001283 vmsvga_bios_write(s, addr, data);
1284 break;
Avi Kivityb1950432011-08-08 16:08:57 +03001285 }
balrog3016d802008-03-06 20:28:49 +00001286}
1287
Avi Kivityb1950432011-08-08 16:08:57 +03001288static const MemoryRegionOps vmsvga_io_ops = {
1289 .read = vmsvga_io_read,
1290 .write = vmsvga_io_write,
1291 .endianness = DEVICE_LITTLE_ENDIAN,
1292 .valid = {
1293 .min_access_size = 4,
1294 .max_access_size = 4,
Jan Kiszka04e8cd52013-06-22 08:07:02 +02001295 .unaligned = true,
1296 },
1297 .impl = {
1298 .unaligned = true,
Avi Kivityb1950432011-08-08 16:08:57 +03001299 },
1300};
Dave Airlief351d052009-12-18 08:08:06 +10001301
Markus Armbruster9af21db2015-01-19 15:52:30 +01001302static void pci_vmsvga_realize(PCIDevice *dev, Error **errp)
thsd34cab92007-04-02 01:10:46 +00001303{
Peter Crosthwaite39d45982013-06-24 16:58:45 +10001304 struct pci_vmsvga_state_s *s = VMWARE_SVGA(dev);
Avi Kivityb1950432011-08-08 16:08:57 +03001305
Andreas Färberaf21c742013-06-30 15:01:36 +02001306 dev->config[PCI_CACHE_LINE_SIZE] = 0x08;
1307 dev->config[PCI_LATENCY_TIMER] = 0x40;
1308 dev->config[PCI_INTERRUPT_LINE] = 0xff; /* End */
thsd34cab92007-04-02 01:10:46 +00001309
Philippe Mathieu-Daudébecce5e2020-05-26 08:22:49 +02001310 memory_region_init_io(&s->io_bar, OBJECT(dev), &vmsvga_io_ops, &s->chip,
Avi Kivityb1950432011-08-08 16:08:57 +03001311 "vmsvga-io", 0x10);
Jan Kiszkabd8f2f52012-08-23 13:02:33 +02001312 memory_region_set_flush_coalesced(&s->io_bar);
Andreas Färberaf21c742013-06-30 15:01:36 +02001313 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
Dave Airlief351d052009-12-18 08:08:06 +10001314
Gerd Hoffmannaa2beaa2013-04-17 10:21:27 +02001315 vmsvga_init(DEVICE(dev), &s->chip,
1316 pci_address_space(dev), pci_address_space_io(dev));
thsd34cab92007-04-02 01:10:46 +00001317
Andreas Färberaf21c742013-06-30 15:01:36 +02001318 pci_register_bar(dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
BALATON Zoltanaa32b382012-11-03 12:47:08 +01001319 &s->chip.vga.vram);
Andreas Färberaf21c742013-06-30 15:01:36 +02001320 pci_register_bar(dev, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
Avi Kivitye824b2c2011-08-08 16:09:31 +03001321 &s->chip.fifo_ram);
thsd34cab92007-04-02 01:10:46 +00001322}
Gerd Hoffmanna414c302009-07-28 18:18:00 +02001323
Gerd Hoffmann4a1e2442012-05-24 09:59:44 +02001324static Property vga_vmware_properties[] = {
1325 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s,
Gerd Hoffmann9e56edc2012-06-11 10:42:53 +02001326 chip.vga.vram_size_mb, 16),
Gerd Hoffmann1fcfdc42018-07-02 18:33:44 +02001327 DEFINE_PROP_BOOL("global-vmstate", struct pci_vmsvga_state_s,
1328 chip.vga.global_vmstate, false),
Gerd Hoffmann4a1e2442012-05-24 09:59:44 +02001329 DEFINE_PROP_END_OF_LIST(),
1330};
1331
Anthony Liguori40021f02011-12-04 12:22:06 -06001332static void vmsvga_class_init(ObjectClass *klass, void *data)
1333{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001334 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -06001335 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
Isaku Yamahata310faae2011-05-25 10:58:04 +09001336
Markus Armbruster9af21db2015-01-19 15:52:30 +01001337 k->realize = pci_vmsvga_realize;
Anthony Liguori40021f02011-12-04 12:22:06 -06001338 k->romfile = "vgabios-vmware.bin";
1339 k->vendor_id = PCI_VENDOR_ID_VMWARE;
1340 k->device_id = SVGA_PCI_DEVICE_ID;
1341 k->class_id = PCI_CLASS_DISPLAY_VGA;
1342 k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
1343 k->subsystem_id = SVGA_PCI_DEVICE_ID;
Anthony Liguori39bffca2011-12-07 21:34:16 -06001344 dc->reset = vmsvga_reset;
1345 dc->vmsd = &vmstate_vmware_vga;
Marc-André Lureau4f67d302020-01-10 19:30:32 +04001346 device_class_set_props(dc, vga_vmware_properties);
Igor Mammedov2897ae02014-02-05 16:36:48 +01001347 dc->hotpluggable = false;
Marcel Apfelbaum125ee0e2013-07-29 17:17:45 +03001348 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
Anthony Liguori40021f02011-12-04 12:22:06 -06001349}
1350
Andreas Färber8c43a6f2013-01-10 16:19:07 +01001351static const TypeInfo vmsvga_info = {
Peter Crosthwaite39d45982013-06-24 16:58:45 +10001352 .name = TYPE_VMWARE_SVGA,
Anthony Liguori39bffca2011-12-07 21:34:16 -06001353 .parent = TYPE_PCI_DEVICE,
1354 .instance_size = sizeof(struct pci_vmsvga_state_s),
1355 .class_init = vmsvga_class_init,
Eduardo Habkostfd3b02c2017-09-27 16:56:34 -03001356 .interfaces = (InterfaceInfo[]) {
1357 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1358 { },
1359 },
Gerd Hoffmanna414c302009-07-28 18:18:00 +02001360};
1361
Andreas Färber83f7d432012-02-09 15:20:55 +01001362static void vmsvga_register_types(void)
Gerd Hoffmanna414c302009-07-28 18:18:00 +02001363{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001364 type_register_static(&vmsvga_info);
Gerd Hoffmanna414c302009-07-28 18:18:00 +02001365}
Andreas Färber83f7d432012-02-09 15:20:55 +01001366
1367type_init(vmsvga_register_types)