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target-xtensa
3d0be8a
target-xtensa: fix tb invalidation for IBREAK and LOOP
by Max Filippov
· 13 years ago
2050396
Use uintptr_t for various op related functions
by Blue Swirl
· 13 years ago
e554bbc
target-xtensa: Start QOM'ifying CPU init
by Andreas Färber
· 13 years ago
5087a72
target-xtensa: QOM'ify CPU reset
by Andreas Färber
· 13 years ago
a4633e1
target-xtensa: QOM'ify CPU
by Andreas Färber
· 13 years ago
16c1dea
target-xtensa: Move helpers.h to helper.h
by Lluís Vilanova
· 13 years ago
9349b4f
Rename CPUState -> CPUArchState
by Andreas Färber
· 13 years ago
97129ac
target-xtensa: Don't overuse CPUState
by Andreas Färber
· 13 years ago
1bba0dc
Rename cpu_reset() to cpu_state_reset()
by Andreas Färber
· 13 years ago
5a30d3f
Merge branch 'upstream' of git://qemu.weilnetz.de/qemu
by Blue Swirl
· 13 years ago
2ad5201
target-xtensa: Clean includes
by Stefan Weil
· 13 years ago
18da932
target-xtensa: add DEBUG_SECTION to overlay tool
by Max Filippov
· 13 years ago
f14c4b5
target-xtensa: add DBREAK data breakpoints
by Max Filippov
· 13 years ago
35b5c04
target-xtensa: add ICOUNT SR and debug exception
by Max Filippov
· 13 years ago
e61dc8f
target-xtensa: implement instruction breakpoints
by Max Filippov
· 13 years ago
ab58c5b
target-xtensa: add DEBUGCAUSE SR and configuration
by Max Filippov
· 13 years ago
a044ec2
target-xtensa: fetch 3rd opcode byte only when needed
by Max Filippov
· 13 years ago
692f737
target-xtensa: implement info tlb monitor command
by Max Filippov
· 13 years ago
b96ac3e
target-xtensa: define TLB_TEMPLATE for MMU-less cores
by Max Filippov
· 13 years ago
0fdd2e1
target-xtensa: fix MMUv3 initialization
by Max Filippov
· 13 years ago
6b81471
target-xtensa: raise an exception for invalid and reserved opcodes
by Max Filippov
· 13 years ago
0c852e1
target-xtensa: handle cache options in the overlay tool
by Max Filippov
· 13 years ago
53a72df
target-xtensa: mask out undefined bits of WINDOWSTART SR
by Max Filippov
· 13 years ago
935f7a2
target-xtensa: add fsf core
by Max Filippov
· 13 years ago
53add75
target-xtensa: add dc232b core
by Max Filippov
· 13 years ago
ac8b7db
target-xtensa: extract core configuration from overlay
by Max Filippov
· 13 years ago
b8929a5
target-xtensa: implement external interrupt mapping
by Max Filippov
· 13 years ago
63f95e4
target-xtensa: remove hand-written xtensa cores implementations
by Max Filippov
· 13 years ago
7f65f4b
target-xtensa: increase xtensa options accuracy
by Max Filippov
· 13 years ago
6825b6c
target-xtensa: implement MAC16 option
by Max Filippov
· 13 years ago
890c633
target-xtensa: fix guest hang on masked CCOMPARE interrupt
by Max Filippov
· 13 years ago
bccd9ec
softmmu_header: pass CPUState to tlb_fill
by Blue Swirl
· 14 years ago
47d05a8
target-xtensa: add dc232b core and board
by Max Filippov
· 13 years ago
4dd85b6
target-xtensa: implement boolean option
by Max Filippov
· 13 years ago
b67ea0c
target-xtensa: implement memory protection options
by Max Filippov
· 13 years ago
ccfcaba
target-xtensa: add gdb support
by Max Filippov
· 13 years ago
97836ce
target-xtensa: implement relocatable vectors
by Max Filippov
· 13 years ago
f3df4c0
target-xtensa: implement CPENABLE and PRID SRs
by Max Filippov
· 13 years ago
772177c
target-xtensa: implement accurate window check
by Max Filippov
· 13 years ago
b994e91
target-xtensa: implement interrupt option
by Max Filippov
· 13 years ago
1ddeaa5
target-xtensa: implement SIMCALL
by Max Filippov
· 13 years ago
5b4e481
target-xtensa: implement unaligned exception option
by Max Filippov
· 13 years ago
6ad6dbf
target-xtensa: implement extended L32R
by Max Filippov
· 13 years ago
797d780
target-xtensa: implement loop option
by Max Filippov
· 13 years ago
553e44f
target-xtensa: implement windowed registers
by Max Filippov
· 13 years ago
f76ebf5
target-xtensa: implement RST2 group (32 bit mul/div/rem)
by Max Filippov
· 13 years ago
40643d7
target-xtensa: implement exceptions
by Max Filippov
· 13 years ago
f0a548b
target-xtensa: add PS register and access control
by Max Filippov
· 13 years ago
8ffc2d0
target-xtensa: implement CACHE group
by Max Filippov
· 13 years ago
28067b2
target-xtensa: implement SYNC group
by Max Filippov
· 13 years ago
91a5bb7
target-xtensa: mark reserved and TBD opcodes
by Max Filippov
· 13 years ago
809377a
target-xtensa: implement LSAI group
by Max Filippov
· 13 years ago
3580eca
target-xtensa: implement shifts (ST1 and RST1 groups)
by Max Filippov
· 13 years ago
b8132eff
target-xtensa: implement RST3 group
by Max Filippov
· 13 years ago
2af3da9
target-xtensa: add special and user registers
by Max Filippov
· 13 years ago
5da4a6a
target-xtensa: implement JX/RET0/CALLX
by Max Filippov
· 13 years ago
bd57fb9
target-xtensa: implement conditional jumps
by Max Filippov
· 13 years ago
f331fe5
target-xtensa: implement RT0 group
by Max Filippov
· 13 years ago
67882fd
target-xtensa: implement narrow instructions
by Max Filippov
· 13 years ago
dedc5ea
target-xtensa: implement disas_xtensa_insn
by Max Filippov
· 13 years ago
2328826
target-xtensa: add target stubs
by Max Filippov
· 13 years ago