blob: 34088ad185e47401032140b55c1717db36dd4070 [file] [log] [blame]
bellard420557e2004-09-30 22:13:50 +00001/*
blueswir1ee76f822007-12-28 20:59:23 +00002 * QEMU Sun4m & Sun4d & Sun4c System Emulator
ths5fafdf22007-09-16 21:08:06 +00003 *
bellardb81b3b12005-04-06 20:43:37 +00004 * Copyright (c) 2003-2005 Fabrice Bellard
ths5fafdf22007-09-16 21:08:06 +00005 *
bellard420557e2004-09-30 22:13:50 +00006 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Paul Brook9d07d752009-05-14 22:35:07 +010024#include "sysbus.h"
pbrook87ecb682007-11-17 17:14:51 +000025#include "qemu-timer.h"
26#include "sun4m.h"
27#include "nvram.h"
28#include "sparc32_dma.h"
29#include "fdc.h"
30#include "sysemu.h"
31#include "net.h"
32#include "boards.h"
blueswir1d2c63fc2007-11-14 19:35:16 +000033#include "firmware_abi.h"
Gerd Hoffmann1cd3af52009-10-30 09:53:59 +010034#include "esp.h"
blueswir122548762008-05-10 10:12:00 +000035#include "pc.h"
36#include "isa.h"
blueswir13cce6242008-09-18 18:27:29 +000037#include "fw_cfg.h"
blueswir1b4ed08e2009-01-12 17:38:28 +000038#include "escc.h"
Artyom Tarasenko676d9b92010-04-18 00:34:03 +020039#include "empty_slot.h"
Blue Swirl4b48bf02009-08-08 20:24:47 +000040#include "qdev-addr.h"
Blue Swirlca20cf32009-09-20 14:58:02 +000041#include "loader.h"
42#include "elf.h"
Blue Swirl24463332010-08-24 15:22:24 +000043#include "blockdev.h"
Blue Swirl97bf4852010-10-31 09:24:14 +000044#include "trace.h"
bellard420557e2004-09-30 22:13:50 +000045
blueswir136cd9212007-04-01 15:44:43 +000046/*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
blueswir177f193d2008-05-12 16:13:33 +000050 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
blueswir136cd9212007-04-01 15:44:43 +000052 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
blueswir17d858922007-12-28 20:57:43 +000059 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
blueswir1ee76f822007-12-28 20:59:23 +000064 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
blueswir136cd9212007-04-01 15:44:43 +000071 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
bellard420557e2004-09-30 22:13:50 +000074#define KERNEL_LOAD_ADDR 0x00004000
bellardb6f479d2005-03-01 21:51:04 +000075#define CMDLINE_ADDR 0x007ff000
bellard713c45f2005-02-22 19:08:41 +000076#define INITRD_LOAD_ADDR 0x00800000
blueswir1a7227722008-11-02 14:44:35 +000077#define PROM_SIZE_MAX (1024 * 1024)
blueswir140ce0a92007-09-24 19:44:09 +000078#define PROM_VADDR 0xffd00000
blueswir1f930d072007-10-06 11:28:21 +000079#define PROM_FILENAME "openbios-sparc32"
blueswir13cce6242008-09-18 18:27:29 +000080#define CFG_ADDR 0xd00000510ULL
blueswir1fbfcf952008-09-18 18:34:28 +000081#define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
bellardb8174932006-09-10 19:25:12 +000082
bellardba3c64f2005-12-05 20:31:52 +000083#define MAX_CPUS 16
blueswir1b3a23192007-05-27 16:42:29 +000084#define MAX_PILS 16
Bob Breuer9a62fb22010-07-13 11:05:24 -050085#define MAX_VSIMMS 4
bellard420557e2004-09-30 22:13:50 +000086
blueswir1b4ed08e2009-01-12 17:38:28 +000087#define ESCC_CLOCK 4915200
88
blueswir18137cde2008-10-27 15:56:56 +000089struct sun4m_hwdef {
Artyom Tarasenko33863762010-05-08 16:10:14 +020090 target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
Anthony Liguoric227f092009-10-01 16:12:16 -050091 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
92 target_phys_addr_t serial_base, fd_base;
Artyom Tarasenkoc5de3862009-12-13 13:30:19 +000093 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
Anthony Liguoric227f092009-10-01 16:12:16 -050094 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
Bob Breuer9a62fb22010-07-13 11:05:24 -050095 target_phys_addr_t bpp_base, dbri_base, sx_base;
96 struct {
97 target_phys_addr_t reg_base, vram_base;
98 } vsimm[MAX_VSIMMS];
Anthony Liguoric227f092009-10-01 16:12:16 -050099 target_phys_addr_t ecc_base;
blueswir13ebf5aa2007-11-28 20:54:33 +0000100 uint64_t max_mem;
101 const char * const default_cpu_model;
Blue Swirl61999752011-08-07 19:22:46 +0000102 uint32_t ecc_version;
103 uint32_t iommu_version;
104 uint16_t machine_id;
105 uint8_t nvram_machine_id;
blueswir136cd9212007-04-01 15:44:43 +0000106};
107
blueswir17d858922007-12-28 20:57:43 +0000108#define MAX_IOUNITS 5
109
110struct sun4d_hwdef {
Anthony Liguoric227f092009-10-01 16:12:16 -0500111 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
112 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
113 target_phys_addr_t serial_base;
114 target_phys_addr_t espdma_base, esp_base;
115 target_phys_addr_t ledma_base, le_base;
116 target_phys_addr_t tcx_base;
117 target_phys_addr_t sbi_base;
blueswir17d858922007-12-28 20:57:43 +0000118 uint64_t max_mem;
119 const char * const default_cpu_model;
Blue Swirl61999752011-08-07 19:22:46 +0000120 uint32_t iounit_version;
121 uint16_t machine_id;
122 uint8_t nvram_machine_id;
blueswir17d858922007-12-28 20:57:43 +0000123};
124
blueswir18137cde2008-10-27 15:56:56 +0000125struct sun4c_hwdef {
Anthony Liguoric227f092009-10-01 16:12:16 -0500126 target_phys_addr_t iommu_base, slavio_base;
127 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
128 target_phys_addr_t serial_base, fd_base;
129 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
130 target_phys_addr_t tcx_base, aux1_base;
blueswir18137cde2008-10-27 15:56:56 +0000131 uint64_t max_mem;
132 const char * const default_cpu_model;
Blue Swirl61999752011-08-07 19:22:46 +0000133 uint32_t iommu_version;
134 uint16_t machine_id;
135 uint8_t nvram_machine_id;
blueswir18137cde2008-10-27 15:56:56 +0000136};
137
bellard6f7e9ae2005-03-13 09:43:36 +0000138int DMA_get_channel_mode (int nchan)
139{
140 return 0;
141}
142int DMA_read_memory (int nchan, void *buf, int pos, int size)
143{
144 return 0;
145}
146int DMA_write_memory (int nchan, void *buf, int pos, int size)
147{
148 return 0;
149}
150void DMA_hold_DREQ (int nchan) {}
151void DMA_release_DREQ (int nchan) {}
152void DMA_schedule(int nchan) {}
Blue Swirl4556bd82010-05-22 08:00:52 +0000153
154void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155{
156}
157
bellard6f7e9ae2005-03-13 09:43:36 +0000158void DMA_register_channel (int nchan,
159 DMA_transfer_handler transfer_handler,
160 void *opaque)
161{
162}
163
blueswir1513f7892009-03-08 09:51:29 +0000164static int fw_cfg_boot_set(void *opaque, const char *boot_device)
blueswir181864572008-06-20 16:25:56 +0000165{
blueswir1513f7892009-03-08 09:51:29 +0000166 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
blueswir181864572008-06-20 16:25:56 +0000167 return 0;
168}
169
Blue Swirl43a34702010-02-07 08:05:03 +0000170static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171 const char *cmdline, const char *boot_devices,
172 ram_addr_t RAM_size, uint32_t kernel_size,
blueswir1f930d072007-10-06 11:28:21 +0000173 int width, int height, int depth,
blueswir1905fdcb2008-09-18 18:33:18 +0000174 int nvram_machine_id, const char *arch)
bellarde80cfcf2004-12-19 23:18:01 +0000175{
blueswir1d2c63fc2007-11-14 19:35:16 +0000176 unsigned int i;
blueswir166508602007-05-01 14:16:52 +0000177 uint32_t start, end;
blueswir1d2c63fc2007-11-14 19:35:16 +0000178 uint8_t image[0x1ff0];
blueswir1d2c63fc2007-11-14 19:35:16 +0000179 struct OpenBIOS_nvpart_v1 *part_header;
180
181 memset(image, '\0', sizeof(image));
bellarde80cfcf2004-12-19 23:18:01 +0000182
blueswir1513f7892009-03-08 09:51:29 +0000183 start = 0;
bellardb6f479d2005-03-01 21:51:04 +0000184
blueswir166508602007-05-01 14:16:52 +0000185 // OpenBIOS nvram variables
186 // Variable partition
blueswir1d2c63fc2007-11-14 19:35:16 +0000187 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188 part_header->signature = OPENBIOS_PART_SYSTEM;
blueswir1363a37d2008-08-21 17:58:08 +0000189 pstrcpy(part_header->name, sizeof(part_header->name), "system");
blueswir166508602007-05-01 14:16:52 +0000190
blueswir1d2c63fc2007-11-14 19:35:16 +0000191 end = start + sizeof(struct OpenBIOS_nvpart_v1);
blueswir166508602007-05-01 14:16:52 +0000192 for (i = 0; i < nb_prom_envs; i++)
blueswir1d2c63fc2007-11-14 19:35:16 +0000193 end = OpenBIOS_set_var(image, end, prom_envs[i]);
blueswir166508602007-05-01 14:16:52 +0000194
blueswir1d2c63fc2007-11-14 19:35:16 +0000195 // End marker
196 image[end++] = '\0';
197
blueswir166508602007-05-01 14:16:52 +0000198 end = start + ((end - start + 15) & ~15);
blueswir1d2c63fc2007-11-14 19:35:16 +0000199 OpenBIOS_finish_partition(part_header, end - start);
blueswir166508602007-05-01 14:16:52 +0000200
201 // free partition
202 start = end;
blueswir1d2c63fc2007-11-14 19:35:16 +0000203 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204 part_header->signature = OPENBIOS_PART_FREE;
blueswir1363a37d2008-08-21 17:58:08 +0000205 pstrcpy(part_header->name, sizeof(part_header->name), "free");
blueswir166508602007-05-01 14:16:52 +0000206
207 end = 0x1fd0;
blueswir1d2c63fc2007-11-14 19:35:16 +0000208 OpenBIOS_finish_partition(part_header, end - start);
blueswir166508602007-05-01 14:16:52 +0000209
blueswir1905fdcb2008-09-18 18:33:18 +0000210 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211 nvram_machine_id);
bellarde80cfcf2004-12-19 23:18:01 +0000212
blueswir1d2c63fc2007-11-14 19:35:16 +0000213 for (i = 0; i < sizeof(image); i++)
214 m48t59_write(nvram, i, image[i]);
bellarde80cfcf2004-12-19 23:18:01 +0000215}
216
Blue Swirld453c2c2009-08-23 12:23:30 +0000217static DeviceState *slavio_intctl;
bellarde80cfcf2004-12-19 23:18:01 +0000218
Jan Kiszka661f1922011-10-16 11:53:13 +0200219void sun4m_pic_info(Monitor *mon)
bellarde80cfcf2004-12-19 23:18:01 +0000220{
blueswir17d858922007-12-28 20:57:43 +0000221 if (slavio_intctl)
aliguori376253e2009-03-05 23:01:23 +0000222 slavio_pic_info(mon, slavio_intctl);
bellarde80cfcf2004-12-19 23:18:01 +0000223}
224
Jan Kiszka661f1922011-10-16 11:53:13 +0200225void sun4m_irq_info(Monitor *mon)
bellarde80cfcf2004-12-19 23:18:01 +0000226{
blueswir17d858922007-12-28 20:57:43 +0000227 if (slavio_intctl)
aliguori376253e2009-03-05 23:01:23 +0000228 slavio_irq_info(mon, slavio_intctl);
bellarde80cfcf2004-12-19 23:18:01 +0000229}
230
Andreas Färber98cec4a2012-03-14 01:38:24 +0100231void cpu_check_irqs(CPUSPARCState *env)
blueswir1327ac2e2007-08-04 10:50:30 +0000232{
233 if (env->pil_in && (env->interrupt_index == 0 ||
234 (env->interrupt_index & ~15) == TT_EXTINT)) {
235 unsigned int i;
236
237 for (i = 15; i > 0; i--) {
238 if (env->pil_in & (1 << i)) {
239 int old_interrupt = env->interrupt_index;
240
241 env->interrupt_index = TT_EXTINT | i;
blueswir1f32d7ec2008-03-04 20:29:59 +0000242 if (old_interrupt != env->interrupt_index) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000243 trace_sun4m_cpu_interrupt(i);
blueswir1327ac2e2007-08-04 10:50:30 +0000244 cpu_interrupt(env, CPU_INTERRUPT_HARD);
blueswir1f32d7ec2008-03-04 20:29:59 +0000245 }
blueswir1327ac2e2007-08-04 10:50:30 +0000246 break;
247 }
248 }
249 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000250 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
blueswir1327ac2e2007-08-04 10:50:30 +0000251 env->interrupt_index = 0;
252 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
253 }
254}
255
Andreas Färber98cec4a2012-03-14 01:38:24 +0100256static void cpu_kick_irq(CPUSPARCState *env)
Paolo Bonzini94ad5b02011-03-12 17:43:57 +0100257{
258 env->halted = 0;
259 cpu_check_irqs(env);
260 qemu_cpu_kick(env);
261}
262
blueswir1b3a23192007-05-27 16:42:29 +0000263static void cpu_set_irq(void *opaque, int irq, int level)
264{
Andreas Färber98cec4a2012-03-14 01:38:24 +0100265 CPUSPARCState *env = opaque;
blueswir1b3a23192007-05-27 16:42:29 +0000266
267 if (level) {
Blue Swirl97bf4852010-10-31 09:24:14 +0000268 trace_sun4m_cpu_set_irq_raise(irq);
blueswir1327ac2e2007-08-04 10:50:30 +0000269 env->pil_in |= 1 << irq;
Paolo Bonzini94ad5b02011-03-12 17:43:57 +0100270 cpu_kick_irq(env);
blueswir1b3a23192007-05-27 16:42:29 +0000271 } else {
Blue Swirl97bf4852010-10-31 09:24:14 +0000272 trace_sun4m_cpu_set_irq_lower(irq);
blueswir1327ac2e2007-08-04 10:50:30 +0000273 env->pil_in &= ~(1 << irq);
274 cpu_check_irqs(env);
blueswir1b3a23192007-05-27 16:42:29 +0000275 }
276}
277
278static void dummy_cpu_set_irq(void *opaque, int irq, int level)
279{
280}
281
bellardc68ea702005-11-21 23:33:12 +0000282static void main_cpu_reset(void *opaque)
283{
Andreas Färber98cec4a2012-03-14 01:38:24 +0100284 CPUSPARCState *env = opaque;
blueswir13d29fbe2007-05-17 19:21:46 +0000285
Andreas Färber1bba0dc2012-02-08 03:03:33 +0100286 cpu_state_reset(env);
blueswir13d29fbe2007-05-17 19:21:46 +0000287 env->halted = 0;
288}
289
290static void secondary_cpu_reset(void *opaque)
291{
Andreas Färber98cec4a2012-03-14 01:38:24 +0100292 CPUSPARCState *env = opaque;
blueswir13d29fbe2007-05-17 19:21:46 +0000293
Andreas Färber1bba0dc2012-02-08 03:03:33 +0100294 cpu_state_reset(env);
blueswir13d29fbe2007-05-17 19:21:46 +0000295 env->halted = 1;
bellardc68ea702005-11-21 23:33:12 +0000296}
297
blueswir16d0c2932008-11-02 10:51:05 +0000298static void cpu_halt_signal(void *opaque, int irq, int level)
299{
300 if (level && cpu_single_env)
301 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
302}
303
Aurelien Jarno409dbce2010-03-14 21:20:59 +0100304static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
305{
306 return addr - 0xf0000000ULL;
307}
308
blueswir13ebf5aa2007-11-28 20:54:33 +0000309static unsigned long sun4m_load_kernel(const char *kernel_filename,
blueswir1293f78b2008-05-12 17:22:13 +0000310 const char *initrd_filename,
Anthony Liguoric227f092009-10-01 16:12:16 -0500311 ram_addr_t RAM_size)
blueswir13ebf5aa2007-11-28 20:54:33 +0000312{
313 int linux_boot;
314 unsigned int i;
315 long initrd_size, kernel_size;
Gerd Hoffmann3c178e72009-10-07 13:37:06 +0200316 uint8_t *ptr;
blueswir13ebf5aa2007-11-28 20:54:33 +0000317
318 linux_boot = (kernel_filename != NULL);
319
320 kernel_size = 0;
321 if (linux_boot) {
Blue Swirlca20cf32009-09-20 14:58:02 +0000322 int bswap_needed;
323
324#ifdef BSWAP_NEEDED
325 bswap_needed = 1;
326#else
327 bswap_needed = 0;
328#endif
Aurelien Jarno409dbce2010-03-14 21:20:59 +0100329 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
330 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
blueswir13ebf5aa2007-11-28 20:54:33 +0000331 if (kernel_size < 0)
blueswir1293f78b2008-05-12 17:22:13 +0000332 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
Blue Swirlca20cf32009-09-20 14:58:02 +0000333 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
334 TARGET_PAGE_SIZE);
blueswir13ebf5aa2007-11-28 20:54:33 +0000335 if (kernel_size < 0)
blueswir1293f78b2008-05-12 17:22:13 +0000336 kernel_size = load_image_targphys(kernel_filename,
337 KERNEL_LOAD_ADDR,
338 RAM_size - KERNEL_LOAD_ADDR);
blueswir13ebf5aa2007-11-28 20:54:33 +0000339 if (kernel_size < 0) {
340 fprintf(stderr, "qemu: could not load kernel '%s'\n",
341 kernel_filename);
342 exit(1);
343 }
344
345 /* load initrd */
346 initrd_size = 0;
347 if (initrd_filename) {
blueswir1293f78b2008-05-12 17:22:13 +0000348 initrd_size = load_image_targphys(initrd_filename,
349 INITRD_LOAD_ADDR,
350 RAM_size - INITRD_LOAD_ADDR);
blueswir13ebf5aa2007-11-28 20:54:33 +0000351 if (initrd_size < 0) {
352 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
353 initrd_filename);
354 exit(1);
355 }
356 }
357 if (initrd_size > 0) {
358 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
Gerd Hoffmann3c178e72009-10-07 13:37:06 +0200359 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
360 if (ldl_p(ptr) == 0x48647253) { // HdrS
361 stl_p(ptr + 16, INITRD_LOAD_ADDR);
362 stl_p(ptr + 20, initrd_size);
blueswir13ebf5aa2007-11-28 20:54:33 +0000363 break;
364 }
365 }
366 }
367 }
368 return kernel_size;
369}
370
Anthony Liguoric227f092009-10-01 16:12:16 -0500371static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
Blue Swirl4b48bf02009-08-08 20:24:47 +0000372{
373 DeviceState *dev;
374 SysBusDevice *s;
375
376 dev = qdev_create(NULL, "iommu");
377 qdev_prop_set_uint32(dev, "version", version);
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200378 qdev_init_nofail(dev);
Blue Swirl4b48bf02009-08-08 20:24:47 +0000379 s = sysbus_from_qdev(dev);
380 sysbus_connect_irq(s, 0, irq);
381 sysbus_mmio_map(s, 0, addr);
382
383 return s;
384}
385
Anthony Liguoric227f092009-10-01 16:12:16 -0500386static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
Bob Breuer86d1c382010-12-18 11:09:04 -0600387 void *iommu, qemu_irq *dev_irq, int is_ledma)
Paul Brook9d07d752009-05-14 22:35:07 +0100388{
389 DeviceState *dev;
390 SysBusDevice *s;
391
Blue Swirl74ff8d92009-08-08 21:43:12 +0000392 dev = qdev_create(NULL, "sparc32_dma");
393 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
Bob Breuer86d1c382010-12-18 11:09:04 -0600394 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200395 qdev_init_nofail(dev);
Blue Swirl74ff8d92009-08-08 21:43:12 +0000396 s = sysbus_from_qdev(dev);
397 sysbus_connect_irq(s, 0, parent_irq);
398 *dev_irq = qdev_get_gpio_in(dev, 0);
399 sysbus_mmio_map(s, 0, daddr);
400
401 return s;
402}
403
Anthony Liguoric227f092009-10-01 16:12:16 -0500404static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
Blue Swirl74ff8d92009-08-08 21:43:12 +0000405 void *dma_opaque, qemu_irq irq)
406{
407 DeviceState *dev;
408 SysBusDevice *s;
409 qemu_irq reset;
410
Paul Brook9d07d752009-05-14 22:35:07 +0100411 qemu_check_nic_model(&nd_table[0], "lance");
412
413 dev = qdev_create(NULL, "lance");
Gerd Hoffmann76224832009-10-21 15:25:32 +0200414 qdev_set_nic_properties(dev, nd);
Blue Swirldaa65492009-07-21 08:36:52 +0000415 qdev_prop_set_ptr(dev, "dma", dma_opaque);
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200416 qdev_init_nofail(dev);
Paul Brook9d07d752009-05-14 22:35:07 +0100417 s = sysbus_from_qdev(dev);
418 sysbus_mmio_map(s, 0, leaddr);
419 sysbus_connect_irq(s, 0, irq);
Blue Swirl74ff8d92009-08-08 21:43:12 +0000420 reset = qdev_get_gpio_in(dev, 0);
421 qdev_connect_gpio_out(dma_opaque, 0, reset);
Paul Brook9d07d752009-05-14 22:35:07 +0100422}
423
Anthony Liguoric227f092009-10-01 16:12:16 -0500424static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
425 target_phys_addr_t addrg,
Blue Swirl462eda22009-08-25 18:29:36 +0000426 qemu_irq **parent_irq)
Blue Swirl4b48bf02009-08-08 20:24:47 +0000427{
428 DeviceState *dev;
429 SysBusDevice *s;
430 unsigned int i, j;
431
432 dev = qdev_create(NULL, "slavio_intctl");
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200433 qdev_init_nofail(dev);
Blue Swirl4b48bf02009-08-08 20:24:47 +0000434
435 s = sysbus_from_qdev(dev);
436
437 for (i = 0; i < MAX_CPUS; i++) {
438 for (j = 0; j < MAX_PILS; j++) {
439 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
440 }
441 }
442 sysbus_mmio_map(s, 0, addrg);
443 for (i = 0; i < MAX_CPUS; i++) {
444 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
445 }
446
447 return dev;
448}
449
450#define SYS_TIMER_OFFSET 0x10000ULL
451#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
452
Anthony Liguoric227f092009-10-01 16:12:16 -0500453static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
Blue Swirl4b48bf02009-08-08 20:24:47 +0000454 qemu_irq *cpu_irqs, unsigned int num_cpus)
455{
456 DeviceState *dev;
457 SysBusDevice *s;
458 unsigned int i;
459
460 dev = qdev_create(NULL, "slavio_timer");
461 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200462 qdev_init_nofail(dev);
Blue Swirl4b48bf02009-08-08 20:24:47 +0000463 s = sysbus_from_qdev(dev);
464 sysbus_connect_irq(s, 0, master_irq);
465 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
466
467 for (i = 0; i < MAX_CPUS; i++) {
Anthony Liguoric227f092009-10-01 16:12:16 -0500468 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
Blue Swirl4b48bf02009-08-08 20:24:47 +0000469 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
470 }
471}
472
473#define MISC_LEDS 0x01600000
474#define MISC_CFG 0x01800000
475#define MISC_DIAG 0x01a00000
476#define MISC_MDM 0x01b00000
477#define MISC_SYS 0x01f00000
478
Anthony Liguoric227f092009-10-01 16:12:16 -0500479static void slavio_misc_init(target_phys_addr_t base,
480 target_phys_addr_t aux1_base,
481 target_phys_addr_t aux2_base, qemu_irq irq,
Blue Swirlb2b6f6e2009-08-09 07:27:29 +0000482 qemu_irq fdc_tc)
Blue Swirl4b48bf02009-08-08 20:24:47 +0000483{
484 DeviceState *dev;
485 SysBusDevice *s;
486
487 dev = qdev_create(NULL, "slavio_misc");
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200488 qdev_init_nofail(dev);
Blue Swirl4b48bf02009-08-08 20:24:47 +0000489 s = sysbus_from_qdev(dev);
490 if (base) {
491 /* 8 bit registers */
492 /* Slavio control */
493 sysbus_mmio_map(s, 0, base + MISC_CFG);
494 /* Diagnostics */
495 sysbus_mmio_map(s, 1, base + MISC_DIAG);
496 /* Modem control */
497 sysbus_mmio_map(s, 2, base + MISC_MDM);
498 /* 16 bit registers */
499 /* ss600mp diag LEDs */
500 sysbus_mmio_map(s, 3, base + MISC_LEDS);
501 /* 32 bit registers */
502 /* System control */
503 sysbus_mmio_map(s, 4, base + MISC_SYS);
504 }
505 if (aux1_base) {
506 /* AUX 1 (Misc System Functions) */
507 sysbus_mmio_map(s, 5, aux1_base);
508 }
509 if (aux2_base) {
510 /* AUX 2 (Software Powerdown Control) */
511 sysbus_mmio_map(s, 6, aux2_base);
512 }
513 sysbus_connect_irq(s, 0, irq);
514 sysbus_connect_irq(s, 1, fdc_tc);
Blue Swirld9c32312009-08-09 08:42:19 +0000515 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
Blue Swirl4b48bf02009-08-08 20:24:47 +0000516}
517
Anthony Liguoric227f092009-10-01 16:12:16 -0500518static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
Blue Swirl4b48bf02009-08-08 20:24:47 +0000519{
520 DeviceState *dev;
521 SysBusDevice *s;
522
523 dev = qdev_create(NULL, "eccmemctl");
524 qdev_prop_set_uint32(dev, "version", version);
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200525 qdev_init_nofail(dev);
Blue Swirl4b48bf02009-08-08 20:24:47 +0000526 s = sysbus_from_qdev(dev);
527 sysbus_connect_irq(s, 0, irq);
528 sysbus_mmio_map(s, 0, base);
529 if (version == 0) { // SS-600MP only
530 sysbus_mmio_map(s, 1, base + 0x1000);
531 }
532}
533
Anthony Liguoric227f092009-10-01 16:12:16 -0500534static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
Blue Swirl4b48bf02009-08-08 20:24:47 +0000535{
536 DeviceState *dev;
537 SysBusDevice *s;
538
539 dev = qdev_create(NULL, "apc");
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200540 qdev_init_nofail(dev);
Blue Swirl4b48bf02009-08-08 20:24:47 +0000541 s = sysbus_from_qdev(dev);
542 /* Power management (APC) XXX: not a Slavio device */
543 sysbus_mmio_map(s, 0, power_base);
544 sysbus_connect_irq(s, 0, cpu_halt);
545}
546
Anthony Liguoric227f092009-10-01 16:12:16 -0500547static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
Blue Swirl4b48bf02009-08-08 20:24:47 +0000548 int height, int depth)
549{
550 DeviceState *dev;
551 SysBusDevice *s;
552
553 dev = qdev_create(NULL, "SUNW,tcx");
554 qdev_prop_set_taddr(dev, "addr", addr);
555 qdev_prop_set_uint32(dev, "vram_size", vram_size);
556 qdev_prop_set_uint16(dev, "width", width);
557 qdev_prop_set_uint16(dev, "height", height);
558 qdev_prop_set_uint16(dev, "depth", depth);
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200559 qdev_init_nofail(dev);
Blue Swirl4b48bf02009-08-08 20:24:47 +0000560 s = sysbus_from_qdev(dev);
561 /* 8-bit plane */
562 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
563 /* DAC */
564 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
565 /* TEC (dummy) */
566 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
567 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
568 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
569 if (depth == 24) {
570 /* 24-bit plane */
571 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
572 /* Control plane */
573 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
574 } else {
575 /* THC 8 bit (dummy) */
576 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
577 }
578}
579
Blue Swirl325f2742009-07-13 16:11:08 +0000580/* NCR89C100/MACIO Internal ID register */
581static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
582
Anthony Liguoric227f092009-10-01 16:12:16 -0500583static void idreg_init(target_phys_addr_t addr)
Blue Swirl325f2742009-07-13 16:11:08 +0000584{
585 DeviceState *dev;
586 SysBusDevice *s;
587
588 dev = qdev_create(NULL, "macio_idreg");
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200589 qdev_init_nofail(dev);
Blue Swirl325f2742009-07-13 16:11:08 +0000590 s = sysbus_from_qdev(dev);
591
592 sysbus_mmio_map(s, 0, addr);
593 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
594}
595
Avi Kivity3150fa52011-10-03 14:27:32 +0200596typedef struct IDRegState {
597 SysBusDevice busdev;
598 MemoryRegion mem;
599} IDRegState;
600
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200601static int idreg_init1(SysBusDevice *dev)
Blue Swirl325f2742009-07-13 16:11:08 +0000602{
Avi Kivity3150fa52011-10-03 14:27:32 +0200603 IDRegState *s = FROM_SYSBUS(IDRegState, dev);
Blue Swirl325f2742009-07-13 16:11:08 +0000604
Avi Kivityc5705a72011-12-20 15:59:12 +0200605 memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data));
606 vmstate_register_ram_global(&s->mem);
Avi Kivity3150fa52011-10-03 14:27:32 +0200607 memory_region_set_readonly(&s->mem, true);
Avi Kivity750ecd42011-11-27 11:38:10 +0200608 sysbus_init_mmio(dev, &s->mem);
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200609 return 0;
Blue Swirl325f2742009-07-13 16:11:08 +0000610}
611
Anthony Liguori999e12b2012-01-24 13:12:29 -0600612static void idreg_class_init(ObjectClass *klass, void *data)
613{
614 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
615
616 k->init = idreg_init1;
617}
618
Anthony Liguori39bffca2011-12-07 21:34:16 -0600619static TypeInfo idreg_info = {
620 .name = "macio_idreg",
621 .parent = TYPE_SYS_BUS_DEVICE,
622 .instance_size = sizeof(IDRegState),
623 .class_init = idreg_class_init,
Blue Swirl325f2742009-07-13 16:11:08 +0000624};
625
Avi Kivity3150fa52011-10-03 14:27:32 +0200626typedef struct AFXState {
627 SysBusDevice busdev;
628 MemoryRegion mem;
629} AFXState;
630
Artyom Tarasenkoc5de3862009-12-13 13:30:19 +0000631/* SS-5 TCX AFX register */
632static void afx_init(target_phys_addr_t addr)
633{
634 DeviceState *dev;
635 SysBusDevice *s;
636
637 dev = qdev_create(NULL, "tcx_afx");
638 qdev_init_nofail(dev);
639 s = sysbus_from_qdev(dev);
640
641 sysbus_mmio_map(s, 0, addr);
642}
643
644static int afx_init1(SysBusDevice *dev)
645{
Avi Kivity3150fa52011-10-03 14:27:32 +0200646 AFXState *s = FROM_SYSBUS(AFXState, dev);
Artyom Tarasenkoc5de3862009-12-13 13:30:19 +0000647
Avi Kivityc5705a72011-12-20 15:59:12 +0200648 memory_region_init_ram(&s->mem, "sun4m.afx", 4);
649 vmstate_register_ram_global(&s->mem);
Avi Kivity750ecd42011-11-27 11:38:10 +0200650 sysbus_init_mmio(dev, &s->mem);
Artyom Tarasenkoc5de3862009-12-13 13:30:19 +0000651 return 0;
652}
653
Anthony Liguori999e12b2012-01-24 13:12:29 -0600654static void afx_class_init(ObjectClass *klass, void *data)
655{
656 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
657
658 k->init = afx_init1;
659}
660
Anthony Liguori39bffca2011-12-07 21:34:16 -0600661static TypeInfo afx_info = {
662 .name = "tcx_afx",
663 .parent = TYPE_SYS_BUS_DEVICE,
664 .instance_size = sizeof(AFXState),
665 .class_init = afx_class_init,
Artyom Tarasenkoc5de3862009-12-13 13:30:19 +0000666};
667
Avi Kivity3150fa52011-10-03 14:27:32 +0200668typedef struct PROMState {
669 SysBusDevice busdev;
670 MemoryRegion prom;
671} PROMState;
672
Blue Swirlf48f6562009-07-16 13:48:10 +0000673/* Boot PROM (OpenBIOS) */
Aurelien Jarno409dbce2010-03-14 21:20:59 +0100674static uint64_t translate_prom_address(void *opaque, uint64_t addr)
675{
676 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
677 return addr + *base_addr - PROM_VADDR;
678}
679
Anthony Liguoric227f092009-10-01 16:12:16 -0500680static void prom_init(target_phys_addr_t addr, const char *bios_name)
Blue Swirlf48f6562009-07-16 13:48:10 +0000681{
682 DeviceState *dev;
683 SysBusDevice *s;
684 char *filename;
685 int ret;
686
687 dev = qdev_create(NULL, "openprom");
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200688 qdev_init_nofail(dev);
Blue Swirlf48f6562009-07-16 13:48:10 +0000689 s = sysbus_from_qdev(dev);
690
691 sysbus_mmio_map(s, 0, addr);
692
693 /* load boot prom */
694 if (bios_name == NULL) {
695 bios_name = PROM_FILENAME;
696 }
697 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
698 if (filename) {
Aurelien Jarno409dbce2010-03-14 21:20:59 +0100699 ret = load_elf(filename, translate_prom_address, &addr, NULL,
700 NULL, NULL, 1, ELF_MACHINE, 0);
Blue Swirlf48f6562009-07-16 13:48:10 +0000701 if (ret < 0 || ret > PROM_SIZE_MAX) {
702 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
703 }
Anthony Liguori7267c092011-08-20 22:09:37 -0500704 g_free(filename);
Blue Swirlf48f6562009-07-16 13:48:10 +0000705 } else {
706 ret = -1;
707 }
708 if (ret < 0 || ret > PROM_SIZE_MAX) {
709 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
710 exit(1);
711 }
712}
713
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200714static int prom_init1(SysBusDevice *dev)
Blue Swirlf48f6562009-07-16 13:48:10 +0000715{
Avi Kivity3150fa52011-10-03 14:27:32 +0200716 PROMState *s = FROM_SYSBUS(PROMState, dev);
Blue Swirlf48f6562009-07-16 13:48:10 +0000717
Avi Kivityc5705a72011-12-20 15:59:12 +0200718 memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
719 vmstate_register_ram_global(&s->prom);
Avi Kivity3150fa52011-10-03 14:27:32 +0200720 memory_region_set_readonly(&s->prom, true);
Avi Kivity750ecd42011-11-27 11:38:10 +0200721 sysbus_init_mmio(dev, &s->prom);
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200722 return 0;
Blue Swirlf48f6562009-07-16 13:48:10 +0000723}
724
Anthony Liguori999e12b2012-01-24 13:12:29 -0600725static Property prom_properties[] = {
726 {/* end of property list */},
727};
728
729static void prom_class_init(ObjectClass *klass, void *data)
730{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600731 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600732 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
733
734 k->init = prom_init1;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600735 dc->props = prom_properties;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600736}
737
Anthony Liguori39bffca2011-12-07 21:34:16 -0600738static TypeInfo prom_info = {
739 .name = "openprom",
740 .parent = TYPE_SYS_BUS_DEVICE,
741 .instance_size = sizeof(PROMState),
742 .class_init = prom_class_init,
Blue Swirlf48f6562009-07-16 13:48:10 +0000743};
744
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200745typedef struct RamDevice
746{
747 SysBusDevice busdev;
Avi Kivity3150fa52011-10-03 14:27:32 +0200748 MemoryRegion ram;
Blue Swirl04843622009-07-21 11:20:11 +0000749 uint64_t size;
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200750} RamDevice;
751
Blue Swirla350db82009-07-16 13:48:14 +0000752/* System RAM */
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200753static int ram_init1(SysBusDevice *dev)
Blue Swirla350db82009-07-16 13:48:14 +0000754{
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200755 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
Blue Swirla350db82009-07-16 13:48:14 +0000756
Avi Kivityc5705a72011-12-20 15:59:12 +0200757 memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
758 vmstate_register_ram_global(&d->ram);
Avi Kivity750ecd42011-11-27 11:38:10 +0200759 sysbus_init_mmio(dev, &d->ram);
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200760 return 0;
Blue Swirla350db82009-07-16 13:48:14 +0000761}
762
Anthony Liguoric227f092009-10-01 16:12:16 -0500763static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
Blue Swirla350db82009-07-16 13:48:14 +0000764 uint64_t max_mem)
765{
766 DeviceState *dev;
767 SysBusDevice *s;
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200768 RamDevice *d;
Blue Swirla350db82009-07-16 13:48:14 +0000769
770 /* allocate RAM */
771 if ((uint64_t)RAM_size > max_mem) {
772 fprintf(stderr,
773 "qemu: Too much memory for this machine: %d, maximum %d\n",
774 (unsigned int)(RAM_size / (1024 * 1024)),
775 (unsigned int)(max_mem / (1024 * 1024)));
776 exit(1);
777 }
778 dev = qdev_create(NULL, "memory");
Blue Swirla350db82009-07-16 13:48:14 +0000779 s = sysbus_from_qdev(dev);
780
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200781 d = FROM_SYSBUS(RamDevice, s);
782 d->size = RAM_size;
Markus Armbrustere23a1b32009-10-07 01:15:58 +0200783 qdev_init_nofail(dev);
Gerd Hoffmannee6847d2009-07-15 13:43:31 +0200784
Blue Swirla350db82009-07-16 13:48:14 +0000785 sysbus_mmio_map(s, 0, addr);
786}
787
Anthony Liguori999e12b2012-01-24 13:12:29 -0600788static Property ram_properties[] = {
789 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
790 DEFINE_PROP_END_OF_LIST(),
791};
792
793static void ram_class_init(ObjectClass *klass, void *data)
794{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600795 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori999e12b2012-01-24 13:12:29 -0600796 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
797
798 k->init = ram_init1;
Anthony Liguori39bffca2011-12-07 21:34:16 -0600799 dc->props = ram_properties;
Anthony Liguori999e12b2012-01-24 13:12:29 -0600800}
801
Anthony Liguori39bffca2011-12-07 21:34:16 -0600802static TypeInfo ram_info = {
803 .name = "memory",
804 .parent = TYPE_SYS_BUS_DEVICE,
805 .instance_size = sizeof(RamDevice),
806 .class_init = ram_class_init,
Blue Swirla350db82009-07-16 13:48:14 +0000807};
808
Blue Swirl89835362010-01-13 18:52:50 +0000809static void cpu_devinit(const char *cpu_model, unsigned int id,
810 uint64_t prom_addr, qemu_irq **cpu_irqs)
Blue Swirl666713c2009-07-16 13:48:20 +0000811{
Andreas Färber98cec4a2012-03-14 01:38:24 +0100812 CPUSPARCState *env;
Blue Swirl666713c2009-07-16 13:48:20 +0000813
814 env = cpu_init(cpu_model);
815 if (!env) {
816 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
817 exit(1);
818 }
819
820 cpu_sparc_set_id(env, id);
821 if (id == 0) {
822 qemu_register_reset(main_cpu_reset, env);
823 } else {
824 qemu_register_reset(secondary_cpu_reset, env);
825 env->halted = 1;
826 }
827 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
828 env->prom_addr = prom_addr;
Blue Swirl666713c2009-07-16 13:48:20 +0000829}
830
Anthony Liguoric227f092009-10-01 16:12:16 -0500831static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
blueswir13ebf5aa2007-11-28 20:54:33 +0000832 const char *boot_device,
aliguori3023f332009-01-16 19:04:14 +0000833 const char *kernel_filename,
blueswir13ebf5aa2007-11-28 20:54:33 +0000834 const char *kernel_cmdline,
835 const char *initrd_filename, const char *cpu_model)
bellard420557e2004-09-30 22:13:50 +0000836{
bellard713c45f2005-02-22 19:08:41 +0000837 unsigned int i;
Paul Brookcfb9de92009-05-14 22:35:07 +0100838 void *iommu, *espdma, *ledma, *nvram;
Blue Swirla1961a42009-07-16 14:15:34 +0000839 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
Blue Swirl6f6260c2009-07-15 20:45:19 +0000840 espdma_irq, ledma_irq;
Blue Swirl73d74342010-09-11 16:38:33 +0000841 qemu_irq esp_reset, dma_enable;
Blue Swirl2582cfa2009-07-13 16:51:27 +0000842 qemu_irq fdc_tc;
blueswir16d0c2932008-11-02 10:51:05 +0000843 qemu_irq *cpu_halt;
blueswir15c6602c2008-11-05 19:25:39 +0000844 unsigned long kernel_size;
Gerd Hoffmannfd8014e2009-09-22 13:53:18 +0200845 DriveInfo *fd[MAX_FD];
blueswir13cce6242008-09-18 18:27:29 +0000846 void *fw_cfg;
Bob Breuer9a62fb22010-07-13 11:05:24 -0500847 unsigned int num_vsimms;
bellard420557e2004-09-30 22:13:50 +0000848
bellardba3c64f2005-12-05 20:31:52 +0000849 /* init CPUs */
blueswir13ebf5aa2007-11-28 20:54:33 +0000850 if (!cpu_model)
851 cpu_model = hwdef->default_cpu_model;
blueswir1b3a23192007-05-27 16:42:29 +0000852
bellardba3c64f2005-12-05 20:31:52 +0000853 for(i = 0; i < smp_cpus; i++) {
Blue Swirl89835362010-01-13 18:52:50 +0000854 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
bellardba3c64f2005-12-05 20:31:52 +0000855 }
blueswir1b3a23192007-05-27 16:42:29 +0000856
857 for (i = smp_cpus; i < MAX_CPUS; i++)
858 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
859
blueswir13ebf5aa2007-11-28 20:54:33 +0000860
blueswir13ebf5aa2007-11-28 20:54:33 +0000861 /* set up devices */
Blue Swirla350db82009-07-16 13:48:14 +0000862 ram_init(0, RAM_size, hwdef->max_mem);
Artyom Tarasenko676d9b92010-04-18 00:34:03 +0200863 /* models without ECC don't trap when missing ram is accessed */
864 if (!hwdef->ecc_base) {
865 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
866 }
Blue Swirla350db82009-07-16 13:48:14 +0000867
Blue Swirlf48f6562009-07-16 13:48:10 +0000868 prom_init(hwdef->slavio_base, bios_name);
869
Blue Swirld453c2c2009-08-23 12:23:30 +0000870 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
871 hwdef->intctl_base + 0x10000ULL,
Blue Swirl462eda22009-08-25 18:29:36 +0000872 cpu_irqs);
Blue Swirla1961a42009-07-16 14:15:34 +0000873
874 for (i = 0; i < 32; i++) {
Blue Swirld453c2c2009-08-23 12:23:30 +0000875 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
Blue Swirla1961a42009-07-16 14:15:34 +0000876 }
877 for (i = 0; i < MAX_CPUS; i++) {
Blue Swirld453c2c2009-08-23 12:23:30 +0000878 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
Blue Swirla1961a42009-07-16 14:15:34 +0000879 }
blueswir1b3a23192007-05-27 16:42:29 +0000880
blueswir1fe096122008-12-24 20:21:18 +0000881 if (hwdef->idreg_base) {
Blue Swirl325f2742009-07-13 16:11:08 +0000882 idreg_init(hwdef->idreg_base);
blueswir14c2485d2007-12-27 20:26:23 +0000883 }
884
Artyom Tarasenkoc5de3862009-12-13 13:30:19 +0000885 if (hwdef->afx_base) {
886 afx_init(hwdef->afx_base);
887 }
888
blueswir1ff403da2008-01-01 17:04:45 +0000889 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
Blue Swirlc533e0b2009-08-08 20:55:37 +0000890 slavio_irq[30]);
blueswir1ff403da2008-01-01 17:04:45 +0000891
Artyom Tarasenko33863762010-05-08 16:10:14 +0200892 if (hwdef->iommu_pad_base) {
893 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
894 Software shouldn't use aliased addresses, neither should it crash
895 when does. Using empty_slot instead of aliasing can help with
896 debugging such accesses */
897 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
898 }
899
Blue Swirlc533e0b2009-08-08 20:55:37 +0000900 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
Bob Breuer86d1c382010-12-18 11:09:04 -0600901 iommu, &espdma_irq, 0);
blueswir12d069ba2007-08-16 19:56:27 +0000902
blueswir15aca8c32007-05-26 17:39:43 +0000903 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
Bob Breuer86d1c382010-12-18 11:09:04 -0600904 slavio_irq[16], iommu, &ledma_irq, 1);
bellardba3c64f2005-12-05 20:31:52 +0000905
blueswir1eee0b832007-04-21 19:45:49 +0000906 if (graphic_depth != 8 && graphic_depth != 24) {
907 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
908 exit (1);
909 }
Bob Breuer9a62fb22010-07-13 11:05:24 -0500910 num_vsimms = 0;
911 if (num_vsimms == 0) {
912 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
913 graphic_depth);
914 }
915
916 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
917 /* vsimm registers probed by OBP */
918 if (hwdef->vsimm[i].reg_base) {
919 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
920 }
921 }
922
923 if (hwdef->sx_base) {
924 empty_slot_init(hwdef->sx_base, 0x2000);
925 }
blueswir1dbe06e12007-05-27 19:38:20 +0000926
Blue Swirl74ff8d92009-08-08 21:43:12 +0000927 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
blueswir1dbe06e12007-05-27 19:38:20 +0000928
Blue Swirld95d8f12009-08-08 21:04:18 +0000929 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
blueswir181732d12007-10-06 11:25:43 +0000930
Blue Swirlc533e0b2009-08-08 20:55:37 +0000931 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
blueswir181732d12007-10-06 11:25:43 +0000932
Blue Swirlc533e0b2009-08-08 20:55:37 +0000933 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
Anthony Liguori993fbfd2009-05-21 16:54:00 -0500934 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
Stefan Weil5cbdb3a2012-04-07 09:23:39 +0200935 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
936 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
Blue Swirlc533e0b2009-08-08 20:55:37 +0000937 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
aurel32aeeb69c2009-01-14 14:47:56 +0000938 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
blueswir1741402f2007-11-04 11:59:15 +0000939
blueswir16d0c2932008-11-02 10:51:05 +0000940 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
Blue Swirlb2b6f6e2009-08-09 07:27:29 +0000941 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
942 slavio_irq[30], fdc_tc);
943
Blue Swirl2582cfa2009-07-13 16:51:27 +0000944 if (hwdef->apc_base) {
945 apc_init(hwdef->apc_base, cpu_halt[0]);
946 }
blueswir12be17eb2008-03-21 18:05:23 +0000947
blueswir1fe096122008-12-24 20:21:18 +0000948 if (hwdef->fd_base) {
thse4bcb142007-12-02 04:51:10 +0000949 /* there is zero or one floppy drive */
blueswir1309e60b2008-02-29 19:26:20 +0000950 memset(fd, 0, sizeof(fd));
Gerd Hoffmannfd8014e2009-09-22 13:53:18 +0200951 fd[0] = drive_get(IF_FLOPPY, 0, 0);
Blue Swirlc533e0b2009-08-08 20:55:37 +0000952 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
Blue Swirl2582cfa2009-07-13 16:51:27 +0000953 &fdc_tc);
thse4bcb142007-12-02 04:51:10 +0000954 }
955
956 if (drive_get_max_bus(IF_SCSI) > 0) {
957 fprintf(stderr, "qemu: too many SCSI bus\n");
958 exit(1);
959 }
960
Paul Brookcfb9de92009-05-14 22:35:07 +0100961 esp_init(hwdef->esp_base, 2,
962 espdma_memory_read, espdma_memory_write,
Blue Swirl73d74342010-09-11 16:38:33 +0000963 espdma, espdma_irq, &esp_reset, &dma_enable);
Blue Swirl74ff8d92009-08-08 21:43:12 +0000964
Blue Swirl73d74342010-09-11 16:38:33 +0000965 qdev_connect_gpio_out(espdma, 0, esp_reset);
966 qdev_connect_gpio_out(espdma, 1, dma_enable);
thsf1587552007-01-10 11:46:13 +0000967
Blue Swirlfa28ec52009-07-16 13:47:45 +0000968 if (hwdef->cs_base) {
969 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
Blue Swirlc533e0b2009-08-08 20:55:37 +0000970 slavio_irq[5]);
Blue Swirlfa28ec52009-07-16 13:47:45 +0000971 }
blueswir1b3ceef22007-06-25 19:56:13 +0000972
Bob Breuer9a62fb22010-07-13 11:05:24 -0500973 if (hwdef->dbri_base) {
974 /* ISDN chip with attached CS4215 audio codec */
975 /* prom space */
976 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
977 /* reg space */
978 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
979 }
980
981 if (hwdef->bpp_base) {
982 /* parallel port */
983 empty_slot_init(hwdef->bpp_base, 0x20);
984 }
985
blueswir1293f78b2008-05-12 17:22:13 +0000986 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
987 RAM_size);
blueswir136cd9212007-04-01 15:44:43 +0000988
blueswir136cd9212007-04-01 15:44:43 +0000989 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
blueswir1b3ceef22007-06-25 19:56:13 +0000990 boot_device, RAM_size, kernel_size, graphic_width,
blueswir1905fdcb2008-09-18 18:33:18 +0000991 graphic_height, graphic_depth, hwdef->nvram_machine_id,
992 "Sun4m");
blueswir17eb0c8e2007-12-09 17:03:50 +0000993
blueswir1fe096122008-12-24 20:21:18 +0000994 if (hwdef->ecc_base)
Blue Swirlc533e0b2009-08-08 20:55:37 +0000995 ecc_init(hwdef->ecc_base, slavio_irq[28],
blueswir1e42c20b2008-01-17 21:04:16 +0000996 hwdef->ecc_version);
blueswir13cce6242008-09-18 18:27:29 +0000997
998 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
999 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
blueswir1905fdcb2008-09-18 18:33:18 +00001000 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1001 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
blueswir1fbfcf952008-09-18 18:34:28 +00001002 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
blueswir1513f7892009-03-08 09:51:29 +00001003 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1004 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1005 if (kernel_cmdline) {
1006 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
Gerd Hoffmann3c178e72009-10-07 13:37:06 +02001007 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
Blue Swirl6bb4ca52009-12-27 18:25:49 +00001008 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1009 (uint8_t*)strdup(kernel_cmdline),
1010 strlen(kernel_cmdline) + 1);
Blue Swirl748a4ee2010-08-03 21:00:58 +00001011 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1012 strlen(kernel_cmdline) + 1);
blueswir1513f7892009-03-08 09:51:29 +00001013 } else {
1014 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
Blue Swirl748a4ee2010-08-03 21:00:58 +00001015 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
blueswir1513f7892009-03-08 09:51:29 +00001016 }
1017 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1018 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1019 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1020 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
bellard420557e2004-09-30 22:13:50 +00001021}
bellardc0e564d2005-06-05 15:17:28 +00001022
blueswir1905fdcb2008-09-18 18:33:18 +00001023enum {
1024 ss2_id = 0,
1025 ss5_id = 32,
1026 vger_id,
1027 lx_id,
1028 ss4_id,
1029 scls_id,
1030 sbook_id,
1031 ss10_id = 64,
1032 ss20_id,
1033 ss600mp_id,
1034 ss1000_id = 96,
1035 ss2000_id,
1036};
1037
blueswir18137cde2008-10-27 15:56:56 +00001038static const struct sun4m_hwdef sun4m_hwdefs[] = {
blueswir136cd9212007-04-01 15:44:43 +00001039 /* SS-5 */
1040 {
1041 .iommu_base = 0x10000000,
Artyom Tarasenko33863762010-05-08 16:10:14 +02001042 .iommu_pad_base = 0x10004000,
1043 .iommu_pad_len = 0x0fffb000,
blueswir136cd9212007-04-01 15:44:43 +00001044 .tcx_base = 0x50000000,
1045 .cs_base = 0x6c000000,
blueswir1384ccb52007-05-06 17:33:14 +00001046 .slavio_base = 0x70000000,
blueswir136cd9212007-04-01 15:44:43 +00001047 .ms_kb_base = 0x71000000,
1048 .serial_base = 0x71100000,
1049 .nvram_base = 0x71200000,
1050 .fd_base = 0x71400000,
1051 .counter_base = 0x71d00000,
1052 .intctl_base = 0x71e00000,
blueswir14c2485d2007-12-27 20:26:23 +00001053 .idreg_base = 0x78000000,
blueswir136cd9212007-04-01 15:44:43 +00001054 .dma_base = 0x78400000,
1055 .esp_base = 0x78800000,
1056 .le_base = 0x78c00000,
blueswir1127fc402008-02-01 20:12:40 +00001057 .apc_base = 0x6a000000,
Artyom Tarasenkoc5de3862009-12-13 13:30:19 +00001058 .afx_base = 0x6e000000,
blueswir10019ad52008-01-27 09:49:28 +00001059 .aux1_base = 0x71900000,
1060 .aux2_base = 0x71910000,
blueswir1905fdcb2008-09-18 18:33:18 +00001061 .nvram_machine_id = 0x80,
1062 .machine_id = ss5_id,
blueswir1cf3102a2007-12-29 09:07:00 +00001063 .iommu_version = 0x05000000,
blueswir13ebf5aa2007-11-28 20:54:33 +00001064 .max_mem = 0x10000000,
1065 .default_cpu_model = "Fujitsu MB86904",
blueswir1e0353fe2007-04-01 15:55:28 +00001066 },
1067 /* SS-10 */
blueswir1e0353fe2007-04-01 15:55:28 +00001068 {
blueswir15dcb6b92007-05-19 12:58:30 +00001069 .iommu_base = 0xfe0000000ULL,
1070 .tcx_base = 0xe20000000ULL,
blueswir15dcb6b92007-05-19 12:58:30 +00001071 .slavio_base = 0xff0000000ULL,
1072 .ms_kb_base = 0xff1000000ULL,
1073 .serial_base = 0xff1100000ULL,
1074 .nvram_base = 0xff1200000ULL,
1075 .fd_base = 0xff1700000ULL,
1076 .counter_base = 0xff1300000ULL,
1077 .intctl_base = 0xff1400000ULL,
blueswir14c2485d2007-12-27 20:26:23 +00001078 .idreg_base = 0xef0000000ULL,
blueswir15dcb6b92007-05-19 12:58:30 +00001079 .dma_base = 0xef0400000ULL,
1080 .esp_base = 0xef0800000ULL,
1081 .le_base = 0xef0c00000ULL,
blueswir10019ad52008-01-27 09:49:28 +00001082 .apc_base = 0xefa000000ULL, // XXX should not exist
blueswir1127fc402008-02-01 20:12:40 +00001083 .aux1_base = 0xff1800000ULL,
1084 .aux2_base = 0xff1a01000ULL,
blueswir17eb0c8e2007-12-09 17:03:50 +00001085 .ecc_base = 0xf00000000ULL,
1086 .ecc_version = 0x10000000, // version 0, implementation 1
blueswir1905fdcb2008-09-18 18:33:18 +00001087 .nvram_machine_id = 0x72,
1088 .machine_id = ss10_id,
blueswir17fbfb132007-11-17 09:04:09 +00001089 .iommu_version = 0x03000000,
blueswir16ef05b92008-05-01 18:21:46 +00001090 .max_mem = 0xf00000000ULL,
blueswir13ebf5aa2007-11-28 20:54:33 +00001091 .default_cpu_model = "TI SuperSparc II",
blueswir136cd9212007-04-01 15:44:43 +00001092 },
blueswir16a3b9cc2007-11-11 17:56:38 +00001093 /* SS-600MP */
1094 {
1095 .iommu_base = 0xfe0000000ULL,
1096 .tcx_base = 0xe20000000ULL,
blueswir16a3b9cc2007-11-11 17:56:38 +00001097 .slavio_base = 0xff0000000ULL,
1098 .ms_kb_base = 0xff1000000ULL,
1099 .serial_base = 0xff1100000ULL,
1100 .nvram_base = 0xff1200000ULL,
blueswir16a3b9cc2007-11-11 17:56:38 +00001101 .counter_base = 0xff1300000ULL,
1102 .intctl_base = 0xff1400000ULL,
1103 .dma_base = 0xef0081000ULL,
1104 .esp_base = 0xef0080000ULL,
1105 .le_base = 0xef0060000ULL,
blueswir10019ad52008-01-27 09:49:28 +00001106 .apc_base = 0xefa000000ULL, // XXX should not exist
blueswir1127fc402008-02-01 20:12:40 +00001107 .aux1_base = 0xff1800000ULL,
1108 .aux2_base = 0xff1a01000ULL, // XXX should not exist
blueswir17eb0c8e2007-12-09 17:03:50 +00001109 .ecc_base = 0xf00000000ULL,
1110 .ecc_version = 0x00000000, // version 0, implementation 0
blueswir1905fdcb2008-09-18 18:33:18 +00001111 .nvram_machine_id = 0x71,
1112 .machine_id = ss600mp_id,
blueswir17fbfb132007-11-17 09:04:09 +00001113 .iommu_version = 0x01000000,
blueswir16ef05b92008-05-01 18:21:46 +00001114 .max_mem = 0xf00000000ULL,
blueswir13ebf5aa2007-11-28 20:54:33 +00001115 .default_cpu_model = "TI SuperSparc II",
blueswir16a3b9cc2007-11-11 17:56:38 +00001116 },
blueswir1ae409722007-12-10 20:00:11 +00001117 /* SS-20 */
1118 {
1119 .iommu_base = 0xfe0000000ULL,
1120 .tcx_base = 0xe20000000ULL,
blueswir1ae409722007-12-10 20:00:11 +00001121 .slavio_base = 0xff0000000ULL,
1122 .ms_kb_base = 0xff1000000ULL,
1123 .serial_base = 0xff1100000ULL,
1124 .nvram_base = 0xff1200000ULL,
1125 .fd_base = 0xff1700000ULL,
1126 .counter_base = 0xff1300000ULL,
1127 .intctl_base = 0xff1400000ULL,
blueswir14c2485d2007-12-27 20:26:23 +00001128 .idreg_base = 0xef0000000ULL,
blueswir1ae409722007-12-10 20:00:11 +00001129 .dma_base = 0xef0400000ULL,
1130 .esp_base = 0xef0800000ULL,
1131 .le_base = 0xef0c00000ULL,
Bob Breuer9a62fb22010-07-13 11:05:24 -05001132 .bpp_base = 0xef4800000ULL,
blueswir10019ad52008-01-27 09:49:28 +00001133 .apc_base = 0xefa000000ULL, // XXX should not exist
blueswir1577d8dd2008-02-11 20:01:36 +00001134 .aux1_base = 0xff1800000ULL,
1135 .aux2_base = 0xff1a01000ULL,
Bob Breuer9a62fb22010-07-13 11:05:24 -05001136 .dbri_base = 0xee0000000ULL,
1137 .sx_base = 0xf80000000ULL,
1138 .vsimm = {
1139 {
1140 .reg_base = 0x9c000000ULL,
1141 .vram_base = 0xfc000000ULL
1142 }, {
1143 .reg_base = 0x90000000ULL,
1144 .vram_base = 0xf0000000ULL
1145 }, {
1146 .reg_base = 0x94000000ULL
1147 }, {
1148 .reg_base = 0x98000000ULL
1149 }
1150 },
blueswir1ae409722007-12-10 20:00:11 +00001151 .ecc_base = 0xf00000000ULL,
1152 .ecc_version = 0x20000000, // version 0, implementation 2
blueswir1905fdcb2008-09-18 18:33:18 +00001153 .nvram_machine_id = 0x72,
1154 .machine_id = ss20_id,
blueswir1ae409722007-12-10 20:00:11 +00001155 .iommu_version = 0x13000000,
blueswir16ef05b92008-05-01 18:21:46 +00001156 .max_mem = 0xf00000000ULL,
blueswir1ae409722007-12-10 20:00:11 +00001157 .default_cpu_model = "TI SuperSparc II",
1158 },
blueswir1a526a312008-03-05 18:27:45 +00001159 /* Voyager */
1160 {
1161 .iommu_base = 0x10000000,
1162 .tcx_base = 0x50000000,
blueswir1a526a312008-03-05 18:27:45 +00001163 .slavio_base = 0x70000000,
1164 .ms_kb_base = 0x71000000,
1165 .serial_base = 0x71100000,
1166 .nvram_base = 0x71200000,
1167 .fd_base = 0x71400000,
1168 .counter_base = 0x71d00000,
1169 .intctl_base = 0x71e00000,
1170 .idreg_base = 0x78000000,
1171 .dma_base = 0x78400000,
1172 .esp_base = 0x78800000,
1173 .le_base = 0x78c00000,
1174 .apc_base = 0x71300000, // pmc
1175 .aux1_base = 0x71900000,
1176 .aux2_base = 0x71910000,
blueswir1905fdcb2008-09-18 18:33:18 +00001177 .nvram_machine_id = 0x80,
1178 .machine_id = vger_id,
blueswir1a526a312008-03-05 18:27:45 +00001179 .iommu_version = 0x05000000,
blueswir1a526a312008-03-05 18:27:45 +00001180 .max_mem = 0x10000000,
1181 .default_cpu_model = "Fujitsu MB86904",
1182 },
1183 /* LX */
1184 {
1185 .iommu_base = 0x10000000,
Artyom Tarasenko33863762010-05-08 16:10:14 +02001186 .iommu_pad_base = 0x10004000,
1187 .iommu_pad_len = 0x0fffb000,
blueswir1a526a312008-03-05 18:27:45 +00001188 .tcx_base = 0x50000000,
blueswir1a526a312008-03-05 18:27:45 +00001189 .slavio_base = 0x70000000,
1190 .ms_kb_base = 0x71000000,
1191 .serial_base = 0x71100000,
1192 .nvram_base = 0x71200000,
1193 .fd_base = 0x71400000,
1194 .counter_base = 0x71d00000,
1195 .intctl_base = 0x71e00000,
1196 .idreg_base = 0x78000000,
1197 .dma_base = 0x78400000,
1198 .esp_base = 0x78800000,
1199 .le_base = 0x78c00000,
blueswir1a526a312008-03-05 18:27:45 +00001200 .aux1_base = 0x71900000,
1201 .aux2_base = 0x71910000,
blueswir1905fdcb2008-09-18 18:33:18 +00001202 .nvram_machine_id = 0x80,
1203 .machine_id = lx_id,
blueswir1a526a312008-03-05 18:27:45 +00001204 .iommu_version = 0x04000000,
blueswir1a526a312008-03-05 18:27:45 +00001205 .max_mem = 0x10000000,
1206 .default_cpu_model = "TI MicroSparc I",
1207 },
1208 /* SS-4 */
1209 {
1210 .iommu_base = 0x10000000,
1211 .tcx_base = 0x50000000,
1212 .cs_base = 0x6c000000,
1213 .slavio_base = 0x70000000,
1214 .ms_kb_base = 0x71000000,
1215 .serial_base = 0x71100000,
1216 .nvram_base = 0x71200000,
1217 .fd_base = 0x71400000,
1218 .counter_base = 0x71d00000,
1219 .intctl_base = 0x71e00000,
1220 .idreg_base = 0x78000000,
1221 .dma_base = 0x78400000,
1222 .esp_base = 0x78800000,
1223 .le_base = 0x78c00000,
1224 .apc_base = 0x6a000000,
1225 .aux1_base = 0x71900000,
1226 .aux2_base = 0x71910000,
blueswir1905fdcb2008-09-18 18:33:18 +00001227 .nvram_machine_id = 0x80,
1228 .machine_id = ss4_id,
blueswir1a526a312008-03-05 18:27:45 +00001229 .iommu_version = 0x05000000,
blueswir1a526a312008-03-05 18:27:45 +00001230 .max_mem = 0x10000000,
1231 .default_cpu_model = "Fujitsu MB86904",
1232 },
1233 /* SPARCClassic */
1234 {
1235 .iommu_base = 0x10000000,
1236 .tcx_base = 0x50000000,
blueswir1a526a312008-03-05 18:27:45 +00001237 .slavio_base = 0x70000000,
1238 .ms_kb_base = 0x71000000,
1239 .serial_base = 0x71100000,
1240 .nvram_base = 0x71200000,
1241 .fd_base = 0x71400000,
1242 .counter_base = 0x71d00000,
1243 .intctl_base = 0x71e00000,
1244 .idreg_base = 0x78000000,
1245 .dma_base = 0x78400000,
1246 .esp_base = 0x78800000,
1247 .le_base = 0x78c00000,
1248 .apc_base = 0x6a000000,
1249 .aux1_base = 0x71900000,
1250 .aux2_base = 0x71910000,
blueswir1905fdcb2008-09-18 18:33:18 +00001251 .nvram_machine_id = 0x80,
1252 .machine_id = scls_id,
blueswir1a526a312008-03-05 18:27:45 +00001253 .iommu_version = 0x05000000,
blueswir1a526a312008-03-05 18:27:45 +00001254 .max_mem = 0x10000000,
1255 .default_cpu_model = "TI MicroSparc I",
1256 },
1257 /* SPARCbook */
1258 {
1259 .iommu_base = 0x10000000,
1260 .tcx_base = 0x50000000, // XXX
blueswir1a526a312008-03-05 18:27:45 +00001261 .slavio_base = 0x70000000,
1262 .ms_kb_base = 0x71000000,
1263 .serial_base = 0x71100000,
1264 .nvram_base = 0x71200000,
1265 .fd_base = 0x71400000,
1266 .counter_base = 0x71d00000,
1267 .intctl_base = 0x71e00000,
1268 .idreg_base = 0x78000000,
1269 .dma_base = 0x78400000,
1270 .esp_base = 0x78800000,
1271 .le_base = 0x78c00000,
1272 .apc_base = 0x6a000000,
1273 .aux1_base = 0x71900000,
1274 .aux2_base = 0x71910000,
blueswir1905fdcb2008-09-18 18:33:18 +00001275 .nvram_machine_id = 0x80,
1276 .machine_id = sbook_id,
blueswir1a526a312008-03-05 18:27:45 +00001277 .iommu_version = 0x05000000,
blueswir1a526a312008-03-05 18:27:45 +00001278 .max_mem = 0x10000000,
1279 .default_cpu_model = "TI MicroSparc I",
1280 },
blueswir136cd9212007-04-01 15:44:43 +00001281};
1282
blueswir136cd9212007-04-01 15:44:43 +00001283/* SPARCstation 5 hardware initialisation */
Anthony Liguoric227f092009-10-01 16:12:16 -05001284static void ss5_init(ram_addr_t RAM_size,
aliguori3023f332009-01-16 19:04:14 +00001285 const char *boot_device,
blueswir1b881c2c2007-11-18 08:46:58 +00001286 const char *kernel_filename, const char *kernel_cmdline,
1287 const char *initrd_filename, const char *cpu_model)
blueswir136cd9212007-04-01 15:44:43 +00001288{
aliguori3023f332009-01-16 19:04:14 +00001289 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
blueswir13ebf5aa2007-11-28 20:54:33 +00001290 kernel_cmdline, initrd_filename, cpu_model);
blueswir136cd9212007-04-01 15:44:43 +00001291}
1292
blueswir1e0353fe2007-04-01 15:55:28 +00001293/* SPARCstation 10 hardware initialisation */
Anthony Liguoric227f092009-10-01 16:12:16 -05001294static void ss10_init(ram_addr_t RAM_size,
aliguori3023f332009-01-16 19:04:14 +00001295 const char *boot_device,
blueswir1b881c2c2007-11-18 08:46:58 +00001296 const char *kernel_filename, const char *kernel_cmdline,
1297 const char *initrd_filename, const char *cpu_model)
blueswir1e0353fe2007-04-01 15:55:28 +00001298{
aliguori3023f332009-01-16 19:04:14 +00001299 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
blueswir13ebf5aa2007-11-28 20:54:33 +00001300 kernel_cmdline, initrd_filename, cpu_model);
blueswir1e0353fe2007-04-01 15:55:28 +00001301}
1302
blueswir16a3b9cc2007-11-11 17:56:38 +00001303/* SPARCserver 600MP hardware initialisation */
Anthony Liguoric227f092009-10-01 16:12:16 -05001304static void ss600mp_init(ram_addr_t RAM_size,
aliguori3023f332009-01-16 19:04:14 +00001305 const char *boot_device,
blueswir177f193d2008-05-12 16:13:33 +00001306 const char *kernel_filename,
1307 const char *kernel_cmdline,
blueswir16a3b9cc2007-11-11 17:56:38 +00001308 const char *initrd_filename, const char *cpu_model)
1309{
aliguori3023f332009-01-16 19:04:14 +00001310 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
blueswir13ebf5aa2007-11-28 20:54:33 +00001311 kernel_cmdline, initrd_filename, cpu_model);
blueswir16a3b9cc2007-11-11 17:56:38 +00001312}
1313
blueswir1ae409722007-12-10 20:00:11 +00001314/* SPARCstation 20 hardware initialisation */
Anthony Liguoric227f092009-10-01 16:12:16 -05001315static void ss20_init(ram_addr_t RAM_size,
aliguori3023f332009-01-16 19:04:14 +00001316 const char *boot_device,
blueswir1ae409722007-12-10 20:00:11 +00001317 const char *kernel_filename, const char *kernel_cmdline,
1318 const char *initrd_filename, const char *cpu_model)
1319{
aliguori3023f332009-01-16 19:04:14 +00001320 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
blueswir1ee76f822007-12-28 20:59:23 +00001321 kernel_cmdline, initrd_filename, cpu_model);
1322}
1323
blueswir1a526a312008-03-05 18:27:45 +00001324/* SPARCstation Voyager hardware initialisation */
Anthony Liguoric227f092009-10-01 16:12:16 -05001325static void vger_init(ram_addr_t RAM_size,
aliguori3023f332009-01-16 19:04:14 +00001326 const char *boot_device,
blueswir1a526a312008-03-05 18:27:45 +00001327 const char *kernel_filename, const char *kernel_cmdline,
1328 const char *initrd_filename, const char *cpu_model)
1329{
aliguori3023f332009-01-16 19:04:14 +00001330 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
blueswir1a526a312008-03-05 18:27:45 +00001331 kernel_cmdline, initrd_filename, cpu_model);
1332}
1333
1334/* SPARCstation LX hardware initialisation */
Anthony Liguoric227f092009-10-01 16:12:16 -05001335static void ss_lx_init(ram_addr_t RAM_size,
aliguori3023f332009-01-16 19:04:14 +00001336 const char *boot_device,
blueswir1a526a312008-03-05 18:27:45 +00001337 const char *kernel_filename, const char *kernel_cmdline,
1338 const char *initrd_filename, const char *cpu_model)
1339{
aliguori3023f332009-01-16 19:04:14 +00001340 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
blueswir1a526a312008-03-05 18:27:45 +00001341 kernel_cmdline, initrd_filename, cpu_model);
1342}
1343
1344/* SPARCstation 4 hardware initialisation */
Anthony Liguoric227f092009-10-01 16:12:16 -05001345static void ss4_init(ram_addr_t RAM_size,
aliguori3023f332009-01-16 19:04:14 +00001346 const char *boot_device,
blueswir1a526a312008-03-05 18:27:45 +00001347 const char *kernel_filename, const char *kernel_cmdline,
1348 const char *initrd_filename, const char *cpu_model)
1349{
aliguori3023f332009-01-16 19:04:14 +00001350 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
blueswir1a526a312008-03-05 18:27:45 +00001351 kernel_cmdline, initrd_filename, cpu_model);
1352}
1353
1354/* SPARCClassic hardware initialisation */
Anthony Liguoric227f092009-10-01 16:12:16 -05001355static void scls_init(ram_addr_t RAM_size,
aliguori3023f332009-01-16 19:04:14 +00001356 const char *boot_device,
blueswir1a526a312008-03-05 18:27:45 +00001357 const char *kernel_filename, const char *kernel_cmdline,
1358 const char *initrd_filename, const char *cpu_model)
1359{
aliguori3023f332009-01-16 19:04:14 +00001360 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
blueswir1a526a312008-03-05 18:27:45 +00001361 kernel_cmdline, initrd_filename, cpu_model);
1362}
1363
1364/* SPARCbook hardware initialisation */
Anthony Liguoric227f092009-10-01 16:12:16 -05001365static void sbook_init(ram_addr_t RAM_size,
aliguori3023f332009-01-16 19:04:14 +00001366 const char *boot_device,
blueswir1a526a312008-03-05 18:27:45 +00001367 const char *kernel_filename, const char *kernel_cmdline,
1368 const char *initrd_filename, const char *cpu_model)
1369{
aliguori3023f332009-01-16 19:04:14 +00001370 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
blueswir1a526a312008-03-05 18:27:45 +00001371 kernel_cmdline, initrd_filename, cpu_model);
1372}
1373
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001374static QEMUMachine ss5_machine = {
blueswir166de7332008-08-12 15:51:09 +00001375 .name = "SS-5",
1376 .desc = "Sun4m platform, SPARCstation 5",
1377 .init = ss5_init,
blueswir1c9b1ae22008-09-28 18:55:17 +00001378 .use_scsi = 1,
Anthony Liguori0c257432009-05-21 20:41:01 -05001379 .is_default = 1,
bellardc0e564d2005-06-05 15:17:28 +00001380};
blueswir1e0353fe2007-04-01 15:55:28 +00001381
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001382static QEMUMachine ss10_machine = {
blueswir166de7332008-08-12 15:51:09 +00001383 .name = "SS-10",
1384 .desc = "Sun4m platform, SPARCstation 10",
1385 .init = ss10_init,
blueswir1c9b1ae22008-09-28 18:55:17 +00001386 .use_scsi = 1,
blueswir11bcee012008-11-02 16:51:02 +00001387 .max_cpus = 4,
blueswir1e0353fe2007-04-01 15:55:28 +00001388};
blueswir16a3b9cc2007-11-11 17:56:38 +00001389
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001390static QEMUMachine ss600mp_machine = {
blueswir166de7332008-08-12 15:51:09 +00001391 .name = "SS-600MP",
1392 .desc = "Sun4m platform, SPARCserver 600MP",
1393 .init = ss600mp_init,
blueswir1c9b1ae22008-09-28 18:55:17 +00001394 .use_scsi = 1,
blueswir11bcee012008-11-02 16:51:02 +00001395 .max_cpus = 4,
blueswir16a3b9cc2007-11-11 17:56:38 +00001396};
blueswir1ae409722007-12-10 20:00:11 +00001397
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001398static QEMUMachine ss20_machine = {
blueswir166de7332008-08-12 15:51:09 +00001399 .name = "SS-20",
1400 .desc = "Sun4m platform, SPARCstation 20",
1401 .init = ss20_init,
blueswir1c9b1ae22008-09-28 18:55:17 +00001402 .use_scsi = 1,
blueswir11bcee012008-11-02 16:51:02 +00001403 .max_cpus = 4,
blueswir1ae409722007-12-10 20:00:11 +00001404};
1405
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001406static QEMUMachine voyager_machine = {
blueswir166de7332008-08-12 15:51:09 +00001407 .name = "Voyager",
1408 .desc = "Sun4m platform, SPARCstation Voyager",
1409 .init = vger_init,
blueswir1c9b1ae22008-09-28 18:55:17 +00001410 .use_scsi = 1,
blueswir1a526a312008-03-05 18:27:45 +00001411};
1412
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001413static QEMUMachine ss_lx_machine = {
blueswir166de7332008-08-12 15:51:09 +00001414 .name = "LX",
1415 .desc = "Sun4m platform, SPARCstation LX",
1416 .init = ss_lx_init,
blueswir1c9b1ae22008-09-28 18:55:17 +00001417 .use_scsi = 1,
blueswir1a526a312008-03-05 18:27:45 +00001418};
1419
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001420static QEMUMachine ss4_machine = {
blueswir166de7332008-08-12 15:51:09 +00001421 .name = "SS-4",
1422 .desc = "Sun4m platform, SPARCstation 4",
1423 .init = ss4_init,
blueswir1c9b1ae22008-09-28 18:55:17 +00001424 .use_scsi = 1,
blueswir1a526a312008-03-05 18:27:45 +00001425};
1426
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001427static QEMUMachine scls_machine = {
blueswir166de7332008-08-12 15:51:09 +00001428 .name = "SPARCClassic",
1429 .desc = "Sun4m platform, SPARCClassic",
1430 .init = scls_init,
blueswir1c9b1ae22008-09-28 18:55:17 +00001431 .use_scsi = 1,
blueswir1a526a312008-03-05 18:27:45 +00001432};
1433
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001434static QEMUMachine sbook_machine = {
blueswir166de7332008-08-12 15:51:09 +00001435 .name = "SPARCbook",
1436 .desc = "Sun4m platform, SPARCbook",
1437 .init = sbook_init,
blueswir1c9b1ae22008-09-28 18:55:17 +00001438 .use_scsi = 1,
blueswir1a526a312008-03-05 18:27:45 +00001439};
1440
blueswir17d858922007-12-28 20:57:43 +00001441static const struct sun4d_hwdef sun4d_hwdefs[] = {
1442 /* SS-1000 */
1443 {
1444 .iounit_bases = {
1445 0xfe0200000ULL,
1446 0xfe1200000ULL,
1447 0xfe2200000ULL,
1448 0xfe3200000ULL,
1449 -1,
1450 },
1451 .tcx_base = 0x820000000ULL,
1452 .slavio_base = 0xf00000000ULL,
1453 .ms_kb_base = 0xf00240000ULL,
1454 .serial_base = 0xf00200000ULL,
1455 .nvram_base = 0xf00280000ULL,
1456 .counter_base = 0xf00300000ULL,
1457 .espdma_base = 0x800081000ULL,
1458 .esp_base = 0x800080000ULL,
1459 .ledma_base = 0x800040000ULL,
1460 .le_base = 0x800060000ULL,
1461 .sbi_base = 0xf02800000ULL,
blueswir1905fdcb2008-09-18 18:33:18 +00001462 .nvram_machine_id = 0x80,
1463 .machine_id = ss1000_id,
blueswir17d858922007-12-28 20:57:43 +00001464 .iounit_version = 0x03000000,
blueswir16ef05b92008-05-01 18:21:46 +00001465 .max_mem = 0xf00000000ULL,
blueswir17d858922007-12-28 20:57:43 +00001466 .default_cpu_model = "TI SuperSparc II",
1467 },
1468 /* SS-2000 */
1469 {
1470 .iounit_bases = {
1471 0xfe0200000ULL,
1472 0xfe1200000ULL,
1473 0xfe2200000ULL,
1474 0xfe3200000ULL,
1475 0xfe4200000ULL,
1476 },
1477 .tcx_base = 0x820000000ULL,
1478 .slavio_base = 0xf00000000ULL,
1479 .ms_kb_base = 0xf00240000ULL,
1480 .serial_base = 0xf00200000ULL,
1481 .nvram_base = 0xf00280000ULL,
1482 .counter_base = 0xf00300000ULL,
1483 .espdma_base = 0x800081000ULL,
1484 .esp_base = 0x800080000ULL,
1485 .ledma_base = 0x800040000ULL,
1486 .le_base = 0x800060000ULL,
1487 .sbi_base = 0xf02800000ULL,
blueswir1905fdcb2008-09-18 18:33:18 +00001488 .nvram_machine_id = 0x80,
1489 .machine_id = ss2000_id,
blueswir17d858922007-12-28 20:57:43 +00001490 .iounit_version = 0x03000000,
blueswir16ef05b92008-05-01 18:21:46 +00001491 .max_mem = 0xf00000000ULL,
blueswir17d858922007-12-28 20:57:43 +00001492 .default_cpu_model = "TI SuperSparc II",
1493 },
1494};
1495
Anthony Liguoric227f092009-10-01 16:12:16 -05001496static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
Blue Swirl4b48bf02009-08-08 20:24:47 +00001497{
1498 DeviceState *dev;
1499 SysBusDevice *s;
1500 unsigned int i;
1501
1502 dev = qdev_create(NULL, "sbi");
Markus Armbrustere23a1b32009-10-07 01:15:58 +02001503 qdev_init_nofail(dev);
Blue Swirl4b48bf02009-08-08 20:24:47 +00001504
1505 s = sysbus_from_qdev(dev);
1506
1507 for (i = 0; i < MAX_CPUS; i++) {
1508 sysbus_connect_irq(s, i, *parent_irq[i]);
1509 }
1510
1511 sysbus_mmio_map(s, 0, addr);
1512
1513 return dev;
1514}
1515
Anthony Liguoric227f092009-10-01 16:12:16 -05001516static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
blueswir17d858922007-12-28 20:57:43 +00001517 const char *boot_device,
aliguori3023f332009-01-16 19:04:14 +00001518 const char *kernel_filename,
blueswir17d858922007-12-28 20:57:43 +00001519 const char *kernel_cmdline,
1520 const char *initrd_filename, const char *cpu_model)
1521{
blueswir17d858922007-12-28 20:57:43 +00001522 unsigned int i;
Blue Swirl7fc06732009-07-21 19:25:59 +00001523 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1524 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
Blue Swirl6f6260c2009-07-15 20:45:19 +00001525 espdma_irq, ledma_irq;
Blue Swirl73d74342010-09-11 16:38:33 +00001526 qemu_irq esp_reset, dma_enable;
blueswir15c6602c2008-11-05 19:25:39 +00001527 unsigned long kernel_size;
blueswir13cce6242008-09-18 18:27:29 +00001528 void *fw_cfg;
Blue Swirl7fc06732009-07-21 19:25:59 +00001529 DeviceState *dev;
blueswir17d858922007-12-28 20:57:43 +00001530
1531 /* init CPUs */
1532 if (!cpu_model)
1533 cpu_model = hwdef->default_cpu_model;
1534
Blue Swirl666713c2009-07-16 13:48:20 +00001535 for(i = 0; i < smp_cpus; i++) {
Blue Swirl89835362010-01-13 18:52:50 +00001536 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
blueswir17d858922007-12-28 20:57:43 +00001537 }
1538
1539 for (i = smp_cpus; i < MAX_CPUS; i++)
1540 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1541
blueswir17d858922007-12-28 20:57:43 +00001542 /* set up devices */
Blue Swirla350db82009-07-16 13:48:14 +00001543 ram_init(0, RAM_size, hwdef->max_mem);
1544
Blue Swirlf48f6562009-07-16 13:48:10 +00001545 prom_init(hwdef->slavio_base, bios_name);
1546
Blue Swirl7fc06732009-07-21 19:25:59 +00001547 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1548
1549 for (i = 0; i < 32; i++) {
1550 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1551 }
1552 for (i = 0; i < MAX_CPUS; i++) {
1553 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1554 }
blueswir17d858922007-12-28 20:57:43 +00001555
1556 for (i = 0; i < MAX_IOUNITS; i++)
Anthony Liguoric227f092009-10-01 16:12:16 -05001557 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
blueswir1ff403da2008-01-01 17:04:45 +00001558 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1559 hwdef->iounit_version,
Blue Swirlc533e0b2009-08-08 20:55:37 +00001560 sbi_irq[0]);
blueswir17d858922007-12-28 20:57:43 +00001561
Blue Swirlc533e0b2009-08-08 20:55:37 +00001562 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
Bob Breuer86d1c382010-12-18 11:09:04 -06001563 iounits[0], &espdma_irq, 0);
blueswir17d858922007-12-28 20:57:43 +00001564
Bob Breuer86d1c382010-12-18 11:09:04 -06001565 /* should be lebuffer instead */
Blue Swirlc533e0b2009-08-08 20:55:37 +00001566 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
Bob Breuer86d1c382010-12-18 11:09:04 -06001567 iounits[0], &ledma_irq, 0);
blueswir17d858922007-12-28 20:57:43 +00001568
1569 if (graphic_depth != 8 && graphic_depth != 24) {
1570 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1571 exit (1);
1572 }
Blue Swirld95d8f12009-08-08 21:04:18 +00001573 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
pbrookdc828ca2009-04-09 22:21:07 +00001574 graphic_depth);
blueswir17d858922007-12-28 20:57:43 +00001575
Blue Swirl74ff8d92009-08-08 21:43:12 +00001576 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
blueswir17d858922007-12-28 20:57:43 +00001577
Blue Swirld95d8f12009-08-08 21:04:18 +00001578 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
blueswir17d858922007-12-28 20:57:43 +00001579
Blue Swirlc533e0b2009-08-08 20:55:37 +00001580 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
blueswir17d858922007-12-28 20:57:43 +00001581
Blue Swirlc533e0b2009-08-08 20:55:37 +00001582 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
Anthony Liguori993fbfd2009-05-21 16:54:00 -05001583 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
Stefan Weil5cbdb3a2012-04-07 09:23:39 +02001584 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1585 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
Blue Swirlc533e0b2009-08-08 20:55:37 +00001586 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
aurel32aeeb69c2009-01-14 14:47:56 +00001587 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
blueswir17d858922007-12-28 20:57:43 +00001588
1589 if (drive_get_max_bus(IF_SCSI) > 0) {
1590 fprintf(stderr, "qemu: too many SCSI bus\n");
1591 exit(1);
1592 }
1593
Paul Brookcfb9de92009-05-14 22:35:07 +01001594 esp_init(hwdef->esp_base, 2,
1595 espdma_memory_read, espdma_memory_write,
Blue Swirl73d74342010-09-11 16:38:33 +00001596 espdma, espdma_irq, &esp_reset, &dma_enable);
1597
1598 qdev_connect_gpio_out(espdma, 0, esp_reset);
1599 qdev_connect_gpio_out(espdma, 1, dma_enable);
blueswir17d858922007-12-28 20:57:43 +00001600
blueswir1293f78b2008-05-12 17:22:13 +00001601 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1602 RAM_size);
blueswir17d858922007-12-28 20:57:43 +00001603
1604 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1605 boot_device, RAM_size, kernel_size, graphic_width,
blueswir1905fdcb2008-09-18 18:33:18 +00001606 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1607 "Sun4d");
blueswir13cce6242008-09-18 18:27:29 +00001608
1609 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1610 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
blueswir1905fdcb2008-09-18 18:33:18 +00001611 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1612 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
blueswir1513f7892009-03-08 09:51:29 +00001613 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1614 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1615 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1616 if (kernel_cmdline) {
1617 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
Gerd Hoffmann3c178e72009-10-07 13:37:06 +02001618 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
Blue Swirl6bb4ca52009-12-27 18:25:49 +00001619 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1620 (uint8_t*)strdup(kernel_cmdline),
1621 strlen(kernel_cmdline) + 1);
blueswir1513f7892009-03-08 09:51:29 +00001622 } else {
1623 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1624 }
1625 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1626 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1627 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1628 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
blueswir17d858922007-12-28 20:57:43 +00001629}
1630
1631/* SPARCserver 1000 hardware initialisation */
Anthony Liguoric227f092009-10-01 16:12:16 -05001632static void ss1000_init(ram_addr_t RAM_size,
aliguori3023f332009-01-16 19:04:14 +00001633 const char *boot_device,
blueswir17d858922007-12-28 20:57:43 +00001634 const char *kernel_filename, const char *kernel_cmdline,
1635 const char *initrd_filename, const char *cpu_model)
1636{
aliguori3023f332009-01-16 19:04:14 +00001637 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
blueswir17d858922007-12-28 20:57:43 +00001638 kernel_cmdline, initrd_filename, cpu_model);
1639}
1640
1641/* SPARCcenter 2000 hardware initialisation */
Anthony Liguoric227f092009-10-01 16:12:16 -05001642static void ss2000_init(ram_addr_t RAM_size,
aliguori3023f332009-01-16 19:04:14 +00001643 const char *boot_device,
blueswir17d858922007-12-28 20:57:43 +00001644 const char *kernel_filename, const char *kernel_cmdline,
1645 const char *initrd_filename, const char *cpu_model)
1646{
aliguori3023f332009-01-16 19:04:14 +00001647 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
blueswir17d858922007-12-28 20:57:43 +00001648 kernel_cmdline, initrd_filename, cpu_model);
1649}
1650
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001651static QEMUMachine ss1000_machine = {
blueswir166de7332008-08-12 15:51:09 +00001652 .name = "SS-1000",
1653 .desc = "Sun4d platform, SPARCserver 1000",
1654 .init = ss1000_init,
blueswir1c9b1ae22008-09-28 18:55:17 +00001655 .use_scsi = 1,
blueswir11bcee012008-11-02 16:51:02 +00001656 .max_cpus = 8,
blueswir17d858922007-12-28 20:57:43 +00001657};
1658
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001659static QEMUMachine ss2000_machine = {
blueswir166de7332008-08-12 15:51:09 +00001660 .name = "SS-2000",
1661 .desc = "Sun4d platform, SPARCcenter 2000",
1662 .init = ss2000_init,
blueswir1c9b1ae22008-09-28 18:55:17 +00001663 .use_scsi = 1,
blueswir11bcee012008-11-02 16:51:02 +00001664 .max_cpus = 20,
blueswir17d858922007-12-28 20:57:43 +00001665};
blueswir18137cde2008-10-27 15:56:56 +00001666
1667static const struct sun4c_hwdef sun4c_hwdefs[] = {
1668 /* SS-2 */
1669 {
1670 .iommu_base = 0xf8000000,
1671 .tcx_base = 0xfe000000,
blueswir18137cde2008-10-27 15:56:56 +00001672 .slavio_base = 0xf6000000,
1673 .intctl_base = 0xf5000000,
1674 .counter_base = 0xf3000000,
1675 .ms_kb_base = 0xf0000000,
1676 .serial_base = 0xf1000000,
1677 .nvram_base = 0xf2000000,
1678 .fd_base = 0xf7200000,
1679 .dma_base = 0xf8400000,
1680 .esp_base = 0xf8800000,
1681 .le_base = 0xf8c00000,
blueswir18137cde2008-10-27 15:56:56 +00001682 .aux1_base = 0xf7400003,
blueswir18137cde2008-10-27 15:56:56 +00001683 .nvram_machine_id = 0x55,
1684 .machine_id = ss2_id,
1685 .max_mem = 0x10000000,
1686 .default_cpu_model = "Cypress CY7C601",
1687 },
1688};
1689
Anthony Liguoric227f092009-10-01 16:12:16 -05001690static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
Blue Swirl4b48bf02009-08-08 20:24:47 +00001691 qemu_irq *parent_irq)
1692{
1693 DeviceState *dev;
1694 SysBusDevice *s;
1695 unsigned int i;
1696
1697 dev = qdev_create(NULL, "sun4c_intctl");
Markus Armbrustere23a1b32009-10-07 01:15:58 +02001698 qdev_init_nofail(dev);
Blue Swirl4b48bf02009-08-08 20:24:47 +00001699
1700 s = sysbus_from_qdev(dev);
1701
1702 for (i = 0; i < MAX_PILS; i++) {
1703 sysbus_connect_irq(s, i, parent_irq[i]);
1704 }
1705 sysbus_mmio_map(s, 0, addr);
1706
1707 return dev;
1708}
1709
Anthony Liguoric227f092009-10-01 16:12:16 -05001710static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
blueswir18137cde2008-10-27 15:56:56 +00001711 const char *boot_device,
aliguori3023f332009-01-16 19:04:14 +00001712 const char *kernel_filename,
blueswir18137cde2008-10-27 15:56:56 +00001713 const char *kernel_cmdline,
1714 const char *initrd_filename, const char *cpu_model)
1715{
Paul Brookcfb9de92009-05-14 22:35:07 +01001716 void *iommu, *espdma, *ledma, *nvram;
Blue Swirle32cba22009-07-21 19:57:32 +00001717 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
Blue Swirl73d74342010-09-11 16:38:33 +00001718 qemu_irq esp_reset, dma_enable;
Blue Swirl2582cfa2009-07-13 16:51:27 +00001719 qemu_irq fdc_tc;
blueswir15c6602c2008-11-05 19:25:39 +00001720 unsigned long kernel_size;
Gerd Hoffmannfd8014e2009-09-22 13:53:18 +02001721 DriveInfo *fd[MAX_FD];
blueswir18137cde2008-10-27 15:56:56 +00001722 void *fw_cfg;
Blue Swirle32cba22009-07-21 19:57:32 +00001723 DeviceState *dev;
1724 unsigned int i;
blueswir18137cde2008-10-27 15:56:56 +00001725
1726 /* init CPU */
1727 if (!cpu_model)
1728 cpu_model = hwdef->default_cpu_model;
1729
Blue Swirl89835362010-01-13 18:52:50 +00001730 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
blueswir18137cde2008-10-27 15:56:56 +00001731
blueswir18137cde2008-10-27 15:56:56 +00001732 /* set up devices */
Blue Swirla350db82009-07-16 13:48:14 +00001733 ram_init(0, RAM_size, hwdef->max_mem);
1734
Blue Swirlf48f6562009-07-16 13:48:10 +00001735 prom_init(hwdef->slavio_base, bios_name);
1736
Blue Swirle32cba22009-07-21 19:57:32 +00001737 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1738
1739 for (i = 0; i < 8; i++) {
1740 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1741 }
blueswir18137cde2008-10-27 15:56:56 +00001742
1743 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
Blue Swirlc533e0b2009-08-08 20:55:37 +00001744 slavio_irq[1]);
blueswir18137cde2008-10-27 15:56:56 +00001745
Blue Swirlc533e0b2009-08-08 20:55:37 +00001746 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
Bob Breuer86d1c382010-12-18 11:09:04 -06001747 iommu, &espdma_irq, 0);
blueswir18137cde2008-10-27 15:56:56 +00001748
1749 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
Bob Breuer86d1c382010-12-18 11:09:04 -06001750 slavio_irq[3], iommu, &ledma_irq, 1);
blueswir18137cde2008-10-27 15:56:56 +00001751
1752 if (graphic_depth != 8 && graphic_depth != 24) {
1753 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1754 exit (1);
1755 }
Blue Swirld95d8f12009-08-08 21:04:18 +00001756 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
pbrookdc828ca2009-04-09 22:21:07 +00001757 graphic_depth);
blueswir18137cde2008-10-27 15:56:56 +00001758
Blue Swirl74ff8d92009-08-08 21:43:12 +00001759 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
blueswir18137cde2008-10-27 15:56:56 +00001760
Blue Swirld95d8f12009-08-08 21:04:18 +00001761 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
blueswir18137cde2008-10-27 15:56:56 +00001762
Blue Swirlc533e0b2009-08-08 20:55:37 +00001763 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
Anthony Liguori993fbfd2009-05-21 16:54:00 -05001764 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
Stefan Weil5cbdb3a2012-04-07 09:23:39 +02001765 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1766 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
Blue Swirlc533e0b2009-08-08 20:55:37 +00001767 escc_init(hwdef->serial_base, slavio_irq[1],
1768 slavio_irq[1], serial_hds[0], serial_hds[1],
aurel32aeeb69c2009-01-14 14:47:56 +00001769 ESCC_CLOCK, 1);
blueswir18137cde2008-10-27 15:56:56 +00001770
Blue Swirlb2b6f6e2009-08-09 07:27:29 +00001771 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
blueswir18137cde2008-10-27 15:56:56 +00001772
Anthony Liguoric227f092009-10-01 16:12:16 -05001773 if (hwdef->fd_base != (target_phys_addr_t)-1) {
blueswir18137cde2008-10-27 15:56:56 +00001774 /* there is zero or one floppy drive */
blueswir1ce802582008-11-29 16:42:40 +00001775 memset(fd, 0, sizeof(fd));
Gerd Hoffmannfd8014e2009-09-22 13:53:18 +02001776 fd[0] = drive_get(IF_FLOPPY, 0, 0);
Blue Swirlc533e0b2009-08-08 20:55:37 +00001777 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
Blue Swirl2582cfa2009-07-13 16:51:27 +00001778 &fdc_tc);
blueswir18137cde2008-10-27 15:56:56 +00001779 }
1780
1781 if (drive_get_max_bus(IF_SCSI) > 0) {
1782 fprintf(stderr, "qemu: too many SCSI bus\n");
1783 exit(1);
1784 }
1785
Paul Brookcfb9de92009-05-14 22:35:07 +01001786 esp_init(hwdef->esp_base, 2,
1787 espdma_memory_read, espdma_memory_write,
Blue Swirl73d74342010-09-11 16:38:33 +00001788 espdma, espdma_irq, &esp_reset, &dma_enable);
1789
1790 qdev_connect_gpio_out(espdma, 0, esp_reset);
1791 qdev_connect_gpio_out(espdma, 1, dma_enable);
blueswir18137cde2008-10-27 15:56:56 +00001792
1793 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1794 RAM_size);
1795
1796 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1797 boot_device, RAM_size, kernel_size, graphic_width,
1798 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1799 "Sun4c");
1800
1801 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1802 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1803 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1804 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
blueswir1513f7892009-03-08 09:51:29 +00001805 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1806 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1807 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1808 if (kernel_cmdline) {
1809 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
Gerd Hoffmann3c178e72009-10-07 13:37:06 +02001810 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
Blue Swirl6bb4ca52009-12-27 18:25:49 +00001811 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1812 (uint8_t*)strdup(kernel_cmdline),
1813 strlen(kernel_cmdline) + 1);
blueswir1513f7892009-03-08 09:51:29 +00001814 } else {
1815 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1816 }
1817 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1818 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1819 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1820 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
blueswir18137cde2008-10-27 15:56:56 +00001821}
1822
1823/* SPARCstation 2 hardware initialisation */
Anthony Liguoric227f092009-10-01 16:12:16 -05001824static void ss2_init(ram_addr_t RAM_size,
aliguori3023f332009-01-16 19:04:14 +00001825 const char *boot_device,
blueswir18137cde2008-10-27 15:56:56 +00001826 const char *kernel_filename, const char *kernel_cmdline,
1827 const char *initrd_filename, const char *cpu_model)
1828{
aliguori3023f332009-01-16 19:04:14 +00001829 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
blueswir18137cde2008-10-27 15:56:56 +00001830 kernel_cmdline, initrd_filename, cpu_model);
1831}
1832
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001833static QEMUMachine ss2_machine = {
blueswir18137cde2008-10-27 15:56:56 +00001834 .name = "SS-2",
1835 .desc = "Sun4c platform, SPARCstation 2",
1836 .init = ss2_init,
blueswir18137cde2008-10-27 15:56:56 +00001837 .use_scsi = 1,
blueswir18137cde2008-10-27 15:56:56 +00001838};
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001839
Andreas Färber83f7d432012-02-09 15:20:55 +01001840static void sun4m_register_types(void)
1841{
1842 type_register_static(&idreg_info);
1843 type_register_static(&afx_info);
1844 type_register_static(&prom_info);
1845 type_register_static(&ram_info);
1846}
1847
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001848static void ss2_machine_init(void)
1849{
1850 qemu_register_machine(&ss5_machine);
1851 qemu_register_machine(&ss10_machine);
1852 qemu_register_machine(&ss600mp_machine);
1853 qemu_register_machine(&ss20_machine);
1854 qemu_register_machine(&voyager_machine);
1855 qemu_register_machine(&ss_lx_machine);
1856 qemu_register_machine(&ss4_machine);
1857 qemu_register_machine(&scls_machine);
1858 qemu_register_machine(&sbook_machine);
1859 qemu_register_machine(&ss1000_machine);
1860 qemu_register_machine(&ss2000_machine);
1861 qemu_register_machine(&ss2_machine);
1862}
1863
Andreas Färber83f7d432012-02-09 15:20:55 +01001864type_init(sun4m_register_types)
Anthony Liguorif80f9ec2009-05-20 18:38:09 -05001865machine_init(ss2_machine_init);