qemu /
qemu /
462eda24e5f9cf41a7078a8503ff01865f83d372 Sparc32: improve interrupt handling
Level 15 interrupts are broadcast to all CPUs, each CPU can clear the
interrupt using the local Clear Pending register.
Update intbit_to_level table.
Don't try to raise level 0 interrupts.
Calculate pending interrupts based on the separate inputs from master
register. Setting or resetting the pending level isn't correct because of
overlap of levels.
Level 14 is always used for CPU timer interrupts, remove the property.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2 files changed
