bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1 | #if !defined (__MIPS_CPU_H__) |
| 2 | #define __MIPS_CPU_H__ |
| 3 | |
Blue Swirl | 3e45717 | 2011-07-13 12:44:15 +0000 | [diff] [blame] | 4 | //#define DEBUG_OP |
| 5 | |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 6 | #define TARGET_HAS_ICE 1 |
| 7 | |
ths | 9042c0e | 2006-12-23 14:18:40 +0000 | [diff] [blame] | 8 | #define ELF_MACHINE EM_MIPS |
| 9 | |
Andreas Färber | 9349b4f | 2012-03-14 01:38:32 +0100 | [diff] [blame] | 10 | #define CPUArchState struct CPUMIPSState |
pbrook | c276471 | 2009-03-07 15:24:59 +0000 | [diff] [blame] | 11 | |
bellard | c5d6edc | 2006-06-14 16:49:24 +0000 | [diff] [blame] | 12 | #include "config.h" |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 13 | #include "qemu-common.h" |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 14 | #include "mips-defs.h" |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 15 | #include "exec/cpu-defs.h" |
Paolo Bonzini | 6b4c305 | 2012-10-24 13:12:00 +0200 | [diff] [blame] | 16 | #include "fpu/softfloat.h" |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 17 | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 18 | struct CPUMIPSState; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 19 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 20 | typedef struct r4k_tlb_t r4k_tlb_t; |
| 21 | struct r4k_tlb_t { |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 22 | target_ulong VPN; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 23 | uint32_t PageMask; |
pbrook | 98c1b82 | 2006-03-11 16:20:36 +0000 | [diff] [blame] | 24 | uint_fast8_t ASID; |
| 25 | uint_fast16_t G:1; |
| 26 | uint_fast16_t C0:3; |
| 27 | uint_fast16_t C1:3; |
| 28 | uint_fast16_t V0:1; |
| 29 | uint_fast16_t V1:1; |
| 30 | uint_fast16_t D0:1; |
| 31 | uint_fast16_t D1:1; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 32 | target_ulong PFN[2]; |
| 33 | }; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 34 | |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 35 | #if !defined(CONFIG_USER_ONLY) |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 36 | typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; |
| 37 | struct CPUMIPSTLBContext { |
| 38 | uint32_t nb_tlb; |
| 39 | uint32_t tlb_in_use; |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 40 | int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 41 | void (*helper_tlbwi)(struct CPUMIPSState *env); |
| 42 | void (*helper_tlbwr)(struct CPUMIPSState *env); |
| 43 | void (*helper_tlbp)(struct CPUMIPSState *env); |
| 44 | void (*helper_tlbr)(struct CPUMIPSState *env); |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 45 | union { |
| 46 | struct { |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 47 | r4k_tlb_t tlb[MIPS_TLB_MAX]; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 48 | } r4k; |
| 49 | } mmu; |
| 50 | }; |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 51 | #endif |
ths | 51b2772 | 2007-05-30 20:46:02 +0000 | [diff] [blame] | 52 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 53 | typedef union fpr_t fpr_t; |
| 54 | union fpr_t { |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 55 | float64 fd; /* ieee double precision */ |
| 56 | float32 fs[2];/* ieee single precision */ |
| 57 | uint64_t d; /* binary double fixed-point */ |
| 58 | uint32_t w[2]; /* binary single fixed-point */ |
| 59 | }; |
| 60 | /* define FP_ENDIAN_IDX to access the same location |
Stefan Weil | 4ff9786 | 2011-03-13 15:44:02 +0100 | [diff] [blame] | 61 | * in the fpr_t union regardless of the host endianness |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 62 | */ |
Juan Quintela | e2542fe | 2009-07-27 16:13:06 +0200 | [diff] [blame] | 63 | #if defined(HOST_WORDS_BIGENDIAN) |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 64 | # define FP_ENDIAN_IDX 1 |
| 65 | #else |
| 66 | # define FP_ENDIAN_IDX 0 |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 67 | #endif |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 68 | |
| 69 | typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; |
| 70 | struct CPUMIPSFPUContext { |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 71 | /* Floating point registers */ |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 72 | fpr_t fpr[32]; |
bellard | 6ea83fe | 2006-06-14 12:56:19 +0000 | [diff] [blame] | 73 | float_status fp_status; |
ths | 5a5012e | 2007-05-07 13:55:33 +0000 | [diff] [blame] | 74 | /* fpu implementation/revision register (fir) */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 75 | uint32_t fcr0; |
ths | 5a5012e | 2007-05-07 13:55:33 +0000 | [diff] [blame] | 76 | #define FCR0_F64 22 |
| 77 | #define FCR0_L 21 |
| 78 | #define FCR0_W 20 |
| 79 | #define FCR0_3D 19 |
| 80 | #define FCR0_PS 18 |
| 81 | #define FCR0_D 17 |
| 82 | #define FCR0_S 16 |
| 83 | #define FCR0_PRID 8 |
| 84 | #define FCR0_REV 0 |
bellard | 6ea83fe | 2006-06-14 12:56:19 +0000 | [diff] [blame] | 85 | /* fcsr */ |
| 86 | uint32_t fcr31; |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 87 | #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
| 88 | #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
| 89 | #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) |
ths | 5a5012e | 2007-05-07 13:55:33 +0000 | [diff] [blame] | 90 | #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
| 91 | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) |
| 92 | #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) |
| 93 | #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) |
| 94 | #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) |
| 95 | #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) |
| 96 | #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) |
bellard | 6ea83fe | 2006-06-14 12:56:19 +0000 | [diff] [blame] | 97 | #define FP_INEXACT 1 |
| 98 | #define FP_UNDERFLOW 2 |
| 99 | #define FP_OVERFLOW 4 |
| 100 | #define FP_DIV0 8 |
| 101 | #define FP_INVALID 16 |
| 102 | #define FP_UNIMPLEMENTED 32 |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 103 | }; |
ths | 36d2395 | 2007-02-28 22:37:42 +0000 | [diff] [blame] | 104 | |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 105 | #define NB_MMU_MODES 3 |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 106 | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 107 | typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; |
| 108 | struct CPUMIPSMVPContext { |
| 109 | int32_t CP0_MVPControl; |
| 110 | #define CP0MVPCo_CPA 3 |
| 111 | #define CP0MVPCo_STLB 2 |
| 112 | #define CP0MVPCo_VPC 1 |
| 113 | #define CP0MVPCo_EVP 0 |
| 114 | int32_t CP0_MVPConf0; |
| 115 | #define CP0MVPC0_M 31 |
| 116 | #define CP0MVPC0_TLBS 29 |
| 117 | #define CP0MVPC0_GS 28 |
| 118 | #define CP0MVPC0_PCP 27 |
| 119 | #define CP0MVPC0_PTLBE 16 |
| 120 | #define CP0MVPC0_TCA 15 |
| 121 | #define CP0MVPC0_PVPE 10 |
| 122 | #define CP0MVPC0_PTC 0 |
| 123 | int32_t CP0_MVPConf1; |
| 124 | #define CP0MVPC1_CIM 31 |
| 125 | #define CP0MVPC1_CIF 30 |
| 126 | #define CP0MVPC1_PCX 20 |
| 127 | #define CP0MVPC1_PCP2 10 |
| 128 | #define CP0MVPC1_PCP1 0 |
| 129 | }; |
| 130 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 131 | typedef struct mips_def_t mips_def_t; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 132 | |
| 133 | #define MIPS_SHADOW_SET_MAX 16 |
| 134 | #define MIPS_TC_MAX 5 |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 135 | #define MIPS_FPU_MAX 1 |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 136 | #define MIPS_DSP_ACC 4 |
| 137 | |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 138 | typedef struct TCState TCState; |
| 139 | struct TCState { |
| 140 | target_ulong gpr[32]; |
| 141 | target_ulong PC; |
| 142 | target_ulong HI[MIPS_DSP_ACC]; |
| 143 | target_ulong LO[MIPS_DSP_ACC]; |
| 144 | target_ulong ACX[MIPS_DSP_ACC]; |
| 145 | target_ulong DSPControl; |
| 146 | int32_t CP0_TCStatus; |
| 147 | #define CP0TCSt_TCU3 31 |
| 148 | #define CP0TCSt_TCU2 30 |
| 149 | #define CP0TCSt_TCU1 29 |
| 150 | #define CP0TCSt_TCU0 28 |
| 151 | #define CP0TCSt_TMX 27 |
| 152 | #define CP0TCSt_RNST 23 |
| 153 | #define CP0TCSt_TDS 21 |
| 154 | #define CP0TCSt_DT 20 |
| 155 | #define CP0TCSt_DA 15 |
| 156 | #define CP0TCSt_A 13 |
| 157 | #define CP0TCSt_TKSU 11 |
| 158 | #define CP0TCSt_IXMT 10 |
| 159 | #define CP0TCSt_TASID 0 |
| 160 | int32_t CP0_TCBind; |
| 161 | #define CP0TCBd_CurTC 21 |
| 162 | #define CP0TCBd_TBE 17 |
| 163 | #define CP0TCBd_CurVPE 0 |
| 164 | target_ulong CP0_TCHalt; |
| 165 | target_ulong CP0_TCContext; |
| 166 | target_ulong CP0_TCSchedule; |
| 167 | target_ulong CP0_TCScheFBack; |
| 168 | int32_t CP0_Debug_tcstatus; |
| 169 | }; |
| 170 | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 171 | typedef struct CPUMIPSState CPUMIPSState; |
| 172 | struct CPUMIPSState { |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 173 | TCState active_tc; |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 174 | CPUMIPSFPUContext active_fpu; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 175 | |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 176 | uint32_t current_tc; |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 177 | uint32_t current_fpu; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 178 | |
ths | e034e2c | 2007-06-23 18:04:12 +0000 | [diff] [blame] | 179 | uint32_t SEGBITS; |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 180 | uint32_t PABITS; |
ths | b6d96be | 2008-07-09 11:05:10 +0000 | [diff] [blame] | 181 | target_ulong SEGMask; |
ths | 6d35524 | 2007-12-25 03:13:56 +0000 | [diff] [blame] | 182 | target_ulong PAMask; |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 183 | |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 184 | int32_t CP0_Index; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 185 | /* CP0_MVP* are per MVP registers. */ |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 186 | int32_t CP0_Random; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 187 | int32_t CP0_VPEControl; |
| 188 | #define CP0VPECo_YSI 21 |
| 189 | #define CP0VPECo_GSI 20 |
| 190 | #define CP0VPECo_EXCPT 16 |
| 191 | #define CP0VPECo_TE 15 |
| 192 | #define CP0VPECo_TargTC 0 |
| 193 | int32_t CP0_VPEConf0; |
| 194 | #define CP0VPEC0_M 31 |
| 195 | #define CP0VPEC0_XTC 21 |
| 196 | #define CP0VPEC0_TCS 19 |
| 197 | #define CP0VPEC0_SCS 18 |
| 198 | #define CP0VPEC0_DSC 17 |
| 199 | #define CP0VPEC0_ICS 16 |
| 200 | #define CP0VPEC0_MVP 1 |
| 201 | #define CP0VPEC0_VPA 0 |
| 202 | int32_t CP0_VPEConf1; |
| 203 | #define CP0VPEC1_NCX 20 |
| 204 | #define CP0VPEC1_NCP2 10 |
| 205 | #define CP0VPEC1_NCP1 0 |
| 206 | target_ulong CP0_YQMask; |
| 207 | target_ulong CP0_VPESchedule; |
| 208 | target_ulong CP0_VPEScheFBack; |
| 209 | int32_t CP0_VPEOpt; |
| 210 | #define CP0VPEOpt_IWX7 15 |
| 211 | #define CP0VPEOpt_IWX6 14 |
| 212 | #define CP0VPEOpt_IWX5 13 |
| 213 | #define CP0VPEOpt_IWX4 12 |
| 214 | #define CP0VPEOpt_IWX3 11 |
| 215 | #define CP0VPEOpt_IWX2 10 |
| 216 | #define CP0VPEOpt_IWX1 9 |
| 217 | #define CP0VPEOpt_IWX0 8 |
| 218 | #define CP0VPEOpt_DWX7 7 |
| 219 | #define CP0VPEOpt_DWX6 6 |
| 220 | #define CP0VPEOpt_DWX5 5 |
| 221 | #define CP0VPEOpt_DWX4 4 |
| 222 | #define CP0VPEOpt_DWX3 3 |
| 223 | #define CP0VPEOpt_DWX2 2 |
| 224 | #define CP0VPEOpt_DWX1 1 |
| 225 | #define CP0VPEOpt_DWX0 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 226 | target_ulong CP0_EntryLo0; |
| 227 | target_ulong CP0_EntryLo1; |
| 228 | target_ulong CP0_Context; |
| 229 | int32_t CP0_PageMask; |
| 230 | int32_t CP0_PageGrain; |
| 231 | int32_t CP0_Wired; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 232 | int32_t CP0_SRSConf0_rw_bitmask; |
| 233 | int32_t CP0_SRSConf0; |
| 234 | #define CP0SRSC0_M 31 |
| 235 | #define CP0SRSC0_SRS3 20 |
| 236 | #define CP0SRSC0_SRS2 10 |
| 237 | #define CP0SRSC0_SRS1 0 |
| 238 | int32_t CP0_SRSConf1_rw_bitmask; |
| 239 | int32_t CP0_SRSConf1; |
| 240 | #define CP0SRSC1_M 31 |
| 241 | #define CP0SRSC1_SRS6 20 |
| 242 | #define CP0SRSC1_SRS5 10 |
| 243 | #define CP0SRSC1_SRS4 0 |
| 244 | int32_t CP0_SRSConf2_rw_bitmask; |
| 245 | int32_t CP0_SRSConf2; |
| 246 | #define CP0SRSC2_M 31 |
| 247 | #define CP0SRSC2_SRS9 20 |
| 248 | #define CP0SRSC2_SRS8 10 |
| 249 | #define CP0SRSC2_SRS7 0 |
| 250 | int32_t CP0_SRSConf3_rw_bitmask; |
| 251 | int32_t CP0_SRSConf3; |
| 252 | #define CP0SRSC3_M 31 |
| 253 | #define CP0SRSC3_SRS12 20 |
| 254 | #define CP0SRSC3_SRS11 10 |
| 255 | #define CP0SRSC3_SRS10 0 |
| 256 | int32_t CP0_SRSConf4_rw_bitmask; |
| 257 | int32_t CP0_SRSConf4; |
| 258 | #define CP0SRSC4_SRS15 20 |
| 259 | #define CP0SRSC4_SRS14 10 |
| 260 | #define CP0SRSC4_SRS13 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 261 | int32_t CP0_HWREna; |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 262 | target_ulong CP0_BadVAddr; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 263 | int32_t CP0_Count; |
| 264 | target_ulong CP0_EntryHi; |
| 265 | int32_t CP0_Compare; |
| 266 | int32_t CP0_Status; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 267 | #define CP0St_CU3 31 |
| 268 | #define CP0St_CU2 30 |
| 269 | #define CP0St_CU1 29 |
| 270 | #define CP0St_CU0 28 |
| 271 | #define CP0St_RP 27 |
bellard | 6ea83fe | 2006-06-14 12:56:19 +0000 | [diff] [blame] | 272 | #define CP0St_FR 26 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 273 | #define CP0St_RE 25 |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 274 | #define CP0St_MX 24 |
| 275 | #define CP0St_PX 23 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 276 | #define CP0St_BEV 22 |
| 277 | #define CP0St_TS 21 |
| 278 | #define CP0St_SR 20 |
| 279 | #define CP0St_NMI 19 |
| 280 | #define CP0St_IM 8 |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 281 | #define CP0St_KX 7 |
| 282 | #define CP0St_SX 6 |
| 283 | #define CP0St_UX 5 |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 284 | #define CP0St_KSU 3 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 285 | #define CP0St_ERL 2 |
| 286 | #define CP0St_EXL 1 |
| 287 | #define CP0St_IE 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 288 | int32_t CP0_IntCtl; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 289 | #define CP0IntCtl_IPTI 29 |
| 290 | #define CP0IntCtl_IPPC1 26 |
| 291 | #define CP0IntCtl_VS 5 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 292 | int32_t CP0_SRSCtl; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 293 | #define CP0SRSCtl_HSS 26 |
| 294 | #define CP0SRSCtl_EICSS 18 |
| 295 | #define CP0SRSCtl_ESS 12 |
| 296 | #define CP0SRSCtl_PSS 6 |
| 297 | #define CP0SRSCtl_CSS 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 298 | int32_t CP0_SRSMap; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 299 | #define CP0SRSMap_SSV7 28 |
| 300 | #define CP0SRSMap_SSV6 24 |
| 301 | #define CP0SRSMap_SSV5 20 |
| 302 | #define CP0SRSMap_SSV4 16 |
| 303 | #define CP0SRSMap_SSV3 12 |
| 304 | #define CP0SRSMap_SSV2 8 |
| 305 | #define CP0SRSMap_SSV1 4 |
| 306 | #define CP0SRSMap_SSV0 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 307 | int32_t CP0_Cause; |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 308 | #define CP0Ca_BD 31 |
| 309 | #define CP0Ca_TI 30 |
| 310 | #define CP0Ca_CE 28 |
| 311 | #define CP0Ca_DC 27 |
| 312 | #define CP0Ca_PCI 26 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 313 | #define CP0Ca_IV 23 |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 314 | #define CP0Ca_WP 22 |
| 315 | #define CP0Ca_IP 8 |
ths | 4de9b24 | 2007-01-24 01:47:51 +0000 | [diff] [blame] | 316 | #define CP0Ca_IP_mask 0x0000FF00 |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 317 | #define CP0Ca_EC 2 |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 318 | target_ulong CP0_EPC; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 319 | int32_t CP0_PRid; |
ths | b29a034 | 2007-01-24 18:01:23 +0000 | [diff] [blame] | 320 | int32_t CP0_EBase; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 321 | int32_t CP0_Config0; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 322 | #define CP0C0_M 31 |
| 323 | #define CP0C0_K23 28 |
| 324 | #define CP0C0_KU 25 |
| 325 | #define CP0C0_MDU 20 |
| 326 | #define CP0C0_MM 17 |
| 327 | #define CP0C0_BM 16 |
| 328 | #define CP0C0_BE 15 |
| 329 | #define CP0C0_AT 13 |
| 330 | #define CP0C0_AR 10 |
| 331 | #define CP0C0_MT 7 |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 332 | #define CP0C0_VI 3 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 333 | #define CP0C0_K0 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 334 | int32_t CP0_Config1; |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 335 | #define CP0C1_M 31 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 336 | #define CP0C1_MMU 25 |
| 337 | #define CP0C1_IS 22 |
| 338 | #define CP0C1_IL 19 |
| 339 | #define CP0C1_IA 16 |
| 340 | #define CP0C1_DS 13 |
| 341 | #define CP0C1_DL 10 |
| 342 | #define CP0C1_DA 7 |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 343 | #define CP0C1_C2 6 |
| 344 | #define CP0C1_MD 5 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 345 | #define CP0C1_PC 4 |
| 346 | #define CP0C1_WR 3 |
| 347 | #define CP0C1_CA 2 |
| 348 | #define CP0C1_EP 1 |
| 349 | #define CP0C1_FP 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 350 | int32_t CP0_Config2; |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 351 | #define CP0C2_M 31 |
| 352 | #define CP0C2_TU 28 |
| 353 | #define CP0C2_TS 24 |
| 354 | #define CP0C2_TL 20 |
| 355 | #define CP0C2_TA 16 |
| 356 | #define CP0C2_SU 12 |
| 357 | #define CP0C2_SS 8 |
| 358 | #define CP0C2_SL 4 |
| 359 | #define CP0C2_SA 0 |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 360 | int32_t CP0_Config3; |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 361 | #define CP0C3_M 31 |
Nathan Froyd | bbfa8f7 | 2010-06-08 13:30:01 -0700 | [diff] [blame] | 362 | #define CP0C3_ISA_ON_EXC 16 |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 363 | #define CP0C3_DSPP 10 |
| 364 | #define CP0C3_LPA 7 |
| 365 | #define CP0C3_VEIC 6 |
| 366 | #define CP0C3_VInt 5 |
| 367 | #define CP0C3_SP 4 |
| 368 | #define CP0C3_MT 2 |
| 369 | #define CP0C3_SM 1 |
| 370 | #define CP0C3_TL 0 |
ths | e397ee3 | 2007-03-23 00:43:28 +0000 | [diff] [blame] | 371 | int32_t CP0_Config6; |
| 372 | int32_t CP0_Config7; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 373 | /* XXX: Maybe make LLAddr per-TC? */ |
Aurelien Jarno | 5499b6f | 2009-11-22 13:08:14 +0100 | [diff] [blame] | 374 | target_ulong lladdr; |
Paul Brook | 590bc60 | 2009-07-09 17:45:17 +0100 | [diff] [blame] | 375 | target_ulong llval; |
| 376 | target_ulong llnewval; |
| 377 | target_ulong llreg; |
Aurelien Jarno | 2a6e32d | 2009-11-22 13:22:54 +0100 | [diff] [blame] | 378 | target_ulong CP0_LLAddr_rw_bitmask; |
| 379 | int CP0_LLAddr_shift; |
ths | fd88b6a | 2007-05-23 08:24:25 +0000 | [diff] [blame] | 380 | target_ulong CP0_WatchLo[8]; |
| 381 | int32_t CP0_WatchHi[8]; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 382 | target_ulong CP0_XContext; |
| 383 | int32_t CP0_Framemask; |
| 384 | int32_t CP0_Debug; |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 385 | #define CP0DB_DBD 31 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 386 | #define CP0DB_DM 30 |
| 387 | #define CP0DB_LSNM 28 |
| 388 | #define CP0DB_Doze 27 |
| 389 | #define CP0DB_Halt 26 |
| 390 | #define CP0DB_CNT 25 |
| 391 | #define CP0DB_IBEP 24 |
| 392 | #define CP0DB_DBEP 21 |
| 393 | #define CP0DB_IEXI 20 |
| 394 | #define CP0DB_VER 15 |
| 395 | #define CP0DB_DEC 10 |
| 396 | #define CP0DB_SSt 8 |
| 397 | #define CP0DB_DINT 5 |
| 398 | #define CP0DB_DIB 4 |
| 399 | #define CP0DB_DDBS 3 |
| 400 | #define CP0DB_DDBL 2 |
| 401 | #define CP0DB_DBp 1 |
| 402 | #define CP0DB_DSS 0 |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 403 | target_ulong CP0_DEPC; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 404 | int32_t CP0_Performance0; |
| 405 | int32_t CP0_TagLo; |
| 406 | int32_t CP0_DataLo; |
| 407 | int32_t CP0_TagHi; |
| 408 | int32_t CP0_DataHi; |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 409 | target_ulong CP0_ErrorEPC; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 410 | int32_t CP0_DESAVE; |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 411 | /* We waste some space so we can handle shadow registers like TCs. */ |
| 412 | TCState tcs[MIPS_SHADOW_SET_MAX]; |
ths | f01be15 | 2008-09-18 11:57:27 +0000 | [diff] [blame] | 413 | CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; |
Stefan Weil | 5cbdb3a | 2012-04-07 09:23:39 +0200 | [diff] [blame] | 414 | /* QEMU */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 415 | int error_code; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 416 | uint32_t hflags; /* CPU State */ |
| 417 | /* TMASK defines different execution modes */ |
Jia Liu | 853c324 | 2012-10-24 22:17:02 +0800 | [diff] [blame] | 418 | #define MIPS_HFLAG_TMASK 0xC07FF |
Nathan Froyd | 79ef2c4 | 2009-12-08 08:06:22 -0800 | [diff] [blame] | 419 | #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 420 | /* The KSU flags must be the lowest bits in hflags. The flag order |
| 421 | must be the same as defined for CP0 Status. This allows to use |
| 422 | the bits as the value of mmu_idx. */ |
Nathan Froyd | 79ef2c4 | 2009-12-08 08:06:22 -0800 | [diff] [blame] | 423 | #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ |
| 424 | #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ |
| 425 | #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ |
| 426 | #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ |
| 427 | #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ |
| 428 | #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ |
| 429 | #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ |
| 430 | #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ |
| 431 | #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ |
ths | b8aa459 | 2007-12-30 15:36:58 +0000 | [diff] [blame] | 432 | /* True if the MIPS IV COP1X instructions can be used. This also |
| 433 | controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S |
| 434 | and RSQRT.D. */ |
Nathan Froyd | 79ef2c4 | 2009-12-08 08:06:22 -0800 | [diff] [blame] | 435 | #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ |
| 436 | #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ |
| 437 | #define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */ |
| 438 | #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ |
| 439 | #define MIPS_HFLAG_M16_SHIFT 10 |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 440 | /* If translation is interrupted between the branch instruction and |
| 441 | * the delay slot, record what type of branch it is so that we can |
| 442 | * resume translation properly. It might be possible to reduce |
| 443 | * this from three bits to two. */ |
Nathan Froyd | 79ef2c4 | 2009-12-08 08:06:22 -0800 | [diff] [blame] | 444 | #define MIPS_HFLAG_BMASK_BASE 0x03800 |
| 445 | #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ |
| 446 | #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ |
| 447 | #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ |
| 448 | #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ |
| 449 | /* Extra flags about the current pending branch. */ |
| 450 | #define MIPS_HFLAG_BMASK_EXT 0x3C000 |
| 451 | #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ |
| 452 | #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ |
| 453 | #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ |
| 454 | #define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */ |
| 455 | #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) |
Jia Liu | 853c324 | 2012-10-24 22:17:02 +0800 | [diff] [blame] | 456 | /* MIPS DSP resources access. */ |
| 457 | #define MIPS_HFLAG_DSP 0x40000 /* Enable access to MIPS DSP resources. */ |
| 458 | #define MIPS_HFLAG_DSPR2 0x80000 /* Enable access to MIPS DSPR2 resources. */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 459 | target_ulong btarget; /* Jump / branch target */ |
aurel32 | 1ba74fb | 2009-03-29 01:18:52 +0000 | [diff] [blame] | 460 | target_ulong bcond; /* Branch condition (if needed) */ |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 461 | |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 462 | int SYNCI_Step; /* Address step size for SYNCI */ |
| 463 | int CCRes; /* Cycle count resolution/divisor */ |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 464 | uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ |
| 465 | uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ |
ths | e189e74 | 2007-09-24 12:48:00 +0000 | [diff] [blame] | 466 | int insn_flags; /* Supported instruction set */ |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 467 | |
ths | 0eaef5a | 2008-07-23 16:14:22 +0000 | [diff] [blame] | 468 | target_ulong tls_value; /* For usermode emulation */ |
ths | 6f5b89a | 2007-03-02 20:48:00 +0000 | [diff] [blame] | 469 | |
bellard | a316d33 | 2005-11-20 10:32:34 +0000 | [diff] [blame] | 470 | CPU_COMMON |
ths | 6ae8177 | 2006-12-06 17:48:52 +0000 | [diff] [blame] | 471 | |
Blue Swirl | 51cc2e7 | 2009-11-08 12:50:21 +0200 | [diff] [blame] | 472 | CPUMIPSMVPContext *mvp; |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 473 | #if !defined(CONFIG_USER_ONLY) |
Blue Swirl | 51cc2e7 | 2009-11-08 12:50:21 +0200 | [diff] [blame] | 474 | CPUMIPSTLBContext *tlb; |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 475 | #endif |
Blue Swirl | 51cc2e7 | 2009-11-08 12:50:21 +0200 | [diff] [blame] | 476 | |
Anthony Liguori | c227f09 | 2009-10-01 16:12:16 -0500 | [diff] [blame] | 477 | const mips_def_t *cpu_model; |
ths | 33ac7f1 | 2007-05-31 16:18:58 +0000 | [diff] [blame] | 478 | void *irq[8]; |
ths | 6ae8177 | 2006-12-06 17:48:52 +0000 | [diff] [blame] | 479 | struct QEMUTimer *timer; /* Internal timer */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 480 | }; |
| 481 | |
Andreas Färber | 0f71a70 | 2012-04-15 23:29:19 +0200 | [diff] [blame] | 482 | #include "cpu-qom.h" |
| 483 | |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 484 | #if !defined(CONFIG_USER_ONLY) |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 485 | int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 486 | target_ulong address, int rw, int access_type); |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 487 | int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 488 | target_ulong address, int rw, int access_type); |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 489 | int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
ths | 29929e3 | 2007-05-13 13:49:44 +0000 | [diff] [blame] | 490 | target_ulong address, int rw, int access_type); |
Blue Swirl | 895c2d0 | 2012-09-02 14:52:59 +0000 | [diff] [blame] | 491 | void r4k_helper_tlbwi(CPUMIPSState *env); |
| 492 | void r4k_helper_tlbwr(CPUMIPSState *env); |
| 493 | void r4k_helper_tlbp(CPUMIPSState *env); |
| 494 | void r4k_helper_tlbr(CPUMIPSState *env); |
ths | 33d68b5 | 2007-03-18 00:30:29 +0000 | [diff] [blame] | 495 | |
Andreas Färber | c658b94 | 2013-05-27 06:49:53 +0200 | [diff] [blame] | 496 | void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr, |
| 497 | bool is_write, bool is_exec, int unused, |
| 498 | unsigned size); |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 499 | #endif |
| 500 | |
Stefan Weil | 9a78eea | 2010-10-22 23:03:33 +0200 | [diff] [blame] | 501 | void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); |
ths | 647de6c | 2007-10-20 19:45:44 +0000 | [diff] [blame] | 502 | |
ths | 9467d44 | 2007-06-03 21:02:38 +0000 | [diff] [blame] | 503 | #define cpu_exec cpu_mips_exec |
| 504 | #define cpu_gen_code cpu_mips_gen_code |
| 505 | #define cpu_signal_handler cpu_mips_signal_handler |
j_mayer | c732abe | 2007-10-12 06:47:46 +0000 | [diff] [blame] | 506 | #define cpu_list mips_cpu_list |
ths | 9467d44 | 2007-06-03 21:02:38 +0000 | [diff] [blame] | 507 | |
Richard Henderson | 084d049 | 2013-02-10 10:30:44 -0800 | [diff] [blame] | 508 | extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); |
| 509 | extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); |
| 510 | |
pbrook | b3c7724 | 2008-06-30 16:31:04 +0000 | [diff] [blame] | 511 | #define CPU_SAVE_VERSION 3 |
| 512 | |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 513 | /* MMU modes definitions. We carefully match the indices with our |
| 514 | hflags layout. */ |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 515 | #define MMU_MODE0_SUFFIX _kernel |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 516 | #define MMU_MODE1_SUFFIX _super |
| 517 | #define MMU_MODE2_SUFFIX _user |
| 518 | #define MMU_USER_IDX 2 |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 519 | static inline int cpu_mmu_index (CPUMIPSState *env) |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 520 | { |
ths | 623a930 | 2007-10-28 19:45:05 +0000 | [diff] [blame] | 521 | return env->hflags & MIPS_HFLAG_KSU; |
j_mayer | 6ebbf39 | 2007-10-14 07:07:08 +0000 | [diff] [blame] | 522 | } |
| 523 | |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 524 | static inline void cpu_clone_regs(CPUMIPSState *env, target_ulong newsp) |
pbrook | 6e68e07 | 2008-05-30 17:22:15 +0000 | [diff] [blame] | 525 | { |
pbrook | f8ed707 | 2008-05-30 17:54:15 +0000 | [diff] [blame] | 526 | if (newsp) |
ths | b5dc773 | 2008-06-27 10:02:35 +0000 | [diff] [blame] | 527 | env->active_tc.gpr[29] = newsp; |
| 528 | env->active_tc.gpr[7] = 0; |
| 529 | env->active_tc.gpr[2] = 0; |
pbrook | 6e68e07 | 2008-05-30 17:22:15 +0000 | [diff] [blame] | 530 | } |
pbrook | 6e68e07 | 2008-05-30 17:22:15 +0000 | [diff] [blame] | 531 | |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 532 | static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env) |
Edgar E. Iglesias | 138afb0 | 2010-08-06 12:21:16 +0200 | [diff] [blame] | 533 | { |
| 534 | int32_t pending; |
| 535 | int32_t status; |
| 536 | int r; |
| 537 | |
Aurelien Jarno | 4cdc1cd | 2010-12-25 22:56:32 +0100 | [diff] [blame] | 538 | if (!(env->CP0_Status & (1 << CP0St_IE)) || |
| 539 | (env->CP0_Status & (1 << CP0St_EXL)) || |
| 540 | (env->CP0_Status & (1 << CP0St_ERL)) || |
Edgar E. Iglesias | 344eecf | 2011-08-30 00:44:28 +0200 | [diff] [blame] | 541 | /* Note that the TCStatus IXMT field is initialized to zero, |
| 542 | and only MT capable cores can set it to one. So we don't |
| 543 | need to check for MT capabilities here. */ |
| 544 | (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) || |
Aurelien Jarno | 4cdc1cd | 2010-12-25 22:56:32 +0100 | [diff] [blame] | 545 | (env->hflags & MIPS_HFLAG_DM)) { |
| 546 | /* Interrupts are disabled */ |
| 547 | return 0; |
| 548 | } |
| 549 | |
Edgar E. Iglesias | 138afb0 | 2010-08-06 12:21:16 +0200 | [diff] [blame] | 550 | pending = env->CP0_Cause & CP0Ca_IP_mask; |
| 551 | status = env->CP0_Status & CP0Ca_IP_mask; |
| 552 | |
| 553 | if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { |
| 554 | /* A MIPS configured with a vectorizing external interrupt controller |
| 555 | will feed a vector into the Cause pending lines. The core treats |
| 556 | the status lines as a vector level, not as indiviual masks. */ |
| 557 | r = pending > status; |
| 558 | } else { |
| 559 | /* A MIPS configured with compatibility or VInt (Vectored Interrupts) |
| 560 | treats the pending lines as individual interrupt lines, the status |
| 561 | lines are individual masks. */ |
| 562 | r = pending & status; |
| 563 | } |
| 564 | return r; |
| 565 | } |
| 566 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 567 | #include "exec/cpu-all.h" |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 568 | |
| 569 | /* Memory access type : |
| 570 | * may be needed for precise access rights control and precise exceptions. |
| 571 | */ |
| 572 | enum { |
| 573 | /* 1 bit to define user level / supervisor access */ |
| 574 | ACCESS_USER = 0x00, |
| 575 | ACCESS_SUPER = 0x01, |
| 576 | /* 1 bit to indicate direction */ |
| 577 | ACCESS_STORE = 0x02, |
| 578 | /* Type of instruction that generated the access */ |
| 579 | ACCESS_CODE = 0x10, /* Code fetch access */ |
| 580 | ACCESS_INT = 0x20, /* Integer load/store access */ |
| 581 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
| 582 | }; |
| 583 | |
| 584 | /* Exceptions */ |
| 585 | enum { |
| 586 | EXCP_NONE = -1, |
| 587 | EXCP_RESET = 0, |
| 588 | EXCP_SRESET, |
| 589 | EXCP_DSS, |
| 590 | EXCP_DINT, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 591 | EXCP_DDBL, |
| 592 | EXCP_DDBS, |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 593 | EXCP_NMI, |
| 594 | EXCP_MCHECK, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 595 | EXCP_EXT_INTERRUPT, /* 8 */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 596 | EXCP_DFWATCH, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 597 | EXCP_DIB, |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 598 | EXCP_IWATCH, |
| 599 | EXCP_AdEL, |
| 600 | EXCP_AdES, |
| 601 | EXCP_TLBF, |
| 602 | EXCP_IBE, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 603 | EXCP_DBp, /* 16 */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 604 | EXCP_SYSCALL, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 605 | EXCP_BREAK, |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 606 | EXCP_CpU, |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 607 | EXCP_RI, |
| 608 | EXCP_OVERFLOW, |
| 609 | EXCP_TRAP, |
ths | 5a5012e | 2007-05-07 13:55:33 +0000 | [diff] [blame] | 610 | EXCP_FPE, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 611 | EXCP_DWATCH, /* 24 */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 612 | EXCP_LTLBL, |
| 613 | EXCP_TLBL, |
| 614 | EXCP_TLBS, |
| 615 | EXCP_DBE, |
ths | ead9360 | 2007-09-06 00:18:15 +0000 | [diff] [blame] | 616 | EXCP_THREAD, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 617 | EXCP_MDMX, |
| 618 | EXCP_C2E, |
| 619 | EXCP_CACHE, /* 32 */ |
Jia Liu | 853c324 | 2012-10-24 22:17:02 +0800 | [diff] [blame] | 620 | EXCP_DSPDIS, |
ths | 14e51cc | 2007-12-26 19:34:03 +0000 | [diff] [blame] | 621 | |
Jia Liu | 853c324 | 2012-10-24 22:17:02 +0800 | [diff] [blame] | 622 | EXCP_LAST = EXCP_DSPDIS, |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 623 | }; |
Paul Brook | 590bc60 | 2009-07-09 17:45:17 +0100 | [diff] [blame] | 624 | /* Dummy exception for conditional stores. */ |
| 625 | #define EXCP_SC 0x100 |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 626 | |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 627 | /* |
| 628 | * This is an interrnally generated WAKE request line. |
| 629 | * It is driven by the CPU itself. Raised when the MT |
| 630 | * block wants to wake a VPE from an inactive state and |
| 631 | * cleared when VPE goes from active to inactive. |
| 632 | */ |
| 633 | #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 |
| 634 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 635 | int cpu_mips_exec(CPUMIPSState *s); |
Andreas Färber | 78ce64f | 2013-01-20 01:22:25 +0100 | [diff] [blame] | 636 | void mips_tcg_init(void); |
Andreas Färber | 30bf942 | 2012-05-05 13:33:04 +0200 | [diff] [blame] | 637 | MIPSCPU *cpu_mips_init(const char *cpu_model); |
ths | 388bb21 | 2007-05-13 13:58:00 +0000 | [diff] [blame] | 638 | int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 639 | |
Andreas Färber | 30bf942 | 2012-05-05 13:33:04 +0200 | [diff] [blame] | 640 | static inline CPUMIPSState *cpu_init(const char *cpu_model) |
| 641 | { |
| 642 | MIPSCPU *cpu = cpu_mips_init(cpu_model); |
| 643 | if (cpu == NULL) { |
| 644 | return NULL; |
| 645 | } |
| 646 | return &cpu->env; |
| 647 | } |
| 648 | |
Andreas Färber | b7e516c | 2012-05-05 15:43:31 +0200 | [diff] [blame] | 649 | /* TODO QOM'ify CPU reset and remove */ |
| 650 | void cpu_state_reset(CPUMIPSState *s); |
| 651 | |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 652 | /* mips_timer.c */ |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 653 | uint32_t cpu_mips_get_random (CPUMIPSState *env); |
| 654 | uint32_t cpu_mips_get_count (CPUMIPSState *env); |
| 655 | void cpu_mips_store_count (CPUMIPSState *env, uint32_t value); |
| 656 | void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value); |
| 657 | void cpu_mips_start_count(CPUMIPSState *env); |
| 658 | void cpu_mips_stop_count(CPUMIPSState *env); |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 659 | |
Aurelien Jarno | 5dc5d9f | 2010-07-25 16:51:29 +0200 | [diff] [blame] | 660 | /* mips_int.c */ |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 661 | void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); |
Aurelien Jarno | 5dc5d9f | 2010-07-25 16:51:29 +0200 | [diff] [blame] | 662 | |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 663 | /* helper.c */ |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 664 | int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw, |
Blue Swirl | 97b348e | 2011-08-01 16:12:17 +0000 | [diff] [blame] | 665 | int mmu_idx); |
Nathan Froyd | 0b5c1ce | 2009-08-10 13:37:36 -0700 | [diff] [blame] | 666 | #define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 667 | #if !defined(CONFIG_USER_ONLY) |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 668 | void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra); |
Avi Kivity | a8170e5 | 2012-10-23 12:30:10 +0200 | [diff] [blame] | 669 | hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, |
Aurelien Jarno | c36bbb2 | 2010-02-06 17:02:45 +0100 | [diff] [blame] | 670 | int rw); |
Paul Brook | 3c7b48b | 2010-03-01 04:11:28 +0000 | [diff] [blame] | 671 | #endif |
Kwok Cheung Yeung | 1239b47 | 2013-05-17 14:51:21 -0700 | [diff] [blame] | 672 | target_ulong exception_resume_pc (CPUMIPSState *env); |
ths | f9480ff | 2008-12-20 19:42:14 +0000 | [diff] [blame] | 673 | |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 674 | static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, |
aliguori | 6b91754 | 2008-11-18 19:46:41 +0000 | [diff] [blame] | 675 | target_ulong *cs_base, int *flags) |
| 676 | { |
| 677 | *pc = env->active_tc.PC; |
| 678 | *cs_base = 0; |
| 679 | *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); |
| 680 | } |
| 681 | |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 682 | static inline void cpu_set_tls(CPUMIPSState *env, target_ulong newtls) |
Paul Brook | ff867dd | 2009-07-09 15:07:57 +0100 | [diff] [blame] | 683 | { |
| 684 | env->tls_value = newtls; |
| 685 | } |
| 686 | |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 687 | static inline int mips_vpe_active(CPUMIPSState *env) |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 688 | { |
| 689 | int active = 1; |
| 690 | |
| 691 | /* Check that the VPE is enabled. */ |
| 692 | if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { |
| 693 | active = 0; |
| 694 | } |
Dong Xu Wang | 4abf79a | 2011-11-22 18:06:21 +0800 | [diff] [blame] | 695 | /* Check that the VPE is activated. */ |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 696 | if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { |
| 697 | active = 0; |
| 698 | } |
| 699 | |
| 700 | /* Now verify that there are active thread contexts in the VPE. |
| 701 | |
| 702 | This assumes the CPU model will internally reschedule threads |
| 703 | if the active one goes to sleep. If there are no threads available |
| 704 | the active one will be in a sleeping state, and we can turn off |
| 705 | the entire VPE. */ |
| 706 | if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { |
| 707 | /* TC is not activated. */ |
| 708 | active = 0; |
| 709 | } |
| 710 | if (env->active_tc.CP0_TCHalt & 1) { |
| 711 | /* TC is in halt state. */ |
| 712 | active = 0; |
| 713 | } |
| 714 | |
| 715 | return active; |
| 716 | } |
| 717 | |
Andreas Färber | 3993c6b | 2012-05-03 06:43:49 +0200 | [diff] [blame] | 718 | static inline bool cpu_has_work(CPUState *cpu) |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 719 | { |
Andreas Färber | 3993c6b | 2012-05-03 06:43:49 +0200 | [diff] [blame] | 720 | CPUMIPSState *env = &MIPS_CPU(cpu)->env; |
| 721 | bool has_work = false; |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 722 | |
| 723 | /* It is implementation dependent if non-enabled interrupts |
| 724 | wake-up the CPU, however most of the implementations only |
| 725 | check for interrupts that can be taken. */ |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 726 | if ((cpu->interrupt_request & CPU_INTERRUPT_HARD) && |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 727 | cpu_mips_hw_interrupts_pending(env)) { |
Andreas Färber | 3993c6b | 2012-05-03 06:43:49 +0200 | [diff] [blame] | 728 | has_work = true; |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 729 | } |
| 730 | |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 731 | /* MIPS-MT has the ability to halt the CPU. */ |
| 732 | if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
| 733 | /* The QEMU model will issue an _WAKE request whenever the CPUs |
| 734 | should be woken up. */ |
Andreas Färber | 259186a | 2013-01-17 18:51:17 +0100 | [diff] [blame] | 735 | if (cpu->interrupt_request & CPU_INTERRUPT_WAKE) { |
Andreas Färber | 3993c6b | 2012-05-03 06:43:49 +0200 | [diff] [blame] | 736 | has_work = true; |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 737 | } |
| 738 | |
| 739 | if (!mips_vpe_active(env)) { |
Andreas Färber | 3993c6b | 2012-05-03 06:43:49 +0200 | [diff] [blame] | 740 | has_work = false; |
Edgar E. Iglesias | f249412 | 2011-08-29 23:07:40 +0200 | [diff] [blame] | 741 | } |
| 742 | } |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 743 | return has_work; |
| 744 | } |
| 745 | |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 746 | #include "exec/exec-all.h" |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 747 | |
Andreas Färber | 7db13fa | 2012-03-14 01:38:22 +0100 | [diff] [blame] | 748 | static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb) |
Blue Swirl | f081c76 | 2011-05-21 07:10:23 +0000 | [diff] [blame] | 749 | { |
| 750 | env->active_tc.PC = tb->pc; |
| 751 | env->hflags &= ~MIPS_HFLAG_BMASK; |
| 752 | env->hflags |= tb->flags & MIPS_HFLAG_BMASK; |
| 753 | } |
| 754 | |
Maciej W. Rozycki | 03e6e50 | 2012-06-08 02:04:40 +0100 | [diff] [blame] | 755 | static inline void compute_hflags(CPUMIPSState *env) |
| 756 | { |
| 757 | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | |
| 758 | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | |
Eric Johnson | e1a4019 | 2013-01-07 22:26:44 -0800 | [diff] [blame] | 759 | MIPS_HFLAG_UX | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2); |
Maciej W. Rozycki | 03e6e50 | 2012-06-08 02:04:40 +0100 | [diff] [blame] | 760 | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
| 761 | !(env->CP0_Status & (1 << CP0St_ERL)) && |
| 762 | !(env->hflags & MIPS_HFLAG_DM)) { |
| 763 | env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; |
| 764 | } |
| 765 | #if defined(TARGET_MIPS64) |
| 766 | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || |
| 767 | (env->CP0_Status & (1 << CP0St_PX)) || |
| 768 | (env->CP0_Status & (1 << CP0St_UX))) { |
| 769 | env->hflags |= MIPS_HFLAG_64; |
| 770 | } |
| 771 | if (env->CP0_Status & (1 << CP0St_UX)) { |
| 772 | env->hflags |= MIPS_HFLAG_UX; |
| 773 | } |
| 774 | #endif |
| 775 | if ((env->CP0_Status & (1 << CP0St_CU0)) || |
| 776 | !(env->hflags & MIPS_HFLAG_KSU)) { |
| 777 | env->hflags |= MIPS_HFLAG_CP0; |
| 778 | } |
| 779 | if (env->CP0_Status & (1 << CP0St_CU1)) { |
| 780 | env->hflags |= MIPS_HFLAG_FPU; |
| 781 | } |
| 782 | if (env->CP0_Status & (1 << CP0St_FR)) { |
| 783 | env->hflags |= MIPS_HFLAG_F64; |
| 784 | } |
Jia Liu | 853c324 | 2012-10-24 22:17:02 +0800 | [diff] [blame] | 785 | if (env->insn_flags & ASE_DSPR2) { |
| 786 | /* Enables access MIPS DSP resources, now our cpu is DSP ASER2, |
| 787 | so enable to access DSPR2 resources. */ |
| 788 | if (env->CP0_Status & (1 << CP0St_MX)) { |
| 789 | env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2; |
| 790 | } |
| 791 | |
| 792 | } else if (env->insn_flags & ASE_DSP) { |
| 793 | /* Enables access MIPS DSP resources, now our cpu is DSP ASE, |
| 794 | so enable to access DSP resources. */ |
| 795 | if (env->CP0_Status & (1 << CP0St_MX)) { |
| 796 | env->hflags |= MIPS_HFLAG_DSP; |
| 797 | } |
| 798 | |
| 799 | } |
Maciej W. Rozycki | 03e6e50 | 2012-06-08 02:04:40 +0100 | [diff] [blame] | 800 | if (env->insn_flags & ISA_MIPS32R2) { |
| 801 | if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { |
| 802 | env->hflags |= MIPS_HFLAG_COP1X; |
| 803 | } |
| 804 | } else if (env->insn_flags & ISA_MIPS32) { |
| 805 | if (env->hflags & MIPS_HFLAG_64) { |
| 806 | env->hflags |= MIPS_HFLAG_COP1X; |
| 807 | } |
| 808 | } else if (env->insn_flags & ISA_MIPS4) { |
| 809 | /* All supported MIPS IV CPUs use the XX (CU3) to enable |
| 810 | and disable the MIPS IV extensions to the MIPS III ISA. |
| 811 | Some other MIPS IV CPUs ignore the bit, so the check here |
| 812 | would be too restrictive for them. */ |
| 813 | if (env->CP0_Status & (1 << CP0St_CU3)) { |
| 814 | env->hflags |= MIPS_HFLAG_COP1X; |
| 815 | } |
| 816 | } |
| 817 | } |
| 818 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 819 | #endif /* !defined (__MIPS_CPU_H__) */ |