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Andreas Färberdec9c2d2012-03-29 04:50:31 +00001/*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
Peter Maydell74c21bd2015-12-07 16:23:44 +000021#include "qemu/osdep.h"
Peter Maydell181962f2018-03-02 10:45:36 +000022#include "target/arm/idau.h"
Wei Huang929e7542016-10-28 14:12:31 +010023#include "qemu/error-report.h"
Markus Armbrusterda34e652016-03-14 09:01:28 +010024#include "qapi/error.h"
Andreas Färber778c3a02012-04-20 07:39:14 +000025#include "cpu.h"
Peter Maydellccd38082014-04-15 19:18:37 +010026#include "internals.h"
Andreas Färberdec9c2d2012-03-29 04:50:31 +000027#include "qemu-common.h"
Paolo Bonzini63c91552016-03-15 13:18:37 +010028#include "exec/exec-all.h"
Peter Maydell5de16432013-11-22 17:17:13 +000029#include "hw/qdev-properties.h"
Peter Maydell3c30dd52012-04-20 17:58:36 +000030#if !defined(CONFIG_USER_ONLY)
31#include "hw/loader.h"
32#endif
Peter Maydell7c1840b2013-08-20 14:54:28 +010033#include "hw/arm/arm.h"
Paolo Bonzini9c17d612012-12-17 18:20:04 +010034#include "sysemu/sysemu.h"
Vincent Palatinb3946622017-01-10 11:59:55 +010035#include "sysemu/hw_accel.h"
Paolo Bonzini50a2c6e2013-03-20 13:11:56 +010036#include "kvm_arm.h"
Richard Henderson110f6c72017-09-14 09:51:06 -070037#include "disas/capstone.h"
Alex Bennée24f91e82018-01-19 18:24:22 +000038#include "fpu/softfloat.h"
Andreas Färberdec9c2d2012-03-29 04:50:31 +000039
Andreas Färberf45748f2013-06-21 19:09:18 +020040static void arm_cpu_set_pc(CPUState *cs, vaddr value)
41{
42 ARMCPU *cpu = ARM_CPU(cs);
43
44 cpu->env.regs[15] = value;
45}
46
Andreas Färber8c2e1b02013-08-25 18:53:55 +020047static bool arm_cpu_has_work(CPUState *cs)
48{
Rob Herring543486d2014-10-24 12:19:12 +010049 ARMCPU *cpu = ARM_CPU(cs);
50
Alex Bennée062ba092017-02-23 18:29:23 +000051 return (cpu->power_state != PSCI_OFF)
Rob Herring543486d2014-10-24 12:19:12 +010052 && cs->interrupt_request &
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +010053 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
54 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
55 | CPU_INTERRUPT_EXITTB);
Andreas Färber8c2e1b02013-08-25 18:53:55 +020056}
57
Aaron Lindsayb5c53d12018-04-26 11:04:39 +010058void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
59 void *opaque)
60{
61 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
62
63 entry->hook = hook;
64 entry->opaque = opaque;
65
66 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
67}
68
Aaron Lindsay08267482018-04-26 11:04:39 +010069void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
Peter Maydellbd7d00f2016-06-17 15:23:46 +010070 void *opaque)
71{
Aaron Lindsay08267482018-04-26 11:04:39 +010072 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
73
74 entry->hook = hook;
75 entry->opaque = opaque;
76
77 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
Peter Maydellbd7d00f2016-06-17 15:23:46 +010078}
79
Peter Maydell4b6a83f2012-06-20 11:57:06 +000080static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
81{
82 /* Reset a single ARMCPRegInfo register */
83 ARMCPRegInfo *ri = value;
84 ARMCPU *cpu = opaque;
85
Sergey Fedorovb061a822015-06-19 14:17:44 +010086 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
Peter Maydell4b6a83f2012-06-20 11:57:06 +000087 return;
88 }
89
90 if (ri->resetfn) {
91 ri->resetfn(&cpu->env, ri);
92 return;
93 }
94
95 /* A zero offset is never possible as it would be regs[0]
96 * so we use it to indicate that reset is being handled elsewhere.
97 * This is basically only used for fields in non-core coprocessors
98 * (like the pxa2xx ones).
99 */
100 if (!ri->fieldoffset) {
101 return;
102 }
103
Peter Maydell67ed7712014-02-26 17:20:01 +0000104 if (cpreg_field_is_64bit(ri)) {
Peter Maydell4b6a83f2012-06-20 11:57:06 +0000105 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
106 } else {
107 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
108 }
109}
110
Peter Maydell49a66192015-08-13 11:26:21 +0100111static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
112{
113 /* Purely an assertion check: we've already done reset once,
114 * so now check that running the reset for the cpreg doesn't
115 * change its value. This traps bugs where two different cpregs
116 * both try to reset the same state field but to different values.
117 */
118 ARMCPRegInfo *ri = value;
119 ARMCPU *cpu = opaque;
120 uint64_t oldvalue, newvalue;
121
122 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
123 return;
124 }
125
126 oldvalue = read_raw_cp_reg(&cpu->env, ri);
127 cp_reg_reset(key, value, opaque);
128 newvalue = read_raw_cp_reg(&cpu->env, ri);
129 assert(oldvalue == newvalue);
130}
131
Andreas Färberdec9c2d2012-03-29 04:50:31 +0000132/* CPUClass::reset() */
133static void arm_cpu_reset(CPUState *s)
134{
135 ARMCPU *cpu = ARM_CPU(s);
136 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
Peter Maydell3c30dd52012-04-20 17:58:36 +0000137 CPUARMState *env = &cpu->env;
Peter Maydell3c30dd52012-04-20 17:58:36 +0000138
Andreas Färberdec9c2d2012-03-29 04:50:31 +0000139 acc->parent_reset(s);
140
Alex Bennée1f5c00c2016-11-14 14:19:17 +0000141 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
142
Peter Maydell4b6a83f2012-06-20 11:57:06 +0000143 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
Peter Maydell49a66192015-08-13 11:26:21 +0100144 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
145
Peter Maydell3c30dd52012-04-20 17:58:36 +0000146 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
147 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
148 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
Peter Maydella50c0f52014-04-15 19:18:44 +0100149 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
Peter Maydell3c30dd52012-04-20 17:58:36 +0000150
Alex Bennée062ba092017-02-23 18:29:23 +0000151 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
Rob Herring543486d2014-10-24 12:19:12 +0100152 s->halted = cpu->start_powered_off;
153
Peter Maydell3c30dd52012-04-20 17:58:36 +0000154 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
155 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
156 }
157
Alexander Graf3926cc82013-09-03 20:12:09 +0100158 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
159 /* 64 bit CPUs always start in 64 bit mode */
160 env->aarch64 = 1;
Peter Maydelld3563122013-12-17 19:42:30 +0000161#if defined(CONFIG_USER_ONLY)
162 env->pstate = PSTATE_MODE_EL0t;
Peter Maydell14e5f102014-10-24 12:19:13 +0100163 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
Fabian Aggeler137feaa2014-12-11 12:07:50 +0000164 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
Peter Maydell8c6afa62014-04-15 19:18:39 +0100165 /* and to the FP/Neon instructions */
Sergey Fedorov7ebd5f22015-04-26 16:49:25 +0100166 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
Peter Maydelld3563122013-12-17 19:42:30 +0000167#else
Greg Bellows50972272015-02-05 13:37:22 +0000168 /* Reset into the highest available EL */
169 if (arm_feature(env, ARM_FEATURE_EL3)) {
170 env->pstate = PSTATE_MODE_EL3h;
171 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
172 env->pstate = PSTATE_MODE_EL2h;
173 } else {
174 env->pstate = PSTATE_MODE_EL1h;
175 }
Peter Maydell39334432014-04-15 19:18:48 +0100176 env->pc = cpu->rvbar;
Peter Maydelld3563122013-12-17 19:42:30 +0000177#endif
Peter Maydell8c6afa62014-04-15 19:18:39 +0100178 } else {
179#if defined(CONFIG_USER_ONLY)
180 /* Userspace expects access to cp10 and cp11 for FP/Neon */
Sergey Fedorov7ebd5f22015-04-26 16:49:25 +0100181 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
Peter Maydell8c6afa62014-04-15 19:18:39 +0100182#endif
Alexander Graf3926cc82013-09-03 20:12:09 +0100183 }
184
Peter Maydell3c30dd52012-04-20 17:58:36 +0000185#if defined(CONFIG_USER_ONLY)
186 env->uncached_cpsr = ARM_CPU_MODE_USR;
187 /* For user mode we must enable access to coprocessors */
188 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
189 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
190 env->cp15.c15_cpar = 3;
191 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
192 env->cp15.c15_cpar = 1;
193 }
194#else
195 /* SVC mode with interrupts disabled. */
Peter Maydell4cc35612014-02-26 17:20:06 +0000196 env->uncached_cpsr = ARM_CPU_MODE_SVC;
197 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
Michael Davidsaverdc7abe42017-01-27 15:20:24 +0000198
Peter Maydell531c60a2017-01-27 15:20:22 +0000199 if (arm_feature(env, ARM_FEATURE_M)) {
Martin Galvan6e3cf5d2014-09-12 14:06:48 +0100200 uint32_t initial_msp; /* Loaded from 0x0 */
201 uint32_t initial_pc; /* Loaded from 0x4 */
Peter Maydell3c30dd52012-04-20 17:58:36 +0000202 uint8_t *rom;
Peter Maydell38e2a772018-03-02 10:45:37 +0000203 uint32_t vecbase;
Martin Galvan6e3cf5d2014-09-12 14:06:48 +0100204
Peter Maydell1e577cc2017-09-07 13:54:52 +0100205 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
206 env->v7m.secure = true;
Peter Maydell3b2e9342017-09-12 19:13:52 +0100207 } else {
208 /* This bit resets to 0 if security is supported, but 1 if
209 * it is not. The bit is not present in v7M, but we set it
210 * here so we can avoid having to make checks on it conditional
211 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
212 */
213 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
Peter Maydell1e577cc2017-09-07 13:54:52 +0100214 }
215
Peter Maydell9d40cd82017-09-07 13:54:54 +0100216 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
Peter Maydell2c4da502017-01-27 15:20:23 +0000217 * that it resets to 1, so QEMU always does that rather than making
Peter Maydell9d40cd82017-09-07 13:54:54 +0100218 * it dependent on CPU model. In v8M it is RES1.
Peter Maydell2c4da502017-01-27 15:20:23 +0000219 */
Peter Maydell9d40cd82017-09-07 13:54:54 +0100220 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
221 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
222 if (arm_feature(env, ARM_FEATURE_V8)) {
223 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
224 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
225 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
226 }
Peter Maydell2c4da502017-01-27 15:20:23 +0000227
Peter Maydell056f43d2017-01-27 15:20:24 +0000228 /* Unlike A/R profile, M profile defines the reset LR value */
229 env->regs[14] = 0xffffffff;
230
Peter Maydell38e2a772018-03-02 10:45:37 +0000231 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
232
233 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
234 vecbase = env->v7m.vecbase[env->v7m.secure];
235 rom = rom_ptr(vecbase);
Peter Maydell3c30dd52012-04-20 17:58:36 +0000236 if (rom) {
Martin Galvan6e3cf5d2014-09-12 14:06:48 +0100237 /* Address zero is covered by ROM which hasn't yet been
238 * copied into physical memory.
239 */
240 initial_msp = ldl_p(rom);
241 initial_pc = ldl_p(rom + 4);
242 } else {
243 /* Address zero not covered by a ROM blob, or the ROM blob
244 * is in non-modifiable memory and this is a second reset after
245 * it got copied into memory. In the latter case, rom_ptr
246 * will return a NULL pointer and we should use ldl_phys instead.
247 */
Peter Maydell38e2a772018-03-02 10:45:37 +0000248 initial_msp = ldl_phys(s->as, vecbase);
249 initial_pc = ldl_phys(s->as, vecbase + 4);
Peter Maydell3c30dd52012-04-20 17:58:36 +0000250 }
Martin Galvan6e3cf5d2014-09-12 14:06:48 +0100251
252 env->regs[13] = initial_msp & 0xFFFFFFFC;
253 env->regs[15] = initial_pc & ~1;
254 env->thumb = initial_pc & 1;
Peter Maydell3c30dd52012-04-20 17:58:36 +0000255 }
Antony Pavlov387f9802013-12-17 19:42:29 +0000256
Fabian Aggeler137feaa2014-12-11 12:07:50 +0000257 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
258 * executing as AArch32 then check if highvecs are enabled and
259 * adjust the PC accordingly.
260 */
261 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
Martin Galvan34bf7742014-09-12 14:06:48 +0100262 env->regs[15] = 0xFFFF0000;
Antony Pavlov387f9802013-12-17 19:42:29 +0000263 }
264
Peter Maydelldc3c4c12017-09-14 18:43:16 +0100265 /* M profile requires that reset clears the exclusive monitor;
266 * A profile does not, but clearing it makes more sense than having it
267 * set with an exclusive access on address zero.
268 */
269 arm_clear_exclusive(env);
270
Peter Maydell3c30dd52012-04-20 17:58:36 +0000271 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
Peter Maydell3c30dd52012-04-20 17:58:36 +0000272#endif
Peter Maydell69ceea62017-07-27 11:59:09 +0100273
Peter Maydell0e1a46b2017-09-07 13:54:51 +0100274 if (arm_feature(env, ARM_FEATURE_PMSA)) {
Peter Maydell69ceea62017-07-27 11:59:09 +0100275 if (cpu->pmsav7_dregion > 0) {
Peter Maydell0e1a46b2017-09-07 13:54:51 +0100276 if (arm_feature(env, ARM_FEATURE_V8)) {
Peter Maydell62c58ee2017-09-07 13:54:53 +0100277 memset(env->pmsav8.rbar[M_REG_NS], 0,
278 sizeof(*env->pmsav8.rbar[M_REG_NS])
279 * cpu->pmsav7_dregion);
280 memset(env->pmsav8.rlar[M_REG_NS], 0,
281 sizeof(*env->pmsav8.rlar[M_REG_NS])
282 * cpu->pmsav7_dregion);
283 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
284 memset(env->pmsav8.rbar[M_REG_S], 0,
285 sizeof(*env->pmsav8.rbar[M_REG_S])
286 * cpu->pmsav7_dregion);
287 memset(env->pmsav8.rlar[M_REG_S], 0,
288 sizeof(*env->pmsav8.rlar[M_REG_S])
289 * cpu->pmsav7_dregion);
290 }
Peter Maydell0e1a46b2017-09-07 13:54:51 +0100291 } else if (arm_feature(env, ARM_FEATURE_V7)) {
292 memset(env->pmsav7.drbar, 0,
293 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
294 memset(env->pmsav7.drsr, 0,
295 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
296 memset(env->pmsav7.dracr, 0,
297 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
298 }
Peter Maydell69ceea62017-07-27 11:59:09 +0100299 }
Peter Maydell1bc04a82017-09-07 13:54:53 +0100300 env->pmsav7.rnr[M_REG_NS] = 0;
301 env->pmsav7.rnr[M_REG_S] = 0;
Peter Maydell4125e6f2017-09-07 13:54:53 +0100302 env->pmsav8.mair0[M_REG_NS] = 0;
303 env->pmsav8.mair0[M_REG_S] = 0;
304 env->pmsav8.mair1[M_REG_NS] = 0;
305 env->pmsav8.mair1[M_REG_S] = 0;
Peter Maydell69ceea62017-07-27 11:59:09 +0100306 }
307
Peter Maydell9901c572017-10-06 16:46:49 +0100308 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
309 if (cpu->sau_sregion > 0) {
310 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
311 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
312 }
313 env->sau.rnr = 0;
314 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
315 * the Cortex-M33 does.
316 */
317 env->sau.ctrl = 0;
318 }
319
Peter Maydell3c30dd52012-04-20 17:58:36 +0000320 set_flush_to_zero(1, &env->vfp.standard_fp_status);
321 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
322 set_default_nan_mode(1, &env->vfp.standard_fp_status);
323 set_float_detect_tininess(float_tininess_before_rounding,
324 &env->vfp.fp_status);
325 set_float_detect_tininess(float_tininess_before_rounding,
326 &env->vfp.standard_fp_status);
Paolo Bonzini50a2c6e2013-03-20 13:11:56 +0100327#ifndef CONFIG_USER_ONLY
328 if (kvm_enabled()) {
329 kvm_arm_reset_vcpu(cpu);
330 }
331#endif
Peter Maydell9ee98ce2014-09-12 14:06:49 +0100332
Peter Maydell46747d12014-09-29 18:48:46 +0100333 hw_breakpoint_update_all(cpu);
Peter Maydell9ee98ce2014-09-12 14:06:49 +0100334 hw_watchpoint_update_all(cpu);
Andreas Färberdec9c2d2012-03-29 04:50:31 +0000335}
336
Richard Hendersone8925712014-09-13 09:45:25 -0700337bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
338{
339 CPUClass *cc = CPU_GET_CLASS(cs);
Greg Bellows012a9062015-05-29 11:28:51 +0100340 CPUARMState *env = cs->env_ptr;
341 uint32_t cur_el = arm_current_el(env);
342 bool secure = arm_is_secure(env);
343 uint32_t target_el;
344 uint32_t excp_idx;
Richard Hendersone8925712014-09-13 09:45:25 -0700345 bool ret = false;
346
Greg Bellows012a9062015-05-29 11:28:51 +0100347 if (interrupt_request & CPU_INTERRUPT_FIQ) {
348 excp_idx = EXCP_FIQ;
349 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
350 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
351 cs->exception_index = excp_idx;
352 env->exception.target_el = target_el;
353 cc->do_interrupt(cs);
354 ret = true;
355 }
Richard Hendersone8925712014-09-13 09:45:25 -0700356 }
Greg Bellows012a9062015-05-29 11:28:51 +0100357 if (interrupt_request & CPU_INTERRUPT_HARD) {
358 excp_idx = EXCP_IRQ;
359 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
360 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
361 cs->exception_index = excp_idx;
362 env->exception.target_el = target_el;
363 cc->do_interrupt(cs);
364 ret = true;
365 }
Richard Hendersone8925712014-09-13 09:45:25 -0700366 }
Greg Bellows012a9062015-05-29 11:28:51 +0100367 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
368 excp_idx = EXCP_VIRQ;
369 target_el = 1;
370 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
371 cs->exception_index = excp_idx;
372 env->exception.target_el = target_el;
373 cc->do_interrupt(cs);
374 ret = true;
375 }
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +0100376 }
Greg Bellows012a9062015-05-29 11:28:51 +0100377 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
378 excp_idx = EXCP_VFIQ;
379 target_el = 1;
380 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
381 cs->exception_index = excp_idx;
382 env->exception.target_el = target_el;
383 cc->do_interrupt(cs);
384 ret = true;
385 }
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +0100386 }
Richard Hendersone8925712014-09-13 09:45:25 -0700387
388 return ret;
389}
390
Peter Maydellb5c633c2014-10-30 15:48:51 +0000391#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
392static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
393{
394 CPUClass *cc = CPU_GET_CLASS(cs);
395 ARMCPU *cpu = ARM_CPU(cs);
396 CPUARMState *env = &cpu->env;
397 bool ret = false;
398
Peter Maydellf4e8e4e2017-04-20 17:32:31 +0100399 /* ARMv7-M interrupt masking works differently than -A or -R.
Peter Maydell7ecdaa42017-02-28 12:08:17 +0000400 * There is no FIQ/IRQ distinction. Instead of I and F bits
401 * masking FIQ and IRQ interrupts, an exception is taken only
402 * if it is higher priority than the current execution priority
403 * (which depends on state like BASEPRI, FAULTMASK and the
404 * currently active exception).
Peter Maydellb5c633c2014-10-30 15:48:51 +0000405 */
406 if (interrupt_request & CPU_INTERRUPT_HARD
Peter Maydellf4e8e4e2017-04-20 17:32:31 +0100407 && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
Peter Maydellb5c633c2014-10-30 15:48:51 +0000408 cs->exception_index = EXCP_IRQ;
409 cc->do_interrupt(cs);
410 ret = true;
411 }
412 return ret;
413}
414#endif
415
Peter Maydell7c1840b2013-08-20 14:54:28 +0100416#ifndef CONFIG_USER_ONLY
417static void arm_cpu_set_irq(void *opaque, int irq, int level)
418{
419 ARMCPU *cpu = opaque;
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +0100420 CPUARMState *env = &cpu->env;
Peter Maydell7c1840b2013-08-20 14:54:28 +0100421 CPUState *cs = CPU(cpu);
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +0100422 static const int mask[] = {
423 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
424 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
425 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
426 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
427 };
Peter Maydell7c1840b2013-08-20 14:54:28 +0100428
429 switch (irq) {
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +0100430 case ARM_CPU_VIRQ:
431 case ARM_CPU_VFIQ:
Peter Crosthwaitef128bf22015-09-07 10:39:29 +0100432 assert(arm_feature(env, ARM_FEATURE_EL2));
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +0100433 /* fall through */
434 case ARM_CPU_IRQ:
Peter Maydell7c1840b2013-08-20 14:54:28 +0100435 case ARM_CPU_FIQ:
436 if (level) {
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +0100437 cpu_interrupt(cs, mask[irq]);
Peter Maydell7c1840b2013-08-20 14:54:28 +0100438 } else {
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +0100439 cpu_reset_interrupt(cs, mask[irq]);
Peter Maydell7c1840b2013-08-20 14:54:28 +0100440 }
441 break;
442 default:
Peter Crosthwaite8f6fd322015-09-07 10:39:29 +0100443 g_assert_not_reached();
Peter Maydell7c1840b2013-08-20 14:54:28 +0100444 }
445}
446
447static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
448{
449#ifdef CONFIG_KVM
450 ARMCPU *cpu = opaque;
451 CPUState *cs = CPU(cpu);
452 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
453
454 switch (irq) {
455 case ARM_CPU_IRQ:
456 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
457 break;
458 case ARM_CPU_FIQ:
459 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
460 break;
461 default:
Peter Crosthwaite8f6fd322015-09-07 10:39:29 +0100462 g_assert_not_reached();
Peter Maydell7c1840b2013-08-20 14:54:28 +0100463 }
464 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
465 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
466#endif
467}
Pranavkumar Sawargaonkar84f2bed2015-02-05 13:37:25 +0000468
Peter Crosthwaiteed50ff72016-03-04 11:30:19 +0000469static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
Pranavkumar Sawargaonkar84f2bed2015-02-05 13:37:25 +0000470{
471 ARMCPU *cpu = ARM_CPU(cs);
472 CPUARMState *env = &cpu->env;
Pranavkumar Sawargaonkar84f2bed2015-02-05 13:37:25 +0000473
474 cpu_synchronize_state(cs);
Peter Crosthwaiteed50ff72016-03-04 11:30:19 +0000475 return arm_cpu_data_is_big_endian(env);
Pranavkumar Sawargaonkar84f2bed2015-02-05 13:37:25 +0000476}
477
Peter Maydell7c1840b2013-08-20 14:54:28 +0100478#endif
479
Peter Maydell581be092012-04-20 17:58:31 +0000480static inline void set_feature(CPUARMState *env, int feature)
481{
Peter Maydell918f5dc2012-07-12 10:59:06 +0000482 env->features |= 1ULL << feature;
Peter Maydell581be092012-04-20 17:58:31 +0000483}
484
Greg Bellows08828482014-12-15 17:09:45 -0600485static inline void unset_feature(CPUARMState *env, int feature)
486{
487 env->features &= ~(1ULL << feature);
488}
489
Peter Crosthwaite48440622015-06-23 20:57:35 -0700490static int
491print_insn_thumb1(bfd_vma pc, disassemble_info *info)
492{
493 return print_insn_arm(pc | 1, info);
494}
495
496static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
497{
498 ARMCPU *ac = ARM_CPU(cpu);
499 CPUARMState *env = &ac->env;
Richard Henderson7bcdbf52017-10-19 14:13:02 -0700500 bool sctlr_b;
Peter Crosthwaite48440622015-06-23 20:57:35 -0700501
502 if (is_a64(env)) {
503 /* We might not be compiled with the A64 disassembler
504 * because it needs a C++ compiler. Leave print_insn
505 * unset in this case to use the caller default behaviour.
506 */
507#if defined(CONFIG_ARM_A64_DIS)
508 info->print_insn = print_insn_arm_a64;
509#endif
Richard Henderson110f6c72017-09-14 09:51:06 -0700510 info->cap_arch = CS_ARCH_ARM64;
Richard Henderson15fa1a02017-11-07 13:19:18 +0100511 info->cap_insn_unit = 4;
512 info->cap_insn_split = 4;
Peter Crosthwaite48440622015-06-23 20:57:35 -0700513 } else {
Richard Henderson110f6c72017-09-14 09:51:06 -0700514 int cap_mode;
515 if (env->thumb) {
516 info->print_insn = print_insn_thumb1;
Richard Henderson15fa1a02017-11-07 13:19:18 +0100517 info->cap_insn_unit = 2;
518 info->cap_insn_split = 4;
Richard Henderson110f6c72017-09-14 09:51:06 -0700519 cap_mode = CS_MODE_THUMB;
520 } else {
521 info->print_insn = print_insn_arm;
Richard Henderson15fa1a02017-11-07 13:19:18 +0100522 info->cap_insn_unit = 4;
523 info->cap_insn_split = 4;
Richard Henderson110f6c72017-09-14 09:51:06 -0700524 cap_mode = CS_MODE_ARM;
525 }
526 if (arm_feature(env, ARM_FEATURE_V8)) {
527 cap_mode |= CS_MODE_V8;
528 }
529 if (arm_feature(env, ARM_FEATURE_M)) {
530 cap_mode |= CS_MODE_MCLASS;
531 }
532 info->cap_arch = CS_ARCH_ARM;
533 info->cap_mode = cap_mode;
Peter Crosthwaite48440622015-06-23 20:57:35 -0700534 }
Richard Henderson7bcdbf52017-10-19 14:13:02 -0700535
536 sctlr_b = arm_sctlr_b(env);
537 if (bswap_code(sctlr_b)) {
Peter Crosthwaite48440622015-06-23 20:57:35 -0700538#ifdef TARGET_WORDS_BIGENDIAN
539 info->endian = BFD_ENDIAN_LITTLE;
540#else
541 info->endian = BFD_ENDIAN_BIG;
542#endif
543 }
Julian Brownf7478a92017-02-07 18:29:59 +0000544 info->flags &= ~INSN_ARM_BE32;
Richard Henderson7bcdbf52017-10-19 14:13:02 -0700545#ifndef CONFIG_USER_ONLY
546 if (sctlr_b) {
Julian Brownf7478a92017-02-07 18:29:59 +0000547 info->flags |= INSN_ARM_BE32;
548 }
Richard Henderson7bcdbf52017-10-19 14:13:02 -0700549#endif
Peter Crosthwaite48440622015-06-23 20:57:35 -0700550}
551
Igor Mammedov46de5912017-05-03 14:56:56 +0200552uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
553{
554 uint32_t Aff1 = idx / clustersz;
555 uint32_t Aff0 = idx % clustersz;
556 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
557}
558
Peter Maydell777dc782012-04-20 17:58:31 +0000559static void arm_cpu_initfn(Object *obj)
560{
Andreas Färberc05efcb2013-01-17 12:13:41 +0100561 CPUState *cs = CPU(obj);
Peter Maydell777dc782012-04-20 17:58:31 +0000562 ARMCPU *cpu = ARM_CPU(obj);
563
Andreas Färberc05efcb2013-01-17 12:13:41 +0100564 cs->env_ptr = &cpu->env;
Peter Maydell4b6a83f2012-06-20 11:57:06 +0000565 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
566 g_free, g_free);
Andreas Färber79614b72013-01-19 07:37:45 +0100567
Aaron Lindsayb5c53d12018-04-26 11:04:39 +0100568 QLIST_INIT(&cpu->pre_el_change_hooks);
Aaron Lindsay08267482018-04-26 11:04:39 +0100569 QLIST_INIT(&cpu->el_change_hooks);
570
Peter Maydell7c1840b2013-08-20 14:54:28 +0100571#ifndef CONFIG_USER_ONLY
572 /* Our inbound IRQ and FIQ lines */
573 if (kvm_enabled()) {
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +0100574 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
575 * the same interface as non-KVM CPUs.
576 */
577 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
Peter Maydell7c1840b2013-08-20 14:54:28 +0100578 } else {
Edgar E. Iglesias136e67e2014-09-29 18:48:51 +0100579 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
Peter Maydell7c1840b2013-08-20 14:54:28 +0100580 }
Peter Maydell55d284a2013-08-20 14:54:31 +0100581
Alex Blighbc72ad62013-08-21 16:03:08 +0100582 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
Peter Maydell55d284a2013-08-20 14:54:31 +0100583 arm_gt_ptimer_cb, cpu);
Alex Blighbc72ad62013-08-21 16:03:08 +0100584 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
Peter Maydell55d284a2013-08-20 14:54:31 +0100585 arm_gt_vtimer_cb, cpu);
Edgar E. Iglesiasb0e66d92015-08-13 11:26:18 +0100586 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
587 arm_gt_htimer_cb, cpu);
Peter Maydellb4d39782015-08-13 11:26:22 +0100588 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
589 arm_gt_stimer_cb, cpu);
Peter Maydell55d284a2013-08-20 14:54:31 +0100590 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
591 ARRAY_SIZE(cpu->gt_timer_outputs));
Peter Maydellaa1b3112017-01-20 11:15:09 +0000592
593 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
594 "gicv3-maintenance-interrupt", 1);
Andrew Jones07f48732017-09-04 15:21:53 +0100595 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
596 "pmu-interrupt", 1);
Peter Maydell7c1840b2013-08-20 14:54:28 +0100597#endif
598
Peter Maydell54d3e3f2013-11-22 17:17:12 +0000599 /* DTB consumers generally don't in fact care what the 'compatible'
600 * string is, so always provide some string and trust that a hypothetical
601 * picky DTB consumer will also provide a helpful error message.
602 */
603 cpu->dtb_compatible = "qemu,unknown";
Pranavkumar Sawargaonkardd032e32014-06-19 18:06:26 +0100604 cpu->psci_version = 1; /* By default assume PSCI v0.1 */
Peter Maydell3541add2013-11-22 17:17:16 +0000605 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
Peter Maydell54d3e3f2013-11-22 17:17:12 +0000606
Rob Herring98128602014-10-24 12:19:13 +0100607 if (tcg_enabled()) {
608 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
Andreas Färber79614b72013-01-19 07:37:45 +0100609 }
Peter Maydell4b6a83f2012-06-20 11:57:06 +0000610}
611
Peter Crosthwaite07a5b0d2013-12-17 19:42:28 +0000612static Property arm_cpu_reset_cbar_property =
Peter Maydellf318cec2014-04-15 19:18:49 +0100613 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
Peter Crosthwaite07a5b0d2013-12-17 19:42:28 +0000614
Antony Pavlov68e0a402013-12-17 19:42:29 +0000615static Property arm_cpu_reset_hivecs_property =
616 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
617
Peter Maydell39334432014-04-15 19:18:48 +0100618static Property arm_cpu_rvbar_property =
619 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
620
Peter Maydellc25bd182017-01-20 11:15:10 +0000621static Property arm_cpu_has_el2_property =
622 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
623
Greg Bellows51942ae2014-12-15 17:09:46 -0600624static Property arm_cpu_has_el3_property =
625 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
626
Julian Brown3a062d52017-02-07 18:29:59 +0000627static Property arm_cpu_cfgend_property =
628 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
629
Wei Huang929e7542016-10-28 14:12:31 +0100630/* use property name "pmu" to match other archs and virt tools */
631static Property arm_cpu_has_pmu_property =
632 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
633
Peter Crosthwaite8f325f52015-06-15 18:06:10 +0100634static Property arm_cpu_has_mpu_property =
635 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
636
Peter Maydell8d92e262017-07-17 13:36:07 +0100637/* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
638 * because the CPU initfn will have already set cpu->pmsav7_dregion to
639 * the right value for that particular CPU type, and we don't want
640 * to override that with an incorrect constant value.
641 */
Peter Crosthwaite3281af82015-06-19 14:17:44 +0100642static Property arm_cpu_pmsav7_dregion_property =
Peter Maydell8d92e262017-07-17 13:36:07 +0100643 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
644 pmsav7_dregion,
645 qdev_prop_uint32, uint32_t);
Peter Crosthwaite3281af82015-06-19 14:17:44 +0100646
Peter Maydell38e2a772018-03-02 10:45:37 +0000647/* M profile: initial value of the Secure VTOR */
648static Property arm_cpu_initsvtor_property =
649 DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0);
650
Peter Crosthwaite07a5b0d2013-12-17 19:42:28 +0000651static void arm_cpu_post_init(Object *obj)
652{
653 ARMCPU *cpu = ARM_CPU(obj);
Peter Crosthwaite07a5b0d2013-12-17 19:42:28 +0000654
Peter Maydell790a1152017-06-02 11:51:48 +0100655 /* M profile implies PMSA. We have to do this here rather than
656 * in realize with the other feature-implication checks because
657 * we look at the PMSA bit to see if we should add some properties.
658 */
659 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
660 set_feature(&cpu->env, ARM_FEATURE_PMSA);
661 }
662
Peter Maydellf318cec2014-04-15 19:18:49 +0100663 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
664 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
Peter Crosthwaite07a5b0d2013-12-17 19:42:28 +0000665 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
Peter Crosthwaite5433a0a2014-01-01 18:48:08 -0800666 &error_abort);
Peter Crosthwaite07a5b0d2013-12-17 19:42:28 +0000667 }
Antony Pavlov68e0a402013-12-17 19:42:29 +0000668
669 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
670 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
Peter Crosthwaite5433a0a2014-01-01 18:48:08 -0800671 &error_abort);
Antony Pavlov68e0a402013-12-17 19:42:29 +0000672 }
Peter Maydell39334432014-04-15 19:18:48 +0100673
674 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
675 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
676 &error_abort);
677 }
Greg Bellows51942ae2014-12-15 17:09:46 -0600678
679 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
680 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
681 * prevent "has_el3" from existing on CPUs which cannot support EL3.
682 */
683 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
684 &error_abort);
Peter Maydell9e273ef2016-01-21 14:15:06 +0000685
686#ifndef CONFIG_USER_ONLY
687 object_property_add_link(obj, "secure-memory",
688 TYPE_MEMORY_REGION,
689 (Object **)&cpu->secure_memory,
690 qdev_prop_allow_set_link_before_realize,
691 OBJ_PROP_LINK_UNREF_ON_RELEASE,
692 &error_abort);
693#endif
Greg Bellows51942ae2014-12-15 17:09:46 -0600694 }
Peter Crosthwaite8f325f52015-06-15 18:06:10 +0100695
Peter Maydellc25bd182017-01-20 11:15:10 +0000696 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
697 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property,
698 &error_abort);
699 }
700
Wei Huang929e7542016-10-28 14:12:31 +0100701 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
702 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
703 &error_abort);
704 }
705
Peter Maydell452a0952017-06-02 11:51:47 +0100706 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
Peter Crosthwaite8f325f52015-06-15 18:06:10 +0100707 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
708 &error_abort);
Peter Crosthwaite3281af82015-06-19 14:17:44 +0100709 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
710 qdev_property_add_static(DEVICE(obj),
711 &arm_cpu_pmsav7_dregion_property,
712 &error_abort);
713 }
Peter Crosthwaite8f325f52015-06-15 18:06:10 +0100714 }
715
Peter Maydell181962f2018-03-02 10:45:36 +0000716 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
717 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
718 qdev_prop_allow_set_link_before_realize,
719 OBJ_PROP_LINK_UNREF_ON_RELEASE,
720 &error_abort);
Peter Maydell38e2a772018-03-02 10:45:37 +0000721 qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property,
722 &error_abort);
Peter Maydell181962f2018-03-02 10:45:36 +0000723 }
724
Julian Brown3a062d52017-02-07 18:29:59 +0000725 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
726 &error_abort);
Peter Crosthwaite07a5b0d2013-12-17 19:42:28 +0000727}
728
Peter Maydell4b6a83f2012-06-20 11:57:06 +0000729static void arm_cpu_finalizefn(Object *obj)
730{
731 ARMCPU *cpu = ARM_CPU(obj);
Aaron Lindsay08267482018-04-26 11:04:39 +0100732 ARMELChangeHook *hook, *next;
733
Peter Maydell4b6a83f2012-06-20 11:57:06 +0000734 g_hash_table_destroy(cpu->cp_regs);
Aaron Lindsay08267482018-04-26 11:04:39 +0100735
Aaron Lindsayb5c53d12018-04-26 11:04:39 +0100736 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
737 QLIST_REMOVE(hook, node);
738 g_free(hook);
739 }
Aaron Lindsay08267482018-04-26 11:04:39 +0100740 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
741 QLIST_REMOVE(hook, node);
742 g_free(hook);
743 }
Peter Maydell777dc782012-04-20 17:58:31 +0000744}
745
Andreas Färber14969262013-01-05 10:18:18 +0100746static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
Peter Maydell581be092012-04-20 17:58:31 +0000747{
Andreas Färber14a10fc2013-07-27 02:53:25 +0200748 CPUState *cs = CPU(dev);
Andreas Färber14969262013-01-05 10:18:18 +0100749 ARMCPU *cpu = ARM_CPU(dev);
750 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
Peter Maydell581be092012-04-20 17:58:31 +0000751 CPUARMState *env = &cpu->env;
Peter Maydelle97da982016-10-24 16:26:50 +0100752 int pagebits;
Laurent Vivierce5b1bb2016-10-20 13:26:03 +0200753 Error *local_err = NULL;
754
Peter Maydellc4487d72018-03-09 17:09:44 +0000755 /* If we needed to query the host kernel for the CPU features
756 * then it's possible that might have failed in the initfn, but
757 * this is the first point where we can report it.
758 */
759 if (cpu->host_cpu_probe_failed) {
760 if (!kvm_enabled()) {
761 error_setg(errp, "The 'host' CPU type can only be used with KVM");
762 } else {
763 error_setg(errp, "Failed to retrieve host CPU features");
764 }
765 return;
766 }
767
Laurent Vivierce5b1bb2016-10-20 13:26:03 +0200768 cpu_exec_realizefn(cs, &local_err);
769 if (local_err != NULL) {
770 error_propagate(errp, local_err);
771 return;
772 }
Andreas Färber14969262013-01-05 10:18:18 +0100773
Peter Maydell581be092012-04-20 17:58:31 +0000774 /* Some features automatically imply others: */
Mans Rullgard81e69fb2013-07-15 14:35:25 +0100775 if (arm_feature(env, ARM_FEATURE_V8)) {
776 set_feature(env, ARM_FEATURE_V7);
777 set_feature(env, ARM_FEATURE_ARM_DIV);
778 set_feature(env, ARM_FEATURE_LPAE);
779 }
Peter Maydell581be092012-04-20 17:58:31 +0000780 if (arm_feature(env, ARM_FEATURE_V7)) {
781 set_feature(env, ARM_FEATURE_VAPA);
782 set_feature(env, ARM_FEATURE_THUMB2);
Peter Maydell81bdde92012-06-20 11:57:20 +0000783 set_feature(env, ARM_FEATURE_MPIDR);
Peter Maydell581be092012-04-20 17:58:31 +0000784 if (!arm_feature(env, ARM_FEATURE_M)) {
785 set_feature(env, ARM_FEATURE_V6K);
786 } else {
787 set_feature(env, ARM_FEATURE_V6);
788 }
Cédric Le Goater91db4642016-12-27 14:59:30 +0000789
790 /* Always define VBAR for V7 CPUs even if it doesn't exist in
791 * non-EL3 configs. This is needed by some legacy boards.
792 */
793 set_feature(env, ARM_FEATURE_VBAR);
Peter Maydell581be092012-04-20 17:58:31 +0000794 }
795 if (arm_feature(env, ARM_FEATURE_V6K)) {
796 set_feature(env, ARM_FEATURE_V6);
797 set_feature(env, ARM_FEATURE_MVFR);
798 }
799 if (arm_feature(env, ARM_FEATURE_V6)) {
800 set_feature(env, ARM_FEATURE_V5);
Portia Stephensc99a55d2017-09-07 13:54:55 +0100801 set_feature(env, ARM_FEATURE_JAZELLE);
Peter Maydell581be092012-04-20 17:58:31 +0000802 if (!arm_feature(env, ARM_FEATURE_M)) {
803 set_feature(env, ARM_FEATURE_AUXCR);
804 }
805 }
806 if (arm_feature(env, ARM_FEATURE_V5)) {
807 set_feature(env, ARM_FEATURE_V4T);
808 }
809 if (arm_feature(env, ARM_FEATURE_M)) {
810 set_feature(env, ARM_FEATURE_THUMB_DIV);
811 }
812 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
813 set_feature(env, ARM_FEATURE_THUMB_DIV);
814 }
815 if (arm_feature(env, ARM_FEATURE_VFP4)) {
816 set_feature(env, ARM_FEATURE_VFP3);
Peter Maydellda5141f2014-06-09 15:43:25 +0100817 set_feature(env, ARM_FEATURE_VFP_FP16);
Peter Maydell581be092012-04-20 17:58:31 +0000818 }
819 if (arm_feature(env, ARM_FEATURE_VFP3)) {
820 set_feature(env, ARM_FEATURE_VFP);
821 }
Peter Maydellde9b05b2012-07-12 10:59:05 +0000822 if (arm_feature(env, ARM_FEATURE_LPAE)) {
Peter Maydellbdcc1502013-06-25 18:16:08 +0100823 set_feature(env, ARM_FEATURE_V7MP);
Peter Maydellde9b05b2012-07-12 10:59:05 +0000824 set_feature(env, ARM_FEATURE_PXN);
825 }
Peter Maydellf318cec2014-04-15 19:18:49 +0100826 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
827 set_feature(env, ARM_FEATURE_CBAR);
828 }
Aurelio C. Remonda62b44f02015-06-15 18:06:09 +0100829 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
830 !arm_feature(env, ARM_FEATURE_M)) {
831 set_feature(env, ARM_FEATURE_THUMB_DSP);
832 }
Peter Maydell2ceb98c2012-06-20 11:57:09 +0000833
Peter Maydelle97da982016-10-24 16:26:50 +0100834 if (arm_feature(env, ARM_FEATURE_V7) &&
835 !arm_feature(env, ARM_FEATURE_M) &&
Peter Maydell452a0952017-06-02 11:51:47 +0100836 !arm_feature(env, ARM_FEATURE_PMSA)) {
Peter Maydelle97da982016-10-24 16:26:50 +0100837 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
838 * can use 4K pages.
839 */
840 pagebits = 12;
841 } else {
842 /* For CPUs which might have tiny 1K pages, or which have an
843 * MPU and might have small region sizes, stick with 1K pages.
844 */
845 pagebits = 10;
846 }
847 if (!set_preferred_target_page_bits(pagebits)) {
848 /* This can only ever happen for hotplugging a CPU, or if
849 * the board code incorrectly creates a CPU which it has
850 * promised via minimum_page_size that it will not.
851 */
852 error_setg(errp, "This CPU requires a smaller page size than the "
853 "system is using");
854 return;
855 }
856
Laurent Vivierce5b1bb2016-10-20 13:26:03 +0200857 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
858 * We don't support setting cluster ID ([16..23]) (known as Aff2
859 * in later ARM ARM versions), or any of the higher affinity level fields,
860 * so these bits always RAZ.
861 */
862 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
Igor Mammedov46de5912017-05-03 14:56:56 +0200863 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
864 ARM_DEFAULT_CPUS_PER_CLUSTER);
Laurent Vivierce5b1bb2016-10-20 13:26:03 +0200865 }
866
Antony Pavlov68e0a402013-12-17 19:42:29 +0000867 if (cpu->reset_hivecs) {
868 cpu->reset_sctlr |= (1 << 13);
869 }
870
Julian Brown3a062d52017-02-07 18:29:59 +0000871 if (cpu->cfgend) {
872 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
873 cpu->reset_sctlr |= SCTLR_EE;
874 } else {
875 cpu->reset_sctlr |= SCTLR_B;
876 }
877 }
878
Greg Bellows51942ae2014-12-15 17:09:46 -0600879 if (!cpu->has_el3) {
880 /* If the has_el3 CPU property is disabled then we need to disable the
881 * feature.
882 */
883 unset_feature(env, ARM_FEATURE_EL3);
884
885 /* Disable the security extension feature bits in the processor feature
Sergey Fedorov3d5c84f2015-04-26 16:49:26 +0100886 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
Greg Bellows51942ae2014-12-15 17:09:46 -0600887 */
888 cpu->id_pfr1 &= ~0xf0;
Sergey Fedorov3d5c84f2015-04-26 16:49:26 +0100889 cpu->id_aa64pfr0 &= ~0xf000;
Greg Bellows51942ae2014-12-15 17:09:46 -0600890 }
891
Peter Maydellc25bd182017-01-20 11:15:10 +0000892 if (!cpu->has_el2) {
893 unset_feature(env, ARM_FEATURE_EL2);
894 }
895
Wei Huangd6f02ce2017-02-10 17:40:28 +0000896 if (!cpu->has_pmu) {
Wei Huang929e7542016-10-28 14:12:31 +0100897 unset_feature(env, ARM_FEATURE_PMU);
Wei Huang2b3ffa92017-06-02 11:51:47 +0100898 cpu->id_aa64dfr0 &= ~0xf00;
Wei Huang929e7542016-10-28 14:12:31 +0100899 }
900
Peter Maydell3c2f7bb2016-02-02 18:20:42 +0000901 if (!arm_feature(env, ARM_FEATURE_EL2)) {
902 /* Disable the hypervisor feature bits in the processor feature
903 * registers if we don't have EL2. These are id_pfr1[15:12] and
904 * id_aa64pfr0_el1[11:8].
905 */
906 cpu->id_aa64pfr0 &= ~0xf00;
907 cpu->id_pfr1 &= ~0xf000;
908 }
909
Peter Maydellf50cd312017-06-02 11:51:47 +0100910 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
911 * to false or by setting pmsav7-dregion to 0.
912 */
Peter Crosthwaite8f325f52015-06-15 18:06:10 +0100913 if (!cpu->has_mpu) {
Peter Maydellf50cd312017-06-02 11:51:47 +0100914 cpu->pmsav7_dregion = 0;
915 }
916 if (cpu->pmsav7_dregion == 0) {
917 cpu->has_mpu = false;
Peter Crosthwaite8f325f52015-06-15 18:06:10 +0100918 }
919
Peter Maydell452a0952017-06-02 11:51:47 +0100920 if (arm_feature(env, ARM_FEATURE_PMSA) &&
Peter Crosthwaite3281af82015-06-19 14:17:44 +0100921 arm_feature(env, ARM_FEATURE_V7)) {
922 uint32_t nr = cpu->pmsav7_dregion;
923
924 if (nr > 0xff) {
Markus Armbruster9af9e0f2015-12-18 16:35:19 +0100925 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
Peter Crosthwaite3281af82015-06-19 14:17:44 +0100926 return;
927 }
Peter Crosthwaite6cb0b012015-06-19 14:17:44 +0100928
929 if (nr) {
Peter Maydell0e1a46b2017-09-07 13:54:51 +0100930 if (arm_feature(env, ARM_FEATURE_V8)) {
931 /* PMSAv8 */
Peter Maydell62c58ee2017-09-07 13:54:53 +0100932 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
933 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
934 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
935 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
936 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
937 }
Peter Maydell0e1a46b2017-09-07 13:54:51 +0100938 } else {
939 env->pmsav7.drbar = g_new0(uint32_t, nr);
940 env->pmsav7.drsr = g_new0(uint32_t, nr);
941 env->pmsav7.dracr = g_new0(uint32_t, nr);
942 }
Peter Crosthwaite6cb0b012015-06-19 14:17:44 +0100943 }
Peter Crosthwaite3281af82015-06-19 14:17:44 +0100944 }
945
Peter Maydell9901c572017-10-06 16:46:49 +0100946 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
947 uint32_t nr = cpu->sau_sregion;
948
949 if (nr > 0xff) {
950 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
951 return;
952 }
953
954 if (nr) {
955 env->sau.rbar = g_new0(uint32_t, nr);
956 env->sau.rlar = g_new0(uint32_t, nr);
957 }
958 }
959
Cédric Le Goater91db4642016-12-27 14:59:30 +0000960 if (arm_feature(env, ARM_FEATURE_EL3)) {
961 set_feature(env, ARM_FEATURE_VBAR);
962 }
963
Peter Maydell2ceb98c2012-06-20 11:57:09 +0000964 register_cp_regs_for_features(cpu);
Andreas Färber14969262013-01-05 10:18:18 +0100965 arm_cpu_register_gdb_regs_for_features(cpu);
966
Peter Maydell721fae12013-06-25 18:16:07 +0100967 init_cpreg_list(cpu);
968
Peter Maydell9e273ef2016-01-21 14:15:06 +0000969#ifndef CONFIG_USER_ONLY
Peter Maydell1d2091b2017-09-07 13:54:52 +0100970 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
Peter Maydell1d2091b2017-09-07 13:54:52 +0100971 cs->num_ases = 2;
972
Peter Maydell9e273ef2016-01-21 14:15:06 +0000973 if (!cpu->secure_memory) {
974 cpu->secure_memory = cs->memory;
975 }
Peter Xu80ceb072017-11-23 17:23:32 +0800976 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
977 cpu->secure_memory);
Peter Maydell1d2091b2017-09-07 13:54:52 +0100978 } else {
979 cs->num_ases = 1;
Peter Maydell9e273ef2016-01-21 14:15:06 +0000980 }
Peter Xu80ceb072017-11-23 17:23:32 +0800981 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
Alistair Francisf9a69712018-03-09 17:09:43 +0000982
983 /* No core_count specified, default to smp_cpus. */
984 if (cpu->core_count == -1) {
985 cpu->core_count = smp_cpus;
986 }
Peter Maydell9e273ef2016-01-21 14:15:06 +0000987#endif
988
Andreas Färber14a10fc2013-07-27 02:53:25 +0200989 qemu_init_vcpu(cs);
Christoffer Dall00d0f7c2014-05-27 14:37:43 +0200990 cpu_reset(cs);
Andreas Färber14969262013-01-05 10:18:18 +0100991
992 acc->parent_realize(dev, errp);
Peter Maydell581be092012-04-20 17:58:31 +0000993}
994
Andreas Färber5900d6b2013-01-21 16:11:43 +0100995static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
996{
997 ObjectClass *oc;
Andreas Färber51492fd2013-01-27 17:30:10 +0100998 char *typename;
Greg Bellowsfb8d6c22015-02-13 05:46:08 +0000999 char **cpuname;
Peter Maydella0032cc2018-03-09 17:09:44 +00001000 const char *cpunamestr;
Andreas Färber5900d6b2013-01-21 16:11:43 +01001001
Greg Bellowsfb8d6c22015-02-13 05:46:08 +00001002 cpuname = g_strsplit(cpu_model, ",", 1);
Peter Maydella0032cc2018-03-09 17:09:44 +00001003 cpunamestr = cpuname[0];
1004#ifdef CONFIG_USER_ONLY
1005 /* For backwards compatibility usermode emulation allows "-cpu any",
1006 * which has the same semantics as "-cpu max".
1007 */
1008 if (!strcmp(cpunamestr, "any")) {
1009 cpunamestr = "max";
1010 }
1011#endif
1012 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
Andreas Färber51492fd2013-01-27 17:30:10 +01001013 oc = object_class_by_name(typename);
Greg Bellowsfb8d6c22015-02-13 05:46:08 +00001014 g_strfreev(cpuname);
Andreas Färber51492fd2013-01-27 17:30:10 +01001015 g_free(typename);
Andreas Färber245fb542013-01-23 12:32:49 +01001016 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
1017 object_class_is_abstract(oc)) {
Andreas Färber5900d6b2013-01-21 16:11:43 +01001018 return NULL;
1019 }
1020 return oc;
1021}
1022
Peter Maydell15ee7762013-09-03 20:12:08 +01001023/* CPU models. These are not needed for the AArch64 linux-user build. */
1024#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1025
Peter Maydell777dc782012-04-20 17:58:31 +00001026static void arm926_initfn(Object *obj)
1027{
1028 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001029
1030 cpu->dtb_compatible = "arm,arm926";
Peter Maydell581be092012-04-20 17:58:31 +00001031 set_feature(&cpu->env, ARM_FEATURE_V5);
1032 set_feature(&cpu->env, ARM_FEATURE_VFP);
Peter Maydellc4804212012-06-20 11:57:17 +00001033 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1034 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
Portia Stephensc99a55d2017-09-07 13:54:55 +01001035 set_feature(&cpu->env, ARM_FEATURE_JAZELLE);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001036 cpu->midr = 0x41069265;
Peter Maydell325b3ce2012-04-20 17:58:32 +00001037 cpu->reset_fpsid = 0x41011090;
Peter Maydell64e16712012-04-20 17:58:33 +00001038 cpu->ctr = 0x1dd20d2;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001039 cpu->reset_sctlr = 0x00090078;
Peter Maydell777dc782012-04-20 17:58:31 +00001040}
1041
1042static void arm946_initfn(Object *obj)
1043{
1044 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001045
1046 cpu->dtb_compatible = "arm,arm946";
Peter Maydell581be092012-04-20 17:58:31 +00001047 set_feature(&cpu->env, ARM_FEATURE_V5);
Peter Maydell452a0952017-06-02 11:51:47 +01001048 set_feature(&cpu->env, ARM_FEATURE_PMSA);
Peter Maydellc4804212012-06-20 11:57:17 +00001049 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001050 cpu->midr = 0x41059461;
Peter Maydell64e16712012-04-20 17:58:33 +00001051 cpu->ctr = 0x0f004006;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001052 cpu->reset_sctlr = 0x00000078;
Peter Maydell777dc782012-04-20 17:58:31 +00001053}
1054
1055static void arm1026_initfn(Object *obj)
1056{
1057 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001058
1059 cpu->dtb_compatible = "arm,arm1026";
Peter Maydell581be092012-04-20 17:58:31 +00001060 set_feature(&cpu->env, ARM_FEATURE_V5);
1061 set_feature(&cpu->env, ARM_FEATURE_VFP);
1062 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
Peter Maydellc4804212012-06-20 11:57:17 +00001063 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1064 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
Portia Stephensc99a55d2017-09-07 13:54:55 +01001065 set_feature(&cpu->env, ARM_FEATURE_JAZELLE);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001066 cpu->midr = 0x4106a262;
Peter Maydell325b3ce2012-04-20 17:58:32 +00001067 cpu->reset_fpsid = 0x410110a0;
Peter Maydell64e16712012-04-20 17:58:33 +00001068 cpu->ctr = 0x1dd20d2;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001069 cpu->reset_sctlr = 0x00090078;
Peter Maydell2771db22012-06-20 11:57:18 +00001070 cpu->reset_auxcr = 1;
Peter Maydell06d76f32012-06-20 11:57:17 +00001071 {
1072 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1073 ARMCPRegInfo ifar = {
1074 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1075 .access = PL1_RW,
Fabian Aggelerb848ce22014-12-11 12:07:51 +00001076 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
Peter Maydell06d76f32012-06-20 11:57:17 +00001077 .resetvalue = 0
1078 };
1079 define_one_arm_cp_reg(cpu, &ifar);
1080 }
Peter Maydell777dc782012-04-20 17:58:31 +00001081}
1082
1083static void arm1136_r2_initfn(Object *obj)
1084{
1085 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell2e4d7e32012-04-20 17:58:34 +00001086 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1087 * older core than plain "arm1136". In particular this does not
1088 * have the v6K features.
1089 * These ID register values are correct for 1136 but may be wrong
1090 * for 1136_r2 (in particular r0p2 does not actually implement most
1091 * of the ID registers).
1092 */
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001093
1094 cpu->dtb_compatible = "arm,arm1136";
Peter Maydell581be092012-04-20 17:58:31 +00001095 set_feature(&cpu->env, ARM_FEATURE_V6);
1096 set_feature(&cpu->env, ARM_FEATURE_VFP);
Peter Maydellc4804212012-06-20 11:57:17 +00001097 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1098 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1099 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001100 cpu->midr = 0x4107b362;
Peter Maydell325b3ce2012-04-20 17:58:32 +00001101 cpu->reset_fpsid = 0x410120b4;
Peter Maydellbd35c352012-04-20 17:58:32 +00001102 cpu->mvfr0 = 0x11111111;
1103 cpu->mvfr1 = 0x00000000;
Peter Maydell64e16712012-04-20 17:58:33 +00001104 cpu->ctr = 0x1dd20d2;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001105 cpu->reset_sctlr = 0x00050078;
Peter Maydell2e4d7e32012-04-20 17:58:34 +00001106 cpu->id_pfr0 = 0x111;
1107 cpu->id_pfr1 = 0x1;
1108 cpu->id_dfr0 = 0x2;
1109 cpu->id_afr0 = 0x3;
1110 cpu->id_mmfr0 = 0x01130003;
1111 cpu->id_mmfr1 = 0x10030302;
1112 cpu->id_mmfr2 = 0x01222110;
1113 cpu->id_isar0 = 0x00140011;
1114 cpu->id_isar1 = 0x12002111;
1115 cpu->id_isar2 = 0x11231111;
1116 cpu->id_isar3 = 0x01102131;
1117 cpu->id_isar4 = 0x141;
Peter Maydell2771db22012-06-20 11:57:18 +00001118 cpu->reset_auxcr = 7;
Peter Maydell777dc782012-04-20 17:58:31 +00001119}
1120
1121static void arm1136_initfn(Object *obj)
1122{
1123 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001124
1125 cpu->dtb_compatible = "arm,arm1136";
Peter Maydell581be092012-04-20 17:58:31 +00001126 set_feature(&cpu->env, ARM_FEATURE_V6K);
1127 set_feature(&cpu->env, ARM_FEATURE_V6);
1128 set_feature(&cpu->env, ARM_FEATURE_VFP);
Peter Maydellc4804212012-06-20 11:57:17 +00001129 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1130 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1131 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001132 cpu->midr = 0x4117b363;
Peter Maydell325b3ce2012-04-20 17:58:32 +00001133 cpu->reset_fpsid = 0x410120b4;
Peter Maydellbd35c352012-04-20 17:58:32 +00001134 cpu->mvfr0 = 0x11111111;
1135 cpu->mvfr1 = 0x00000000;
Peter Maydell64e16712012-04-20 17:58:33 +00001136 cpu->ctr = 0x1dd20d2;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001137 cpu->reset_sctlr = 0x00050078;
Peter Maydell2e4d7e32012-04-20 17:58:34 +00001138 cpu->id_pfr0 = 0x111;
1139 cpu->id_pfr1 = 0x1;
1140 cpu->id_dfr0 = 0x2;
1141 cpu->id_afr0 = 0x3;
1142 cpu->id_mmfr0 = 0x01130003;
1143 cpu->id_mmfr1 = 0x10030302;
1144 cpu->id_mmfr2 = 0x01222110;
1145 cpu->id_isar0 = 0x00140011;
1146 cpu->id_isar1 = 0x12002111;
1147 cpu->id_isar2 = 0x11231111;
1148 cpu->id_isar3 = 0x01102131;
1149 cpu->id_isar4 = 0x141;
Peter Maydell2771db22012-06-20 11:57:18 +00001150 cpu->reset_auxcr = 7;
Peter Maydell777dc782012-04-20 17:58:31 +00001151}
1152
1153static void arm1176_initfn(Object *obj)
1154{
1155 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001156
1157 cpu->dtb_compatible = "arm,arm1176";
Peter Maydell581be092012-04-20 17:58:31 +00001158 set_feature(&cpu->env, ARM_FEATURE_V6K);
1159 set_feature(&cpu->env, ARM_FEATURE_VFP);
1160 set_feature(&cpu->env, ARM_FEATURE_VAPA);
Peter Maydellc4804212012-06-20 11:57:17 +00001161 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1162 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1163 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
Fabian Aggelerc0ccb022014-12-15 17:09:52 -06001164 set_feature(&cpu->env, ARM_FEATURE_EL3);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001165 cpu->midr = 0x410fb767;
Peter Maydell325b3ce2012-04-20 17:58:32 +00001166 cpu->reset_fpsid = 0x410120b5;
Peter Maydellbd35c352012-04-20 17:58:32 +00001167 cpu->mvfr0 = 0x11111111;
1168 cpu->mvfr1 = 0x00000000;
Peter Maydell64e16712012-04-20 17:58:33 +00001169 cpu->ctr = 0x1dd20d2;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001170 cpu->reset_sctlr = 0x00050078;
Peter Maydell2e4d7e32012-04-20 17:58:34 +00001171 cpu->id_pfr0 = 0x111;
1172 cpu->id_pfr1 = 0x11;
1173 cpu->id_dfr0 = 0x33;
1174 cpu->id_afr0 = 0;
1175 cpu->id_mmfr0 = 0x01130003;
1176 cpu->id_mmfr1 = 0x10030302;
1177 cpu->id_mmfr2 = 0x01222100;
1178 cpu->id_isar0 = 0x0140011;
1179 cpu->id_isar1 = 0x12002111;
1180 cpu->id_isar2 = 0x11231121;
1181 cpu->id_isar3 = 0x01102131;
1182 cpu->id_isar4 = 0x01141;
Peter Maydell2771db22012-06-20 11:57:18 +00001183 cpu->reset_auxcr = 7;
Peter Maydell777dc782012-04-20 17:58:31 +00001184}
1185
1186static void arm11mpcore_initfn(Object *obj)
1187{
1188 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001189
1190 cpu->dtb_compatible = "arm,arm11mpcore";
Peter Maydell581be092012-04-20 17:58:31 +00001191 set_feature(&cpu->env, ARM_FEATURE_V6K);
1192 set_feature(&cpu->env, ARM_FEATURE_VFP);
1193 set_feature(&cpu->env, ARM_FEATURE_VAPA);
Peter Maydell81bdde92012-06-20 11:57:20 +00001194 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
Peter Maydellc4804212012-06-20 11:57:17 +00001195 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001196 cpu->midr = 0x410fb022;
Peter Maydell325b3ce2012-04-20 17:58:32 +00001197 cpu->reset_fpsid = 0x410120b4;
Peter Maydellbd35c352012-04-20 17:58:32 +00001198 cpu->mvfr0 = 0x11111111;
1199 cpu->mvfr1 = 0x00000000;
Peter Maydell200bf592012-06-20 11:57:06 +00001200 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
Peter Maydell2e4d7e32012-04-20 17:58:34 +00001201 cpu->id_pfr0 = 0x111;
1202 cpu->id_pfr1 = 0x1;
1203 cpu->id_dfr0 = 0;
1204 cpu->id_afr0 = 0x2;
1205 cpu->id_mmfr0 = 0x01100103;
1206 cpu->id_mmfr1 = 0x10020302;
1207 cpu->id_mmfr2 = 0x01222000;
1208 cpu->id_isar0 = 0x00100011;
1209 cpu->id_isar1 = 0x12002111;
1210 cpu->id_isar2 = 0x11221011;
1211 cpu->id_isar3 = 0x01102131;
1212 cpu->id_isar4 = 0x141;
Peter Maydell2771db22012-06-20 11:57:18 +00001213 cpu->reset_auxcr = 1;
Peter Maydell777dc782012-04-20 17:58:31 +00001214}
1215
1216static void cortex_m3_initfn(Object *obj)
1217{
1218 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell581be092012-04-20 17:58:31 +00001219 set_feature(&cpu->env, ARM_FEATURE_V7);
1220 set_feature(&cpu->env, ARM_FEATURE_M);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001221 cpu->midr = 0x410fc231;
Peter Maydell8d92e262017-07-17 13:36:07 +01001222 cpu->pmsav7_dregion = 8;
Peter Maydell5a53e2c2018-02-15 18:29:37 +00001223 cpu->id_pfr0 = 0x00000030;
1224 cpu->id_pfr1 = 0x00000200;
1225 cpu->id_dfr0 = 0x00100000;
1226 cpu->id_afr0 = 0x00000000;
1227 cpu->id_mmfr0 = 0x00000030;
1228 cpu->id_mmfr1 = 0x00000000;
1229 cpu->id_mmfr2 = 0x00000000;
1230 cpu->id_mmfr3 = 0x00000000;
1231 cpu->id_isar0 = 0x01141110;
1232 cpu->id_isar1 = 0x02111000;
1233 cpu->id_isar2 = 0x21112231;
1234 cpu->id_isar3 = 0x01111110;
1235 cpu->id_isar4 = 0x01310102;
1236 cpu->id_isar5 = 0x00000000;
Peter Maydell777dc782012-04-20 17:58:31 +00001237}
1238
Aurelio C. Remondaba890a92015-06-19 14:17:44 +01001239static void cortex_m4_initfn(Object *obj)
1240{
1241 ARMCPU *cpu = ARM_CPU(obj);
1242
1243 set_feature(&cpu->env, ARM_FEATURE_V7);
1244 set_feature(&cpu->env, ARM_FEATURE_M);
1245 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1246 cpu->midr = 0x410fc240; /* r0p0 */
Peter Maydell8d92e262017-07-17 13:36:07 +01001247 cpu->pmsav7_dregion = 8;
Peter Maydell5a53e2c2018-02-15 18:29:37 +00001248 cpu->id_pfr0 = 0x00000030;
1249 cpu->id_pfr1 = 0x00000200;
1250 cpu->id_dfr0 = 0x00100000;
1251 cpu->id_afr0 = 0x00000000;
1252 cpu->id_mmfr0 = 0x00000030;
1253 cpu->id_mmfr1 = 0x00000000;
1254 cpu->id_mmfr2 = 0x00000000;
1255 cpu->id_mmfr3 = 0x00000000;
1256 cpu->id_isar0 = 0x01141110;
1257 cpu->id_isar1 = 0x02111000;
1258 cpu->id_isar2 = 0x21112231;
1259 cpu->id_isar3 = 0x01111110;
1260 cpu->id_isar4 = 0x01310102;
1261 cpu->id_isar5 = 0x00000000;
Aurelio C. Remondaba890a92015-06-19 14:17:44 +01001262}
Peter Maydell9901c572017-10-06 16:46:49 +01001263
Peter Maydellc7b26382018-03-02 10:45:37 +00001264static void cortex_m33_initfn(Object *obj)
1265{
1266 ARMCPU *cpu = ARM_CPU(obj);
1267
1268 set_feature(&cpu->env, ARM_FEATURE_V8);
1269 set_feature(&cpu->env, ARM_FEATURE_M);
1270 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
1271 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1272 cpu->midr = 0x410fd213; /* r0p3 */
1273 cpu->pmsav7_dregion = 16;
1274 cpu->sau_sregion = 8;
1275 cpu->id_pfr0 = 0x00000030;
1276 cpu->id_pfr1 = 0x00000210;
1277 cpu->id_dfr0 = 0x00200000;
1278 cpu->id_afr0 = 0x00000000;
1279 cpu->id_mmfr0 = 0x00101F40;
1280 cpu->id_mmfr1 = 0x00000000;
1281 cpu->id_mmfr2 = 0x01000000;
1282 cpu->id_mmfr3 = 0x00000000;
1283 cpu->id_isar0 = 0x01101110;
1284 cpu->id_isar1 = 0x02212000;
1285 cpu->id_isar2 = 0x20232232;
1286 cpu->id_isar3 = 0x01111131;
1287 cpu->id_isar4 = 0x01310132;
1288 cpu->id_isar5 = 0x00000000;
1289 cpu->clidr = 0x00000000;
1290 cpu->ctr = 0x8000c000;
1291}
1292
Andreas Färbere6f010c2013-02-02 12:33:14 +01001293static void arm_v7m_class_init(ObjectClass *oc, void *data)
1294{
Andreas Färbere6f010c2013-02-02 12:33:14 +01001295 CPUClass *cc = CPU_CLASS(oc);
1296
Peter Maydellb5c633c2014-10-30 15:48:51 +00001297#ifndef CONFIG_USER_ONLY
Andreas Färbere6f010c2013-02-02 12:33:14 +01001298 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1299#endif
Peter Maydellb5c633c2014-10-30 15:48:51 +00001300
1301 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
Andreas Färbere6f010c2013-02-02 12:33:14 +01001302}
1303
Peter Crosthwaited6a6b132015-06-19 14:17:45 +01001304static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1305 /* Dummy the TCM region regs for the moment */
1306 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1307 .access = PL1_RW, .type = ARM_CP_CONST },
1308 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1309 .access = PL1_RW, .type = ARM_CP_CONST },
Luc MICHEL95e9a242017-04-28 14:56:32 +02001310 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
1311 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
Peter Crosthwaited6a6b132015-06-19 14:17:45 +01001312 REGINFO_SENTINEL
1313};
1314
1315static void cortex_r5_initfn(Object *obj)
1316{
1317 ARMCPU *cpu = ARM_CPU(obj);
1318
1319 set_feature(&cpu->env, ARM_FEATURE_V7);
1320 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
1321 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1322 set_feature(&cpu->env, ARM_FEATURE_V7MP);
Peter Maydell452a0952017-06-02 11:51:47 +01001323 set_feature(&cpu->env, ARM_FEATURE_PMSA);
Peter Crosthwaited6a6b132015-06-19 14:17:45 +01001324 cpu->midr = 0x411fc153; /* r1p3 */
1325 cpu->id_pfr0 = 0x0131;
1326 cpu->id_pfr1 = 0x001;
1327 cpu->id_dfr0 = 0x010400;
1328 cpu->id_afr0 = 0x0;
1329 cpu->id_mmfr0 = 0x0210030;
1330 cpu->id_mmfr1 = 0x00000000;
1331 cpu->id_mmfr2 = 0x01200000;
1332 cpu->id_mmfr3 = 0x0211;
1333 cpu->id_isar0 = 0x2101111;
1334 cpu->id_isar1 = 0x13112111;
1335 cpu->id_isar2 = 0x21232141;
1336 cpu->id_isar3 = 0x01112131;
1337 cpu->id_isar4 = 0x0010142;
1338 cpu->id_isar5 = 0x0;
1339 cpu->mp_is_up = true;
Peter Maydell8d92e262017-07-17 13:36:07 +01001340 cpu->pmsav7_dregion = 16;
Peter Crosthwaited6a6b132015-06-19 14:17:45 +01001341 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1342}
1343
Peter Maydell34f90522012-06-20 11:57:18 +00001344static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1345 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1346 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1347 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1348 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1349 REGINFO_SENTINEL
1350};
1351
Peter Maydell777dc782012-04-20 17:58:31 +00001352static void cortex_a8_initfn(Object *obj)
1353{
1354 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001355
1356 cpu->dtb_compatible = "arm,cortex-a8";
Peter Maydell581be092012-04-20 17:58:31 +00001357 set_feature(&cpu->env, ARM_FEATURE_V7);
1358 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1359 set_feature(&cpu->env, ARM_FEATURE_NEON);
1360 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
Peter Maydellc4804212012-06-20 11:57:17 +00001361 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
Fabian Aggelerc0ccb022014-12-15 17:09:52 -06001362 set_feature(&cpu->env, ARM_FEATURE_EL3);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001363 cpu->midr = 0x410fc080;
Peter Maydell325b3ce2012-04-20 17:58:32 +00001364 cpu->reset_fpsid = 0x410330c0;
Peter Maydellbd35c352012-04-20 17:58:32 +00001365 cpu->mvfr0 = 0x11110222;
Julian Brown0f194472016-12-27 14:59:23 +00001366 cpu->mvfr1 = 0x00011111;
Peter Maydell64e16712012-04-20 17:58:33 +00001367 cpu->ctr = 0x82048004;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001368 cpu->reset_sctlr = 0x00c50078;
Peter Maydell2e4d7e32012-04-20 17:58:34 +00001369 cpu->id_pfr0 = 0x1031;
1370 cpu->id_pfr1 = 0x11;
1371 cpu->id_dfr0 = 0x400;
1372 cpu->id_afr0 = 0;
1373 cpu->id_mmfr0 = 0x31100003;
1374 cpu->id_mmfr1 = 0x20000000;
1375 cpu->id_mmfr2 = 0x01202000;
1376 cpu->id_mmfr3 = 0x11;
1377 cpu->id_isar0 = 0x00101111;
1378 cpu->id_isar1 = 0x12112111;
1379 cpu->id_isar2 = 0x21232031;
1380 cpu->id_isar3 = 0x11112131;
1381 cpu->id_isar4 = 0x00111142;
Peter Maydell48eb3ae2014-08-19 18:56:25 +01001382 cpu->dbgdidr = 0x15141000;
Peter Maydell85df3782012-04-20 17:58:35 +00001383 cpu->clidr = (1 << 27) | (2 << 24) | 3;
1384 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1385 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1386 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
Peter Maydell2771db22012-06-20 11:57:18 +00001387 cpu->reset_auxcr = 2;
Peter Maydell34f90522012-06-20 11:57:18 +00001388 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
Peter Maydell777dc782012-04-20 17:58:31 +00001389}
1390
Peter Maydell1047b9d2012-06-20 11:57:15 +00001391static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1392 /* power_control should be set to maximum latency. Again,
1393 * default to 0 and set by private hook
1394 */
1395 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1396 .access = PL1_RW, .resetvalue = 0,
1397 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1398 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1399 .access = PL1_RW, .resetvalue = 0,
1400 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1401 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1402 .access = PL1_RW, .resetvalue = 0,
1403 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1404 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1405 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1406 /* TLB lockdown control */
1407 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1408 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1409 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1410 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1411 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1412 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1413 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1414 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1415 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1416 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1417 REGINFO_SENTINEL
1418};
1419
Peter Maydell777dc782012-04-20 17:58:31 +00001420static void cortex_a9_initfn(Object *obj)
1421{
1422 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001423
1424 cpu->dtb_compatible = "arm,cortex-a9";
Peter Maydell581be092012-04-20 17:58:31 +00001425 set_feature(&cpu->env, ARM_FEATURE_V7);
1426 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1427 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1428 set_feature(&cpu->env, ARM_FEATURE_NEON);
1429 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
Fabian Aggelerc0ccb022014-12-15 17:09:52 -06001430 set_feature(&cpu->env, ARM_FEATURE_EL3);
Peter Maydell581be092012-04-20 17:58:31 +00001431 /* Note that A9 supports the MP extensions even for
1432 * A9UP and single-core A9MP (which are both different
1433 * and valid configurations; we don't model A9UP).
1434 */
1435 set_feature(&cpu->env, ARM_FEATURE_V7MP);
Peter Crosthwaited8ba7802013-12-17 19:42:28 +00001436 set_feature(&cpu->env, ARM_FEATURE_CBAR);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001437 cpu->midr = 0x410fc090;
Peter Maydell325b3ce2012-04-20 17:58:32 +00001438 cpu->reset_fpsid = 0x41033090;
Peter Maydellbd35c352012-04-20 17:58:32 +00001439 cpu->mvfr0 = 0x11110222;
1440 cpu->mvfr1 = 0x01111111;
Peter Maydell64e16712012-04-20 17:58:33 +00001441 cpu->ctr = 0x80038003;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001442 cpu->reset_sctlr = 0x00c50078;
Peter Maydell2e4d7e32012-04-20 17:58:34 +00001443 cpu->id_pfr0 = 0x1031;
1444 cpu->id_pfr1 = 0x11;
1445 cpu->id_dfr0 = 0x000;
1446 cpu->id_afr0 = 0;
1447 cpu->id_mmfr0 = 0x00100103;
1448 cpu->id_mmfr1 = 0x20000000;
1449 cpu->id_mmfr2 = 0x01230000;
1450 cpu->id_mmfr3 = 0x00002111;
1451 cpu->id_isar0 = 0x00101111;
1452 cpu->id_isar1 = 0x13112111;
1453 cpu->id_isar2 = 0x21232041;
1454 cpu->id_isar3 = 0x11112131;
1455 cpu->id_isar4 = 0x00111142;
Peter Maydell48eb3ae2014-08-19 18:56:25 +01001456 cpu->dbgdidr = 0x35141000;
Peter Maydell85df3782012-04-20 17:58:35 +00001457 cpu->clidr = (1 << 27) | (1 << 24) | 3;
Peter Crosthwaitef7838b52014-08-19 18:56:27 +01001458 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1459 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
Peter Crosthwaited8ba7802013-12-17 19:42:28 +00001460 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
Peter Maydell777dc782012-04-20 17:58:31 +00001461}
1462
Peter Maydell34f90522012-06-20 11:57:18 +00001463#ifndef CONFIG_USER_ONLY
Peter Maydellc4241c72014-02-20 10:35:54 +00001464static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
Peter Maydell34f90522012-06-20 11:57:18 +00001465{
1466 /* Linux wants the number of processors from here.
1467 * Might as well set the interrupt-controller bit too.
1468 */
Peter Maydellc4241c72014-02-20 10:35:54 +00001469 return ((smp_cpus - 1) << 24) | (1 << 23);
Peter Maydell34f90522012-06-20 11:57:18 +00001470}
1471#endif
1472
1473static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1474#ifndef CONFIG_USER_ONLY
1475 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1476 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1477 .writefn = arm_cp_write_ignore, },
1478#endif
1479 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1480 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1481 REGINFO_SENTINEL
1482};
1483
Andrey Yurovskydcf578e2016-09-22 18:13:05 +01001484static void cortex_a7_initfn(Object *obj)
1485{
1486 ARMCPU *cpu = ARM_CPU(obj);
1487
1488 cpu->dtb_compatible = "arm,cortex-a7";
1489 set_feature(&cpu->env, ARM_FEATURE_V7);
1490 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1491 set_feature(&cpu->env, ARM_FEATURE_NEON);
1492 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1493 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1494 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1495 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1496 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1497 set_feature(&cpu->env, ARM_FEATURE_LPAE);
1498 set_feature(&cpu->env, ARM_FEATURE_EL3);
1499 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
1500 cpu->midr = 0x410fc075;
1501 cpu->reset_fpsid = 0x41023075;
1502 cpu->mvfr0 = 0x10110222;
1503 cpu->mvfr1 = 0x11111111;
1504 cpu->ctr = 0x84448003;
1505 cpu->reset_sctlr = 0x00c50078;
1506 cpu->id_pfr0 = 0x00001131;
1507 cpu->id_pfr1 = 0x00011011;
1508 cpu->id_dfr0 = 0x02010555;
1509 cpu->pmceid0 = 0x00000000;
1510 cpu->pmceid1 = 0x00000000;
1511 cpu->id_afr0 = 0x00000000;
1512 cpu->id_mmfr0 = 0x10101105;
1513 cpu->id_mmfr1 = 0x40000000;
1514 cpu->id_mmfr2 = 0x01240000;
1515 cpu->id_mmfr3 = 0x02102211;
1516 cpu->id_isar0 = 0x01101110;
1517 cpu->id_isar1 = 0x13112111;
1518 cpu->id_isar2 = 0x21232041;
1519 cpu->id_isar3 = 0x11112131;
1520 cpu->id_isar4 = 0x10011142;
1521 cpu->dbgdidr = 0x3515f005;
1522 cpu->clidr = 0x0a200023;
1523 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1524 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1525 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1526 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
1527}
1528
Peter Maydell777dc782012-04-20 17:58:31 +00001529static void cortex_a15_initfn(Object *obj)
1530{
1531 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001532
1533 cpu->dtb_compatible = "arm,cortex-a15";
Peter Maydell581be092012-04-20 17:58:31 +00001534 set_feature(&cpu->env, ARM_FEATURE_V7);
1535 set_feature(&cpu->env, ARM_FEATURE_VFP4);
Peter Maydell581be092012-04-20 17:58:31 +00001536 set_feature(&cpu->env, ARM_FEATURE_NEON);
1537 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1538 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
Peter Maydell581be092012-04-20 17:58:31 +00001539 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
Peter Maydellc4804212012-06-20 11:57:17 +00001540 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
Peter Maydellc29f9a02014-04-15 19:18:49 +01001541 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
Peter Maydellde9b05b2012-07-12 10:59:05 +00001542 set_feature(&cpu->env, ARM_FEATURE_LPAE);
Fabian Aggelerc0ccb022014-12-15 17:09:52 -06001543 set_feature(&cpu->env, ARM_FEATURE_EL3);
Peter Maydell3541add2013-11-22 17:17:16 +00001544 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
Peter Maydellb2d06f92012-06-20 11:57:23 +00001545 cpu->midr = 0x412fc0f1;
Peter Maydell325b3ce2012-04-20 17:58:32 +00001546 cpu->reset_fpsid = 0x410430f0;
Peter Maydellbd35c352012-04-20 17:58:32 +00001547 cpu->mvfr0 = 0x10110222;
1548 cpu->mvfr1 = 0x11111111;
Peter Maydell64e16712012-04-20 17:58:33 +00001549 cpu->ctr = 0x8444c004;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001550 cpu->reset_sctlr = 0x00c50078;
Peter Maydell2e4d7e32012-04-20 17:58:34 +00001551 cpu->id_pfr0 = 0x00001131;
1552 cpu->id_pfr1 = 0x00011011;
1553 cpu->id_dfr0 = 0x02010555;
Alistair Francis4054bfa2016-02-18 14:16:17 +00001554 cpu->pmceid0 = 0x0000000;
1555 cpu->pmceid1 = 0x00000000;
Peter Maydell2e4d7e32012-04-20 17:58:34 +00001556 cpu->id_afr0 = 0x00000000;
1557 cpu->id_mmfr0 = 0x10201105;
1558 cpu->id_mmfr1 = 0x20000000;
1559 cpu->id_mmfr2 = 0x01240000;
1560 cpu->id_mmfr3 = 0x02102211;
1561 cpu->id_isar0 = 0x02101110;
1562 cpu->id_isar1 = 0x13112111;
1563 cpu->id_isar2 = 0x21232041;
1564 cpu->id_isar3 = 0x11112131;
1565 cpu->id_isar4 = 0x10011142;
Peter Maydell48eb3ae2014-08-19 18:56:25 +01001566 cpu->dbgdidr = 0x3515f021;
Peter Maydell85df3782012-04-20 17:58:35 +00001567 cpu->clidr = 0x0a200023;
1568 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1569 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1570 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
Peter Maydell34f90522012-06-20 11:57:18 +00001571 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
Peter Maydell777dc782012-04-20 17:58:31 +00001572}
1573
1574static void ti925t_initfn(Object *obj)
1575{
1576 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell581be092012-04-20 17:58:31 +00001577 set_feature(&cpu->env, ARM_FEATURE_V4T);
1578 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
Peter Maydell777dc782012-04-20 17:58:31 +00001579 cpu->midr = ARM_CPUID_TI925T;
Peter Maydell64e16712012-04-20 17:58:33 +00001580 cpu->ctr = 0x5109149;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001581 cpu->reset_sctlr = 0x00000070;
Peter Maydell777dc782012-04-20 17:58:31 +00001582}
1583
1584static void sa1100_initfn(Object *obj)
1585{
1586 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001587
1588 cpu->dtb_compatible = "intel,sa1100";
Peter Maydell581be092012-04-20 17:58:31 +00001589 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
Peter Maydellc4804212012-06-20 11:57:17 +00001590 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001591 cpu->midr = 0x4401A11B;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001592 cpu->reset_sctlr = 0x00000070;
Peter Maydell777dc782012-04-20 17:58:31 +00001593}
1594
1595static void sa1110_initfn(Object *obj)
1596{
1597 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell581be092012-04-20 17:58:31 +00001598 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
Peter Maydellc4804212012-06-20 11:57:17 +00001599 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001600 cpu->midr = 0x6901B119;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001601 cpu->reset_sctlr = 0x00000070;
Peter Maydell777dc782012-04-20 17:58:31 +00001602}
1603
1604static void pxa250_initfn(Object *obj)
1605{
1606 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001607
1608 cpu->dtb_compatible = "marvell,xscale";
Peter Maydell581be092012-04-20 17:58:31 +00001609 set_feature(&cpu->env, ARM_FEATURE_V5);
1610 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001611 cpu->midr = 0x69052100;
Peter Maydell64e16712012-04-20 17:58:33 +00001612 cpu->ctr = 0xd172172;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001613 cpu->reset_sctlr = 0x00000078;
Peter Maydell777dc782012-04-20 17:58:31 +00001614}
1615
1616static void pxa255_initfn(Object *obj)
1617{
1618 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001619
1620 cpu->dtb_compatible = "marvell,xscale";
Peter Maydell581be092012-04-20 17:58:31 +00001621 set_feature(&cpu->env, ARM_FEATURE_V5);
1622 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001623 cpu->midr = 0x69052d00;
Peter Maydell64e16712012-04-20 17:58:33 +00001624 cpu->ctr = 0xd172172;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001625 cpu->reset_sctlr = 0x00000078;
Peter Maydell777dc782012-04-20 17:58:31 +00001626}
1627
1628static void pxa260_initfn(Object *obj)
1629{
1630 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001631
1632 cpu->dtb_compatible = "marvell,xscale";
Peter Maydell581be092012-04-20 17:58:31 +00001633 set_feature(&cpu->env, ARM_FEATURE_V5);
1634 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001635 cpu->midr = 0x69052903;
Peter Maydell64e16712012-04-20 17:58:33 +00001636 cpu->ctr = 0xd172172;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001637 cpu->reset_sctlr = 0x00000078;
Peter Maydell777dc782012-04-20 17:58:31 +00001638}
1639
1640static void pxa261_initfn(Object *obj)
1641{
1642 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001643
1644 cpu->dtb_compatible = "marvell,xscale";
Peter Maydell581be092012-04-20 17:58:31 +00001645 set_feature(&cpu->env, ARM_FEATURE_V5);
1646 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001647 cpu->midr = 0x69052d05;
Peter Maydell64e16712012-04-20 17:58:33 +00001648 cpu->ctr = 0xd172172;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001649 cpu->reset_sctlr = 0x00000078;
Peter Maydell777dc782012-04-20 17:58:31 +00001650}
1651
1652static void pxa262_initfn(Object *obj)
1653{
1654 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001655
1656 cpu->dtb_compatible = "marvell,xscale";
Peter Maydell581be092012-04-20 17:58:31 +00001657 set_feature(&cpu->env, ARM_FEATURE_V5);
1658 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001659 cpu->midr = 0x69052d06;
Peter Maydell64e16712012-04-20 17:58:33 +00001660 cpu->ctr = 0xd172172;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001661 cpu->reset_sctlr = 0x00000078;
Peter Maydell777dc782012-04-20 17:58:31 +00001662}
1663
1664static void pxa270a0_initfn(Object *obj)
1665{
1666 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001667
1668 cpu->dtb_compatible = "marvell,xscale";
Peter Maydell581be092012-04-20 17:58:31 +00001669 set_feature(&cpu->env, ARM_FEATURE_V5);
1670 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1671 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001672 cpu->midr = 0x69054110;
Peter Maydell64e16712012-04-20 17:58:33 +00001673 cpu->ctr = 0xd172172;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001674 cpu->reset_sctlr = 0x00000078;
Peter Maydell777dc782012-04-20 17:58:31 +00001675}
1676
1677static void pxa270a1_initfn(Object *obj)
1678{
1679 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001680
1681 cpu->dtb_compatible = "marvell,xscale";
Peter Maydell581be092012-04-20 17:58:31 +00001682 set_feature(&cpu->env, ARM_FEATURE_V5);
1683 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1684 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001685 cpu->midr = 0x69054111;
Peter Maydell64e16712012-04-20 17:58:33 +00001686 cpu->ctr = 0xd172172;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001687 cpu->reset_sctlr = 0x00000078;
Peter Maydell777dc782012-04-20 17:58:31 +00001688}
1689
1690static void pxa270b0_initfn(Object *obj)
1691{
1692 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001693
1694 cpu->dtb_compatible = "marvell,xscale";
Peter Maydell581be092012-04-20 17:58:31 +00001695 set_feature(&cpu->env, ARM_FEATURE_V5);
1696 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1697 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001698 cpu->midr = 0x69054112;
Peter Maydell64e16712012-04-20 17:58:33 +00001699 cpu->ctr = 0xd172172;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001700 cpu->reset_sctlr = 0x00000078;
Peter Maydell777dc782012-04-20 17:58:31 +00001701}
1702
1703static void pxa270b1_initfn(Object *obj)
1704{
1705 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001706
1707 cpu->dtb_compatible = "marvell,xscale";
Peter Maydell581be092012-04-20 17:58:31 +00001708 set_feature(&cpu->env, ARM_FEATURE_V5);
1709 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1710 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001711 cpu->midr = 0x69054113;
Peter Maydell64e16712012-04-20 17:58:33 +00001712 cpu->ctr = 0xd172172;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001713 cpu->reset_sctlr = 0x00000078;
Peter Maydell777dc782012-04-20 17:58:31 +00001714}
1715
1716static void pxa270c0_initfn(Object *obj)
1717{
1718 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001719
1720 cpu->dtb_compatible = "marvell,xscale";
Peter Maydell581be092012-04-20 17:58:31 +00001721 set_feature(&cpu->env, ARM_FEATURE_V5);
1722 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1723 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001724 cpu->midr = 0x69054114;
Peter Maydell64e16712012-04-20 17:58:33 +00001725 cpu->ctr = 0xd172172;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001726 cpu->reset_sctlr = 0x00000078;
Peter Maydell777dc782012-04-20 17:58:31 +00001727}
1728
1729static void pxa270c5_initfn(Object *obj)
1730{
1731 ARMCPU *cpu = ARM_CPU(obj);
Peter Maydell54d3e3f2013-11-22 17:17:12 +00001732
1733 cpu->dtb_compatible = "marvell,xscale";
Peter Maydell581be092012-04-20 17:58:31 +00001734 set_feature(&cpu->env, ARM_FEATURE_V5);
1735 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1736 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
Peter Maydellb2d06f92012-06-20 11:57:23 +00001737 cpu->midr = 0x69054117;
Peter Maydell64e16712012-04-20 17:58:33 +00001738 cpu->ctr = 0xd172172;
Peter Maydell0ca7e012012-04-20 17:58:33 +00001739 cpu->reset_sctlr = 0x00000078;
Peter Maydell777dc782012-04-20 17:58:31 +00001740}
1741
Peter Maydellbab52d42018-03-09 17:09:44 +00001742#ifndef TARGET_AARCH64
1743/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
1744 * otherwise, a CPU with as many features enabled as our emulation supports.
1745 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
1746 * this only needs to handle 32 bits.
1747 */
1748static void arm_max_initfn(Object *obj)
1749{
1750 ARMCPU *cpu = ARM_CPU(obj);
1751
1752 if (kvm_enabled()) {
1753 kvm_arm_set_cpu_features_from_host(cpu);
1754 } else {
1755 cortex_a15_initfn(obj);
Peter Maydellf5f6d382013-09-10 19:09:32 +01001756#ifdef CONFIG_USER_ONLY
Peter Maydella0032cc2018-03-09 17:09:44 +00001757 /* We don't set these in system emulation mode for the moment,
1758 * since we don't correctly set the ID registers to advertise them,
1759 */
1760 set_feature(&cpu->env, ARM_FEATURE_V8);
1761 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1762 set_feature(&cpu->env, ARM_FEATURE_NEON);
1763 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1764 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1765 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1766 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1767 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1768 set_feature(&cpu->env, ARM_FEATURE_CRC);
1769 set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
1770 set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
1771#endif
1772 }
Peter Maydell777dc782012-04-20 17:58:31 +00001773}
Peter Maydellf5f6d382013-09-10 19:09:32 +01001774#endif
Peter Maydell777dc782012-04-20 17:58:31 +00001775
Peter Maydell15ee7762013-09-03 20:12:08 +01001776#endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1777
Peter Maydell777dc782012-04-20 17:58:31 +00001778typedef struct ARMCPUInfo {
1779 const char *name;
1780 void (*initfn)(Object *obj);
Andreas Färbere6f010c2013-02-02 12:33:14 +01001781 void (*class_init)(ObjectClass *oc, void *data);
Peter Maydell777dc782012-04-20 17:58:31 +00001782} ARMCPUInfo;
1783
1784static const ARMCPUInfo arm_cpus[] = {
Peter Maydell15ee7762013-09-03 20:12:08 +01001785#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
Peter Maydell777dc782012-04-20 17:58:31 +00001786 { .name = "arm926", .initfn = arm926_initfn },
1787 { .name = "arm946", .initfn = arm946_initfn },
1788 { .name = "arm1026", .initfn = arm1026_initfn },
1789 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1790 * older core than plain "arm1136". In particular this does not
1791 * have the v6K features.
1792 */
1793 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1794 { .name = "arm1136", .initfn = arm1136_initfn },
1795 { .name = "arm1176", .initfn = arm1176_initfn },
1796 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
Andreas Färbere6f010c2013-02-02 12:33:14 +01001797 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1798 .class_init = arm_v7m_class_init },
Aurelio C. Remondaba890a92015-06-19 14:17:44 +01001799 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1800 .class_init = arm_v7m_class_init },
Peter Maydellc7b26382018-03-02 10:45:37 +00001801 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
1802 .class_init = arm_v7m_class_init },
Peter Crosthwaited6a6b132015-06-19 14:17:45 +01001803 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
Andrey Yurovskydcf578e2016-09-22 18:13:05 +01001804 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
Peter Maydell777dc782012-04-20 17:58:31 +00001805 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1806 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1807 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
1808 { .name = "ti925t", .initfn = ti925t_initfn },
1809 { .name = "sa1100", .initfn = sa1100_initfn },
1810 { .name = "sa1110", .initfn = sa1110_initfn },
1811 { .name = "pxa250", .initfn = pxa250_initfn },
1812 { .name = "pxa255", .initfn = pxa255_initfn },
1813 { .name = "pxa260", .initfn = pxa260_initfn },
1814 { .name = "pxa261", .initfn = pxa261_initfn },
1815 { .name = "pxa262", .initfn = pxa262_initfn },
1816 /* "pxa270" is an alias for "pxa270-a0" */
1817 { .name = "pxa270", .initfn = pxa270a0_initfn },
1818 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1819 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1820 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1821 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1822 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1823 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
Peter Maydellbab52d42018-03-09 17:09:44 +00001824#ifndef TARGET_AARCH64
1825 { .name = "max", .initfn = arm_max_initfn },
1826#endif
Peter Maydellf5f6d382013-09-10 19:09:32 +01001827#ifdef CONFIG_USER_ONLY
Peter Maydella0032cc2018-03-09 17:09:44 +00001828 { .name = "any", .initfn = arm_max_initfn },
Peter Maydellf5f6d382013-09-10 19:09:32 +01001829#endif
Peter Maydell15ee7762013-09-03 20:12:08 +01001830#endif
Peter Maydell83e68132014-01-13 10:26:16 +00001831 { .name = NULL }
Peter Maydell777dc782012-04-20 17:58:31 +00001832};
1833
Peter Maydell5de16432013-11-22 17:17:13 +00001834static Property arm_cpu_properties[] = {
1835 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
Rob Herring98128602014-10-24 12:19:13 +01001836 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
Alistair Francis51a9b042014-01-31 14:47:32 +00001837 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
Laurent Vivierce5b1bb2016-10-20 13:26:03 +02001838 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
1839 mp_affinity, ARM64_AFFINITY_INVALID),
Igor Mammedov15f8b142017-05-30 18:24:00 +02001840 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
Alistair Francisf9a69712018-03-09 17:09:43 +00001841 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
Peter Maydell5de16432013-11-22 17:17:13 +00001842 DEFINE_PROP_END_OF_LIST()
1843};
1844
Peter Maydell8c6084b2015-05-29 11:28:51 +01001845#ifdef CONFIG_USER_ONLY
Laurent Vivier98670d42018-01-18 20:38:40 +01001846static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
1847 int rw, int mmu_idx)
Peter Maydell8c6084b2015-05-29 11:28:51 +01001848{
1849 ARMCPU *cpu = ARM_CPU(cs);
1850 CPUARMState *env = &cpu->env;
1851
1852 env->exception.vaddress = address;
1853 if (rw == 2) {
1854 cs->exception_index = EXCP_PREFETCH_ABORT;
1855 } else {
1856 cs->exception_index = EXCP_DATA_ABORT;
1857 }
1858 return 1;
1859}
1860#endif
1861
David Hildenbrandb3820e62015-12-03 13:14:41 +01001862static gchar *arm_gdb_arch_name(CPUState *cs)
1863{
1864 ARMCPU *cpu = ARM_CPU(cs);
1865 CPUARMState *env = &cpu->env;
1866
1867 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1868 return g_strdup("iwmmxt");
1869 }
1870 return g_strdup("arm");
1871}
1872
Andreas Färberdec9c2d2012-03-29 04:50:31 +00001873static void arm_cpu_class_init(ObjectClass *oc, void *data)
1874{
1875 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1876 CPUClass *cc = CPU_CLASS(acc);
Andreas Färber14969262013-01-05 10:18:18 +01001877 DeviceClass *dc = DEVICE_CLASS(oc);
1878
Philippe Mathieu-Daudébf853882018-01-13 23:04:12 -03001879 device_class_set_parent_realize(dc, arm_cpu_realizefn,
1880 &acc->parent_realize);
Peter Maydell5de16432013-11-22 17:17:13 +00001881 dc->props = arm_cpu_properties;
Andreas Färberdec9c2d2012-03-29 04:50:31 +00001882
1883 acc->parent_reset = cc->reset;
1884 cc->reset = arm_cpu_reset;
Andreas Färber5900d6b2013-01-21 16:11:43 +01001885
1886 cc->class_by_name = arm_cpu_class_by_name;
Andreas Färber8c2e1b02013-08-25 18:53:55 +02001887 cc->has_work = arm_cpu_has_work;
Richard Hendersone8925712014-09-13 09:45:25 -07001888 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
Andreas Färber878096e2013-05-27 01:33:50 +02001889 cc->dump_state = arm_cpu_dump_state;
Andreas Färberf45748f2013-06-21 19:09:18 +02001890 cc->set_pc = arm_cpu_set_pc;
Andreas Färber5b50e792013-06-29 04:18:45 +02001891 cc->gdb_read_register = arm_cpu_gdb_read_register;
1892 cc->gdb_write_register = arm_cpu_gdb_write_register;
Andreas Färber75104542013-08-26 03:01:33 +02001893#ifdef CONFIG_USER_ONLY
1894 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1895#else
Rob Herring0adf7d32014-10-24 12:19:12 +01001896 cc->do_interrupt = arm_cpu_do_interrupt;
Andrew Baumann30901472015-12-17 13:37:13 +00001897 cc->do_unaligned_access = arm_cpu_do_unaligned_access;
Peter Maydellc79c0a32017-09-07 13:54:55 +01001898 cc->do_transaction_failed = arm_cpu_do_transaction_failed;
Peter Maydell0faea0c2016-01-21 14:15:07 +00001899 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
Peter Maydell017518c2016-01-21 14:15:06 +00001900 cc->asidx_from_attrs = arm_asidx_from_attrs;
Andreas Färber00b941e2013-06-29 18:55:54 +02001901 cc->vmsd = &vmstate_arm_cpu;
Peter Crosthwaiteed50ff72016-03-04 11:30:19 +00001902 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
Andrew Jonesda2b9142016-01-11 20:56:22 +01001903 cc->write_elf64_note = arm_cpu_write_elf64_note;
1904 cc->write_elf32_note = arm_cpu_write_elf32_note;
Andreas Färber00b941e2013-06-29 18:55:54 +02001905#endif
Andreas Färbera0e372f2013-06-28 23:18:47 +02001906 cc->gdb_num_core_regs = 26;
Andreas Färber5b24c642013-07-07 15:08:22 +02001907 cc->gdb_core_xml_file = "arm-core.xml";
David Hildenbrandb3820e62015-12-03 13:14:41 +01001908 cc->gdb_arch_name = arm_gdb_arch_name;
Peter Maydell2472b6c2014-09-12 19:04:17 +01001909 cc->gdb_stop_before_watchpoint = true;
Peter Maydell3ff6fc92014-09-12 14:06:49 +01001910 cc->debug_excp_handler = arm_debug_excp_handler;
Sergey Fedorov38261212016-02-11 11:17:32 +00001911 cc->debug_check_watchpoint = arm_debug_check_watchpoint;
Julian Brown40612002017-02-07 18:29:59 +00001912#if !defined(CONFIG_USER_ONLY)
1913 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
1914#endif
Peter Crosthwaite48440622015-06-23 20:57:35 -07001915
1916 cc->disas_set_info = arm_disas_set_info;
Richard Henderson74d7fc72017-10-26 15:58:14 +02001917#ifdef CONFIG_TCG
Richard Henderson55c3cee2017-10-15 19:02:42 -07001918 cc->tcg_initialize = arm_translate_init;
Richard Henderson74d7fc72017-10-26 15:58:14 +02001919#endif
Andreas Färberdec9c2d2012-03-29 04:50:31 +00001920}
1921
Peter Maydell86f0a182018-03-09 17:09:44 +00001922#ifdef CONFIG_KVM
1923static void arm_host_initfn(Object *obj)
1924{
1925 ARMCPU *cpu = ARM_CPU(obj);
1926
1927 kvm_arm_set_cpu_features_from_host(cpu);
1928}
1929
1930static const TypeInfo host_arm_cpu_type_info = {
1931 .name = TYPE_ARM_HOST_CPU,
1932#ifdef TARGET_AARCH64
1933 .parent = TYPE_AARCH64_CPU,
1934#else
1935 .parent = TYPE_ARM_CPU,
1936#endif
1937 .instance_init = arm_host_initfn,
1938};
1939
1940#endif
1941
Peter Maydell777dc782012-04-20 17:58:31 +00001942static void cpu_register(const ARMCPUInfo *info)
1943{
1944 TypeInfo type_info = {
Peter Maydell777dc782012-04-20 17:58:31 +00001945 .parent = TYPE_ARM_CPU,
1946 .instance_size = sizeof(ARMCPU),
1947 .instance_init = info->initfn,
1948 .class_size = sizeof(ARMCPUClass),
Andreas Färbere6f010c2013-02-02 12:33:14 +01001949 .class_init = info->class_init,
Peter Maydell777dc782012-04-20 17:58:31 +00001950 };
1951
Andreas Färber51492fd2013-01-27 17:30:10 +01001952 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
Eduardo Habkost918fd082013-01-11 15:21:22 +00001953 type_register(&type_info);
Andreas Färber51492fd2013-01-27 17:30:10 +01001954 g_free((void *)type_info.name);
Peter Maydell777dc782012-04-20 17:58:31 +00001955}
1956
Andreas Färberdec9c2d2012-03-29 04:50:31 +00001957static const TypeInfo arm_cpu_type_info = {
1958 .name = TYPE_ARM_CPU,
1959 .parent = TYPE_CPU,
1960 .instance_size = sizeof(ARMCPU),
Peter Maydell777dc782012-04-20 17:58:31 +00001961 .instance_init = arm_cpu_initfn,
Peter Crosthwaite07a5b0d2013-12-17 19:42:28 +00001962 .instance_post_init = arm_cpu_post_init,
Peter Maydell4b6a83f2012-06-20 11:57:06 +00001963 .instance_finalize = arm_cpu_finalizefn,
Peter Maydell777dc782012-04-20 17:58:31 +00001964 .abstract = true,
Andreas Färberdec9c2d2012-03-29 04:50:31 +00001965 .class_size = sizeof(ARMCPUClass),
1966 .class_init = arm_cpu_class_init,
1967};
1968
Peter Maydell181962f2018-03-02 10:45:36 +00001969static const TypeInfo idau_interface_type_info = {
1970 .name = TYPE_IDAU_INTERFACE,
1971 .parent = TYPE_INTERFACE,
1972 .class_size = sizeof(IDAUInterfaceClass),
1973};
1974
Andreas Färberdec9c2d2012-03-29 04:50:31 +00001975static void arm_cpu_register_types(void)
1976{
Peter Maydell83e68132014-01-13 10:26:16 +00001977 const ARMCPUInfo *info = arm_cpus;
Peter Maydell777dc782012-04-20 17:58:31 +00001978
Andreas Färberdec9c2d2012-03-29 04:50:31 +00001979 type_register_static(&arm_cpu_type_info);
Peter Maydell181962f2018-03-02 10:45:36 +00001980 type_register_static(&idau_interface_type_info);
Peter Maydell83e68132014-01-13 10:26:16 +00001981
1982 while (info->name) {
1983 cpu_register(info);
1984 info++;
Peter Maydell777dc782012-04-20 17:58:31 +00001985 }
Peter Maydell86f0a182018-03-09 17:09:44 +00001986
1987#ifdef CONFIG_KVM
1988 type_register_static(&host_arm_cpu_type_info);
1989#endif
Andreas Färberdec9c2d2012-03-29 04:50:31 +00001990}
1991
1992type_init(arm_cpu_register_types)