blob: 93263f8e065dc540fd09d09c7ca64c95e883bdd0 [file] [log] [blame]
Michael Clarkc7b95172019-01-04 23:23:55 +00001/*
2 * RISC-V Control and Status Registers.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "qemu/osdep.h"
21#include "qemu/log.h"
22#include "cpu.h"
23#include "qemu/main-loop.h"
24#include "exec/exec-all.h"
25
26/* CSR function table */
27static riscv_csr_operations csr_ops[];
28
29/* CSR function table constants */
30enum {
31 CSR_TABLE_SIZE = 0x1000
32};
33
34/* CSR function table public API */
35void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
36{
37 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
38}
39
40void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
41{
42 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
43}
44
Michael Clarka88365c2019-01-04 23:24:14 +000045/* Predicates */
46static int fs(CPURISCVState *env, int csrno)
47{
48#if !defined(CONFIG_USER_ONLY)
LIU Zhiwei8e3a1f12020-07-01 23:24:51 +080049 /* loose check condition for fcsr in vector extension */
50 if ((csrno == CSR_FCSR) && (env->misa & RVV)) {
51 return 0;
52 }
Alistair Francisb345b482019-07-30 16:35:24 -070053 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
Alistair Francis57cb2082020-08-12 12:13:46 -070054 return -RISCV_EXCP_ILLEGAL_INST;
Michael Clarka88365c2019-01-04 23:24:14 +000055 }
56#endif
57 return 0;
58}
59
LIU Zhiwei8e3a1f12020-07-01 23:24:51 +080060static int vs(CPURISCVState *env, int csrno)
61{
62 if (env->misa & RVV) {
63 return 0;
64 }
65 return -1;
66}
67
Michael Clarka88365c2019-01-04 23:24:14 +000068static int ctr(CPURISCVState *env, int csrno)
69{
70#if !defined(CONFIG_USER_ONLY)
Alistair Francis0a13a5b2019-06-17 18:31:22 -070071 CPUState *cs = env_cpu(env);
72 RISCVCPU *cpu = RISCV_CPU(cs);
Alistair Francis0a13a5b2019-06-17 18:31:22 -070073
74 if (!cpu->cfg.ext_counters) {
75 /* The Counters extensions is not enabled */
Alistair Francis57cb2082020-08-12 12:13:46 -070076 return -RISCV_EXCP_ILLEGAL_INST;
Alistair Francis0a13a5b2019-06-17 18:31:22 -070077 }
Alistair Francise39a8322020-08-12 12:13:49 -070078
79 if (riscv_cpu_virt_enabled(env)) {
80 switch (csrno) {
81 case CSR_CYCLE:
82 if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
83 get_field(env->mcounteren, HCOUNTEREN_CY)) {
84 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
85 }
86 break;
87 case CSR_TIME:
88 if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
89 get_field(env->mcounteren, HCOUNTEREN_TM)) {
90 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
91 }
92 break;
93 case CSR_INSTRET:
94 if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
95 get_field(env->mcounteren, HCOUNTEREN_IR)) {
96 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
97 }
98 break;
99 case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
100 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
101 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
102 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
103 }
104 break;
105#if defined(TARGET_RISCV32)
106 case CSR_CYCLEH:
107 if (!get_field(env->hcounteren, HCOUNTEREN_CY) &&
108 get_field(env->mcounteren, HCOUNTEREN_CY)) {
109 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
110 }
111 break;
112 case CSR_TIMEH:
113 if (!get_field(env->hcounteren, HCOUNTEREN_TM) &&
114 get_field(env->mcounteren, HCOUNTEREN_TM)) {
115 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
116 }
117 break;
118 case CSR_INSTRETH:
119 if (!get_field(env->hcounteren, HCOUNTEREN_IR) &&
120 get_field(env->mcounteren, HCOUNTEREN_IR)) {
121 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
122 }
123 break;
124 case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
125 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
126 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
127 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
128 }
129 break;
130#endif
131 }
132 }
Michael Clarka88365c2019-01-04 23:24:14 +0000133#endif
134 return 0;
135}
136
137#if !defined(CONFIG_USER_ONLY)
138static int any(CPURISCVState *env, int csrno)
139{
140 return 0;
141}
142
143static int smode(CPURISCVState *env, int csrno)
144{
145 return -!riscv_has_ext(env, RVS);
146}
147
Alistair Francisff2cc122020-01-31 17:02:04 -0800148static int hmode(CPURISCVState *env, int csrno)
149{
150 if (riscv_has_ext(env, RVS) &&
151 riscv_has_ext(env, RVH)) {
152 /* Hypervisor extension is supported */
153 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
154 env->priv == PRV_M) {
155 return 0;
Alistair Francise39a8322020-08-12 12:13:49 -0700156 } else {
157 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
Alistair Francisff2cc122020-01-31 17:02:04 -0800158 }
159 }
160
Alistair Francis57cb2082020-08-12 12:13:46 -0700161 return -RISCV_EXCP_ILLEGAL_INST;
Alistair Francisff2cc122020-01-31 17:02:04 -0800162}
163
Michael Clarka88365c2019-01-04 23:24:14 +0000164static int pmp(CPURISCVState *env, int csrno)
165{
166 return -!riscv_feature(env, RISCV_FEATURE_PMP);
167}
168#endif
169
Michael Clarkc7b95172019-01-04 23:23:55 +0000170/* User Floating-Point CSRs */
171static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
172{
173#if !defined(CONFIG_USER_ONLY)
Alistair Francisb345b482019-07-30 16:35:24 -0700174 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
Alistair Francis57cb2082020-08-12 12:13:46 -0700175 return -RISCV_EXCP_ILLEGAL_INST;
Michael Clarkc7b95172019-01-04 23:23:55 +0000176 }
177#endif
Michael Clarkfb738832019-01-14 23:58:23 +0000178 *val = riscv_cpu_get_fflags(env);
Michael Clarkc7b95172019-01-04 23:23:55 +0000179 return 0;
180}
181
182static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
183{
184#if !defined(CONFIG_USER_ONLY)
Alistair Francisb345b482019-07-30 16:35:24 -0700185 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
Alistair Francis57cb2082020-08-12 12:13:46 -0700186 return -RISCV_EXCP_ILLEGAL_INST;
Michael Clarkc7b95172019-01-04 23:23:55 +0000187 }
188 env->mstatus |= MSTATUS_FS;
189#endif
Michael Clarkfb738832019-01-14 23:58:23 +0000190 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
Michael Clarkc7b95172019-01-04 23:23:55 +0000191 return 0;
192}
193
194static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
195{
196#if !defined(CONFIG_USER_ONLY)
Alistair Francisb345b482019-07-30 16:35:24 -0700197 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
Alistair Francis57cb2082020-08-12 12:13:46 -0700198 return -RISCV_EXCP_ILLEGAL_INST;
Michael Clarkc7b95172019-01-04 23:23:55 +0000199 }
200#endif
201 *val = env->frm;
202 return 0;
203}
204
205static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
206{
207#if !defined(CONFIG_USER_ONLY)
Alistair Francisb345b482019-07-30 16:35:24 -0700208 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
Alistair Francis57cb2082020-08-12 12:13:46 -0700209 return -RISCV_EXCP_ILLEGAL_INST;
Michael Clarkc7b95172019-01-04 23:23:55 +0000210 }
211 env->mstatus |= MSTATUS_FS;
212#endif
213 env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
214 return 0;
215}
216
217static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
218{
219#if !defined(CONFIG_USER_ONLY)
Alistair Francisb345b482019-07-30 16:35:24 -0700220 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
Alistair Francis57cb2082020-08-12 12:13:46 -0700221 return -RISCV_EXCP_ILLEGAL_INST;
Michael Clarkc7b95172019-01-04 23:23:55 +0000222 }
223#endif
Michael Clarkfb738832019-01-14 23:58:23 +0000224 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
Michael Clarkc7b95172019-01-04 23:23:55 +0000225 | (env->frm << FSR_RD_SHIFT);
LIU Zhiwei8e3a1f12020-07-01 23:24:51 +0800226 if (vs(env, csrno) >= 0) {
227 *val |= (env->vxrm << FSR_VXRM_SHIFT)
228 | (env->vxsat << FSR_VXSAT_SHIFT);
229 }
Michael Clarkc7b95172019-01-04 23:23:55 +0000230 return 0;
231}
232
233static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
234{
235#if !defined(CONFIG_USER_ONLY)
Alistair Francisb345b482019-07-30 16:35:24 -0700236 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
Alistair Francis57cb2082020-08-12 12:13:46 -0700237 return -RISCV_EXCP_ILLEGAL_INST;
Michael Clarkc7b95172019-01-04 23:23:55 +0000238 }
239 env->mstatus |= MSTATUS_FS;
240#endif
241 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
LIU Zhiwei8e3a1f12020-07-01 23:24:51 +0800242 if (vs(env, csrno) >= 0) {
243 env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
244 env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
245 }
Michael Clarkfb738832019-01-14 23:58:23 +0000246 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
Michael Clarkc7b95172019-01-04 23:23:55 +0000247 return 0;
248}
249
LIU Zhiwei8e3a1f12020-07-01 23:24:51 +0800250static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val)
251{
252 *val = env->vtype;
253 return 0;
254}
255
256static int read_vl(CPURISCVState *env, int csrno, target_ulong *val)
257{
258 *val = env->vl;
259 return 0;
260}
261
262static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
263{
264 *val = env->vxrm;
265 return 0;
266}
267
268static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
269{
270 env->vxrm = val;
271 return 0;
272}
273
274static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
275{
276 *val = env->vxsat;
277 return 0;
278}
279
280static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
281{
282 env->vxsat = val;
283 return 0;
284}
285
286static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
287{
288 *val = env->vstart;
289 return 0;
290}
291
292static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
293{
294 env->vstart = val;
295 return 0;
296}
297
Michael Clarkc7b95172019-01-04 23:23:55 +0000298/* User Timers and Counters */
Michael Clarkc7b95172019-01-04 23:23:55 +0000299static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
300{
Michael Clarkc7b95172019-01-04 23:23:55 +0000301#if !defined(CONFIG_USER_ONLY)
Claudio Fontana740b1752020-08-19 13:17:19 +0200302 if (icount_enabled()) {
Claudio Fontana8191d362020-08-31 16:18:34 +0200303 *val = icount_get();
Michael Clarkc7b95172019-01-04 23:23:55 +0000304 } else {
305 *val = cpu_get_host_ticks();
306 }
307#else
308 *val = cpu_get_host_ticks();
309#endif
310 return 0;
311}
312
313#if defined(TARGET_RISCV32)
314static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
315{
Michael Clarkc7b95172019-01-04 23:23:55 +0000316#if !defined(CONFIG_USER_ONLY)
Claudio Fontana740b1752020-08-19 13:17:19 +0200317 if (icount_enabled()) {
Claudio Fontana8191d362020-08-31 16:18:34 +0200318 *val = icount_get() >> 32;
Michael Clarkc7b95172019-01-04 23:23:55 +0000319 } else {
320 *val = cpu_get_host_ticks() >> 32;
321 }
322#else
323 *val = cpu_get_host_ticks() >> 32;
324#endif
325 return 0;
326}
327#endif /* TARGET_RISCV32 */
328
329#if defined(CONFIG_USER_ONLY)
330static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
331{
332 *val = cpu_get_host_ticks();
333 return 0;
334}
335
336#if defined(TARGET_RISCV32)
337static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
338{
339 *val = cpu_get_host_ticks() >> 32;
340 return 0;
341}
342#endif
343
344#else /* CONFIG_USER_ONLY */
345
Anup Patelc6957242020-02-02 19:12:16 +0530346static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
347{
348 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
349
350 if (!env->rdtime_fn) {
Alistair Francis57cb2082020-08-12 12:13:46 -0700351 return -RISCV_EXCP_ILLEGAL_INST;
Anup Patelc6957242020-02-02 19:12:16 +0530352 }
353
Bin Menga47ef6e2020-09-01 09:39:10 +0800354 *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
Anup Patelc6957242020-02-02 19:12:16 +0530355 return 0;
356}
357
358#if defined(TARGET_RISCV32)
359static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
360{
361 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
362
363 if (!env->rdtime_fn) {
Alistair Francis57cb2082020-08-12 12:13:46 -0700364 return -RISCV_EXCP_ILLEGAL_INST;
Anup Patelc6957242020-02-02 19:12:16 +0530365 }
366
Bin Menga47ef6e2020-09-01 09:39:10 +0800367 *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
Anup Patelc6957242020-02-02 19:12:16 +0530368 return 0;
369}
370#endif
371
Michael Clarkc7b95172019-01-04 23:23:55 +0000372/* Machine constants */
373
Alistair Francisff2cc122020-01-31 17:02:04 -0800374#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
375#define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
376#define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
Michael Clarkc7b95172019-01-04 23:23:55 +0000377
Alistair Francisd0e53ce2020-01-31 17:02:17 -0800378static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
379 VS_MODE_INTERRUPTS;
380static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
381 VS_MODE_INTERRUPTS;
Michael Clarkc7b95172019-01-04 23:23:55 +0000382static const target_ulong delegable_excps =
383 (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) |
384 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) |
385 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) |
386 (1ULL << (RISCV_EXCP_BREAKPOINT)) |
387 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) |
388 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) |
389 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) |
390 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) |
391 (1ULL << (RISCV_EXCP_U_ECALL)) |
392 (1ULL << (RISCV_EXCP_S_ECALL)) |
Alistair Francisab67a1d2020-01-31 17:01:46 -0800393 (1ULL << (RISCV_EXCP_VS_ECALL)) |
Michael Clarkc7b95172019-01-04 23:23:55 +0000394 (1ULL << (RISCV_EXCP_M_ECALL)) |
395 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) |
396 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) |
Alistair Francisab67a1d2020-01-31 17:01:46 -0800397 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) |
398 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
399 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
Alistair Francise39a8322020-08-12 12:13:49 -0700400 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
Alistair Francisab67a1d2020-01-31 17:01:46 -0800401 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
Michael Clarkc7b95172019-01-04 23:23:55 +0000402static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
403 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
404 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
Jonathan Behrens087b0512019-05-07 18:36:46 -0400405static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
Alistair Francisff2cc122020-01-31 17:02:04 -0800406static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
Alistair Francis8747c9e2020-01-31 17:02:07 -0800407static const target_ulong vsip_writable_mask = MIP_VSSIP;
Michael Clarkc7b95172019-01-04 23:23:55 +0000408
409#if defined(TARGET_RISCV32)
Michael Clarkc7b95172019-01-04 23:23:55 +0000410static const char valid_vm_1_10[16] = {
411 [VM_1_10_MBARE] = 1,
412 [VM_1_10_SV32] = 1
413};
414#elif defined(TARGET_RISCV64)
Michael Clarkc7b95172019-01-04 23:23:55 +0000415static const char valid_vm_1_10[16] = {
416 [VM_1_10_MBARE] = 1,
417 [VM_1_10_SV39] = 1,
418 [VM_1_10_SV48] = 1,
419 [VM_1_10_SV57] = 1
420};
421#endif /* CONFIG_USER_ONLY */
422
423/* Machine Information Registers */
424static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
425{
426 return *val = 0;
427}
428
429static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val)
430{
431 *val = env->mhartid;
432 return 0;
433}
434
435/* Machine Trap Setup */
436static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
437{
438 *val = env->mstatus;
439 return 0;
440}
441
442static int validate_vm(CPURISCVState *env, target_ulong vm)
443{
Alistair Francis1a9540d2020-05-05 13:04:50 -0700444 return valid_vm_1_10[vm & 0xf];
Michael Clarkc7b95172019-01-04 23:23:55 +0000445}
446
447static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
448{
Yifei Jiang284d6972020-10-26 19:55:25 +0800449 uint64_t mstatus = env->mstatus;
450 uint64_t mask = 0;
Alistair Francisb345b482019-07-30 16:35:24 -0700451 int dirty;
Michael Clarkc7b95172019-01-04 23:23:55 +0000452
453 /* flush tlb on mstatus fields that affect VM */
Alistair Francis1a9540d2020-05-05 13:04:50 -0700454 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
455 MSTATUS_MPRV | MSTATUS_SUM)) {
456 tlb_flush(env_cpu(env));
Michael Clarkc7b95172019-01-04 23:23:55 +0000457 }
Alistair Francis1a9540d2020-05-05 13:04:50 -0700458 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
459 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
460 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
461 MSTATUS_TW;
Alistair Francis1f0419c2019-04-20 02:27:18 +0000462#if defined(TARGET_RISCV64)
Alistair Francis1a9540d2020-05-05 13:04:50 -0700463 /*
Alistair Francis9034e902020-08-12 12:13:27 -0700464 * RV32: MPV and GVA are not in mstatus. The current plan is to
Alistair Francis1a9540d2020-05-05 13:04:50 -0700465 * add them to mstatush. For now, we just don't support it.
466 */
Alistair Francis9034e902020-08-12 12:13:27 -0700467 mask |= MSTATUS_MPV | MSTATUS_GVA;
Alistair Francis1f0419c2019-04-20 02:27:18 +0000468#endif
Michael Clarkc7b95172019-01-04 23:23:55 +0000469
470 mstatus = (mstatus & ~mask) | (val & mask);
471
ShihPo Hung82f01462020-01-14 22:17:33 -0800472 dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
Alistair Francisb345b482019-07-30 16:35:24 -0700473 ((mstatus & MSTATUS_XS) == MSTATUS_XS);
Michael Clarkc7b95172019-01-04 23:23:55 +0000474 mstatus = set_field(mstatus, MSTATUS_SD, dirty);
475 env->mstatus = mstatus;
476
477 return 0;
478}
479
Alistair Francis551fa7e2020-01-31 17:03:05 -0800480#ifdef TARGET_RISCV32
481static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
482{
Yifei Jiang284d6972020-10-26 19:55:25 +0800483 *val = env->mstatus >> 32;
Alistair Francis551fa7e2020-01-31 17:03:05 -0800484 return 0;
485}
486
487static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
488{
Yifei Jiang284d6972020-10-26 19:55:25 +0800489 uint64_t valh = (uint64_t)val << 32;
490 uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
491
492 if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
Alistair Francis551fa7e2020-01-31 17:03:05 -0800493 tlb_flush(env_cpu(env));
494 }
495
Yifei Jiang284d6972020-10-26 19:55:25 +0800496 env->mstatus = (env->mstatus & ~mask) | (valh & mask);
Alistair Francis551fa7e2020-01-31 17:03:05 -0800497
498 return 0;
499}
500#endif
501
Michael Clarkc7b95172019-01-04 23:23:55 +0000502static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
503{
504 *val = env->misa;
505 return 0;
506}
507
Michael Clarkf18637c2019-01-14 23:59:00 +0000508static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
509{
510 if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
511 /* drop write to misa */
512 return 0;
513 }
514
515 /* 'I' or 'E' must be present */
516 if (!(val & (RVI | RVE))) {
517 /* It is not, drop write to misa */
518 return 0;
519 }
520
521 /* 'E' excludes all other extensions */
522 if (val & RVE) {
523 /* when we support 'E' we can do "val = RVE;" however
524 * for now we just drop writes if 'E' is present.
525 */
526 return 0;
527 }
528
529 /* Mask extensions that are not supported by this hart */
530 val &= env->misa_mask;
531
532 /* Mask extensions that are not supported by QEMU */
533 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
534
535 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
536 if ((val & RVD) && !(val & RVF)) {
537 val &= ~RVD;
538 }
539
540 /* Suppress 'C' if next instruction is not aligned
541 * TODO: this should check next_pc
542 */
543 if ((val & RVC) && (GETPC() & ~3) != 0) {
544 val &= ~RVC;
545 }
546
547 /* misa.MXL writes are not supported by QEMU */
548 val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
549
550 /* flush translation cache */
551 if (val != env->misa) {
Richard Henderson3109cd92019-03-22 19:11:37 -0700552 tb_flush(env_cpu(env));
Michael Clarkf18637c2019-01-14 23:59:00 +0000553 }
554
555 env->misa = val;
556
557 return 0;
558}
559
Michael Clarkc7b95172019-01-04 23:23:55 +0000560static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
561{
562 *val = env->medeleg;
563 return 0;
564}
565
566static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val)
567{
568 env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
569 return 0;
570}
571
572static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
573{
574 *val = env->mideleg;
575 return 0;
576}
577
578static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
579{
580 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
Alistair Francis713d8362020-01-31 17:02:15 -0800581 if (riscv_has_ext(env, RVH)) {
582 env->mideleg |= VS_MODE_INTERRUPTS;
583 }
Michael Clarkc7b95172019-01-04 23:23:55 +0000584 return 0;
585}
586
587static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)
588{
589 *val = env->mie;
590 return 0;
591}
592
593static int write_mie(CPURISCVState *env, int csrno, target_ulong val)
594{
595 env->mie = (env->mie & ~all_ints) | (val & all_ints);
596 return 0;
597}
598
599static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
600{
601 *val = env->mtvec;
602 return 0;
603}
604
605static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
606{
607 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
Michael Clarkacbbb942019-03-16 01:21:03 +0000608 if ((val & 3) < 2) {
609 env->mtvec = val;
Michael Clarkc7b95172019-01-04 23:23:55 +0000610 } else {
Michael Clarkacbbb942019-03-16 01:21:03 +0000611 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
Michael Clarkc7b95172019-01-04 23:23:55 +0000612 }
613 return 0;
614}
615
616static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
617{
Michael Clarkc7b95172019-01-04 23:23:55 +0000618 *val = env->mcounteren;
619 return 0;
620}
621
622static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
623{
Michael Clarkc7b95172019-01-04 23:23:55 +0000624 env->mcounteren = val;
625 return 0;
626}
627
Alistair Francis747a43e2019-06-17 18:31:08 -0700628/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
Michael Clarkc7b95172019-01-04 23:23:55 +0000629static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
630{
Alistair Francis1a9540d2020-05-05 13:04:50 -0700631 if (env->priv_ver < PRIV_VERSION_1_11_0) {
Alistair Francis57cb2082020-08-12 12:13:46 -0700632 return -RISCV_EXCP_ILLEGAL_INST;
Michael Clarkc7b95172019-01-04 23:23:55 +0000633 }
634 *val = env->mcounteren;
635 return 0;
636}
637
Alistair Francis747a43e2019-06-17 18:31:08 -0700638/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
Michael Clarkc7b95172019-01-04 23:23:55 +0000639static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
640{
Alistair Francis1a9540d2020-05-05 13:04:50 -0700641 if (env->priv_ver < PRIV_VERSION_1_11_0) {
Alistair Francis57cb2082020-08-12 12:13:46 -0700642 return -RISCV_EXCP_ILLEGAL_INST;
Michael Clarkc7b95172019-01-04 23:23:55 +0000643 }
644 env->mcounteren = val;
645 return 0;
646}
647
Michael Clarkc7b95172019-01-04 23:23:55 +0000648/* Machine Trap Handling */
649static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
650{
651 *val = env->mscratch;
652 return 0;
653}
654
655static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val)
656{
657 env->mscratch = val;
658 return 0;
659}
660
661static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val)
662{
663 *val = env->mepc;
664 return 0;
665}
666
667static int write_mepc(CPURISCVState *env, int csrno, target_ulong val)
668{
669 env->mepc = val;
670 return 0;
671}
672
673static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val)
674{
675 *val = env->mcause;
676 return 0;
677}
678
679static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
680{
681 env->mcause = val;
682 return 0;
683}
684
685static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
686{
687 *val = env->mbadaddr;
688 return 0;
689}
690
691static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
692{
693 env->mbadaddr = val;
694 return 0;
695}
696
Michael Clark71877e22019-01-04 23:24:04 +0000697static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
698 target_ulong new_value, target_ulong write_mask)
Michael Clarkc7b95172019-01-04 23:23:55 +0000699{
Richard Henderson3109cd92019-03-22 19:11:37 -0700700 RISCVCPU *cpu = env_archcpu(env);
Michael Clarke3e70392019-03-16 01:20:20 +0000701 /* Allow software control of delegable interrupts not claimed by hardware */
702 target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
Michael Clark71877e22019-01-04 23:24:04 +0000703 uint32_t old_mip;
Michael Clarkc7b95172019-01-04 23:23:55 +0000704
Michael Clark71877e22019-01-04 23:24:04 +0000705 if (mask) {
Michael Clark71877e22019-01-04 23:24:04 +0000706 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
Michael Clark71877e22019-01-04 23:24:04 +0000707 } else {
Alistair Francis7ec5d302019-10-08 15:04:18 -0700708 old_mip = env->mip;
Michael Clark71877e22019-01-04 23:24:04 +0000709 }
710
711 if (ret_value) {
712 *ret_value = old_mip;
713 }
Michael Clarkc7b95172019-01-04 23:23:55 +0000714
715 return 0;
716}
717
718/* Supervisor Trap Setup */
719static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
720{
Alistair Francis1a9540d2020-05-05 13:04:50 -0700721 target_ulong mask = (sstatus_v1_10_mask);
Michael Clarkc7b95172019-01-04 23:23:55 +0000722 *val = env->mstatus & mask;
723 return 0;
724}
725
726static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
727{
Alistair Francis1a9540d2020-05-05 13:04:50 -0700728 target_ulong mask = (sstatus_v1_10_mask);
Michael Clarkc7b95172019-01-04 23:23:55 +0000729 target_ulong newval = (env->mstatus & ~mask) | (val & mask);
730 return write_mstatus(env, CSR_MSTATUS, newval);
731}
732
733static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
734{
Alistair Francisd0e53ce2020-01-31 17:02:17 -0800735 if (riscv_cpu_virt_enabled(env)) {
736 /* Tell the guest the VS bits, shifted to the S bit locations */
737 *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
738 } else {
739 *val = env->mie & env->mideleg;
740 }
Michael Clarkc7b95172019-01-04 23:23:55 +0000741 return 0;
742}
743
744static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
745{
Alistair Francisd0e53ce2020-01-31 17:02:17 -0800746 target_ulong newval;
747
748 if (riscv_cpu_virt_enabled(env)) {
749 /* Shift the guests S bits to VS */
750 newval = (env->mie & ~VS_MODE_INTERRUPTS) |
751 ((val << 1) & VS_MODE_INTERRUPTS);
752 } else {
753 newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
754 }
755
Michael Clarkc7b95172019-01-04 23:23:55 +0000756 return write_mie(env, CSR_MIE, newval);
757}
758
759static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
760{
761 *val = env->stvec;
762 return 0;
763}
764
765static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
766{
767 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
Michael Clarkacbbb942019-03-16 01:21:03 +0000768 if ((val & 3) < 2) {
769 env->stvec = val;
Michael Clarkc7b95172019-01-04 23:23:55 +0000770 } else {
Michael Clarkacbbb942019-03-16 01:21:03 +0000771 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
Michael Clarkc7b95172019-01-04 23:23:55 +0000772 }
773 return 0;
774}
775
776static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
777{
Michael Clarkc7b95172019-01-04 23:23:55 +0000778 *val = env->scounteren;
779 return 0;
780}
781
782static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
783{
Michael Clarkc7b95172019-01-04 23:23:55 +0000784 env->scounteren = val;
785 return 0;
786}
787
788/* Supervisor Trap Handling */
789static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val)
790{
791 *val = env->sscratch;
792 return 0;
793}
794
795static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val)
796{
797 env->sscratch = val;
798 return 0;
799}
800
801static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val)
802{
803 *val = env->sepc;
804 return 0;
805}
806
807static int write_sepc(CPURISCVState *env, int csrno, target_ulong val)
808{
809 env->sepc = val;
810 return 0;
811}
812
813static int read_scause(CPURISCVState *env, int csrno, target_ulong *val)
814{
815 *val = env->scause;
816 return 0;
817}
818
819static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
820{
821 env->scause = val;
822 return 0;
823}
824
825static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
826{
827 *val = env->sbadaddr;
828 return 0;
829}
830
831static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
832{
833 env->sbadaddr = val;
834 return 0;
835}
836
Michael Clark71877e22019-01-04 23:24:04 +0000837static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
838 target_ulong new_value, target_ulong write_mask)
Michael Clarkc7b95172019-01-04 23:23:55 +0000839{
Alistair Francisa2e9f572020-01-31 17:02:20 -0800840 int ret;
841
842 if (riscv_cpu_virt_enabled(env)) {
843 /* Shift the new values to line up with the VS bits */
844 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
845 (write_mask & sip_writable_mask) << 1 & env->mideleg);
846 ret &= vsip_writable_mask;
847 ret >>= 1;
848 } else {
849 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
Jonathan Behrens087b0512019-05-07 18:36:46 -0400850 write_mask & env->mideleg & sip_writable_mask);
Alistair Francisa2e9f572020-01-31 17:02:20 -0800851 }
852
Jonathan Behrens087b0512019-05-07 18:36:46 -0400853 *ret_value &= env->mideleg;
854 return ret;
Michael Clarkc7b95172019-01-04 23:23:55 +0000855}
856
857/* Supervisor Protection and Translation */
858static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
859{
860 if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
861 *val = 0;
Alistair Francis1a9540d2020-05-05 13:04:50 -0700862 return 0;
Michael Clarkc7b95172019-01-04 23:23:55 +0000863 }
Alistair Francis1a9540d2020-05-05 13:04:50 -0700864
865 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
Alistair Francis57cb2082020-08-12 12:13:46 -0700866 return -RISCV_EXCP_ILLEGAL_INST;
Alistair Francis1a9540d2020-05-05 13:04:50 -0700867 } else {
868 *val = env->satp;
869 }
870
Michael Clarkc7b95172019-01-04 23:23:55 +0000871 return 0;
872}
873
874static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
875{
876 if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
877 return 0;
878 }
Alistair Francis1a9540d2020-05-05 13:04:50 -0700879 if (validate_vm(env, get_field(val, SATP_MODE)) &&
Michael Clarkc7b95172019-01-04 23:23:55 +0000880 ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
881 {
Michael Clark7f2b5ff2019-01-14 23:58:08 +0000882 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
Alistair Francis57cb2082020-08-12 12:13:46 -0700883 return -RISCV_EXCP_ILLEGAL_INST;
Michael Clark7f2b5ff2019-01-14 23:58:08 +0000884 } else {
Xinhao Zhang42281972020-10-30 08:48:15 +0800885 if ((val ^ env->satp) & SATP_ASID) {
Richard Henderson3109cd92019-03-22 19:11:37 -0700886 tlb_flush(env_cpu(env));
Jonathan Behrens1e0d9852019-05-08 13:38:35 -0400887 }
Michael Clark7f2b5ff2019-01-14 23:58:08 +0000888 env->satp = val;
889 }
Michael Clarkc7b95172019-01-04 23:23:55 +0000890 }
891 return 0;
892}
893
Alistair Francisff2cc122020-01-31 17:02:04 -0800894/* Hypervisor Extensions */
895static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
896{
897 *val = env->hstatus;
Alistair Francisf8dc8782020-08-12 12:13:38 -0700898#ifdef TARGET_RISCV64
899 /* We only support 64-bit VSXL */
900 *val = set_field(*val, HSTATUS_VSXL, 2);
901#endif
Alistair Francis30f663b2020-08-12 12:13:41 -0700902 /* We only support little endian */
903 *val = set_field(*val, HSTATUS_VSBE, 0);
Alistair Francisff2cc122020-01-31 17:02:04 -0800904 return 0;
905}
906
907static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
908{
909 env->hstatus = val;
Alistair Francisf8dc8782020-08-12 12:13:38 -0700910#ifdef TARGET_RISCV64
911 if (get_field(val, HSTATUS_VSXL) != 2) {
912 qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
913 }
914#endif
Alistair Francis30f663b2020-08-12 12:13:41 -0700915 if (get_field(val, HSTATUS_VSBE) != 0) {
916 qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
917 }
Alistair Francisff2cc122020-01-31 17:02:04 -0800918 return 0;
919}
920
921static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
922{
923 *val = env->hedeleg;
924 return 0;
925}
926
927static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
928{
929 env->hedeleg = val;
930 return 0;
931}
932
933static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
934{
935 *val = env->hideleg;
936 return 0;
937}
938
939static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
940{
941 env->hideleg = val;
942 return 0;
943}
944
Alistair Francis83028092020-08-12 12:13:44 -0700945static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
946 target_ulong new_value, target_ulong write_mask)
947{
948 int ret = rmw_mip(env, 0, ret_value, new_value,
949 write_mask & hip_writable_mask);
950
951 *ret_value &= hip_writable_mask;
952
953 return ret;
954}
955
Alistair Francisff2cc122020-01-31 17:02:04 -0800956static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
957 target_ulong new_value, target_ulong write_mask)
958{
959 int ret = rmw_mip(env, 0, ret_value, new_value,
960 write_mask & hip_writable_mask);
961
Alistair Francis83028092020-08-12 12:13:44 -0700962 *ret_value &= hip_writable_mask;
963
Alistair Francisff2cc122020-01-31 17:02:04 -0800964 return ret;
965}
966
967static int read_hie(CPURISCVState *env, int csrno, target_ulong *val)
968{
969 *val = env->mie & VS_MODE_INTERRUPTS;
970 return 0;
971}
972
973static int write_hie(CPURISCVState *env, int csrno, target_ulong val)
974{
975 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
976 return write_mie(env, CSR_MIE, newval);
977}
978
979static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val)
980{
981 *val = env->hcounteren;
982 return 0;
983}
984
985static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
986{
987 env->hcounteren = val;
988 return 0;
989}
990
Alistair Francis83028092020-08-12 12:13:44 -0700991static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
992{
993 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
994 return 0;
995}
996
997static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
998{
999 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1000 return 0;
1001}
1002
Alistair Francisff2cc122020-01-31 17:02:04 -08001003static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
1004{
1005 *val = env->htval;
1006 return 0;
1007}
1008
1009static int write_htval(CPURISCVState *env, int csrno, target_ulong val)
1010{
1011 env->htval = val;
1012 return 0;
1013}
1014
1015static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
1016{
1017 *val = env->htinst;
1018 return 0;
1019}
1020
1021static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
1022{
Alistair Francisff2cc122020-01-31 17:02:04 -08001023 return 0;
1024}
1025
Alistair Francis83028092020-08-12 12:13:44 -07001026static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
1027{
1028 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1029 return 0;
1030}
1031
1032static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
1033{
1034 qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1035 return 0;
1036}
1037
Alistair Francisff2cc122020-01-31 17:02:04 -08001038static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
1039{
1040 *val = env->hgatp;
1041 return 0;
1042}
1043
1044static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
1045{
1046 env->hgatp = val;
1047 return 0;
1048}
1049
Anup Patelc6957242020-02-02 19:12:16 +05301050static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
1051{
1052 if (!env->rdtime_fn) {
Alistair Francis57cb2082020-08-12 12:13:46 -07001053 return -RISCV_EXCP_ILLEGAL_INST;
Anup Patelc6957242020-02-02 19:12:16 +05301054 }
1055
1056#if defined(TARGET_RISCV32)
1057 *val = env->htimedelta & 0xffffffff;
1058#else
1059 *val = env->htimedelta;
1060#endif
1061 return 0;
1062}
1063
1064static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
1065{
1066 if (!env->rdtime_fn) {
Alistair Francis57cb2082020-08-12 12:13:46 -07001067 return -RISCV_EXCP_ILLEGAL_INST;
Anup Patelc6957242020-02-02 19:12:16 +05301068 }
1069
1070#if defined(TARGET_RISCV32)
1071 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1072#else
1073 env->htimedelta = val;
1074#endif
1075 return 0;
1076}
1077
1078#if defined(TARGET_RISCV32)
1079static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
1080{
1081 if (!env->rdtime_fn) {
Alistair Francis57cb2082020-08-12 12:13:46 -07001082 return -RISCV_EXCP_ILLEGAL_INST;
Anup Patelc6957242020-02-02 19:12:16 +05301083 }
1084
1085 *val = env->htimedelta >> 32;
1086 return 0;
1087}
1088
1089static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
1090{
1091 if (!env->rdtime_fn) {
Alistair Francis57cb2082020-08-12 12:13:46 -07001092 return -RISCV_EXCP_ILLEGAL_INST;
Anup Patelc6957242020-02-02 19:12:16 +05301093 }
1094
1095 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1096 return 0;
1097}
1098#endif
1099
Alistair Francis8747c9e2020-01-31 17:02:07 -08001100/* Virtual CSR Registers */
1101static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
1102{
1103 *val = env->vsstatus;
1104 return 0;
1105}
1106
1107static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
1108{
Yifei Jiang284d6972020-10-26 19:55:25 +08001109 uint64_t mask = (target_ulong)-1;
1110 env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
Alistair Francis8747c9e2020-01-31 17:02:07 -08001111 return 0;
1112}
1113
1114static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
1115 target_ulong new_value, target_ulong write_mask)
1116{
1117 int ret = rmw_mip(env, 0, ret_value, new_value,
1118 write_mask & env->mideleg & vsip_writable_mask);
1119 return ret;
1120}
1121
1122static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
1123{
1124 *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
1125 return 0;
1126}
1127
1128static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
1129{
1130 target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
1131 return write_mie(env, CSR_MIE, newval);
1132}
1133
1134static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1135{
1136 *val = env->vstvec;
1137 return 0;
1138}
1139
1140static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val)
1141{
1142 env->vstvec = val;
1143 return 0;
1144}
1145
1146static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val)
1147{
1148 *val = env->vsscratch;
1149 return 0;
1150}
1151
1152static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val)
1153{
1154 env->vsscratch = val;
1155 return 0;
1156}
1157
1158static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val)
1159{
1160 *val = env->vsepc;
1161 return 0;
1162}
1163
1164static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val)
1165{
1166 env->vsepc = val;
1167 return 0;
1168}
1169
1170static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val)
1171{
1172 *val = env->vscause;
1173 return 0;
1174}
1175
1176static int write_vscause(CPURISCVState *env, int csrno, target_ulong val)
1177{
1178 env->vscause = val;
1179 return 0;
1180}
1181
1182static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val)
1183{
1184 *val = env->vstval;
1185 return 0;
1186}
1187
1188static int write_vstval(CPURISCVState *env, int csrno, target_ulong val)
1189{
1190 env->vstval = val;
1191 return 0;
1192}
1193
1194static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val)
1195{
1196 *val = env->vsatp;
1197 return 0;
1198}
1199
1200static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val)
1201{
1202 env->vsatp = val;
1203 return 0;
1204}
1205
Alistair Francis34cfb5f2020-01-31 17:02:10 -08001206static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
1207{
1208 *val = env->mtval2;
1209 return 0;
1210}
1211
1212static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
1213{
1214 env->mtval2 = val;
1215 return 0;
1216}
1217
1218static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
1219{
1220 *val = env->mtinst;
1221 return 0;
1222}
1223
1224static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
1225{
1226 env->mtinst = val;
1227 return 0;
1228}
1229
Michael Clarkc7b95172019-01-04 23:23:55 +00001230/* Physical Memory Protection */
1231static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
1232{
1233 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1234 return 0;
1235}
1236
1237static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val)
1238{
1239 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1240 return 0;
1241}
1242
1243static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val)
1244{
1245 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1246 return 0;
1247}
1248
1249static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
1250{
1251 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1252 return 0;
1253}
1254
1255#endif
1256
1257/*
1258 * riscv_csrrw - read and/or update control and status register
1259 *
1260 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0);
1261 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1);
1262 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value);
1263 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value);
1264 */
1265
1266int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
1267 target_ulong new_value, target_ulong write_mask)
1268{
1269 int ret;
1270 target_ulong old_value;
Palmer Dabbelt591bdde2019-06-24 01:59:51 -07001271 RISCVCPU *cpu = env_archcpu(env);
Michael Clarkc7b95172019-01-04 23:23:55 +00001272
1273 /* check privileges and return -1 if check fails */
1274#if !defined(CONFIG_USER_ONLY)
Alistair Francis0a42f4c2020-01-31 17:01:56 -08001275 int effective_priv = env->priv;
Michael Clarkc7b95172019-01-04 23:23:55 +00001276 int read_only = get_field(csrno, 0xC00) == 3;
Alistair Francis0a42f4c2020-01-31 17:01:56 -08001277
1278 if (riscv_has_ext(env, RVH) &&
1279 env->priv == PRV_S &&
1280 !riscv_cpu_virt_enabled(env)) {
1281 /*
1282 * We are in S mode without virtualisation, therefore we are in HS Mode.
1283 * Add 1 to the effective privledge level to allow us to access the
1284 * Hypervisor CSRs.
1285 */
1286 effective_priv++;
Bin Menge6e03dc2019-09-20 07:47:14 -07001287 }
Alistair Francis0a42f4c2020-01-31 17:01:56 -08001288
1289 if ((write_mask && read_only) ||
1290 (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
Alistair Francis57cb2082020-08-12 12:13:46 -07001291 return -RISCV_EXCP_ILLEGAL_INST;
Michael Clarkc7b95172019-01-04 23:23:55 +00001292 }
1293#endif
1294
Palmer Dabbelt591bdde2019-06-24 01:59:51 -07001295 /* ensure the CSR extension is enabled. */
1296 if (!cpu->cfg.ext_icsr) {
Alistair Francis57cb2082020-08-12 12:13:46 -07001297 return -RISCV_EXCP_ILLEGAL_INST;
Palmer Dabbelt591bdde2019-06-24 01:59:51 -07001298 }
1299
Michael Clarka88365c2019-01-04 23:24:14 +00001300 /* check predicate */
Alistair Francise39a8322020-08-12 12:13:49 -07001301 if (!csr_ops[csrno].predicate) {
Alistair Francis57cb2082020-08-12 12:13:46 -07001302 return -RISCV_EXCP_ILLEGAL_INST;
Michael Clarka88365c2019-01-04 23:24:14 +00001303 }
Alistair Francise39a8322020-08-12 12:13:49 -07001304 ret = csr_ops[csrno].predicate(env, csrno);
1305 if (ret < 0) {
1306 return ret;
1307 }
Michael Clarka88365c2019-01-04 23:24:14 +00001308
Michael Clarkc7b95172019-01-04 23:23:55 +00001309 /* execute combined read/write operation if it exists */
1310 if (csr_ops[csrno].op) {
1311 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1312 }
1313
1314 /* if no accessor exists then return failure */
1315 if (!csr_ops[csrno].read) {
Alistair Francis57cb2082020-08-12 12:13:46 -07001316 return -RISCV_EXCP_ILLEGAL_INST;
Michael Clarkc7b95172019-01-04 23:23:55 +00001317 }
1318
1319 /* read old value */
1320 ret = csr_ops[csrno].read(env, csrno, &old_value);
1321 if (ret < 0) {
1322 return ret;
1323 }
1324
1325 /* write value if writable and write mask set, otherwise drop writes */
1326 if (write_mask) {
1327 new_value = (old_value & ~write_mask) | (new_value & write_mask);
1328 if (csr_ops[csrno].write) {
1329 ret = csr_ops[csrno].write(env, csrno, new_value);
1330 if (ret < 0) {
1331 return ret;
1332 }
1333 }
1334 }
1335
1336 /* return old value */
1337 if (ret_value) {
1338 *ret_value = old_value;
1339 }
1340
1341 return 0;
1342}
1343
Jim Wilson753e3fe2019-03-15 03:26:58 -07001344/*
1345 * Debugger support. If not in user mode, set env->debugger before the
1346 * riscv_csrrw call and clear it after the call.
1347 */
1348int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
1349 target_ulong new_value, target_ulong write_mask)
1350{
1351 int ret;
1352#if !defined(CONFIG_USER_ONLY)
1353 env->debugger = true;
1354#endif
1355 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
1356#if !defined(CONFIG_USER_ONLY)
1357 env->debugger = false;
1358#endif
1359 return ret;
1360}
1361
Michael Clarkc7b95172019-01-04 23:23:55 +00001362/* Control and Status Register function table */
1363static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
1364 /* User Floating-Point CSRs */
Michael Clarka88365c2019-01-04 23:24:14 +00001365 [CSR_FFLAGS] = { fs, read_fflags, write_fflags },
1366 [CSR_FRM] = { fs, read_frm, write_frm },
1367 [CSR_FCSR] = { fs, read_fcsr, write_fcsr },
LIU Zhiwei8e3a1f12020-07-01 23:24:51 +08001368 /* Vector CSRs */
1369 [CSR_VSTART] = { vs, read_vstart, write_vstart },
1370 [CSR_VXSAT] = { vs, read_vxsat, write_vxsat },
1371 [CSR_VXRM] = { vs, read_vxrm, write_vxrm },
1372 [CSR_VL] = { vs, read_vl },
1373 [CSR_VTYPE] = { vs, read_vtype },
Michael Clarkc7b95172019-01-04 23:23:55 +00001374 /* User Timers and Counters */
Michael Clarka88365c2019-01-04 23:24:14 +00001375 [CSR_CYCLE] = { ctr, read_instret },
1376 [CSR_INSTRET] = { ctr, read_instret },
Michael Clarkc7b95172019-01-04 23:23:55 +00001377#if defined(TARGET_RISCV32)
Michael Clarka88365c2019-01-04 23:24:14 +00001378 [CSR_CYCLEH] = { ctr, read_instreth },
1379 [CSR_INSTRETH] = { ctr, read_instreth },
Michael Clarkc7b95172019-01-04 23:23:55 +00001380#endif
1381
Anup Patelc6957242020-02-02 19:12:16 +05301382 /* In privileged mode, the monitor will have to emulate TIME CSRs only if
1383 * rdtime callback is not provided by machine/platform emulation */
Michael Clarka88365c2019-01-04 23:24:14 +00001384 [CSR_TIME] = { ctr, read_time },
Michael Clarkc7b95172019-01-04 23:23:55 +00001385#if defined(TARGET_RISCV32)
Michael Clarka88365c2019-01-04 23:24:14 +00001386 [CSR_TIMEH] = { ctr, read_timeh },
Michael Clarkc7b95172019-01-04 23:23:55 +00001387#endif
Michael Clarkc7b95172019-01-04 23:23:55 +00001388
1389#if !defined(CONFIG_USER_ONLY)
1390 /* Machine Timers and Counters */
Michael Clarka88365c2019-01-04 23:24:14 +00001391 [CSR_MCYCLE] = { any, read_instret },
1392 [CSR_MINSTRET] = { any, read_instret },
Michael Clarkc7b95172019-01-04 23:23:55 +00001393#if defined(TARGET_RISCV32)
Michael Clarka88365c2019-01-04 23:24:14 +00001394 [CSR_MCYCLEH] = { any, read_instreth },
1395 [CSR_MINSTRETH] = { any, read_instreth },
Michael Clarkc7b95172019-01-04 23:23:55 +00001396#endif
1397
1398 /* Machine Information Registers */
Michael Clarka88365c2019-01-04 23:24:14 +00001399 [CSR_MVENDORID] = { any, read_zero },
1400 [CSR_MARCHID] = { any, read_zero },
1401 [CSR_MIMPID] = { any, read_zero },
1402 [CSR_MHARTID] = { any, read_mhartid },
Michael Clarkc7b95172019-01-04 23:23:55 +00001403
1404 /* Machine Trap Setup */
Michael Clarka88365c2019-01-04 23:24:14 +00001405 [CSR_MSTATUS] = { any, read_mstatus, write_mstatus },
Michael Clarkf18637c2019-01-14 23:59:00 +00001406 [CSR_MISA] = { any, read_misa, write_misa },
Michael Clarka88365c2019-01-04 23:24:14 +00001407 [CSR_MIDELEG] = { any, read_mideleg, write_mideleg },
1408 [CSR_MEDELEG] = { any, read_medeleg, write_medeleg },
1409 [CSR_MIE] = { any, read_mie, write_mie },
1410 [CSR_MTVEC] = { any, read_mtvec, write_mtvec },
1411 [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren },
Michael Clarkc7b95172019-01-04 23:23:55 +00001412
Alistair Francis551fa7e2020-01-31 17:03:05 -08001413#if defined(TARGET_RISCV32)
1414 [CSR_MSTATUSH] = { any, read_mstatush, write_mstatush },
1415#endif
1416
Michael Clarka88365c2019-01-04 23:24:14 +00001417 [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
Michael Clarkc7b95172019-01-04 23:23:55 +00001418
1419 /* Machine Trap Handling */
Michael Clarka88365c2019-01-04 23:24:14 +00001420 [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch },
1421 [CSR_MEPC] = { any, read_mepc, write_mepc },
1422 [CSR_MCAUSE] = { any, read_mcause, write_mcause },
1423 [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr },
1424 [CSR_MIP] = { any, NULL, NULL, rmw_mip },
Michael Clarkc7b95172019-01-04 23:23:55 +00001425
1426 /* Supervisor Trap Setup */
Michael Clarka88365c2019-01-04 23:24:14 +00001427 [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus },
1428 [CSR_SIE] = { smode, read_sie, write_sie },
1429 [CSR_STVEC] = { smode, read_stvec, write_stvec },
1430 [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren },
Michael Clarkc7b95172019-01-04 23:23:55 +00001431
1432 /* Supervisor Trap Handling */
Michael Clarka88365c2019-01-04 23:24:14 +00001433 [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch },
1434 [CSR_SEPC] = { smode, read_sepc, write_sepc },
1435 [CSR_SCAUSE] = { smode, read_scause, write_scause },
1436 [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr },
1437 [CSR_SIP] = { smode, NULL, NULL, rmw_sip },
Michael Clarkc7b95172019-01-04 23:23:55 +00001438
1439 /* Supervisor Protection and Translation */
Michael Clarka88365c2019-01-04 23:24:14 +00001440 [CSR_SATP] = { smode, read_satp, write_satp },
Michael Clarkc7b95172019-01-04 23:23:55 +00001441
Alistair Francisff2cc122020-01-31 17:02:04 -08001442 [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus },
1443 [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg },
1444 [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg },
Alistair Francis83028092020-08-12 12:13:44 -07001445 [CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip },
Alistair Francisff2cc122020-01-31 17:02:04 -08001446 [CSR_HIP] = { hmode, NULL, NULL, rmw_hip },
1447 [CSR_HIE] = { hmode, read_hie, write_hie },
1448 [CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren },
Alistair Francis83028092020-08-12 12:13:44 -07001449 [CSR_HGEIE] = { hmode, read_hgeie, write_hgeie },
Alistair Francisff2cc122020-01-31 17:02:04 -08001450 [CSR_HTVAL] = { hmode, read_htval, write_htval },
1451 [CSR_HTINST] = { hmode, read_htinst, write_htinst },
Alistair Francis83028092020-08-12 12:13:44 -07001452 [CSR_HGEIP] = { hmode, read_hgeip, write_hgeip },
Alistair Francisff2cc122020-01-31 17:02:04 -08001453 [CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
Anup Patelc6957242020-02-02 19:12:16 +05301454 [CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
1455#if defined(TARGET_RISCV32)
1456 [CSR_HTIMEDELTAH] = { hmode, read_htimedeltah, write_htimedeltah},
1457#endif
Alistair Francisff2cc122020-01-31 17:02:04 -08001458
Alistair Francis8747c9e2020-01-31 17:02:07 -08001459 [CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus },
1460 [CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip },
1461 [CSR_VSIE] = { hmode, read_vsie, write_vsie },
1462 [CSR_VSTVEC] = { hmode, read_vstvec, write_vstvec },
1463 [CSR_VSSCRATCH] = { hmode, read_vsscratch, write_vsscratch },
1464 [CSR_VSEPC] = { hmode, read_vsepc, write_vsepc },
1465 [CSR_VSCAUSE] = { hmode, read_vscause, write_vscause },
1466 [CSR_VSTVAL] = { hmode, read_vstval, write_vstval },
1467 [CSR_VSATP] = { hmode, read_vsatp, write_vsatp },
1468
Alistair Francis34cfb5f2020-01-31 17:02:10 -08001469 [CSR_MTVAL2] = { hmode, read_mtval2, write_mtval2 },
1470 [CSR_MTINST] = { hmode, read_mtinst, write_mtinst },
1471
Michael Clarkc7b95172019-01-04 23:23:55 +00001472 /* Physical Memory Protection */
Zong Li8ba26b02020-07-21 20:40:50 +08001473 [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg },
Michael Clarka88365c2019-01-04 23:24:14 +00001474 [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
Michael Clarkc7b95172019-01-04 23:23:55 +00001475
1476 /* Performance Counters */
Michael Clarka88365c2019-01-04 23:24:14 +00001477 [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
1478 [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
1479 [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero },
Michael Clarkc7b95172019-01-04 23:23:55 +00001480#if defined(TARGET_RISCV32)
Michael Clarka88365c2019-01-04 23:24:14 +00001481 [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero },
1482 [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero },
Michael Clarkc7b95172019-01-04 23:23:55 +00001483#endif
1484#endif /* !CONFIG_USER_ONLY */
1485};