bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 1 | /* |
| 2 | * MIPS emulation helpers for qemu. |
| 3 | * |
| 4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
| 5 | * |
| 6 | * This library is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU Lesser General Public |
| 8 | * License as published by the Free Software Foundation; either |
| 9 | * version 2 of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This library is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | * Lesser General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU Lesser General Public |
| 17 | * License along with this library; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | */ |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 20 | #include "exec.h" |
| 21 | |
| 22 | #define MIPS_DEBUG_DISAS |
| 23 | |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 24 | #define GETPC() (__builtin_return_address(0)) |
| 25 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 26 | /*****************************************************************************/ |
| 27 | /* Exceptions processing helpers */ |
| 28 | void cpu_loop_exit(void) |
| 29 | { |
| 30 | longjmp(env->jmp_env, 1); |
| 31 | } |
| 32 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 33 | void do_raise_exception_err (uint32_t exception, int error_code) |
| 34 | { |
| 35 | #if 1 |
| 36 | if (logfile && exception < 0x100) |
| 37 | fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code); |
| 38 | #endif |
| 39 | env->exception_index = exception; |
| 40 | env->error_code = error_code; |
| 41 | T0 = 0; |
| 42 | cpu_loop_exit(); |
| 43 | } |
| 44 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 45 | void do_raise_exception (uint32_t exception) |
| 46 | { |
| 47 | do_raise_exception_err(exception, 0); |
| 48 | } |
| 49 | |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 50 | void do_restore_state (void *pc_ptr) |
| 51 | { |
| 52 | TranslationBlock *tb; |
| 53 | unsigned long pc = (unsigned long) pc_ptr; |
| 54 | |
| 55 | tb = tb_find_pc (pc); |
| 56 | cpu_restore_state (tb, env, pc, NULL); |
| 57 | } |
| 58 | |
| 59 | void do_raise_exception_direct (uint32_t exception) |
| 60 | { |
| 61 | do_restore_state (GETPC ()); |
| 62 | do_raise_exception_err (exception, 0); |
| 63 | } |
| 64 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 65 | #define MEMSUFFIX _raw |
| 66 | #include "op_helper_mem.c" |
| 67 | #undef MEMSUFFIX |
| 68 | #if !defined(CONFIG_USER_ONLY) |
| 69 | #define MEMSUFFIX _user |
| 70 | #include "op_helper_mem.c" |
| 71 | #undef MEMSUFFIX |
| 72 | #define MEMSUFFIX _kernel |
| 73 | #include "op_helper_mem.c" |
| 74 | #undef MEMSUFFIX |
| 75 | #endif |
| 76 | |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 77 | #ifdef MIPS_HAS_MIPS64 |
| 78 | #if TARGET_LONG_BITS > HOST_LONG_BITS |
| 79 | /* Those might call libgcc functions. */ |
| 80 | void do_dsll (void) |
| 81 | { |
| 82 | T0 = T0 << T1; |
| 83 | } |
| 84 | |
| 85 | void do_dsll32 (void) |
| 86 | { |
| 87 | T0 = T0 << (T1 + 32); |
| 88 | } |
| 89 | |
| 90 | void do_dsra (void) |
| 91 | { |
| 92 | T0 = (int64_t)T0 >> T1; |
| 93 | } |
| 94 | |
| 95 | void do_dsra32 (void) |
| 96 | { |
| 97 | T0 = (int64_t)T0 >> (T1 + 32); |
| 98 | } |
| 99 | |
| 100 | void do_dsrl (void) |
| 101 | { |
| 102 | T0 = T0 >> T1; |
| 103 | } |
| 104 | |
| 105 | void do_dsrl32 (void) |
| 106 | { |
| 107 | T0 = T0 >> (T1 + 32); |
| 108 | } |
| 109 | |
| 110 | void do_drotr (void) |
| 111 | { |
| 112 | target_ulong tmp; |
| 113 | |
| 114 | if (T1) { |
| 115 | tmp = T0 << (0x40 - T1); |
| 116 | T0 = (T0 >> T1) | tmp; |
| 117 | } else |
| 118 | T0 = T1; |
| 119 | } |
| 120 | |
| 121 | void do_drotr32 (void) |
| 122 | { |
| 123 | target_ulong tmp; |
| 124 | |
| 125 | if (T1) { |
| 126 | tmp = T0 << (0x40 - (32 + T1)); |
| 127 | T0 = (T0 >> (32 + T1)) | tmp; |
| 128 | } else |
| 129 | T0 = T1; |
| 130 | } |
| 131 | |
| 132 | void do_dsllv (void) |
| 133 | { |
| 134 | T0 = T1 << (T0 & 0x3F); |
| 135 | } |
| 136 | |
| 137 | void do_dsrav (void) |
| 138 | { |
| 139 | T0 = (int64_t)T1 >> (T0 & 0x3F); |
| 140 | } |
| 141 | |
| 142 | void do_dsrlv (void) |
| 143 | { |
| 144 | T0 = T1 >> (T0 & 0x3F); |
| 145 | } |
| 146 | |
| 147 | void do_drotrv (void) |
| 148 | { |
| 149 | target_ulong tmp; |
| 150 | |
| 151 | T0 &= 0x3F; |
| 152 | if (T0) { |
| 153 | tmp = T1 << (0x40 - T0); |
| 154 | T0 = (T1 >> T0) | tmp; |
| 155 | } else |
| 156 | T0 = T1; |
| 157 | } |
| 158 | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
| 159 | #endif /* MIPS_HAS_MIPS64 */ |
| 160 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 161 | /* 64 bits arithmetic for 32 bits hosts */ |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 162 | #if TARGET_LONG_BITS > HOST_LONG_BITS |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 163 | static inline uint64_t get_HILO (void) |
| 164 | { |
ths | 7495fd0 | 2007-01-01 20:32:08 +0000 | [diff] [blame] | 165 | return (env->HI << 32) | (uint32_t)env->LO; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 166 | } |
| 167 | |
| 168 | static inline void set_HILO (uint64_t HILO) |
| 169 | { |
ths | 7495fd0 | 2007-01-01 20:32:08 +0000 | [diff] [blame] | 170 | env->LO = (int32_t)HILO; |
ths | 5dc4b74 | 2006-12-21 13:48:28 +0000 | [diff] [blame] | 171 | env->HI = (int32_t)(HILO >> 32); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | void do_mult (void) |
| 175 | { |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 176 | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | void do_multu (void) |
| 180 | { |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 181 | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 182 | } |
| 183 | |
| 184 | void do_madd (void) |
| 185 | { |
| 186 | int64_t tmp; |
| 187 | |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 188 | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 189 | set_HILO((int64_t)get_HILO() + tmp); |
| 190 | } |
| 191 | |
| 192 | void do_maddu (void) |
| 193 | { |
| 194 | uint64_t tmp; |
| 195 | |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 196 | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 197 | set_HILO(get_HILO() + tmp); |
| 198 | } |
| 199 | |
| 200 | void do_msub (void) |
| 201 | { |
| 202 | int64_t tmp; |
| 203 | |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 204 | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 205 | set_HILO((int64_t)get_HILO() - tmp); |
| 206 | } |
| 207 | |
| 208 | void do_msubu (void) |
| 209 | { |
| 210 | uint64_t tmp; |
| 211 | |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 212 | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 213 | set_HILO(get_HILO() - tmp); |
| 214 | } |
| 215 | #endif |
| 216 | |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 217 | #ifdef MIPS_HAS_MIPS64 |
| 218 | void do_dmult (void) |
| 219 | { |
| 220 | /* XXX */ |
| 221 | set_HILO((int64_t)T0 * (int64_t)T1); |
| 222 | } |
| 223 | |
| 224 | void do_dmultu (void) |
| 225 | { |
| 226 | /* XXX */ |
| 227 | set_HILO((uint64_t)T0 * (uint64_t)T1); |
| 228 | } |
| 229 | |
| 230 | void do_ddiv (void) |
| 231 | { |
| 232 | if (T1 != 0) { |
| 233 | env->LO = (int64_t)T0 / (int64_t)T1; |
| 234 | env->HI = (int64_t)T0 % (int64_t)T1; |
| 235 | } |
| 236 | } |
| 237 | |
| 238 | void do_ddivu (void) |
| 239 | { |
| 240 | if (T1 != 0) { |
| 241 | env->LO = T0 / T1; |
| 242 | env->HI = T0 % T1; |
| 243 | } |
| 244 | } |
| 245 | #endif |
| 246 | |
bellard | 048f6b4 | 2005-11-26 18:47:20 +0000 | [diff] [blame] | 247 | #if defined(CONFIG_USER_ONLY) |
ths | 873eb01 | 2006-12-06 17:59:07 +0000 | [diff] [blame] | 248 | void do_mfc0_random (void) |
bellard | 048f6b4 | 2005-11-26 18:47:20 +0000 | [diff] [blame] | 249 | { |
ths | 873eb01 | 2006-12-06 17:59:07 +0000 | [diff] [blame] | 250 | cpu_abort(env, "mfc0 random\n"); |
bellard | 048f6b4 | 2005-11-26 18:47:20 +0000 | [diff] [blame] | 251 | } |
ths | 873eb01 | 2006-12-06 17:59:07 +0000 | [diff] [blame] | 252 | |
| 253 | void do_mfc0_count (void) |
| 254 | { |
| 255 | cpu_abort(env, "mfc0 count\n"); |
| 256 | } |
| 257 | |
ths | 8c0fdd8 | 2006-12-06 18:19:33 +0000 | [diff] [blame] | 258 | void cpu_mips_store_count(CPUState *env, uint32_t value) |
bellard | 048f6b4 | 2005-11-26 18:47:20 +0000 | [diff] [blame] | 259 | { |
ths | 8c0fdd8 | 2006-12-06 18:19:33 +0000 | [diff] [blame] | 260 | cpu_abort(env, "mtc0 count\n"); |
| 261 | } |
| 262 | |
| 263 | void cpu_mips_store_compare(CPUState *env, uint32_t value) |
| 264 | { |
| 265 | cpu_abort(env, "mtc0 compare\n"); |
| 266 | } |
| 267 | |
ths | 4de9b24 | 2007-01-24 01:47:51 +0000 | [diff] [blame] | 268 | void cpu_mips_update_irq(CPUState *env) |
| 269 | { |
| 270 | cpu_abort(env, "mtc0 status / mtc0 cause\n"); |
| 271 | } |
| 272 | |
ths | 8c0fdd8 | 2006-12-06 18:19:33 +0000 | [diff] [blame] | 273 | void do_mtc0_status_debug(uint32_t old, uint32_t val) |
| 274 | { |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 275 | cpu_abort(env, "mtc0 status debug\n"); |
ths | 8c0fdd8 | 2006-12-06 18:19:33 +0000 | [diff] [blame] | 276 | } |
| 277 | |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 278 | void do_mtc0_status_irqraise_debug (void) |
ths | 8c0fdd8 | 2006-12-06 18:19:33 +0000 | [diff] [blame] | 279 | { |
ths | 7a387ff | 2006-12-06 20:17:30 +0000 | [diff] [blame] | 280 | cpu_abort(env, "mtc0 status irqraise debug\n"); |
bellard | 048f6b4 | 2005-11-26 18:47:20 +0000 | [diff] [blame] | 281 | } |
| 282 | |
| 283 | void do_tlbwi (void) |
| 284 | { |
| 285 | cpu_abort(env, "tlbwi\n"); |
| 286 | } |
| 287 | |
| 288 | void do_tlbwr (void) |
| 289 | { |
| 290 | cpu_abort(env, "tlbwr\n"); |
| 291 | } |
| 292 | |
| 293 | void do_tlbp (void) |
| 294 | { |
| 295 | cpu_abort(env, "tlbp\n"); |
| 296 | } |
| 297 | |
| 298 | void do_tlbr (void) |
| 299 | { |
| 300 | cpu_abort(env, "tlbr\n"); |
| 301 | } |
ths | 873eb01 | 2006-12-06 17:59:07 +0000 | [diff] [blame] | 302 | |
ths | 8c0fdd8 | 2006-12-06 18:19:33 +0000 | [diff] [blame] | 303 | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
| 304 | { |
| 305 | cpu_abort(env, "mips_tlb_flush\n"); |
| 306 | } |
| 307 | |
bellard | 048f6b4 | 2005-11-26 18:47:20 +0000 | [diff] [blame] | 308 | #else |
| 309 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 310 | /* CP0 helpers */ |
ths | 873eb01 | 2006-12-06 17:59:07 +0000 | [diff] [blame] | 311 | void do_mfc0_random (void) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 312 | { |
ths | 5dc4b74 | 2006-12-21 13:48:28 +0000 | [diff] [blame] | 313 | T0 = (int32_t)cpu_mips_get_random(env); |
ths | 873eb01 | 2006-12-06 17:59:07 +0000 | [diff] [blame] | 314 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 315 | |
ths | 873eb01 | 2006-12-06 17:59:07 +0000 | [diff] [blame] | 316 | void do_mfc0_count (void) |
| 317 | { |
ths | 5dc4b74 | 2006-12-21 13:48:28 +0000 | [diff] [blame] | 318 | T0 = (int32_t)cpu_mips_get_count(env); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 319 | } |
| 320 | |
ths | 8c0fdd8 | 2006-12-06 18:19:33 +0000 | [diff] [blame] | 321 | void do_mtc0_status_debug(uint32_t old, uint32_t val) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 322 | { |
ths | 8c0fdd8 | 2006-12-06 18:19:33 +0000 | [diff] [blame] | 323 | const uint32_t mask = 0x0000FF00; |
| 324 | fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n", |
| 325 | old, val, env->CP0_Cause, old & mask, val & mask, |
| 326 | env->CP0_Cause & mask); |
| 327 | } |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 328 | |
ths | 8c0fdd8 | 2006-12-06 18:19:33 +0000 | [diff] [blame] | 329 | void do_mtc0_status_irqraise_debug(void) |
| 330 | { |
| 331 | fprintf(logfile, "Raise pending IRQs\n"); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 332 | } |
| 333 | |
bellard | 6ea83fe | 2006-06-14 12:56:19 +0000 | [diff] [blame] | 334 | #ifdef MIPS_USES_FPU |
| 335 | #include "softfloat.h" |
| 336 | |
| 337 | void fpu_handle_exception(void) |
| 338 | { |
| 339 | #ifdef CONFIG_SOFTFLOAT |
| 340 | int flags = get_float_exception_flags(&env->fp_status); |
| 341 | unsigned int cpuflags = 0, enable, cause = 0; |
| 342 | |
| 343 | enable = GET_FP_ENABLE(env->fcr31); |
| 344 | |
| 345 | /* determine current flags */ |
| 346 | if (flags & float_flag_invalid) { |
| 347 | cpuflags |= FP_INVALID; |
| 348 | cause |= FP_INVALID & enable; |
| 349 | } |
| 350 | if (flags & float_flag_divbyzero) { |
| 351 | cpuflags |= FP_DIV0; |
| 352 | cause |= FP_DIV0 & enable; |
| 353 | } |
| 354 | if (flags & float_flag_overflow) { |
| 355 | cpuflags |= FP_OVERFLOW; |
| 356 | cause |= FP_OVERFLOW & enable; |
| 357 | } |
| 358 | if (flags & float_flag_underflow) { |
| 359 | cpuflags |= FP_UNDERFLOW; |
| 360 | cause |= FP_UNDERFLOW & enable; |
| 361 | } |
| 362 | if (flags & float_flag_inexact) { |
| 363 | cpuflags |= FP_INEXACT; |
| 364 | cause |= FP_INEXACT & enable; |
| 365 | } |
| 366 | SET_FP_FLAGS(env->fcr31, cpuflags); |
| 367 | SET_FP_CAUSE(env->fcr31, cause); |
| 368 | #else |
| 369 | SET_FP_FLAGS(env->fcr31, 0); |
| 370 | SET_FP_CAUSE(env->fcr31, 0); |
| 371 | #endif |
| 372 | } |
| 373 | #endif /* MIPS_USES_FPU */ |
| 374 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 375 | /* TLB management */ |
| 376 | #if defined(MIPS_USES_R4K_TLB) |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 377 | void cpu_mips_tlb_flush (CPUState *env, int flush_global) |
| 378 | { |
| 379 | /* Flush qemu's TLB and discard all shadowed entries. */ |
| 380 | tlb_flush (env, flush_global); |
| 381 | env->tlb_in_use = MIPS_TLB_NB; |
| 382 | } |
| 383 | |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 384 | static void mips_tlb_flush_extra (CPUState *env, int first) |
| 385 | { |
| 386 | /* Discard entries from env->tlb[first] onwards. */ |
| 387 | while (env->tlb_in_use > first) { |
bellard | 2ee4aed | 2007-01-03 15:18:08 +0000 | [diff] [blame] | 388 | invalidate_tlb(env, --env->tlb_in_use, 0); |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 389 | } |
| 390 | } |
| 391 | |
pbrook | 98c1b82 | 2006-03-11 16:20:36 +0000 | [diff] [blame] | 392 | static void fill_tlb (int idx) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 393 | { |
| 394 | tlb_t *tlb; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 395 | |
| 396 | /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ |
| 397 | tlb = &env->tlb[idx]; |
ths | 5dc4b74 | 2006-12-21 13:48:28 +0000 | [diff] [blame] | 398 | tlb->VPN = env->CP0_EntryHi & (int32_t)0xFFFFE000; |
pbrook | 98c1b82 | 2006-03-11 16:20:36 +0000 | [diff] [blame] | 399 | tlb->ASID = env->CP0_EntryHi & 0xFF; |
ths | 3b1c8be | 2007-01-22 20:50:42 +0000 | [diff] [blame] | 400 | tlb->PageMask = env->CP0_PageMask; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 401 | tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; |
pbrook | 98c1b82 | 2006-03-11 16:20:36 +0000 | [diff] [blame] | 402 | tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; |
| 403 | tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; |
| 404 | tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 405 | tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12; |
pbrook | 98c1b82 | 2006-03-11 16:20:36 +0000 | [diff] [blame] | 406 | tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; |
| 407 | tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; |
| 408 | tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 409 | tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12; |
| 410 | } |
| 411 | |
| 412 | void do_tlbwi (void) |
| 413 | { |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 414 | /* Discard cached TLB entries. We could avoid doing this if the |
| 415 | tlbwi is just upgrading access permissions on the current entry; |
| 416 | that might be a further win. */ |
| 417 | mips_tlb_flush_extra (env, MIPS_TLB_NB); |
| 418 | |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 419 | /* Wildly undefined effects for CP0_Index containing a too high value and |
bellard | 7a962d3 | 2005-07-02 15:31:15 +0000 | [diff] [blame] | 420 | MIPS_TLB_NB not being a power of two. But so does real silicon. */ |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 421 | invalidate_tlb(env, env->CP0_Index & (MIPS_TLB_NB - 1), 0); |
| 422 | fill_tlb(env->CP0_Index & (MIPS_TLB_NB - 1)); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 423 | } |
| 424 | |
| 425 | void do_tlbwr (void) |
| 426 | { |
| 427 | int r = cpu_mips_get_random(env); |
| 428 | |
bellard | 2ee4aed | 2007-01-03 15:18:08 +0000 | [diff] [blame] | 429 | invalidate_tlb(env, r, 1); |
pbrook | 98c1b82 | 2006-03-11 16:20:36 +0000 | [diff] [blame] | 430 | fill_tlb(r); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 431 | } |
| 432 | |
| 433 | void do_tlbp (void) |
| 434 | { |
| 435 | tlb_t *tlb; |
| 436 | target_ulong tag; |
| 437 | uint8_t ASID; |
| 438 | int i; |
| 439 | |
ths | 5dc4b74 | 2006-12-21 13:48:28 +0000 | [diff] [blame] | 440 | tag = env->CP0_EntryHi & (int32_t)0xFFFFE000; |
bellard | 3d9fb9fe | 2006-05-22 22:13:29 +0000 | [diff] [blame] | 441 | ASID = env->CP0_EntryHi & 0xFF; |
| 442 | for (i = 0; i < MIPS_TLB_NB; i++) { |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 443 | tlb = &env->tlb[i]; |
| 444 | /* Check ASID, virtual page number & size */ |
| 445 | if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { |
| 446 | /* TLB match */ |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 447 | env->CP0_Index = i; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 448 | break; |
| 449 | } |
| 450 | } |
bellard | 7a962d3 | 2005-07-02 15:31:15 +0000 | [diff] [blame] | 451 | if (i == MIPS_TLB_NB) { |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 452 | /* No match. Discard any shadow entries, if any of them match. */ |
| 453 | for (i = MIPS_TLB_NB; i < env->tlb_in_use; i++) { |
| 454 | tlb = &env->tlb[i]; |
| 455 | |
| 456 | /* Check ASID, virtual page number & size */ |
| 457 | if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) { |
| 458 | mips_tlb_flush_extra (env, i); |
| 459 | break; |
| 460 | } |
| 461 | } |
| 462 | |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 463 | env->CP0_Index |= 0x80000000; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 464 | } |
| 465 | } |
| 466 | |
| 467 | void do_tlbr (void) |
| 468 | { |
| 469 | tlb_t *tlb; |
pbrook | 09c56b8 | 2006-03-11 16:39:23 +0000 | [diff] [blame] | 470 | uint8_t ASID; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 471 | |
pbrook | 09c56b8 | 2006-03-11 16:39:23 +0000 | [diff] [blame] | 472 | ASID = env->CP0_EntryHi & 0xFF; |
ths | 9c2149c | 2007-01-23 22:45:22 +0000 | [diff] [blame] | 473 | tlb = &env->tlb[env->CP0_Index & (MIPS_TLB_NB - 1)]; |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 474 | |
| 475 | /* If this will change the current ASID, flush qemu's TLB. */ |
ths | 814b9a4 | 2006-12-06 17:42:40 +0000 | [diff] [blame] | 476 | if (ASID != tlb->ASID) |
| 477 | cpu_mips_tlb_flush (env, 1); |
| 478 | |
| 479 | mips_tlb_flush_extra(env, MIPS_TLB_NB); |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 480 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 481 | env->CP0_EntryHi = tlb->VPN | tlb->ASID; |
ths | 3b1c8be | 2007-01-22 20:50:42 +0000 | [diff] [blame] | 482 | env->CP0_PageMask = tlb->PageMask; |
ths | 7495fd0 | 2007-01-01 20:32:08 +0000 | [diff] [blame] | 483 | env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | |
| 484 | (tlb->C0 << 3) | (tlb->PFN[0] >> 6); |
| 485 | env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | |
| 486 | (tlb->C1 << 3) | (tlb->PFN[1] >> 6); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 487 | } |
| 488 | #endif |
| 489 | |
bellard | 048f6b4 | 2005-11-26 18:47:20 +0000 | [diff] [blame] | 490 | #endif /* !CONFIG_USER_ONLY */ |
| 491 | |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 492 | void dump_ldst (const unsigned char *func) |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 493 | { |
| 494 | if (loglevel) |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 495 | fprintf(logfile, "%s => " TLSZ " " TLSZ "\n", __func__, T0, T1); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 496 | } |
| 497 | |
| 498 | void dump_sc (void) |
| 499 | { |
| 500 | if (loglevel) { |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 501 | fprintf(logfile, "%s " TLSZ " at " TLSZ " (" TLSZ ")\n", __func__, |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 502 | T1, T0, env->CP0_LLAddr); |
| 503 | } |
| 504 | } |
| 505 | |
| 506 | void debug_eret (void) |
| 507 | { |
| 508 | if (loglevel) { |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 509 | fprintf(logfile, "ERET: pc " TLSZ " EPC " TLSZ " ErrorEPC " TLSZ " (%d)\n", |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 510 | env->PC, env->CP0_EPC, env->CP0_ErrorEPC, |
| 511 | env->hflags & MIPS_HFLAG_ERL ? 1 : 0); |
| 512 | } |
| 513 | } |
| 514 | |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 515 | void do_pmon (int function) |
| 516 | { |
| 517 | function /= 2; |
| 518 | switch (function) { |
| 519 | case 2: /* TODO: char inbyte(int waitflag); */ |
| 520 | if (env->gpr[4] == 0) |
| 521 | env->gpr[2] = -1; |
| 522 | /* Fall through */ |
| 523 | case 11: /* TODO: char inbyte (void); */ |
| 524 | env->gpr[2] = -1; |
| 525 | break; |
| 526 | case 3: |
| 527 | case 12: |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 528 | printf("%c", (char)(env->gpr[4] & 0xFF)); |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 529 | break; |
| 530 | case 17: |
| 531 | break; |
| 532 | case 158: |
| 533 | { |
ths | c570fd1 | 2006-12-21 01:19:56 +0000 | [diff] [blame] | 534 | unsigned char *fmt = (void *)(unsigned long)env->gpr[4]; |
bellard | 6af0bf9 | 2005-07-02 14:58:51 +0000 | [diff] [blame] | 535 | printf("%s", fmt); |
| 536 | } |
| 537 | break; |
| 538 | } |
| 539 | } |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 540 | |
| 541 | #if !defined(CONFIG_USER_ONLY) |
| 542 | |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 543 | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr); |
| 544 | |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 545 | #define MMUSUFFIX _mmu |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 546 | #define ALIGNED_ONLY |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 547 | |
| 548 | #define SHIFT 0 |
| 549 | #include "softmmu_template.h" |
| 550 | |
| 551 | #define SHIFT 1 |
| 552 | #include "softmmu_template.h" |
| 553 | |
| 554 | #define SHIFT 2 |
| 555 | #include "softmmu_template.h" |
| 556 | |
| 557 | #define SHIFT 3 |
| 558 | #include "softmmu_template.h" |
| 559 | |
bellard | 4ad40f3 | 2005-12-05 19:59:36 +0000 | [diff] [blame] | 560 | static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr) |
| 561 | { |
| 562 | env->CP0_BadVAddr = addr; |
| 563 | do_restore_state (retaddr); |
| 564 | do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL); |
| 565 | } |
| 566 | |
bellard | e37e863 | 2005-07-04 22:17:33 +0000 | [diff] [blame] | 567 | void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr) |
| 568 | { |
| 569 | TranslationBlock *tb; |
| 570 | CPUState *saved_env; |
| 571 | unsigned long pc; |
| 572 | int ret; |
| 573 | |
| 574 | /* XXX: hack to restore env in all cases, even if not called from |
| 575 | generated code */ |
| 576 | saved_env = env; |
| 577 | env = cpu_single_env; |
| 578 | ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1); |
| 579 | if (ret) { |
| 580 | if (retaddr) { |
| 581 | /* now we have a real cpu fault */ |
| 582 | pc = (unsigned long)retaddr; |
| 583 | tb = tb_find_pc(pc); |
| 584 | if (tb) { |
| 585 | /* the PC is inside the translated code. It means that we have |
| 586 | a virtual CPU fault */ |
| 587 | cpu_restore_state(tb, env, pc, NULL); |
| 588 | } |
| 589 | } |
| 590 | do_raise_exception_err(env->exception_index, env->error_code); |
| 591 | } |
| 592 | env = saved_env; |
| 593 | } |
| 594 | |
| 595 | #endif |