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balrogef056e42007-11-25 01:57:38 +00001/*
2 * PXA270-based Intel Mainstone platforms.
3 *
4 * Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
5 * <akuster@mvista.com>
6 *
7 * Code based on spitz platform by Andrzej Zaborowski <balrog@zabor.org>
8 *
9 * This code is licensed under the GNU GPL v2.
Paolo Bonzini6b620ca2012-01-13 17:44:23 +010010 *
11 * Contributions after 2012-01-13 are licensed under the terms of the
12 * GNU GPL, version 2 or (at your option) any later version.
balrogef056e42007-11-25 01:57:38 +000013 */
Peter Maydell12b16722015-12-07 16:23:45 +000014#include "qemu/osdep.h"
Markus Armbrusterda34e652016-03-14 09:01:28 +010015#include "qapi/error.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010016#include "hw/hw.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010017#include "hw/arm/pxa.h"
Peter Maydellbd2be152013-04-09 15:26:55 +010018#include "hw/arm/arm.h"
Paolo Bonzini1422e322012-10-24 08:43:34 +020019#include "net/net.h"
Peter Maydellbd2be152013-04-09 15:26:55 +010020#include "hw/devices.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010021#include "hw/boards.h"
Paolo Bonzini0d09e412013-02-05 17:06:20 +010022#include "hw/block/flash.h"
Markus Armbrusterfa1d36d2014-10-07 13:59:13 +020023#include "sysemu/block-backend.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010024#include "hw/sysbus.h"
Paolo Bonzini022c62c2012-12-17 18:19:49 +010025#include "exec/address-spaces.h"
Andreas Färberd2f7c492013-07-29 17:12:41 +020026#include "sysemu/qtest.h"
balrogef056e42007-11-25 01:57:38 +000027
Dmitry Eremin-Solenikov459505a2011-02-12 03:15:25 +030028/* Device addresses */
29#define MST_FPGA_PHYS 0x08000000
30#define MST_ETH_PHYS 0x10000300
31#define MST_FLASH_0 0x00000000
32#define MST_FLASH_1 0x04000000
33
34/* IRQ definitions */
35#define MMC_IRQ 0
36#define USIM_IRQ 1
37#define USBC_IRQ 2
38#define ETHERNET_IRQ 3
39#define AC97_IRQ 4
40#define PEN_IRQ 5
41#define MSINS_IRQ 6
42#define EXBRD_IRQ 7
43#define S0_CD_IRQ 9
44#define S0_STSCHG_IRQ 10
45#define S0_IRQ 11
46#define S1_CD_IRQ 13
47#define S1_STSCHG_IRQ 14
48#define S1_IRQ 15
49
Stefan Weil52975c32013-12-22 15:22:57 +010050static const struct keymap map[0xE0] = {
balrogbd464c22007-12-16 12:19:43 +000051 [0 ... 0xDF] = { -1, -1 },
52 [0x1e] = {0,0}, /* a */
53 [0x30] = {0,1}, /* b */
54 [0x2e] = {0,2}, /* c */
55 [0x20] = {0,3}, /* d */
56 [0x12] = {0,4}, /* e */
57 [0x21] = {0,5}, /* f */
58 [0x22] = {1,0}, /* g */
59 [0x23] = {1,1}, /* h */
60 [0x17] = {1,2}, /* i */
61 [0x24] = {1,3}, /* j */
62 [0x25] = {1,4}, /* k */
63 [0x26] = {1,5}, /* l */
64 [0x32] = {2,0}, /* m */
65 [0x31] = {2,1}, /* n */
66 [0x18] = {2,2}, /* o */
67 [0x19] = {2,3}, /* p */
68 [0x10] = {2,4}, /* q */
69 [0x13] = {2,5}, /* r */
70 [0x1f] = {3,0}, /* s */
71 [0x14] = {3,1}, /* t */
72 [0x16] = {3,2}, /* u */
73 [0x2f] = {3,3}, /* v */
74 [0x11] = {3,4}, /* w */
75 [0x2d] = {3,5}, /* x */
Vijay Kumar B0c74e952016-10-04 13:28:08 +010076 [0x34] = {4,0}, /* . */
balrogbd464c22007-12-16 12:19:43 +000077 [0x15] = {4,2}, /* y */
78 [0x2c] = {4,3}, /* z */
Vijay Kumar B0c74e952016-10-04 13:28:08 +010079 [0x35] = {4,4}, /* / */
balrogbd464c22007-12-16 12:19:43 +000080 [0xc7] = {5,0}, /* Home */
81 [0x2a] = {5,1}, /* shift */
Stefan Weil7dbc1152013-12-22 20:42:05 +010082 /*
83 * There are two matrix positions which map to space,
84 * but QEMU can only use one of them for the reverse
85 * mapping, so simply use the second one.
86 */
87 /* [0x39] = {5,2}, space */
balrogbd464c22007-12-16 12:19:43 +000088 [0x39] = {5,3}, /* space */
Stefan Weil7dbc1152013-12-22 20:42:05 +010089 /*
90 * Matrix position {5,4} and other keys are missing here.
91 * TODO: Compare with Linux code and test real hardware.
92 */
Vijay Kumar B8cb2d2d2016-10-04 13:28:07 +010093 [0x1c] = {5,4}, /* enter */
Vijay Kumar B0c74e952016-10-04 13:28:08 +010094 [0x0e] = {5,5}, /* backspace */
balrogbd464c22007-12-16 12:19:43 +000095 [0xc8] = {6,0}, /* up */
96 [0xd0] = {6,1}, /* down */
97 [0xcb] = {6,2}, /* left */
98 [0xcd] = {6,3}, /* right */
99};
100
balrogef056e42007-11-25 01:57:38 +0000101enum mainstone_model_e { mainstone };
102
balrog7fb4fdc2008-04-24 17:59:27 +0000103#define MAINSTONE_RAM 0x04000000
104#define MAINSTONE_ROM 0x00800000
105#define MAINSTONE_FLASH 0x02000000
106
balrogf93eb9f2008-04-14 20:27:51 +0000107static struct arm_boot_info mainstone_binfo = {
108 .loader_start = PXA2XX_SDRAM_BASE,
109 .ram_size = 0x04000000,
110};
111
Avi Kivity02e5c162011-08-08 21:08:45 +0300112static void mainstone_common_init(MemoryRegion *address_space_mem,
Marcel Apfelbaum3ef96222014-05-07 17:42:57 +0300113 MachineState *machine,
Peter Maydell6efa6d52012-10-30 07:45:08 +0000114 enum mainstone_model_e model, int arm_id)
balrogef056e42007-11-25 01:57:38 +0000115{
balrog6d1f1772008-01-05 19:29:17 +0000116 uint32_t sector_len = 256 * 1024;
Avi Kivitya8170e52012-10-23 12:30:10 +0200117 hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
Andreas Färber1c88de62012-05-14 01:11:15 +0200118 PXA2xxState *mpu;
Dmitry Eremin-Solenikovcb380f62011-02-12 03:15:24 +0300119 DeviceState *mst_irq;
Gerd Hoffmann751c6a12009-07-22 16:42:57 +0200120 DriveInfo *dinfo;
121 int i;
Anthony Liguori01e04512011-08-25 14:39:18 -0500122 int be;
Avi Kivity02e5c162011-08-08 21:08:45 +0300123 MemoryRegion *rom = g_new(MemoryRegion, 1);
Marcel Apfelbaum3ef96222014-05-07 17:42:57 +0300124 const char *cpu_model = machine->cpu_model;
balrogef056e42007-11-25 01:57:38 +0000125
126 if (!cpu_model)
127 cpu_model = "pxa270-c5";
128
129 /* Setup CPU & memory */
Andreas Färber1c88de62012-05-14 01:11:15 +0200130 mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);
Hu Tao49946532014-09-09 13:27:55 +0800131 memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM,
Markus Armbrusterf8ed85a2015-09-11 16:51:43 +0200132 &error_fatal);
Avi Kivityc5705a72011-12-20 15:59:12 +0200133 vmstate_register_ram_global(rom);
Avi Kivity02e5c162011-08-08 21:08:45 +0300134 memory_region_set_readonly(rom, true);
135 memory_region_add_subregion(address_space_mem, 0, rom);
balrogef056e42007-11-25 01:57:38 +0000136
Blue Swirl3d08ff62010-03-29 19:23:56 +0000137#ifdef TARGET_WORDS_BIGENDIAN
Anthony Liguori01e04512011-08-25 14:39:18 -0500138 be = 1;
Blue Swirl3d08ff62010-03-29 19:23:56 +0000139#else
Anthony Liguori01e04512011-08-25 14:39:18 -0500140 be = 0;
Blue Swirl3d08ff62010-03-29 19:23:56 +0000141#endif
thse4bcb142007-12-02 04:51:10 +0000142 /* There are two 32MiB flash devices on the board */
balrog6d1f1772008-01-05 19:29:17 +0000143 for (i = 0; i < 2; i ++) {
Gerd Hoffmann751c6a12009-07-22 16:42:57 +0200144 dinfo = drive_get(IF_PFLASH, 0, i);
145 if (!dinfo) {
Andreas Färberd2f7c492013-07-29 17:12:41 +0200146 if (qtest_enabled()) {
147 break;
148 }
balrog6d1f1772008-01-05 19:29:17 +0000149 fprintf(stderr, "Two flash images must be given with the "
150 "'pflash' parameter\n");
151 exit(1);
152 }
ths7233b352007-12-02 02:20:03 +0000153
Avi Kivitycfe5f012011-08-04 15:55:30 +0300154 if (!pflash_cfi01_register(mainstone_flash_base[i], NULL,
155 i ? "mainstone.flash1" : "mainstone.flash0",
156 MAINSTONE_FLASH,
Markus Armbruster4be74632014-10-07 13:59:18 +0200157 blk_by_legacy_dinfo(dinfo),
Markus Armbrusterfa1d36d2014-10-07 13:59:13 +0200158 sector_len, MAINSTONE_FLASH / sector_len,
159 4, 0, 0, 0, 0, be)) {
balrog6d1f1772008-01-05 19:29:17 +0000160 fprintf(stderr, "qemu: Error registering flash memory.\n");
161 exit(1);
162 }
thse4bcb142007-12-02 04:51:10 +0000163 }
ths7233b352007-12-02 02:20:03 +0000164
Dmitry Eremin-Solenikovcb380f62011-02-12 03:15:24 +0300165 mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
Andreas Färber1c88de62012-05-14 01:11:15 +0200166 qdev_get_gpio_in(mpu->gpio, 0));
thsf1de1332007-12-09 02:38:34 +0000167
balrogbd464c22007-12-16 12:19:43 +0000168 /* setup keypad */
Andreas Färber1c88de62012-05-14 01:11:15 +0200169 pxa27x_register_keypad(mpu->kp, map, 0xe0);
balrogbd464c22007-12-16 12:19:43 +0000170
thsf1de1332007-12-09 02:38:34 +0000171 /* MMC/SD host */
Andreas Färber1c88de62012-05-14 01:11:15 +0200172 pxa2xx_mmci_handlers(mpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));
thsf1de1332007-12-09 02:38:34 +0000173
Andreas Färber1c88de62012-05-14 01:11:15 +0200174 pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[0],
Dmitry Eremin-Solenikovb651fc62011-03-04 03:54:59 +0300175 qdev_get_gpio_in(mst_irq, S0_IRQ),
176 qdev_get_gpio_in(mst_irq, S0_CD_IRQ));
Andreas Färber1c88de62012-05-14 01:11:15 +0200177 pxa2xx_pcmcia_set_irq_cb(mpu->pcmcia[1],
Dmitry Eremin-Solenikovb651fc62011-03-04 03:54:59 +0300178 qdev_get_gpio_in(mst_irq, S1_IRQ),
179 qdev_get_gpio_in(mst_irq, S1_CD_IRQ));
180
Dmitry Eremin-Solenikovcb380f62011-02-12 03:15:24 +0300181 smc91c111_init(&nd_table[0], MST_ETH_PHYS,
182 qdev_get_gpio_in(mst_irq, ETHERNET_IRQ));
balrogef056e42007-11-25 01:57:38 +0000183
Marcel Apfelbaum3ef96222014-05-07 17:42:57 +0300184 mainstone_binfo.kernel_filename = machine->kernel_filename;
185 mainstone_binfo.kernel_cmdline = machine->kernel_cmdline;
186 mainstone_binfo.initrd_filename = machine->initrd_filename;
balrogf93eb9f2008-04-14 20:27:51 +0000187 mainstone_binfo.board_id = arm_id;
Andreas Färber3aaa8df2012-05-14 02:39:57 +0200188 arm_load_kernel(mpu->cpu, &mainstone_binfo);
balrogef056e42007-11-25 01:57:38 +0000189}
190
Marcel Apfelbaum3ef96222014-05-07 17:42:57 +0300191static void mainstone_init(MachineState *machine)
balrogef056e42007-11-25 01:57:38 +0000192{
Marcel Apfelbaum3ef96222014-05-07 17:42:57 +0300193 mainstone_common_init(get_system_memory(), machine, mainstone, 0x196);
balrogef056e42007-11-25 01:57:38 +0000194}
195
Eduardo Habkoste264d292015-09-04 15:37:08 -0300196static void mainstone2_machine_init(MachineClass *mc)
Anthony Liguorif80f9ec2009-05-20 18:38:09 -0500197{
Eduardo Habkoste264d292015-09-04 15:37:08 -0300198 mc->desc = "Mainstone II (PXA27x)";
199 mc->init = mainstone_init;
Anthony Liguorif80f9ec2009-05-20 18:38:09 -0500200}
201
Eduardo Habkoste264d292015-09-04 15:37:08 -0300202DEFINE_MACHINE("mainstone", mainstone2_machine_init)