Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions are met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer in the |
| 11 | * documentation and/or other materials provided with the distribution. |
| 12 | * * Neither the name of the Open Source and Linux Lab nor the |
| 13 | * names of its contributors may be used to endorse or promote products |
| 14 | * derived from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
| 20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include "cpu.h" |
Paolo Bonzini | 022c62c | 2012-12-17 18:19:49 +0100 | [diff] [blame] | 29 | #include "exec/exec-all.h" |
| 30 | #include "exec/gdbstub.h" |
Paolo Bonzini | 1de7afc | 2012-12-17 18:20:00 +0100 | [diff] [blame] | 31 | #include "qemu/host-utils.h" |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 32 | #if !defined(CONFIG_USER_ONLY) |
| 33 | #include "hw/loader.h" |
| 34 | #endif |
| 35 | |
Max Filippov | ac8b7db | 2011-10-16 02:56:04 +0400 | [diff] [blame] | 36 | static struct XtensaConfigList *xtensa_cores; |
| 37 | |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 38 | static void xtensa_core_class_init(ObjectClass *oc, void *data) |
| 39 | { |
Andreas Färber | a0e372f | 2013-06-28 23:18:47 +0200 | [diff] [blame] | 40 | CPUClass *cc = CPU_CLASS(oc); |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 41 | XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc); |
| 42 | const XtensaConfig *config = data; |
| 43 | |
| 44 | xcc->config = config; |
Andreas Färber | a0e372f | 2013-06-28 23:18:47 +0200 | [diff] [blame] | 45 | |
| 46 | /* Use num_core_regs to see only non-privileged registers in an unmodified |
| 47 | * gdb. Use num_regs to see all registers. gdb modification is required |
| 48 | * for that: reset bit 0 in the 'flags' field of the registers definitions |
| 49 | * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay. |
| 50 | */ |
| 51 | cc->gdb_num_core_regs = config->gdb_regmap.num_regs; |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 52 | } |
| 53 | |
Max Filippov | ac8b7db | 2011-10-16 02:56:04 +0400 | [diff] [blame] | 54 | void xtensa_register_core(XtensaConfigList *node) |
| 55 | { |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 56 | TypeInfo type = { |
| 57 | .parent = TYPE_XTENSA_CPU, |
| 58 | .class_init = xtensa_core_class_init, |
| 59 | .class_data = (void *)node->config, |
| 60 | }; |
| 61 | |
Max Filippov | ac8b7db | 2011-10-16 02:56:04 +0400 | [diff] [blame] | 62 | node->next = xtensa_cores; |
| 63 | xtensa_cores = node; |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 64 | type.name = g_strdup_printf("%s-" TYPE_XTENSA_CPU, node->config->name); |
| 65 | type_register(&type); |
| 66 | g_free((gpointer)type.name); |
Max Filippov | ac8b7db | 2011-10-16 02:56:04 +0400 | [diff] [blame] | 67 | } |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 68 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 69 | static uint32_t check_hw_breakpoints(CPUXtensaState *env) |
Max Filippov | f14c4b5 | 2012-01-29 05:28:21 +0400 | [diff] [blame] | 70 | { |
| 71 | unsigned i; |
| 72 | |
| 73 | for (i = 0; i < env->config->ndbreak; ++i) { |
| 74 | if (env->cpu_watchpoint[i] && |
| 75 | env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) { |
| 76 | return DEBUGCAUSE_DB | (i << DEBUGCAUSE_DBNUM_SHIFT); |
| 77 | } |
| 78 | } |
| 79 | return 0; |
| 80 | } |
| 81 | |
Andreas Färber | 25733ea | 2013-01-20 01:46:45 +0100 | [diff] [blame] | 82 | void xtensa_breakpoint_handler(CPUXtensaState *env) |
Max Filippov | f14c4b5 | 2012-01-29 05:28:21 +0400 | [diff] [blame] | 83 | { |
Andreas Färber | ff4700b | 2013-08-26 18:23:18 +0200 | [diff] [blame] | 84 | CPUState *cs = CPU(xtensa_env_get_cpu(env)); |
| 85 | |
| 86 | if (cs->watchpoint_hit) { |
| 87 | if (cs->watchpoint_hit->flags & BP_CPU) { |
Max Filippov | f14c4b5 | 2012-01-29 05:28:21 +0400 | [diff] [blame] | 88 | uint32_t cause; |
| 89 | |
Andreas Färber | ff4700b | 2013-08-26 18:23:18 +0200 | [diff] [blame] | 90 | cs->watchpoint_hit = NULL; |
Max Filippov | f14c4b5 | 2012-01-29 05:28:21 +0400 | [diff] [blame] | 91 | cause = check_hw_breakpoints(env); |
| 92 | if (cause) { |
| 93 | debug_exception_env(env, cause); |
| 94 | } |
Andreas Färber | 0ea8cb8 | 2013-09-03 02:12:23 +0200 | [diff] [blame] | 95 | cpu_resume_from_signal(cs, NULL); |
Max Filippov | f14c4b5 | 2012-01-29 05:28:21 +0400 | [diff] [blame] | 96 | } |
| 97 | } |
Max Filippov | f14c4b5 | 2012-01-29 05:28:21 +0400 | [diff] [blame] | 98 | } |
| 99 | |
Andreas Färber | 15be317 | 2012-05-06 12:41:53 +0200 | [diff] [blame] | 100 | XtensaCPU *cpu_xtensa_init(const char *cpu_model) |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 101 | { |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 102 | ObjectClass *oc; |
Andreas Färber | a4633e1 | 2012-04-11 18:24:48 +0200 | [diff] [blame] | 103 | XtensaCPU *cpu; |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 104 | CPUXtensaState *env; |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 105 | |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 106 | oc = cpu_class_by_name(TYPE_XTENSA_CPU, cpu_model); |
| 107 | if (oc == NULL) { |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 108 | return NULL; |
| 109 | } |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 110 | |
Andreas Färber | 67cce56 | 2013-07-07 01:47:51 +0200 | [diff] [blame] | 111 | cpu = XTENSA_CPU(object_new(object_class_get_name(oc))); |
Andreas Färber | a4633e1 | 2012-04-11 18:24:48 +0200 | [diff] [blame] | 112 | env = &cpu->env; |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 113 | |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 114 | xtensa_irq_init(env); |
Andreas Färber | 5f6c964 | 2013-01-16 04:19:35 +0100 | [diff] [blame] | 115 | |
| 116 | object_property_set_bool(OBJECT(cpu), true, "realized", NULL); |
| 117 | |
Andreas Färber | 15be317 | 2012-05-06 12:41:53 +0200 | [diff] [blame] | 118 | return cpu; |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | |
| 122 | void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf) |
| 123 | { |
Max Filippov | ac8b7db | 2011-10-16 02:56:04 +0400 | [diff] [blame] | 124 | XtensaConfigList *core = xtensa_cores; |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 125 | cpu_fprintf(f, "Available CPUs:\n"); |
Max Filippov | ac8b7db | 2011-10-16 02:56:04 +0400 | [diff] [blame] | 126 | for (; core; core = core->next) { |
| 127 | cpu_fprintf(f, " %s\n", core->config->name); |
Max Filippov | dedc5ea | 2011-09-06 03:55:27 +0400 | [diff] [blame] | 128 | } |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 129 | } |
| 130 | |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 131 | hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 132 | { |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 133 | XtensaCPU *cpu = XTENSA_CPU(cs); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 134 | uint32_t paddr; |
| 135 | uint32_t page_size; |
| 136 | unsigned access; |
| 137 | |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 138 | if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 139 | &paddr, &page_size, &access) == 0) { |
| 140 | return paddr; |
| 141 | } |
Andreas Färber | 00b941e | 2013-06-29 18:55:54 +0200 | [diff] [blame] | 142 | if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 143 | &paddr, &page_size, &access) == 0) { |
| 144 | return paddr; |
| 145 | } |
| 146 | return ~0; |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 147 | } |
| 148 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 149 | static uint32_t relocated_vector(CPUXtensaState *env, uint32_t vector) |
Max Filippov | 97836ce | 2011-09-06 03:55:51 +0400 | [diff] [blame] | 150 | { |
| 151 | if (xtensa_option_enabled(env->config, |
| 152 | XTENSA_OPTION_RELOCATABLE_VECTOR)) { |
| 153 | return vector - env->config->vecbase + env->sregs[VECBASE]; |
| 154 | } else { |
| 155 | return vector; |
| 156 | } |
| 157 | } |
| 158 | |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 159 | /*! |
| 160 | * Handle penging IRQ. |
| 161 | * For the high priority interrupt jump to the corresponding interrupt vector. |
| 162 | * For the level-1 interrupt convert it to either user, kernel or double |
| 163 | * exception with the 'level-1 interrupt' exception cause. |
| 164 | */ |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 165 | static void handle_interrupt(CPUXtensaState *env) |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 166 | { |
| 167 | int level = env->pending_irq_level; |
| 168 | |
| 169 | if (level > xtensa_get_cintlevel(env) && |
| 170 | level <= env->config->nlevel && |
| 171 | (env->config->level_mask[level] & |
| 172 | env->sregs[INTSET] & |
| 173 | env->sregs[INTENABLE])) { |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 174 | CPUState *cs = CPU(xtensa_env_get_cpu(env)); |
| 175 | |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 176 | if (level > 1) { |
| 177 | env->sregs[EPC1 + level - 1] = env->pc; |
| 178 | env->sregs[EPS2 + level - 2] = env->sregs[PS]; |
| 179 | env->sregs[PS] = |
| 180 | (env->sregs[PS] & ~PS_INTLEVEL) | level | PS_EXCM; |
Max Filippov | 97836ce | 2011-09-06 03:55:51 +0400 | [diff] [blame] | 181 | env->pc = relocated_vector(env, |
| 182 | env->config->interrupt_vector[level]); |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 183 | } else { |
| 184 | env->sregs[EXCCAUSE] = LEVEL1_INTERRUPT_CAUSE; |
| 185 | |
| 186 | if (env->sregs[PS] & PS_EXCM) { |
| 187 | if (env->config->ndepc) { |
| 188 | env->sregs[DEPC] = env->pc; |
| 189 | } else { |
| 190 | env->sregs[EPC1] = env->pc; |
| 191 | } |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 192 | cs->exception_index = EXC_DOUBLE; |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 193 | } else { |
| 194 | env->sregs[EPC1] = env->pc; |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 195 | cs->exception_index = |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 196 | (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL; |
| 197 | } |
| 198 | env->sregs[PS] |= PS_EXCM; |
| 199 | } |
| 200 | env->exception_taken = 1; |
| 201 | } |
| 202 | } |
| 203 | |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 204 | void xtensa_cpu_do_interrupt(CPUState *cs) |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 205 | { |
Andreas Färber | 97a8ea5 | 2013-02-02 10:57:51 +0100 | [diff] [blame] | 206 | XtensaCPU *cpu = XTENSA_CPU(cs); |
| 207 | CPUXtensaState *env = &cpu->env; |
| 208 | |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 209 | if (cs->exception_index == EXC_IRQ) { |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 210 | qemu_log_mask(CPU_LOG_INT, |
| 211 | "%s(EXC_IRQ) level = %d, cintlevel = %d, " |
| 212 | "pc = %08x, a0 = %08x, ps = %08x, " |
| 213 | "intset = %08x, intenable = %08x, " |
| 214 | "ccount = %08x\n", |
| 215 | __func__, env->pending_irq_level, xtensa_get_cintlevel(env), |
| 216 | env->pc, env->regs[0], env->sregs[PS], |
| 217 | env->sregs[INTSET], env->sregs[INTENABLE], |
| 218 | env->sregs[CCOUNT]); |
| 219 | handle_interrupt(env); |
| 220 | } |
| 221 | |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 222 | switch (cs->exception_index) { |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 223 | case EXC_WINDOW_OVERFLOW4: |
| 224 | case EXC_WINDOW_UNDERFLOW4: |
| 225 | case EXC_WINDOW_OVERFLOW8: |
| 226 | case EXC_WINDOW_UNDERFLOW8: |
| 227 | case EXC_WINDOW_OVERFLOW12: |
| 228 | case EXC_WINDOW_UNDERFLOW12: |
| 229 | case EXC_KERNEL: |
| 230 | case EXC_USER: |
| 231 | case EXC_DOUBLE: |
Max Filippov | e61dc8f | 2012-01-13 09:21:32 +0400 | [diff] [blame] | 232 | case EXC_DEBUG: |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 233 | qemu_log_mask(CPU_LOG_INT, "%s(%d) " |
| 234 | "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n", |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 235 | __func__, cs->exception_index, |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 236 | env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]); |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 237 | if (env->config->exception_vector[cs->exception_index]) { |
Max Filippov | 97836ce | 2011-09-06 03:55:51 +0400 | [diff] [blame] | 238 | env->pc = relocated_vector(env, |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 239 | env->config->exception_vector[cs->exception_index]); |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 240 | env->exception_taken = 1; |
| 241 | } else { |
| 242 | qemu_log("%s(pc = %08x) bad exception_index: %d\n", |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 243 | __func__, env->pc, cs->exception_index); |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 244 | } |
| 245 | break; |
| 246 | |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 247 | case EXC_IRQ: |
| 248 | break; |
| 249 | |
| 250 | default: |
| 251 | qemu_log("%s(pc = %08x) unknown exception_index: %d\n", |
Andreas Färber | 2710342 | 2013-08-26 08:31:06 +0200 | [diff] [blame] | 252 | __func__, env->pc, cs->exception_index); |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 253 | break; |
Max Filippov | 40643d7 | 2011-09-06 03:55:41 +0400 | [diff] [blame] | 254 | } |
Max Filippov | b994e91 | 2011-09-06 03:55:48 +0400 | [diff] [blame] | 255 | check_interrupts(env); |
Max Filippov | 2328826 | 2011-09-06 03:55:25 +0400 | [diff] [blame] | 256 | } |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 257 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 258 | static void reset_tlb_mmu_all_ways(CPUXtensaState *env, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 259 | const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) |
| 260 | { |
| 261 | unsigned wi, ei; |
| 262 | |
| 263 | for (wi = 0; wi < tlb->nways; ++wi) { |
| 264 | for (ei = 0; ei < tlb->way_size[wi]; ++ei) { |
| 265 | entry[wi][ei].asid = 0; |
| 266 | entry[wi][ei].variable = true; |
| 267 | } |
| 268 | } |
| 269 | } |
| 270 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 271 | static void reset_tlb_mmu_ways56(CPUXtensaState *env, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 272 | const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) |
| 273 | { |
| 274 | if (!tlb->varway56) { |
| 275 | static const xtensa_tlb_entry way5[] = { |
| 276 | { |
| 277 | .vaddr = 0xd0000000, |
| 278 | .paddr = 0, |
| 279 | .asid = 1, |
| 280 | .attr = 7, |
| 281 | .variable = false, |
| 282 | }, { |
| 283 | .vaddr = 0xd8000000, |
| 284 | .paddr = 0, |
| 285 | .asid = 1, |
| 286 | .attr = 3, |
| 287 | .variable = false, |
| 288 | } |
| 289 | }; |
| 290 | static const xtensa_tlb_entry way6[] = { |
| 291 | { |
| 292 | .vaddr = 0xe0000000, |
| 293 | .paddr = 0xf0000000, |
| 294 | .asid = 1, |
| 295 | .attr = 7, |
| 296 | .variable = false, |
| 297 | }, { |
| 298 | .vaddr = 0xf0000000, |
| 299 | .paddr = 0xf0000000, |
| 300 | .asid = 1, |
| 301 | .attr = 3, |
| 302 | .variable = false, |
| 303 | } |
| 304 | }; |
| 305 | memcpy(entry[5], way5, sizeof(way5)); |
| 306 | memcpy(entry[6], way6, sizeof(way6)); |
| 307 | } else { |
| 308 | uint32_t ei; |
| 309 | for (ei = 0; ei < 8; ++ei) { |
| 310 | entry[6][ei].vaddr = ei << 29; |
| 311 | entry[6][ei].paddr = ei << 29; |
| 312 | entry[6][ei].asid = 1; |
Max Filippov | 0fdd2e1 | 2011-11-22 11:59:16 +0400 | [diff] [blame] | 313 | entry[6][ei].attr = 3; |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 314 | } |
| 315 | } |
| 316 | } |
| 317 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 318 | static void reset_tlb_region_way0(CPUXtensaState *env, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 319 | xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) |
| 320 | { |
| 321 | unsigned ei; |
| 322 | |
| 323 | for (ei = 0; ei < 8; ++ei) { |
| 324 | entry[0][ei].vaddr = ei << 29; |
| 325 | entry[0][ei].paddr = ei << 29; |
| 326 | entry[0][ei].asid = 1; |
| 327 | entry[0][ei].attr = 2; |
| 328 | entry[0][ei].variable = true; |
| 329 | } |
| 330 | } |
| 331 | |
Andreas Färber | 5087a72 | 2012-04-11 18:24:49 +0200 | [diff] [blame] | 332 | void reset_mmu(CPUXtensaState *env) |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 333 | { |
| 334 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { |
| 335 | env->sregs[RASID] = 0x04030201; |
| 336 | env->sregs[ITLBCFG] = 0; |
| 337 | env->sregs[DTLBCFG] = 0; |
| 338 | env->autorefill_idx = 0; |
| 339 | reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb); |
| 340 | reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb); |
| 341 | reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb); |
| 342 | reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb); |
| 343 | } else { |
| 344 | reset_tlb_region_way0(env, env->itlb); |
| 345 | reset_tlb_region_way0(env, env->dtlb); |
| 346 | } |
| 347 | } |
| 348 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 349 | static unsigned get_ring(const CPUXtensaState *env, uint8_t asid) |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 350 | { |
| 351 | unsigned i; |
| 352 | for (i = 0; i < 4; ++i) { |
| 353 | if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) { |
| 354 | return i; |
| 355 | } |
| 356 | } |
| 357 | return 0xff; |
| 358 | } |
| 359 | |
| 360 | /*! |
| 361 | * Lookup xtensa TLB for the given virtual address. |
| 362 | * See ISA, 4.6.2.2 |
| 363 | * |
| 364 | * \param pwi: [out] way index |
| 365 | * \param pei: [out] entry index |
| 366 | * \param pring: [out] access ring |
| 367 | * \return 0 if ok, exception cause code otherwise |
| 368 | */ |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 369 | int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 370 | uint32_t *pwi, uint32_t *pei, uint8_t *pring) |
| 371 | { |
| 372 | const xtensa_tlb *tlb = dtlb ? |
| 373 | &env->config->dtlb : &env->config->itlb; |
| 374 | const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ? |
| 375 | env->dtlb : env->itlb; |
| 376 | |
| 377 | int nhits = 0; |
| 378 | unsigned wi; |
| 379 | |
| 380 | for (wi = 0; wi < tlb->nways; ++wi) { |
| 381 | uint32_t vpn; |
| 382 | uint32_t ei; |
| 383 | split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei); |
| 384 | if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) { |
| 385 | unsigned ring = get_ring(env, entry[wi][ei].asid); |
| 386 | if (ring < 4) { |
| 387 | if (++nhits > 1) { |
| 388 | return dtlb ? |
| 389 | LOAD_STORE_TLB_MULTI_HIT_CAUSE : |
| 390 | INST_TLB_MULTI_HIT_CAUSE; |
| 391 | } |
| 392 | *pwi = wi; |
| 393 | *pei = ei; |
| 394 | *pring = ring; |
| 395 | } |
| 396 | } |
| 397 | } |
| 398 | return nhits ? 0 : |
| 399 | (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE); |
| 400 | } |
| 401 | |
| 402 | /*! |
| 403 | * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask. |
| 404 | * See ISA, 4.6.5.10 |
| 405 | */ |
| 406 | static unsigned mmu_attr_to_access(uint32_t attr) |
| 407 | { |
| 408 | unsigned access = 0; |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 409 | |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 410 | if (attr < 12) { |
| 411 | access |= PAGE_READ; |
| 412 | if (attr & 0x1) { |
| 413 | access |= PAGE_EXEC; |
| 414 | } |
| 415 | if (attr & 0x2) { |
| 416 | access |= PAGE_WRITE; |
| 417 | } |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 418 | |
| 419 | switch (attr & 0xc) { |
| 420 | case 0: |
| 421 | access |= PAGE_CACHE_BYPASS; |
| 422 | break; |
| 423 | |
| 424 | case 4: |
| 425 | access |= PAGE_CACHE_WB; |
| 426 | break; |
| 427 | |
| 428 | case 8: |
| 429 | access |= PAGE_CACHE_WT; |
| 430 | break; |
| 431 | } |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 432 | } else if (attr == 13) { |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 433 | access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE; |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 434 | } |
| 435 | return access; |
| 436 | } |
| 437 | |
| 438 | /*! |
| 439 | * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask. |
| 440 | * See ISA, 4.6.3.3 |
| 441 | */ |
| 442 | static unsigned region_attr_to_access(uint32_t attr) |
| 443 | { |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 444 | static const unsigned access[16] = { |
| 445 | [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, |
| 446 | [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, |
| 447 | [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, |
| 448 | [3] = PAGE_EXEC | PAGE_CACHE_WB, |
| 449 | [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, |
| 450 | [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, |
| 451 | [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, |
| 452 | }; |
| 453 | |
| 454 | return access[attr & 0xf]; |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 455 | } |
| 456 | |
Max Filippov | 4e41d2f | 2012-12-05 07:15:21 +0400 | [diff] [blame] | 457 | /*! |
| 458 | * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask. |
| 459 | * See ISA, A.2.14 The Cache Attribute Register |
| 460 | */ |
| 461 | static unsigned cacheattr_attr_to_access(uint32_t attr) |
| 462 | { |
| 463 | static const unsigned access[16] = { |
| 464 | [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, |
| 465 | [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, |
| 466 | [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, |
| 467 | [3] = PAGE_EXEC | PAGE_CACHE_WB, |
| 468 | [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, |
| 469 | [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, |
| 470 | }; |
| 471 | |
| 472 | return access[attr & 0xf]; |
| 473 | } |
| 474 | |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 475 | static bool is_access_granted(unsigned access, int is_write) |
| 476 | { |
| 477 | switch (is_write) { |
| 478 | case 0: |
| 479 | return access & PAGE_READ; |
| 480 | |
| 481 | case 1: |
| 482 | return access & PAGE_WRITE; |
| 483 | |
| 484 | case 2: |
| 485 | return access & PAGE_EXEC; |
| 486 | |
| 487 | default: |
| 488 | return 0; |
| 489 | } |
| 490 | } |
| 491 | |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 492 | static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 493 | |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 494 | static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 495 | uint32_t vaddr, int is_write, int mmu_idx, |
Max Filippov | 57705a6 | 2012-05-27 18:34:53 +0400 | [diff] [blame] | 496 | uint32_t *paddr, uint32_t *page_size, unsigned *access, |
| 497 | bool may_lookup_pt) |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 498 | { |
| 499 | bool dtlb = is_write != 2; |
| 500 | uint32_t wi; |
| 501 | uint32_t ei; |
| 502 | uint8_t ring; |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 503 | uint32_t vpn; |
| 504 | uint32_t pte; |
| 505 | const xtensa_tlb_entry *entry = NULL; |
| 506 | xtensa_tlb_entry tmp_entry; |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 507 | int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); |
| 508 | |
| 509 | if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) && |
Max Filippov | 57705a6 | 2012-05-27 18:34:53 +0400 | [diff] [blame] | 510 | may_lookup_pt && get_pte(env, vaddr, &pte) == 0) { |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 511 | ring = (pte >> 4) & 0x3; |
| 512 | wi = 0; |
| 513 | split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); |
| 514 | |
| 515 | if (update_tlb) { |
| 516 | wi = ++env->autorefill_idx & 0x3; |
| 517 | xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte); |
| 518 | env->sregs[EXCVADDR] = vaddr; |
| 519 | qemu_log("%s: autorefill(%08x): %08x -> %08x\n", |
| 520 | __func__, vaddr, vpn, pte); |
| 521 | } else { |
| 522 | xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte); |
| 523 | entry = &tmp_entry; |
| 524 | } |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 525 | ret = 0; |
| 526 | } |
| 527 | if (ret != 0) { |
| 528 | return ret; |
| 529 | } |
| 530 | |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 531 | if (entry == NULL) { |
| 532 | entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); |
| 533 | } |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 534 | |
| 535 | if (ring < mmu_idx) { |
| 536 | return dtlb ? |
| 537 | LOAD_STORE_PRIVILEGE_CAUSE : |
| 538 | INST_FETCH_PRIVILEGE_CAUSE; |
| 539 | } |
| 540 | |
Max Filippov | 659f807 | 2012-12-13 04:13:41 +0400 | [diff] [blame] | 541 | *access = mmu_attr_to_access(entry->attr) & |
| 542 | ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 543 | if (!is_access_granted(*access, is_write)) { |
| 544 | return dtlb ? |
| 545 | (is_write ? |
| 546 | STORE_PROHIBITED_CAUSE : |
| 547 | LOAD_PROHIBITED_CAUSE) : |
| 548 | INST_FETCH_PROHIBITED_CAUSE; |
| 549 | } |
| 550 | |
| 551 | *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi)); |
| 552 | *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; |
| 553 | |
| 554 | return 0; |
| 555 | } |
| 556 | |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 557 | static int get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 558 | { |
Andreas Färber | 1cf5ccb | 2014-03-09 20:02:29 +0100 | [diff] [blame] | 559 | CPUState *cs = CPU(xtensa_env_get_cpu(env)); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 560 | uint32_t paddr; |
| 561 | uint32_t page_size; |
| 562 | unsigned access; |
| 563 | uint32_t pt_vaddr = |
| 564 | (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc; |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 565 | int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, |
Max Filippov | 57705a6 | 2012-05-27 18:34:53 +0400 | [diff] [blame] | 566 | &paddr, &page_size, &access, false); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 567 | |
| 568 | qemu_log("%s: trying autorefill(%08x) -> %08x\n", __func__, |
| 569 | vaddr, ret ? ~0 : paddr); |
| 570 | |
| 571 | if (ret == 0) { |
Edgar E. Iglesias | fdfba1a | 2013-11-15 14:46:38 +0100 | [diff] [blame] | 572 | *pte = ldl_phys(cs->as, paddr); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 573 | } |
| 574 | return ret; |
| 575 | } |
| 576 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 577 | static int get_physical_addr_region(CPUXtensaState *env, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 578 | uint32_t vaddr, int is_write, int mmu_idx, |
| 579 | uint32_t *paddr, uint32_t *page_size, unsigned *access) |
| 580 | { |
| 581 | bool dtlb = is_write != 2; |
| 582 | uint32_t wi = 0; |
| 583 | uint32_t ei = (vaddr >> 29) & 0x7; |
| 584 | const xtensa_tlb_entry *entry = |
| 585 | xtensa_tlb_get_entry(env, dtlb, wi, ei); |
| 586 | |
| 587 | *access = region_attr_to_access(entry->attr); |
| 588 | if (!is_access_granted(*access, is_write)) { |
| 589 | return dtlb ? |
| 590 | (is_write ? |
| 591 | STORE_PROHIBITED_CAUSE : |
| 592 | LOAD_PROHIBITED_CAUSE) : |
| 593 | INST_FETCH_PROHIBITED_CAUSE; |
| 594 | } |
| 595 | |
| 596 | *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK); |
| 597 | *page_size = ~REGION_PAGE_MASK + 1; |
| 598 | |
| 599 | return 0; |
| 600 | } |
| 601 | |
| 602 | /*! |
| 603 | * Convert virtual address to physical addr. |
| 604 | * MMU may issue pagewalk and change xtensa autorefill TLB way entry. |
| 605 | * |
| 606 | * \return 0 if ok, exception cause code otherwise |
| 607 | */ |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 608 | int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 609 | uint32_t vaddr, int is_write, int mmu_idx, |
| 610 | uint32_t *paddr, uint32_t *page_size, unsigned *access) |
| 611 | { |
| 612 | if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { |
Max Filippov | ae4e798 | 2012-05-27 18:34:52 +0400 | [diff] [blame] | 613 | return get_physical_addr_mmu(env, update_tlb, |
Max Filippov | 57705a6 | 2012-05-27 18:34:53 +0400 | [diff] [blame] | 614 | vaddr, is_write, mmu_idx, paddr, page_size, access, true); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 615 | } else if (xtensa_option_bits_enabled(env->config, |
| 616 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | |
| 617 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) { |
| 618 | return get_physical_addr_region(env, vaddr, is_write, mmu_idx, |
| 619 | paddr, page_size, access); |
| 620 | } else { |
| 621 | *paddr = vaddr; |
| 622 | *page_size = TARGET_PAGE_SIZE; |
Max Filippov | 4e41d2f | 2012-12-05 07:15:21 +0400 | [diff] [blame] | 623 | *access = cacheattr_attr_to_access( |
| 624 | env->sregs[CACHEATTR] >> ((vaddr & 0xe0000000) >> 27)); |
Max Filippov | b67ea0c | 2011-09-06 03:55:53 +0400 | [diff] [blame] | 625 | return 0; |
| 626 | } |
| 627 | } |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 628 | |
| 629 | static void dump_tlb(FILE *f, fprintf_function cpu_fprintf, |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 630 | CPUXtensaState *env, bool dtlb) |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 631 | { |
| 632 | unsigned wi, ei; |
| 633 | const xtensa_tlb *conf = |
| 634 | dtlb ? &env->config->dtlb : &env->config->itlb; |
| 635 | unsigned (*attr_to_access)(uint32_t) = |
| 636 | xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ? |
| 637 | mmu_attr_to_access : region_attr_to_access; |
| 638 | |
| 639 | for (wi = 0; wi < conf->nways; ++wi) { |
| 640 | uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; |
| 641 | const char *sz_text; |
| 642 | bool print_header = true; |
| 643 | |
| 644 | if (sz >= 0x100000) { |
| 645 | sz >>= 20; |
| 646 | sz_text = "MB"; |
| 647 | } else { |
| 648 | sz >>= 10; |
| 649 | sz_text = "KB"; |
| 650 | } |
| 651 | |
| 652 | for (ei = 0; ei < conf->way_size[wi]; ++ei) { |
| 653 | const xtensa_tlb_entry *entry = |
| 654 | xtensa_tlb_get_entry(env, dtlb, wi, ei); |
| 655 | |
| 656 | if (entry->asid) { |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 657 | static const char * const cache_text[8] = { |
| 658 | [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass", |
| 659 | [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT", |
| 660 | [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB", |
| 661 | [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate", |
| 662 | }; |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 663 | unsigned access = attr_to_access(entry->attr); |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 664 | unsigned cache_idx = (access & PAGE_CACHE_MASK) >> |
| 665 | PAGE_CACHE_SHIFT; |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 666 | |
| 667 | if (print_header) { |
| 668 | print_header = false; |
| 669 | cpu_fprintf(f, "Way %u (%d %s)\n", wi, sz, sz_text); |
| 670 | cpu_fprintf(f, |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 671 | "\tVaddr Paddr ASID Attr RWX Cache\n" |
| 672 | "\t---------- ---------- ---- ---- --- -------\n"); |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 673 | } |
| 674 | cpu_fprintf(f, |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 675 | "\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %-7s\n", |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 676 | entry->vaddr, |
| 677 | entry->paddr, |
| 678 | entry->asid, |
| 679 | entry->attr, |
| 680 | (access & PAGE_READ) ? 'R' : '-', |
| 681 | (access & PAGE_WRITE) ? 'W' : '-', |
Max Filippov | fcc803d | 2012-12-05 07:15:20 +0400 | [diff] [blame] | 682 | (access & PAGE_EXEC) ? 'X' : '-', |
| 683 | cache_text[cache_idx] ? cache_text[cache_idx] : |
| 684 | "Invalid"); |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 685 | } |
| 686 | } |
| 687 | } |
| 688 | } |
| 689 | |
Andreas Färber | 97129ac | 2012-03-14 01:38:23 +0100 | [diff] [blame] | 690 | void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env) |
Max Filippov | 692f737 | 2012-01-07 20:02:40 +0400 | [diff] [blame] | 691 | { |
| 692 | if (xtensa_option_bits_enabled(env->config, |
| 693 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | |
| 694 | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) | |
| 695 | XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) { |
| 696 | |
| 697 | cpu_fprintf(f, "ITLB:\n"); |
| 698 | dump_tlb(f, cpu_fprintf, env, false); |
| 699 | cpu_fprintf(f, "\nDTLB:\n"); |
| 700 | dump_tlb(f, cpu_fprintf, env, true); |
| 701 | } else { |
| 702 | cpu_fprintf(f, "No TLB for this CPU core\n"); |
| 703 | } |
| 704 | } |