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thsd34cab92007-04-02 01:10:46 +00001/*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010024#include "hw/hw.h"
25#include "hw/loader.h"
Paolo Bonzini28ecbae2012-11-28 12:06:30 +010026#include "ui/console.h"
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010027#include "hw/pci/pci.h"
thsd34cab92007-04-02 01:10:46 +000028
Jan Kiszkaca0508d2011-08-22 19:12:09 +020029#undef VERBOSE
thsd34cab92007-04-02 01:10:46 +000030#define HW_RECT_ACCEL
31#define HW_FILL_ACCEL
32#define HW_MOUSE_ACCEL
33
Paolo Bonzini83c9f4c2013-02-04 15:40:22 +010034#include "hw/vga_int.h"
BALATON Zoltan5b9575c2012-11-03 12:47:08 +010035
36/* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */
thsd34cab92007-04-02 01:10:46 +000037
38struct vmsvga_state_s {
Avi Kivity4e12cd92009-05-03 22:25:16 +030039 VGACommonState vga;
thsd34cab92007-04-02 01:10:46 +000040
thsd34cab92007-04-02 01:10:46 +000041 int invalidated;
BALATON Zoltan1f202562012-11-04 18:41:59 +010042 int depth;
43 int bypp;
thsd34cab92007-04-02 01:10:46 +000044 int enable;
45 int config;
46 struct {
47 int id;
48 int x;
49 int y;
50 int on;
51 } cursor;
52
thsd34cab92007-04-02 01:10:46 +000053 int index;
54 int scratch_size;
55 uint32_t *scratch;
56 int new_width;
57 int new_height;
58 uint32_t guest;
59 uint32_t svgaid;
BALATON Zoltan1f202562012-11-04 18:41:59 +010060 uint32_t wred;
61 uint32_t wgreen;
62 uint32_t wblue;
thsd34cab92007-04-02 01:10:46 +000063 int syncing;
thsd34cab92007-04-02 01:10:46 +000064
Avi Kivityb1950432011-08-08 16:08:57 +030065 MemoryRegion fifo_ram;
Dave Airlief351d052009-12-18 08:08:06 +100066 uint8_t *fifo_ptr;
67 unsigned int fifo_size;
Dave Airlief351d052009-12-18 08:08:06 +100068
thsd34cab92007-04-02 01:10:46 +000069 union {
70 uint32_t *fifo;
Stefan Weil541dc0d2011-08-31 12:38:01 +020071 struct QEMU_PACKED {
thsd34cab92007-04-02 01:10:46 +000072 uint32_t min;
73 uint32_t max;
74 uint32_t next_cmd;
75 uint32_t stop;
76 /* Add registers here when adding capabilities. */
77 uint32_t fifo[0];
78 } *cmd;
79 };
80
BALATON Zoltan0d793792012-11-03 12:47:08 +010081#define REDRAW_FIFO_LEN 512
thsd34cab92007-04-02 01:10:46 +000082 struct vmsvga_rect_s {
83 int x, y, w, h;
84 } redraw_fifo[REDRAW_FIFO_LEN];
85 int redraw_fifo_first, redraw_fifo_last;
86};
87
88struct pci_vmsvga_state_s {
89 PCIDevice card;
90 struct vmsvga_state_s chip;
Avi Kivityb1950432011-08-08 16:08:57 +030091 MemoryRegion io_bar;
thsd34cab92007-04-02 01:10:46 +000092};
93
BALATON Zoltan0d793792012-11-03 12:47:08 +010094#define SVGA_MAGIC 0x900000UL
95#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
96#define SVGA_ID_0 SVGA_MAKE_ID(0)
97#define SVGA_ID_1 SVGA_MAKE_ID(1)
98#define SVGA_ID_2 SVGA_MAKE_ID(2)
thsd34cab92007-04-02 01:10:46 +000099
BALATON Zoltan0d793792012-11-03 12:47:08 +0100100#define SVGA_LEGACY_BASE_PORT 0x4560
101#define SVGA_INDEX_PORT 0x0
102#define SVGA_VALUE_PORT 0x1
103#define SVGA_BIOS_PORT 0x2
thsd34cab92007-04-02 01:10:46 +0000104
105#define SVGA_VERSION_2
106
107#ifdef SVGA_VERSION_2
BALATON Zoltan0d793792012-11-03 12:47:08 +0100108# define SVGA_ID SVGA_ID_2
109# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
110# define SVGA_IO_MUL 1
111# define SVGA_FIFO_SIZE 0x10000
112# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
thsd34cab92007-04-02 01:10:46 +0000113#else
BALATON Zoltan0d793792012-11-03 12:47:08 +0100114# define SVGA_ID SVGA_ID_1
115# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
116# define SVGA_IO_MUL 4
117# define SVGA_FIFO_SIZE 0x10000
118# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
thsd34cab92007-04-02 01:10:46 +0000119#endif
120
121enum {
122 /* ID 0, 1 and 2 registers */
123 SVGA_REG_ID = 0,
124 SVGA_REG_ENABLE = 1,
125 SVGA_REG_WIDTH = 2,
126 SVGA_REG_HEIGHT = 3,
127 SVGA_REG_MAX_WIDTH = 4,
128 SVGA_REG_MAX_HEIGHT = 5,
129 SVGA_REG_DEPTH = 6,
BALATON Zoltan0d793792012-11-03 12:47:08 +0100130 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
thsd34cab92007-04-02 01:10:46 +0000131 SVGA_REG_PSEUDOCOLOR = 8,
132 SVGA_REG_RED_MASK = 9,
133 SVGA_REG_GREEN_MASK = 10,
134 SVGA_REG_BLUE_MASK = 11,
135 SVGA_REG_BYTES_PER_LINE = 12,
136 SVGA_REG_FB_START = 13,
137 SVGA_REG_FB_OFFSET = 14,
138 SVGA_REG_VRAM_SIZE = 15,
139 SVGA_REG_FB_SIZE = 16,
140
141 /* ID 1 and 2 registers */
142 SVGA_REG_CAPABILITIES = 17,
BALATON Zoltan0d793792012-11-03 12:47:08 +0100143 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
thsd34cab92007-04-02 01:10:46 +0000144 SVGA_REG_MEM_SIZE = 19,
BALATON Zoltan0d793792012-11-03 12:47:08 +0100145 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
146 SVGA_REG_SYNC = 21, /* Write to force synchronization */
147 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
148 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
149 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
150 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
151 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
152 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
153 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
154 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
155 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
156 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
157 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
thsd34cab92007-04-02 01:10:46 +0000158
BALATON Zoltan0d793792012-11-03 12:47:08 +0100159 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
thsd34cab92007-04-02 01:10:46 +0000160 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
161 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
162};
163
BALATON Zoltan0d793792012-11-03 12:47:08 +0100164#define SVGA_CAP_NONE 0
165#define SVGA_CAP_RECT_FILL (1 << 0)
166#define SVGA_CAP_RECT_COPY (1 << 1)
167#define SVGA_CAP_RECT_PAT_FILL (1 << 2)
168#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
169#define SVGA_CAP_RASTER_OP (1 << 4)
170#define SVGA_CAP_CURSOR (1 << 5)
171#define SVGA_CAP_CURSOR_BYPASS (1 << 6)
172#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
173#define SVGA_CAP_8BIT_EMULATION (1 << 8)
174#define SVGA_CAP_ALPHA_CURSOR (1 << 9)
175#define SVGA_CAP_GLYPH (1 << 10)
176#define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
177#define SVGA_CAP_OFFSCREEN_1 (1 << 12)
178#define SVGA_CAP_ALPHA_BLEND (1 << 13)
179#define SVGA_CAP_3D (1 << 14)
180#define SVGA_CAP_EXTENDED_FIFO (1 << 15)
181#define SVGA_CAP_MULTIMON (1 << 16)
182#define SVGA_CAP_PITCHLOCK (1 << 17)
thsd34cab92007-04-02 01:10:46 +0000183
184/*
185 * FIFO offsets (seen as an array of 32-bit words)
186 */
187enum {
188 /*
189 * The original defined FIFO offsets
190 */
191 SVGA_FIFO_MIN = 0,
BALATON Zoltan0d793792012-11-03 12:47:08 +0100192 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
thsd34cab92007-04-02 01:10:46 +0000193 SVGA_FIFO_NEXT_CMD,
194 SVGA_FIFO_STOP,
195
196 /*
197 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
198 */
199 SVGA_FIFO_CAPABILITIES = 4,
200 SVGA_FIFO_FLAGS,
201 SVGA_FIFO_FENCE,
202 SVGA_FIFO_3D_HWVERSION,
203 SVGA_FIFO_PITCHLOCK,
204};
205
BALATON Zoltan0d793792012-11-03 12:47:08 +0100206#define SVGA_FIFO_CAP_NONE 0
207#define SVGA_FIFO_CAP_FENCE (1 << 0)
208#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
209#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
thsd34cab92007-04-02 01:10:46 +0000210
BALATON Zoltan0d793792012-11-03 12:47:08 +0100211#define SVGA_FIFO_FLAG_NONE 0
212#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
thsd34cab92007-04-02 01:10:46 +0000213
214/* These values can probably be changed arbitrarily. */
BALATON Zoltan0d793792012-11-03 12:47:08 +0100215#define SVGA_SCRATCH_SIZE 0x8000
216#define SVGA_MAX_WIDTH 2360
217#define SVGA_MAX_HEIGHT 1770
thsd34cab92007-04-02 01:10:46 +0000218
219#ifdef VERBOSE
BALATON Zoltan0d793792012-11-03 12:47:08 +0100220# define GUEST_OS_BASE 0x5001
thsd34cab92007-04-02 01:10:46 +0000221static const char *vmsvga_guest_id[] = {
balrogf707cfb2007-05-13 13:26:49 +0000222 [0x00] = "Dos",
223 [0x01] = "Windows 3.1",
224 [0x02] = "Windows 95",
225 [0x03] = "Windows 98",
226 [0x04] = "Windows ME",
227 [0x05] = "Windows NT",
228 [0x06] = "Windows 2000",
229 [0x07] = "Linux",
230 [0x08] = "OS/2",
blueswir1511d2b12009-03-07 15:32:56 +0000231 [0x09] = "an unknown OS",
balrogf707cfb2007-05-13 13:26:49 +0000232 [0x0a] = "BSD",
233 [0x0b] = "Whistler",
blueswir1511d2b12009-03-07 15:32:56 +0000234 [0x0c] = "an unknown OS",
235 [0x0d] = "an unknown OS",
236 [0x0e] = "an unknown OS",
237 [0x0f] = "an unknown OS",
238 [0x10] = "an unknown OS",
239 [0x11] = "an unknown OS",
240 [0x12] = "an unknown OS",
241 [0x13] = "an unknown OS",
242 [0x14] = "an unknown OS",
balrogf707cfb2007-05-13 13:26:49 +0000243 [0x15] = "Windows 2003",
thsd34cab92007-04-02 01:10:46 +0000244};
245#endif
246
247enum {
248 SVGA_CMD_INVALID_CMD = 0,
249 SVGA_CMD_UPDATE = 1,
250 SVGA_CMD_RECT_FILL = 2,
251 SVGA_CMD_RECT_COPY = 3,
252 SVGA_CMD_DEFINE_BITMAP = 4,
253 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
254 SVGA_CMD_DEFINE_PIXMAP = 6,
255 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
256 SVGA_CMD_RECT_BITMAP_FILL = 8,
257 SVGA_CMD_RECT_PIXMAP_FILL = 9,
258 SVGA_CMD_RECT_BITMAP_COPY = 10,
259 SVGA_CMD_RECT_PIXMAP_COPY = 11,
260 SVGA_CMD_FREE_OBJECT = 12,
261 SVGA_CMD_RECT_ROP_FILL = 13,
262 SVGA_CMD_RECT_ROP_COPY = 14,
263 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
264 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
265 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
266 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
267 SVGA_CMD_DEFINE_CURSOR = 19,
268 SVGA_CMD_DISPLAY_CURSOR = 20,
269 SVGA_CMD_MOVE_CURSOR = 21,
270 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
271 SVGA_CMD_DRAW_GLYPH = 23,
272 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
273 SVGA_CMD_UPDATE_VERBOSE = 25,
274 SVGA_CMD_SURFACE_FILL = 26,
275 SVGA_CMD_SURFACE_COPY = 27,
276 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
277 SVGA_CMD_FRONT_ROP_FILL = 29,
278 SVGA_CMD_FENCE = 30,
279};
280
281/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
282enum {
283 SVGA_CURSOR_ON_HIDE = 0,
284 SVGA_CURSOR_ON_SHOW = 1,
285 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
286 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
287};
288
289static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
290 int x, int y, int w, int h)
291{
balroga8fbaf92008-03-06 20:43:34 +0000292 int line;
293 int bypl;
294 int width;
295 int start;
296 uint8_t *src;
297 uint8_t *dst;
298
Michael Tokarev8cb6bfb2013-01-25 21:23:24 +0400299 if (x < 0) {
300 fprintf(stderr, "%s: update x was < 0 (%d)\n", __func__, x);
301 w += x;
302 x = 0;
303 }
304 if (w < 0) {
305 fprintf(stderr, "%s: update w was < 0 (%d)\n", __func__, w);
306 w = 0;
307 }
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100308 if (x + w > ds_get_width(s->vga.ds)) {
balroga8fbaf92008-03-06 20:43:34 +0000309 fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
BALATON Zoltan0d793792012-11-03 12:47:08 +0100310 __func__, x, w);
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100311 x = MIN(x, ds_get_width(s->vga.ds));
312 w = ds_get_width(s->vga.ds) - x;
balroga8fbaf92008-03-06 20:43:34 +0000313 }
314
Michael Tokarev8cb6bfb2013-01-25 21:23:24 +0400315 if (y < 0) {
316 fprintf(stderr, "%s: update y was < 0 (%d)\n", __func__, y);
317 h += y;
318 y = 0;
319 }
320 if (h < 0) {
321 fprintf(stderr, "%s: update h was < 0 (%d)\n", __func__, h);
322 h = 0;
323 }
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100324 if (y + h > ds_get_height(s->vga.ds)) {
balroga8fbaf92008-03-06 20:43:34 +0000325 fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
BALATON Zoltan0d793792012-11-03 12:47:08 +0100326 __func__, y, h);
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100327 y = MIN(y, ds_get_height(s->vga.ds));
328 h = ds_get_height(s->vga.ds) - y;
balroga8fbaf92008-03-06 20:43:34 +0000329 }
330
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100331 bypl = ds_get_linesize(s->vga.ds);
332 width = ds_get_bytes_per_pixel(s->vga.ds) * w;
333 start = ds_get_bytes_per_pixel(s->vga.ds) * x + bypl * y;
Avi Kivity4e12cd92009-05-03 22:25:16 +0300334 src = s->vga.vram_ptr + start;
335 dst = ds_get_data(s->vga.ds) + start;
thsd34cab92007-04-02 01:10:46 +0000336
BALATON Zoltan0d793792012-11-03 12:47:08 +0100337 for (line = h; line > 0; line--, src += bypl, dst += bypl) {
thsd34cab92007-04-02 01:10:46 +0000338 memcpy(dst, src, width);
BALATON Zoltan0d793792012-11-03 12:47:08 +0100339 }
Gerd Hoffmanna93a4a22012-09-28 15:02:08 +0200340 dpy_gfx_update(s->vga.ds, x, y, w, h);
thsd34cab92007-04-02 01:10:46 +0000341}
342
thsd34cab92007-04-02 01:10:46 +0000343static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
344 int x, int y, int w, int h)
345{
BALATON Zoltan0d793792012-11-03 12:47:08 +0100346 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++];
347
thsd34cab92007-04-02 01:10:46 +0000348 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
349 rect->x = x;
350 rect->y = y;
351 rect->w = w;
352 rect->h = h;
353}
thsd34cab92007-04-02 01:10:46 +0000354
355static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
356{
357 struct vmsvga_rect_s *rect;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100358
thsd34cab92007-04-02 01:10:46 +0000359 if (s->invalidated) {
360 s->redraw_fifo_first = s->redraw_fifo_last;
361 return;
362 }
363 /* Overlapping region updates can be optimised out here - if someone
364 * knows a smart algorithm to do that, please share. */
365 while (s->redraw_fifo_first != s->redraw_fifo_last) {
BALATON Zoltan0d793792012-11-03 12:47:08 +0100366 rect = &s->redraw_fifo[s->redraw_fifo_first++];
thsd34cab92007-04-02 01:10:46 +0000367 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
368 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
369 }
370}
371
372#ifdef HW_RECT_ACCEL
373static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
374 int x0, int y0, int x1, int y1, int w, int h)
375{
Avi Kivity4e12cd92009-05-03 22:25:16 +0300376 uint8_t *vram = s->vga.vram_ptr;
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100377 int bypl = ds_get_linesize(s->vga.ds);
378 int bypp = ds_get_bytes_per_pixel(s->vga.ds);
379 int width = bypp * w;
thsd34cab92007-04-02 01:10:46 +0000380 int line = h;
381 uint8_t *ptr[2];
382
Jan Kiszka8d121d42011-08-22 19:12:10 +0200383 if (y1 > y0) {
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100384 ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1);
385 ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1);
Jan Kiszka8d121d42011-08-22 19:12:10 +0200386 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) {
387 memmove(ptr[1], ptr[0], width);
388 }
389 } else {
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100390 ptr[0] = vram + bypp * x0 + bypl * y0;
391 ptr[1] = vram + bypp * x1 + bypl * y1;
Jan Kiszka8d121d42011-08-22 19:12:10 +0200392 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) {
393 memmove(ptr[1], ptr[0], width);
thsd34cab92007-04-02 01:10:46 +0000394 }
395 }
396
397 vmsvga_update_rect_delayed(s, x1, y1, w, h);
398}
399#endif
400
401#ifdef HW_FILL_ACCEL
402static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
403 uint32_t c, int x, int y, int w, int h)
404{
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100405 int bypl = ds_get_linesize(s->vga.ds);
406 int width = ds_get_bytes_per_pixel(s->vga.ds) * w;
thsd34cab92007-04-02 01:10:46 +0000407 int line = h;
408 int column;
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100409 uint8_t *fst;
thsd34cab92007-04-02 01:10:46 +0000410 uint8_t *dst;
411 uint8_t *src;
412 uint8_t col[4];
413
Jan Kiszka8d121d42011-08-22 19:12:10 +0200414 col[0] = c;
415 col[1] = c >> 8;
416 col[2] = c >> 16;
417 col[3] = c >> 24;
thsd34cab92007-04-02 01:10:46 +0000418
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100419 fst = s->vga.vram_ptr + ds_get_bytes_per_pixel(s->vga.ds) * x + bypl * y;
420
Jan Kiszka8d121d42011-08-22 19:12:10 +0200421 if (line--) {
422 dst = fst;
423 src = col;
424 for (column = width; column > 0; column--) {
425 *(dst++) = *(src++);
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100426 if (src - col == ds_get_bytes_per_pixel(s->vga.ds)) {
Jan Kiszka8d121d42011-08-22 19:12:10 +0200427 src = col;
thsd34cab92007-04-02 01:10:46 +0000428 }
Jan Kiszka8d121d42011-08-22 19:12:10 +0200429 }
430 dst = fst;
431 for (; line > 0; line--) {
432 dst += bypl;
433 memcpy(dst, fst, width);
thsd34cab92007-04-02 01:10:46 +0000434 }
435 }
436
437 vmsvga_update_rect_delayed(s, x, y, w, h);
438}
439#endif
440
441struct vmsvga_cursor_definition_s {
442 int width;
443 int height;
444 int id;
445 int bpp;
446 int hot_x;
447 int hot_y;
448 uint32_t mask[1024];
Dave Airlie8095cb32009-12-18 08:08:11 +1000449 uint32_t image[4096];
thsd34cab92007-04-02 01:10:46 +0000450};
451
BALATON Zoltan0d793792012-11-03 12:47:08 +0100452#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
453#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
thsd34cab92007-04-02 01:10:46 +0000454
455#ifdef HW_MOUSE_ACCEL
456static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
457 struct vmsvga_cursor_definition_s *c)
458{
Gerd Hoffmannfbe6d7a2010-05-21 11:54:33 +0200459 QEMUCursor *qc;
460 int i, pixels;
461
462 qc = cursor_alloc(c->width, c->height);
463 qc->hot_x = c->hot_x;
464 qc->hot_y = c->hot_y;
465 switch (c->bpp) {
466 case 1:
BALATON Zoltan0d793792012-11-03 12:47:08 +0100467 cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image,
468 1, (void *)c->mask);
Gerd Hoffmannfbe6d7a2010-05-21 11:54:33 +0200469#ifdef DEBUG
470 cursor_print_ascii_art(qc, "vmware/mono");
471#endif
472 break;
473 case 32:
474 /* fill alpha channel from mask, set color to zero */
BALATON Zoltan0d793792012-11-03 12:47:08 +0100475 cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask,
476 1, (void *)c->mask);
Gerd Hoffmannfbe6d7a2010-05-21 11:54:33 +0200477 /* add in rgb values */
478 pixels = c->width * c->height;
479 for (i = 0; i < pixels; i++) {
480 qc->data[i] |= c->image[i] & 0xffffff;
481 }
482#ifdef DEBUG
483 cursor_print_ascii_art(qc, "vmware/32bit");
484#endif
485 break;
486 default:
487 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
BALATON Zoltan0d793792012-11-03 12:47:08 +0100488 __func__, c->bpp);
Gerd Hoffmannfbe6d7a2010-05-21 11:54:33 +0200489 cursor_put(qc);
490 qc = cursor_builtin_left_ptr();
491 }
thsd34cab92007-04-02 01:10:46 +0000492
Gerd Hoffmannbf2fde72012-09-12 07:56:45 +0200493 dpy_cursor_define(s->vga.ds, qc);
Gerd Hoffmannfbe6d7a2010-05-21 11:54:33 +0200494 cursor_put(qc);
thsd34cab92007-04-02 01:10:46 +0000495}
496#endif
497
BALATON Zoltan0d793792012-11-03 12:47:08 +0100498#define CMD(f) le32_to_cpu(s->cmd->f)
balrogff9cf2c2008-07-16 04:45:12 +0000499
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200500static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
thsd34cab92007-04-02 01:10:46 +0000501{
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200502 int num;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100503
504 if (!s->config || !s->enable) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200505 return 0;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100506 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200507 num = CMD(next_cmd) - CMD(stop);
BALATON Zoltan0d793792012-11-03 12:47:08 +0100508 if (num < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200509 num += CMD(max) - CMD(min);
BALATON Zoltan0d793792012-11-03 12:47:08 +0100510 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200511 return num >> 2;
thsd34cab92007-04-02 01:10:46 +0000512}
513
balrogff9cf2c2008-07-16 04:45:12 +0000514static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
thsd34cab92007-04-02 01:10:46 +0000515{
balrogff9cf2c2008-07-16 04:45:12 +0000516 uint32_t cmd = s->fifo[CMD(stop) >> 2];
BALATON Zoltan0d793792012-11-03 12:47:08 +0100517
balrogff9cf2c2008-07-16 04:45:12 +0000518 s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
BALATON Zoltan0d793792012-11-03 12:47:08 +0100519 if (CMD(stop) >= CMD(max)) {
thsd34cab92007-04-02 01:10:46 +0000520 s->cmd->stop = s->cmd->min;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100521 }
thsd34cab92007-04-02 01:10:46 +0000522 return cmd;
523}
524
balrogff9cf2c2008-07-16 04:45:12 +0000525static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
526{
527 return le32_to_cpu(vmsvga_fifo_read_raw(s));
528}
529
thsd34cab92007-04-02 01:10:46 +0000530static void vmsvga_fifo_run(struct vmsvga_state_s *s)
531{
532 uint32_t cmd, colour;
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200533 int args, len;
thsd34cab92007-04-02 01:10:46 +0000534 int x, y, dx, dy, width, height;
535 struct vmsvga_cursor_definition_s cursor;
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200536 uint32_t cmd_start;
537
538 len = vmsvga_fifo_length(s);
539 while (len > 0) {
540 /* May need to go back to the start of the command if incomplete */
541 cmd_start = s->cmd->stop;
542
thsd34cab92007-04-02 01:10:46 +0000543 switch (cmd = vmsvga_fifo_read(s)) {
544 case SVGA_CMD_UPDATE:
545 case SVGA_CMD_UPDATE_VERBOSE:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200546 len -= 5;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100547 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200548 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100549 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200550
thsd34cab92007-04-02 01:10:46 +0000551 x = vmsvga_fifo_read(s);
552 y = vmsvga_fifo_read(s);
553 width = vmsvga_fifo_read(s);
554 height = vmsvga_fifo_read(s);
555 vmsvga_update_rect_delayed(s, x, y, width, height);
556 break;
557
558 case SVGA_CMD_RECT_FILL:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200559 len -= 6;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100560 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200561 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100562 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200563
thsd34cab92007-04-02 01:10:46 +0000564 colour = vmsvga_fifo_read(s);
565 x = vmsvga_fifo_read(s);
566 y = vmsvga_fifo_read(s);
567 width = vmsvga_fifo_read(s);
568 height = vmsvga_fifo_read(s);
569#ifdef HW_FILL_ACCEL
570 vmsvga_fill_rect(s, colour, x, y, width, height);
571 break;
572#else
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200573 args = 0;
thsd34cab92007-04-02 01:10:46 +0000574 goto badcmd;
575#endif
576
577 case SVGA_CMD_RECT_COPY:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200578 len -= 7;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100579 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200580 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100581 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200582
thsd34cab92007-04-02 01:10:46 +0000583 x = vmsvga_fifo_read(s);
584 y = vmsvga_fifo_read(s);
585 dx = vmsvga_fifo_read(s);
586 dy = vmsvga_fifo_read(s);
587 width = vmsvga_fifo_read(s);
588 height = vmsvga_fifo_read(s);
589#ifdef HW_RECT_ACCEL
590 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
591 break;
592#else
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200593 args = 0;
thsd34cab92007-04-02 01:10:46 +0000594 goto badcmd;
595#endif
596
597 case SVGA_CMD_DEFINE_CURSOR:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200598 len -= 8;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100599 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200600 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100601 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200602
thsd34cab92007-04-02 01:10:46 +0000603 cursor.id = vmsvga_fifo_read(s);
604 cursor.hot_x = vmsvga_fifo_read(s);
605 cursor.hot_y = vmsvga_fifo_read(s);
606 cursor.width = x = vmsvga_fifo_read(s);
607 cursor.height = y = vmsvga_fifo_read(s);
608 vmsvga_fifo_read(s);
609 cursor.bpp = vmsvga_fifo_read(s);
Roland Dreierf2d928d2010-01-05 20:43:34 -0800610
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200611 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
Andrzej Zaborowski9f810be2010-09-10 02:30:04 +0200612 if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask ||
BALATON Zoltan0d793792012-11-03 12:47:08 +0100613 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) {
Andrzej Zaborowski9f810be2010-09-10 02:30:04 +0200614 goto badcmd;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100615 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200616
617 len -= args;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100618 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200619 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100620 }
Roland Dreierf2d928d2010-01-05 20:43:34 -0800621
BALATON Zoltan0d793792012-11-03 12:47:08 +0100622 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) {
balrogff9cf2c2008-07-16 04:45:12 +0000623 cursor.mask[args] = vmsvga_fifo_read_raw(s);
BALATON Zoltan0d793792012-11-03 12:47:08 +0100624 }
625 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) {
balrogff9cf2c2008-07-16 04:45:12 +0000626 cursor.image[args] = vmsvga_fifo_read_raw(s);
BALATON Zoltan0d793792012-11-03 12:47:08 +0100627 }
thsd34cab92007-04-02 01:10:46 +0000628#ifdef HW_MOUSE_ACCEL
629 vmsvga_cursor_define(s, &cursor);
630 break;
631#else
632 args = 0;
633 goto badcmd;
634#endif
635
636 /*
637 * Other commands that we at least know the number of arguments
638 * for so we can avoid FIFO desync if driver uses them illegally.
639 */
640 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200641 len -= 6;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100642 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200643 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100644 }
thsd34cab92007-04-02 01:10:46 +0000645 vmsvga_fifo_read(s);
646 vmsvga_fifo_read(s);
647 vmsvga_fifo_read(s);
648 x = vmsvga_fifo_read(s);
649 y = vmsvga_fifo_read(s);
650 args = x * y;
651 goto badcmd;
652 case SVGA_CMD_RECT_ROP_FILL:
653 args = 6;
654 goto badcmd;
655 case SVGA_CMD_RECT_ROP_COPY:
656 args = 7;
657 goto badcmd;
658 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200659 len -= 4;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100660 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200661 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100662 }
thsd34cab92007-04-02 01:10:46 +0000663 vmsvga_fifo_read(s);
664 vmsvga_fifo_read(s);
665 args = 7 + (vmsvga_fifo_read(s) >> 2);
666 goto badcmd;
667 case SVGA_CMD_SURFACE_ALPHA_BLEND:
668 args = 12;
669 goto badcmd;
670
671 /*
672 * Other commands that are not listed as depending on any
673 * CAPABILITIES bits, but are not described in the README either.
674 */
675 case SVGA_CMD_SURFACE_FILL:
676 case SVGA_CMD_SURFACE_COPY:
677 case SVGA_CMD_FRONT_ROP_FILL:
678 case SVGA_CMD_FENCE:
679 case SVGA_CMD_INVALID_CMD:
680 break; /* Nop */
681
682 default:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200683 args = 0;
thsd34cab92007-04-02 01:10:46 +0000684 badcmd:
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200685 len -= args;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100686 if (len < 0) {
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200687 goto rewind;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100688 }
689 while (args--) {
thsd34cab92007-04-02 01:10:46 +0000690 vmsvga_fifo_read(s);
BALATON Zoltan0d793792012-11-03 12:47:08 +0100691 }
thsd34cab92007-04-02 01:10:46 +0000692 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
BALATON Zoltan0d793792012-11-03 12:47:08 +0100693 __func__, cmd);
thsd34cab92007-04-02 01:10:46 +0000694 break;
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200695
696 rewind:
697 s->cmd->stop = cmd_start;
698 break;
thsd34cab92007-04-02 01:10:46 +0000699 }
Andrzej Zaborowski4dedc072010-09-10 02:23:31 +0200700 }
thsd34cab92007-04-02 01:10:46 +0000701
702 s->syncing = 0;
703}
704
705static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
706{
Juan Quintela467d44b2009-10-14 17:49:08 +0200707 struct vmsvga_state_s *s = opaque;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100708
thsd34cab92007-04-02 01:10:46 +0000709 return s->index;
710}
711
712static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
713{
Juan Quintela467d44b2009-10-14 17:49:08 +0200714 struct vmsvga_state_s *s = opaque;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100715
thsd34cab92007-04-02 01:10:46 +0000716 s->index = index;
717}
718
719static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
720{
721 uint32_t caps;
Juan Quintela467d44b2009-10-14 17:49:08 +0200722 struct vmsvga_state_s *s = opaque;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100723
thsd34cab92007-04-02 01:10:46 +0000724 switch (s->index) {
725 case SVGA_REG_ID:
726 return s->svgaid;
727
728 case SVGA_REG_ENABLE:
729 return s->enable;
730
731 case SVGA_REG_WIDTH:
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100732 return ds_get_width(s->vga.ds);
thsd34cab92007-04-02 01:10:46 +0000733
734 case SVGA_REG_HEIGHT:
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100735 return ds_get_height(s->vga.ds);
thsd34cab92007-04-02 01:10:46 +0000736
737 case SVGA_REG_MAX_WIDTH:
738 return SVGA_MAX_WIDTH;
739
740 case SVGA_REG_MAX_HEIGHT:
balrogf707cfb2007-05-13 13:26:49 +0000741 return SVGA_MAX_HEIGHT;
thsd34cab92007-04-02 01:10:46 +0000742
743 case SVGA_REG_DEPTH:
BALATON Zoltan1f202562012-11-04 18:41:59 +0100744 return s->depth;
thsd34cab92007-04-02 01:10:46 +0000745
746 case SVGA_REG_BITS_PER_PIXEL:
BALATON Zoltan1f202562012-11-04 18:41:59 +0100747 return (s->depth + 7) & ~7;
thsd34cab92007-04-02 01:10:46 +0000748
749 case SVGA_REG_PSEUDOCOLOR:
750 return 0x0;
751
752 case SVGA_REG_RED_MASK:
BALATON Zoltan1f202562012-11-04 18:41:59 +0100753 return s->wred;
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100754
thsd34cab92007-04-02 01:10:46 +0000755 case SVGA_REG_GREEN_MASK:
BALATON Zoltan1f202562012-11-04 18:41:59 +0100756 return s->wgreen;
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100757
thsd34cab92007-04-02 01:10:46 +0000758 case SVGA_REG_BLUE_MASK:
BALATON Zoltan1f202562012-11-04 18:41:59 +0100759 return s->wblue;
thsd34cab92007-04-02 01:10:46 +0000760
761 case SVGA_REG_BYTES_PER_LINE:
BALATON Zoltan1f202562012-11-04 18:41:59 +0100762 return s->bypp * s->new_width;
thsd34cab92007-04-02 01:10:46 +0000763
Avi Kivity7b619b92011-08-08 16:08:56 +0300764 case SVGA_REG_FB_START: {
765 struct pci_vmsvga_state_s *pci_vmsvga
766 = container_of(s, struct pci_vmsvga_state_s, chip);
767 return pci_get_bar_addr(&pci_vmsvga->card, 1);
768 }
thsd34cab92007-04-02 01:10:46 +0000769
770 case SVGA_REG_FB_OFFSET:
771 return 0x0;
772
773 case SVGA_REG_VRAM_SIZE:
BALATON Zoltan5b9575c2012-11-03 12:47:08 +0100774 return s->vga.vram_size; /* No physical VRAM besides the framebuffer */
thsd34cab92007-04-02 01:10:46 +0000775
776 case SVGA_REG_FB_SIZE:
BALATON Zoltan5b9575c2012-11-03 12:47:08 +0100777 return s->vga.vram_size;
thsd34cab92007-04-02 01:10:46 +0000778
779 case SVGA_REG_CAPABILITIES:
780 caps = SVGA_CAP_NONE;
781#ifdef HW_RECT_ACCEL
782 caps |= SVGA_CAP_RECT_COPY;
783#endif
784#ifdef HW_FILL_ACCEL
785 caps |= SVGA_CAP_RECT_FILL;
786#endif
787#ifdef HW_MOUSE_ACCEL
Gerd Hoffmannbf2fde72012-09-12 07:56:45 +0200788 if (dpy_cursor_define_supported(s->vga.ds)) {
thsd34cab92007-04-02 01:10:46 +0000789 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
790 SVGA_CAP_CURSOR_BYPASS;
Gerd Hoffmannbf2fde72012-09-12 07:56:45 +0200791 }
thsd34cab92007-04-02 01:10:46 +0000792#endif
793 return caps;
794
Avi Kivityb1950432011-08-08 16:08:57 +0300795 case SVGA_REG_MEM_START: {
796 struct pci_vmsvga_state_s *pci_vmsvga
797 = container_of(s, struct pci_vmsvga_state_s, chip);
798 return pci_get_bar_addr(&pci_vmsvga->card, 2);
799 }
thsd34cab92007-04-02 01:10:46 +0000800
801 case SVGA_REG_MEM_SIZE:
Dave Airlief351d052009-12-18 08:08:06 +1000802 return s->fifo_size;
thsd34cab92007-04-02 01:10:46 +0000803
804 case SVGA_REG_CONFIG_DONE:
805 return s->config;
806
807 case SVGA_REG_SYNC:
808 case SVGA_REG_BUSY:
809 return s->syncing;
810
811 case SVGA_REG_GUEST_ID:
812 return s->guest;
813
814 case SVGA_REG_CURSOR_ID:
815 return s->cursor.id;
816
817 case SVGA_REG_CURSOR_X:
818 return s->cursor.x;
819
820 case SVGA_REG_CURSOR_Y:
821 return s->cursor.x;
822
823 case SVGA_REG_CURSOR_ON:
824 return s->cursor.on;
825
826 case SVGA_REG_HOST_BITS_PER_PIXEL:
BALATON Zoltan1f202562012-11-04 18:41:59 +0100827 return (s->depth + 7) & ~7;
thsd34cab92007-04-02 01:10:46 +0000828
829 case SVGA_REG_SCRATCH_SIZE:
830 return s->scratch_size;
831
832 case SVGA_REG_MEM_REGS:
833 case SVGA_REG_NUM_DISPLAYS:
834 case SVGA_REG_PITCHLOCK:
835 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
836 return 0;
837
838 default:
839 if (s->index >= SVGA_SCRATCH_BASE &&
BALATON Zoltan0d793792012-11-03 12:47:08 +0100840 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
thsd34cab92007-04-02 01:10:46 +0000841 return s->scratch[s->index - SVGA_SCRATCH_BASE];
BALATON Zoltan0d793792012-11-03 12:47:08 +0100842 }
843 printf("%s: Bad register %02x\n", __func__, s->index);
thsd34cab92007-04-02 01:10:46 +0000844 }
845
846 return 0;
847}
848
849static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
850{
Juan Quintela467d44b2009-10-14 17:49:08 +0200851 struct vmsvga_state_s *s = opaque;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100852
thsd34cab92007-04-02 01:10:46 +0000853 switch (s->index) {
854 case SVGA_REG_ID:
BALATON Zoltan0d793792012-11-03 12:47:08 +0100855 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) {
thsd34cab92007-04-02 01:10:46 +0000856 s->svgaid = value;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100857 }
thsd34cab92007-04-02 01:10:46 +0000858 break;
859
860 case SVGA_REG_ENABLE:
BALATON Zoltanb51d7b22012-11-03 12:47:08 +0100861 s->enable = !!value;
thsd34cab92007-04-02 01:10:46 +0000862 s->invalidated = 1;
Avi Kivity4e12cd92009-05-03 22:25:16 +0300863 s->vga.invalidate(&s->vga);
BALATON Zoltanb51d7b22012-11-03 12:47:08 +0100864 if (s->enable && s->config) {
Andrzej Zaborowski9f810be2010-09-10 02:30:04 +0200865 vga_dirty_log_stop(&s->vga);
866 } else {
867 vga_dirty_log_start(&s->vga);
868 }
thsd34cab92007-04-02 01:10:46 +0000869 break;
870
871 case SVGA_REG_WIDTH:
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100872 if (value <= SVGA_MAX_WIDTH) {
873 s->new_width = value;
874 s->invalidated = 1;
875 } else {
876 printf("%s: Bad width: %i\n", __func__, value);
877 }
thsd34cab92007-04-02 01:10:46 +0000878 break;
879
880 case SVGA_REG_HEIGHT:
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100881 if (value <= SVGA_MAX_HEIGHT) {
882 s->new_height = value;
883 s->invalidated = 1;
884 } else {
885 printf("%s: Bad height: %i\n", __func__, value);
886 }
thsd34cab92007-04-02 01:10:46 +0000887 break;
888
thsd34cab92007-04-02 01:10:46 +0000889 case SVGA_REG_BITS_PER_PIXEL:
BALATON Zoltan1f202562012-11-04 18:41:59 +0100890 if (value != s->depth) {
BALATON Zoltan5b9575c2012-11-03 12:47:08 +0100891 printf("%s: Bad bits per pixel: %i bits\n", __func__, value);
thsd34cab92007-04-02 01:10:46 +0000892 s->config = 0;
893 }
894 break;
895
896 case SVGA_REG_CONFIG_DONE:
897 if (value) {
Dave Airlief351d052009-12-18 08:08:06 +1000898 s->fifo = (uint32_t *) s->fifo_ptr;
thsd34cab92007-04-02 01:10:46 +0000899 /* Check range and alignment. */
BALATON Zoltan0d793792012-11-03 12:47:08 +0100900 if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) {
thsd34cab92007-04-02 01:10:46 +0000901 break;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100902 }
903 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) {
thsd34cab92007-04-02 01:10:46 +0000904 break;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100905 }
906 if (CMD(max) > SVGA_FIFO_SIZE) {
thsd34cab92007-04-02 01:10:46 +0000907 break;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100908 }
909 if (CMD(max) < CMD(min) + 10 * 1024) {
thsd34cab92007-04-02 01:10:46 +0000910 break;
BALATON Zoltan0d793792012-11-03 12:47:08 +0100911 }
BALATON Zoltanb51d7b22012-11-03 12:47:08 +0100912 vga_dirty_log_stop(&s->vga);
thsd34cab92007-04-02 01:10:46 +0000913 }
balrogf707cfb2007-05-13 13:26:49 +0000914 s->config = !!value;
thsd34cab92007-04-02 01:10:46 +0000915 break;
916
917 case SVGA_REG_SYNC:
918 s->syncing = 1;
919 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
920 break;
921
922 case SVGA_REG_GUEST_ID:
923 s->guest = value;
924#ifdef VERBOSE
925 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
BALATON Zoltan0d793792012-11-03 12:47:08 +0100926 ARRAY_SIZE(vmsvga_guest_id)) {
927 printf("%s: guest runs %s.\n", __func__,
928 vmsvga_guest_id[value - GUEST_OS_BASE]);
929 }
thsd34cab92007-04-02 01:10:46 +0000930#endif
931 break;
932
933 case SVGA_REG_CURSOR_ID:
934 s->cursor.id = value;
935 break;
936
937 case SVGA_REG_CURSOR_X:
938 s->cursor.x = value;
939 break;
940
941 case SVGA_REG_CURSOR_Y:
942 s->cursor.y = value;
943 break;
944
945 case SVGA_REG_CURSOR_ON:
946 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
947 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
948#ifdef HW_MOUSE_ACCEL
Gerd Hoffmannbf2fde72012-09-12 07:56:45 +0200949 if (value <= SVGA_CURSOR_ON_SHOW) {
950 dpy_mouse_set(s->vga.ds, s->cursor.x, s->cursor.y, s->cursor.on);
951 }
thsd34cab92007-04-02 01:10:46 +0000952#endif
953 break;
954
BALATON Zoltan5b9575c2012-11-03 12:47:08 +0100955 case SVGA_REG_DEPTH:
thsd34cab92007-04-02 01:10:46 +0000956 case SVGA_REG_MEM_REGS:
957 case SVGA_REG_NUM_DISPLAYS:
958 case SVGA_REG_PITCHLOCK:
959 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
960 break;
961
962 default:
963 if (s->index >= SVGA_SCRATCH_BASE &&
964 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
965 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
966 break;
967 }
BALATON Zoltan0d793792012-11-03 12:47:08 +0100968 printf("%s: Bad register %02x\n", __func__, s->index);
thsd34cab92007-04-02 01:10:46 +0000969 }
970}
971
972static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
973{
BALATON Zoltan0d793792012-11-03 12:47:08 +0100974 printf("%s: what are we supposed to return?\n", __func__);
thsd34cab92007-04-02 01:10:46 +0000975 return 0xcafe;
976}
977
978static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
979{
BALATON Zoltan0d793792012-11-03 12:47:08 +0100980 printf("%s: what are we supposed to do with (%08x)?\n", __func__, data);
thsd34cab92007-04-02 01:10:46 +0000981}
982
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100983static inline void vmsvga_check_size(struct vmsvga_state_s *s)
thsd34cab92007-04-02 01:10:46 +0000984{
BALATON Zoltanaa32b382012-11-03 12:47:08 +0100985 if (s->new_width != ds_get_width(s->vga.ds) ||
986 s->new_height != ds_get_height(s->vga.ds)) {
987 qemu_console_resize(s->vga.ds, s->new_width, s->new_height);
thsd34cab92007-04-02 01:10:46 +0000988 s->invalidated = 1;
989 }
990}
991
992static void vmsvga_update_display(void *opaque)
993{
Juan Quintela467d44b2009-10-14 17:49:08 +0200994 struct vmsvga_state_s *s = opaque;
BALATON Zoltanb51d7b22012-11-03 12:47:08 +0100995 bool dirty = false;
996
thsd34cab92007-04-02 01:10:46 +0000997 if (!s->enable) {
Avi Kivity4e12cd92009-05-03 22:25:16 +0300998 s->vga.update(&s->vga);
thsd34cab92007-04-02 01:10:46 +0000999 return;
1000 }
1001
BALATON Zoltanaa32b382012-11-03 12:47:08 +01001002 vmsvga_check_size(s);
thsd34cab92007-04-02 01:10:46 +00001003
1004 vmsvga_fifo_run(s);
1005 vmsvga_update_rect_flush(s);
1006
1007 /*
1008 * Is it more efficient to look at vram VGA-dirty bits or wait
1009 * for the driver to issue SVGA_CMD_UPDATE?
1010 */
BALATON Zoltanb51d7b22012-11-03 12:47:08 +01001011 if (memory_region_is_logging(&s->vga.vram)) {
1012 vga_sync_dirty_bitmap(&s->vga);
1013 dirty = memory_region_get_dirty(&s->vga.vram, 0,
1014 ds_get_linesize(s->vga.ds) * ds_get_height(s->vga.ds),
1015 DIRTY_MEMORY_VGA);
1016 }
1017 if (s->invalidated || dirty) {
thsd34cab92007-04-02 01:10:46 +00001018 s->invalidated = 0;
BALATON Zoltanb51d7b22012-11-03 12:47:08 +01001019 memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr,
1020 ds_get_linesize(s->vga.ds) * ds_get_height(s->vga.ds));
1021 dpy_gfx_update(s->vga.ds, 0, 0,
1022 ds_get_width(s->vga.ds), ds_get_height(s->vga.ds));
1023 }
1024 if (dirty) {
1025 memory_region_reset_dirty(&s->vga.vram, 0,
1026 ds_get_linesize(s->vga.ds) * ds_get_height(s->vga.ds),
1027 DIRTY_MEMORY_VGA);
thsd34cab92007-04-02 01:10:46 +00001028 }
1029}
1030
Jan Kiszka8a9501b2011-08-22 19:12:08 +02001031static void vmsvga_reset(DeviceState *dev)
thsd34cab92007-04-02 01:10:46 +00001032{
Jan Kiszka8a9501b2011-08-22 19:12:08 +02001033 struct pci_vmsvga_state_s *pci =
1034 DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev);
1035 struct vmsvga_state_s *s = &pci->chip;
1036
thsd34cab92007-04-02 01:10:46 +00001037 s->index = 0;
1038 s->enable = 0;
1039 s->config = 0;
thsd34cab92007-04-02 01:10:46 +00001040 s->svgaid = SVGA_ID;
thsd34cab92007-04-02 01:10:46 +00001041 s->cursor.on = 0;
1042 s->redraw_fifo_first = 0;
1043 s->redraw_fifo_last = 0;
thsd34cab92007-04-02 01:10:46 +00001044 s->syncing = 0;
Anthony Liguorib5cc6e32009-12-18 08:08:10 +10001045
1046 vga_dirty_log_start(&s->vga);
thsd34cab92007-04-02 01:10:46 +00001047}
1048
1049static void vmsvga_invalidate_display(void *opaque)
1050{
Juan Quintela467d44b2009-10-14 17:49:08 +02001051 struct vmsvga_state_s *s = opaque;
thsd34cab92007-04-02 01:10:46 +00001052 if (!s->enable) {
Avi Kivity4e12cd92009-05-03 22:25:16 +03001053 s->vga.invalidate(&s->vga);
thsd34cab92007-04-02 01:10:46 +00001054 return;
1055 }
1056
1057 s->invalidated = 1;
1058}
1059
balrogf707cfb2007-05-13 13:26:49 +00001060/* save the vga display in a PPM image even if no display is
1061 available */
Luiz Capitulinod7098132012-05-21 16:41:37 -03001062static void vmsvga_screen_dump(void *opaque, const char *filename, bool cswitch,
1063 Error **errp)
thsd34cab92007-04-02 01:10:46 +00001064{
Juan Quintela467d44b2009-10-14 17:49:08 +02001065 struct vmsvga_state_s *s = opaque;
thsd34cab92007-04-02 01:10:46 +00001066 if (!s->enable) {
Luiz Capitulinod7098132012-05-21 16:41:37 -03001067 s->vga.screen_dump(&s->vga, filename, cswitch, errp);
thsd34cab92007-04-02 01:10:46 +00001068 return;
1069 }
1070
BALATON Zoltanaa32b382012-11-03 12:47:08 +01001071 if (ds_get_bits_per_pixel(s->vga.ds) == 32) {
1072 DisplaySurface *ds = qemu_create_displaysurface_from(
1073 ds_get_width(s->vga.ds),
1074 ds_get_height(s->vga.ds),
1075 32,
1076 ds_get_linesize(s->vga.ds),
Gerd Hoffmannb1424e02013-02-20 09:37:12 +01001077 s->vga.vram_ptr, false);
Luiz Capitulinod6631742012-05-24 10:42:25 -03001078 ppm_save(filename, ds, errp);
Anthony Liguori7267c092011-08-20 22:09:37 -05001079 g_free(ds);
balrogf707cfb2007-05-13 13:26:49 +00001080 }
thsd34cab92007-04-02 01:10:46 +00001081}
1082
Anthony Liguoric227f092009-10-01 16:12:16 -05001083static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
balrog4d3b6f62008-02-10 16:33:14 +00001084{
Juan Quintela467d44b2009-10-14 17:49:08 +02001085 struct vmsvga_state_s *s = opaque;
balrog4d3b6f62008-02-10 16:33:14 +00001086
BALATON Zoltan0d793792012-11-03 12:47:08 +01001087 if (s->vga.text_update) {
Avi Kivity4e12cd92009-05-03 22:25:16 +03001088 s->vga.text_update(&s->vga, chardata);
BALATON Zoltan0d793792012-11-03 12:47:08 +01001089 }
balrog4d3b6f62008-02-10 16:33:14 +00001090}
1091
Juan Quintelabacbe282009-10-14 19:30:22 +02001092static int vmsvga_post_load(void *opaque, int version_id)
thsd34cab92007-04-02 01:10:46 +00001093{
Juan Quintelabacbe282009-10-14 19:30:22 +02001094 struct vmsvga_state_s *s = opaque;
thsd34cab92007-04-02 01:10:46 +00001095
1096 s->invalidated = 1;
BALATON Zoltan0d793792012-11-03 12:47:08 +01001097 if (s->config) {
Dave Airlief351d052009-12-18 08:08:06 +10001098 s->fifo = (uint32_t *) s->fifo_ptr;
BALATON Zoltan0d793792012-11-03 12:47:08 +01001099 }
thsd34cab92007-04-02 01:10:46 +00001100 return 0;
1101}
1102
Blue Swirld05ac8f2009-12-04 20:44:44 +00001103static const VMStateDescription vmstate_vmware_vga_internal = {
Juan Quintelabacbe282009-10-14 19:30:22 +02001104 .name = "vmware_vga_internal",
1105 .version_id = 0,
1106 .minimum_version_id = 0,
1107 .minimum_version_id_old = 0,
1108 .post_load = vmsvga_post_load,
BALATON Zoltan0d793792012-11-03 12:47:08 +01001109 .fields = (VMStateField[]) {
BALATON Zoltan1f202562012-11-04 18:41:59 +01001110 VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
Juan Quintelabacbe282009-10-14 19:30:22 +02001111 VMSTATE_INT32(enable, struct vmsvga_state_s),
1112 VMSTATE_INT32(config, struct vmsvga_state_s),
1113 VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1114 VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1115 VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1116 VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1117 VMSTATE_INT32(index, struct vmsvga_state_s),
1118 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1119 scratch_size, 0, vmstate_info_uint32, uint32_t),
1120 VMSTATE_INT32(new_width, struct vmsvga_state_s),
1121 VMSTATE_INT32(new_height, struct vmsvga_state_s),
1122 VMSTATE_UINT32(guest, struct vmsvga_state_s),
1123 VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1124 VMSTATE_INT32(syncing, struct vmsvga_state_s),
BALATON Zoltan5b9575c2012-11-03 12:47:08 +01001125 VMSTATE_UNUSED(4), /* was fb_size */
Juan Quintelabacbe282009-10-14 19:30:22 +02001126 VMSTATE_END_OF_LIST()
1127 }
1128};
1129
Blue Swirld05ac8f2009-12-04 20:44:44 +00001130static const VMStateDescription vmstate_vmware_vga = {
Juan Quintelabacbe282009-10-14 19:30:22 +02001131 .name = "vmware_vga",
1132 .version_id = 0,
1133 .minimum_version_id = 0,
1134 .minimum_version_id_old = 0,
BALATON Zoltan0d793792012-11-03 12:47:08 +01001135 .fields = (VMStateField[]) {
Juan Quintelabacbe282009-10-14 19:30:22 +02001136 VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
1137 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1138 vmstate_vmware_vga_internal, struct vmsvga_state_s),
1139 VMSTATE_END_OF_LIST()
1140 }
1141};
1142
Gerd Hoffmann4a1e2442012-05-24 09:59:44 +02001143static void vmsvga_init(struct vmsvga_state_s *s,
Richard Henderson0a039dc2011-08-16 08:27:39 -07001144 MemoryRegion *address_space, MemoryRegion *io)
thsd34cab92007-04-02 01:10:46 +00001145{
thsd34cab92007-04-02 01:10:46 +00001146 s->scratch_size = SVGA_SCRATCH_SIZE;
Anthony Liguori7267c092011-08-20 22:09:37 -05001147 s->scratch = g_malloc(s->scratch_size * 4);
thsd34cab92007-04-02 01:10:46 +00001148
Anthony Liguoria6109ff2009-12-18 08:08:09 +10001149 s->vga.ds = graphic_console_init(vmsvga_update_display,
1150 vmsvga_invalidate_display,
1151 vmsvga_screen_dump,
1152 vmsvga_text_update, s);
1153
Andrzej Zaborowski4445b0a2009-08-23 19:00:58 +02001154
Dave Airlief351d052009-12-18 08:08:06 +10001155 s->fifo_size = SVGA_FIFO_SIZE;
Avi Kivityc5705a72011-12-20 15:59:12 +02001156 memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size);
1157 vmstate_register_ram_global(&s->fifo_ram);
Avi Kivityb1950432011-08-08 16:08:57 +03001158 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
Dave Airlief351d052009-12-18 08:08:06 +10001159
Gerd Hoffmann4a1e2442012-05-24 09:59:44 +02001160 vga_common_init(&s->vga);
Richard Henderson0a039dc2011-08-16 08:27:39 -07001161 vga_init(&s->vga, address_space, io, true);
Alex Williamson0be71e32010-06-25 11:09:07 -06001162 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
BALATON Zoltan1f202562012-11-04 18:41:59 +01001163 /* Save some values here in case they are changed later.
1164 * This is suspicious and needs more though why it is needed. */
1165 s->depth = ds_get_bits_per_pixel(s->vga.ds);
1166 s->bypp = ds_get_bytes_per_pixel(s->vga.ds);
1167 s->wred = ds_get_rmask(s->vga.ds);
1168 s->wgreen = ds_get_gmask(s->vga.ds);
1169 s->wblue = ds_get_bmask(s->vga.ds);
thsd34cab92007-04-02 01:10:46 +00001170}
1171
BALATON Zoltanaa32b382012-11-03 12:47:08 +01001172static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size)
balrog1492a3c2008-01-14 01:52:52 +00001173{
Avi Kivityb1950432011-08-08 16:08:57 +03001174 struct vmsvga_state_s *s = opaque;
balrog1492a3c2008-01-14 01:52:52 +00001175
Avi Kivityb1950432011-08-08 16:08:57 +03001176 switch (addr) {
1177 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr);
1178 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr);
1179 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr);
1180 default: return -1u;
1181 }
balrog1492a3c2008-01-14 01:52:52 +00001182}
1183
Avi Kivitya8170e52012-10-23 12:30:10 +02001184static void vmsvga_io_write(void *opaque, hwaddr addr,
Avi Kivityb1950432011-08-08 16:08:57 +03001185 uint64_t data, unsigned size)
balrog3016d802008-03-06 20:28:49 +00001186{
Avi Kivityb1950432011-08-08 16:08:57 +03001187 struct vmsvga_state_s *s = opaque;
balrog3016d802008-03-06 20:28:49 +00001188
Avi Kivityb1950432011-08-08 16:08:57 +03001189 switch (addr) {
1190 case SVGA_IO_MUL * SVGA_INDEX_PORT:
Blue Swirl0ed8b6f2012-07-08 06:56:53 +00001191 vmsvga_index_write(s, addr, data);
1192 break;
Avi Kivityb1950432011-08-08 16:08:57 +03001193 case SVGA_IO_MUL * SVGA_VALUE_PORT:
Blue Swirl0ed8b6f2012-07-08 06:56:53 +00001194 vmsvga_value_write(s, addr, data);
1195 break;
Avi Kivityb1950432011-08-08 16:08:57 +03001196 case SVGA_IO_MUL * SVGA_BIOS_PORT:
Blue Swirl0ed8b6f2012-07-08 06:56:53 +00001197 vmsvga_bios_write(s, addr, data);
1198 break;
Avi Kivityb1950432011-08-08 16:08:57 +03001199 }
balrog3016d802008-03-06 20:28:49 +00001200}
1201
Avi Kivityb1950432011-08-08 16:08:57 +03001202static const MemoryRegionOps vmsvga_io_ops = {
1203 .read = vmsvga_io_read,
1204 .write = vmsvga_io_write,
1205 .endianness = DEVICE_LITTLE_ENDIAN,
1206 .valid = {
1207 .min_access_size = 4,
1208 .max_access_size = 4,
1209 },
1210};
Dave Airlief351d052009-12-18 08:08:06 +10001211
Gerd Hoffmann81a322d2009-08-14 10:36:05 +02001212static int pci_vmsvga_initfn(PCIDevice *dev)
thsd34cab92007-04-02 01:10:46 +00001213{
Gerd Hoffmanna414c302009-07-28 18:18:00 +02001214 struct pci_vmsvga_state_s *s =
1215 DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
Avi Kivityb1950432011-08-08 16:08:57 +03001216
BALATON Zoltan0d793792012-11-03 12:47:08 +01001217 s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
1218 s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */
1219 s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */
thsd34cab92007-04-02 01:10:46 +00001220
Avi Kivityb1950432011-08-08 16:08:57 +03001221 memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip,
1222 "vmsvga-io", 0x10);
Jan Kiszkabd8f2f52012-08-23 13:02:33 +02001223 memory_region_set_flush_coalesced(&s->io_bar);
Avi Kivitye824b2c2011-08-08 16:09:31 +03001224 pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
Dave Airlief351d052009-12-18 08:08:06 +10001225
BALATON Zoltanaa32b382012-11-03 12:47:08 +01001226 vmsvga_init(&s->chip, pci_address_space(dev), pci_address_space_io(dev));
thsd34cab92007-04-02 01:10:46 +00001227
BALATON Zoltanaa32b382012-11-03 12:47:08 +01001228 pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
1229 &s->chip.vga.vram);
Avi Kivitye824b2c2011-08-08 16:09:31 +03001230 pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
1231 &s->chip.fifo_ram);
Avi Kivityb1950432011-08-08 16:08:57 +03001232
Gerd Hoffmann281a26b2010-11-17 12:06:44 +01001233 if (!dev->rom_bar) {
1234 /* compatibility with pc-0.13 and older */
Avi Kivitybe20f9e2011-08-15 17:17:37 +03001235 vga_init_vbe(&s->chip.vga, pci_address_space(dev));
Gerd Hoffmann281a26b2010-11-17 12:06:44 +01001236 }
1237
Gerd Hoffmann81a322d2009-08-14 10:36:05 +02001238 return 0;
thsd34cab92007-04-02 01:10:46 +00001239}
Gerd Hoffmanna414c302009-07-28 18:18:00 +02001240
Gerd Hoffmann4a1e2442012-05-24 09:59:44 +02001241static Property vga_vmware_properties[] = {
1242 DEFINE_PROP_UINT32("vgamem_mb", struct pci_vmsvga_state_s,
Gerd Hoffmann9e56edc2012-06-11 10:42:53 +02001243 chip.vga.vram_size_mb, 16),
Gerd Hoffmann4a1e2442012-05-24 09:59:44 +02001244 DEFINE_PROP_END_OF_LIST(),
1245};
1246
Anthony Liguori40021f02011-12-04 12:22:06 -06001247static void vmsvga_class_init(ObjectClass *klass, void *data)
1248{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001249 DeviceClass *dc = DEVICE_CLASS(klass);
Anthony Liguori40021f02011-12-04 12:22:06 -06001250 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
Isaku Yamahata310faae2011-05-25 10:58:04 +09001251
Anthony Liguori40021f02011-12-04 12:22:06 -06001252 k->no_hotplug = 1;
1253 k->init = pci_vmsvga_initfn;
1254 k->romfile = "vgabios-vmware.bin";
1255 k->vendor_id = PCI_VENDOR_ID_VMWARE;
1256 k->device_id = SVGA_PCI_DEVICE_ID;
1257 k->class_id = PCI_CLASS_DISPLAY_VGA;
1258 k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE;
1259 k->subsystem_id = SVGA_PCI_DEVICE_ID;
Anthony Liguori39bffca2011-12-07 21:34:16 -06001260 dc->reset = vmsvga_reset;
1261 dc->vmsd = &vmstate_vmware_vga;
Gerd Hoffmann4a1e2442012-05-24 09:59:44 +02001262 dc->props = vga_vmware_properties;
Anthony Liguori40021f02011-12-04 12:22:06 -06001263}
1264
Andreas Färber8c43a6f2013-01-10 16:19:07 +01001265static const TypeInfo vmsvga_info = {
Anthony Liguori39bffca2011-12-07 21:34:16 -06001266 .name = "vmware-svga",
1267 .parent = TYPE_PCI_DEVICE,
1268 .instance_size = sizeof(struct pci_vmsvga_state_s),
1269 .class_init = vmsvga_class_init,
Gerd Hoffmanna414c302009-07-28 18:18:00 +02001270};
1271
Andreas Färber83f7d432012-02-09 15:20:55 +01001272static void vmsvga_register_types(void)
Gerd Hoffmanna414c302009-07-28 18:18:00 +02001273{
Anthony Liguori39bffca2011-12-07 21:34:16 -06001274 type_register_static(&vmsvga_info);
Gerd Hoffmanna414c302009-07-28 18:18:00 +02001275}
Andreas Färber83f7d432012-02-09 15:20:55 +01001276
1277type_init(vmsvga_register_types)